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| author | Joachim Fenkes <fenkes@de.ibm.com> | 2019-05-13 13:36:52 +0200 |
|---|---|---|
| committer | Christian R. Geddes <crgeddes@us.ibm.com> | 2019-05-17 09:45:48 -0500 |
| commit | 06a885d8e671610224aa9ec88f93264b80312e62 (patch) | |
| tree | 67826596bbb7c62497cadcc33fa5505deaa846d2 /src | |
| parent | 8231492521707f86e108fa9876d1d8e177238b9f (diff) | |
| download | talos-hostboot-06a885d8e671610224aa9ec88f93264b80312e62.tar.gz talos-hostboot-06a885d8e671610224aa9ec88f93264b80312e62.zip | |
p9_tod_setup: Disable clock doubling when running off LPC clock
On Axone, if TOD is running off the LPC clock, turn off the oscillator
frequency doubling since the LPC clock already toggles at 32 MHz.
Use the clock mux bit from ROOT_CTRL8 directly; it's reserved and always
zero on non-Axone chips so the "Axone only" is implicitly taken care of.
Change-Id: I46d2032550a87f21f486a95dcc84cd62532aeda6
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77184
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Thomas Büchner <tbuechner@de.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/77196
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/nest/p9_tod_setup.C | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_tod_setup.C b/src/import/chips/p9/procedures/hwp/nest/p9_tod_setup.C index 04ce62cd9..4558f282c 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_tod_setup.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_tod_setup.C @@ -44,6 +44,7 @@ const uint64_t M_PATH_CTRL_REG_CLEAR_VALUE = 0x0000000000000000; const uint64_t S_PATH_CTRL_REG_CLEAR_VALUE = 0x0000003F00000000; +static const uint8_t P9A_PERV_ROOT_CTRL8_TP_PLL_CLKIN_SEL9_DC = 21; /// @brief MPIPL specific steps to clear the previous topology, this should be // called only during MPIPL @@ -778,6 +779,16 @@ fapi2::ReturnCode configure_m_path_ctrl_reg( const p9_tod_setup_osc_sel i_osc_sel) { fapi2::buffer<uint64_t> l_m_path_ctrl_reg = 0; + fapi2::buffer<uint64_t> l_root_ctrl8_reg = 0; + bool l_tod_on_lpc_clock = false; + + // Read ROOT_CTRL8 to determine TOD input clock selection + FAPI_TRY(fapi2::getScom(*(i_tod_node->i_target), + PERV_ROOT_CTRL8_SCOM, + l_root_ctrl8_reg), + "Error from getScom (PERV_ROOT_CTRL8_SCOM)!"); + + l_tod_on_lpc_clock = l_root_ctrl8_reg.getBit<P9A_PERV_ROOT_CTRL8_TP_PLL_CLKIN_SEL9_DC>(); // Read PERV_TOD_M_PATH_CTRL_REG to preserve any prior configuration FAPI_TRY(fapi2::getScom(*(i_tod_node->i_target), @@ -785,6 +796,8 @@ fapi2::ReturnCode configure_m_path_ctrl_reg( l_m_path_ctrl_reg), "Error from getScom (PERV_TOD_M_PATH_CTRL_REG)!"); + l_m_path_ctrl_reg.writeBit<PERV_TOD_M_PATH_CTRL_REG_STEP_CREATE_DUAL_EDGE_DISABLE>(l_tod_on_lpc_clock); + // Configure Master OSC0/OSC1 path FAPI_DBG("Configuring Master OSC path in PERV_TOD_M_PATH_CTRL_REG"); |
