summaryrefslogtreecommitdiffstats
path: root/src/usr
diff options
context:
space:
mode:
authorJoe McGill <jmcgill@us.ibm.com>2018-05-01 14:25:39 -0500
committerDaniel M. Crowell <dcrowell@us.ibm.com>2018-06-14 10:51:15 -0400
commitf9a40964fc9dfe9209ea6da3622f39959dd10477 (patch)
tree74966484b5cfb08d309e7d027c3dc240e3df9d72 /src/usr
parentd46f111a8f66830714e32d003982718d13abf66f (diff)
downloadtalos-hostboot-f9a40964fc9dfe9209ea6da3622f39959dd10477.tar.gz
talos-hostboot-f9a40964fc9dfe9209ea6da3622f39959dd10477.zip
support IO reconfig loop for OBUS DL link training failures
- p9c DD1.1+ only, DD1.0 not supported - FW to trigger reconfig loop back to step 0 from sys_proc_fab_iovalid if: 1) sys_proc_fab_iovalid rc = FAPI2_RC_SUCCESS -- AND -- 2) new output o_obus_dl_rcs (vector of P9_FAB_IOVALID_DL_NOT_TRAINED_ERR rc objects identifying links which failed on this chip) has entries - attribute changes: ATTR_LINK_TRAIN -- remove platinit tag, attr should init to zero (both even and odd), and reconfig loop will adjust value as we go CMVC-Prereq:1057645 Change-Id: I95eebd2b893db6d2511aae40798c0a4e049835d6 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59022 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59039 Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/usr')
-rw-r--r--src/usr/isteps/istep09/call_proc_fab_iovalid.C12
-rw-r--r--src/usr/isteps/istep18/smp_unfencing_inter_enclosure_abus_links.C13
2 files changed, 19 insertions, 6 deletions
diff --git a/src/usr/isteps/istep09/call_proc_fab_iovalid.C b/src/usr/isteps/istep09/call_proc_fab_iovalid.C
index b2d40347a..6ef1f732f 100644
--- a/src/usr/isteps/istep09/call_proc_fab_iovalid.C
+++ b/src/usr/isteps/istep09/call_proc_fab_iovalid.C
@@ -84,6 +84,7 @@ void* call_proc_fab_iovalid( void *io_pArgs )
{
IStepError l_StepError;
errlHndl_t l_errl = NULL;
+ std::vector<fapi2::ReturnCode> l_fapiRcs;
TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
"call_proc_fab_iovalid entry" );
@@ -122,16 +123,21 @@ void* call_proc_fab_iovalid( void *io_pArgs )
TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
"Running p9_fab_iovalid HWP on processor target %.8X",
TARGETING::get_huid(l_cpu_target) );
-
+
if (INITSERVICE::isSMPWrapConfig())
{
FAPI_INVOKE_HWP(l_errl, p9_fab_iovalid, l_fapi2_proc_target,
- true, true, true);
+ true, true, true, l_fapiRcs);
}
else
{
+ // Note:
+ // When this HWP gets run under HB, it should only train X PHYS, not Os.
+ // The HWP shouldn't fill anydata into vector l_fapiRcs for X's,
+ // only for O's that could be used to trigger a reconfig loop in FSP.
+ // Therefore, we ignore the check for l_fapiRcs here.
FAPI_INVOKE_HWP(l_errl, p9_fab_iovalid, l_fapi2_proc_target,
- true, true, false);
+ true, true, false, l_fapiRcs);
}
if(l_errl)
{
diff --git a/src/usr/isteps/istep18/smp_unfencing_inter_enclosure_abus_links.C b/src/usr/isteps/istep18/smp_unfencing_inter_enclosure_abus_links.C
index ffea3f394..4e35e5a48 100644
--- a/src/usr/isteps/istep18/smp_unfencing_inter_enclosure_abus_links.C
+++ b/src/usr/isteps/istep18/smp_unfencing_inter_enclosure_abus_links.C
@@ -120,10 +120,10 @@ namespace EDI_EI_INITIALIZATION
assert(sys != NULL, "isPeerPresent system target is NULL");
TARGETING::ATTR_HB_EXISTING_IMAGE_type hb_images;
-
+
l_exists =
sys->tryGetAttr<TARGETING::ATTR_HB_EXISTING_IMAGE>(hb_images);
-
+
if( false == l_exists )
{
TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
@@ -184,6 +184,7 @@ namespace EDI_EI_INITIALIZATION
errlHndl_t smp_unfencing_inter_enclosure_abus_links()
{
errlHndl_t l_errl = NULL;
+ std::vector<fapi2::ReturnCode> l_fapiRcs;
TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
"smp_unfencing_inter_enclosure_abus_links entry" );
@@ -202,8 +203,14 @@ namespace EDI_EI_INITIALIZATION
TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
"Running p9_fab_iovalid HWP on processor target %.8X",
TARGETING::get_huid(l_cpu_target) );
+
+ // Note:
+ // When this HWP gets run under HB, it should only train X PHYS, not Os.
+ // The HWP shouldn't fill anydata into vector l_fapiRcs for X's,
+ // only for O's that could be used to trigger a reconfig loop in FSP.
+ // Therefore, we ignore the check for l_fapiRcs here.
FAPI_INVOKE_HWP(l_errl, p9_fab_iovalid, l_fapi2_proc_target,
- true, true, false);
+ true, true, false, l_fapiRcs);
if(l_errl)
{
TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
OpenPOWER on IntegriCloud