SW287733: HWP mss_thermal_init.C update to configure non-custom DIMM sensor cach

Change-Id: I3abd33412e2a29192a83b897f0f1d9783e6188f9
CQ:SW287733
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/14888
Reviewed-by: Brian H. Horton <brianh@linux.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Richard J. Knight <rjknight@us.ibm.com>
Tested-by: Richard J. Knight <rjknight@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/15296
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

5 files changed, 60 insertions, 10 deletions

diff --git a/src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/mss_thermal_init.C b/src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/mss_thermal_init.C
index c295d0f12..aa217c637 100644
--- a/src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/mss_thermal_init.C
+++ b/src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/mss_thermal_init.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
+/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -22,7 +22,7 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_thermal_init.C,v 1.15 2014/02/26 21:19:10 pardeik Exp $
+// $Id: mss_thermal_init.C,v 1.18 2015/01/23 17:54:09 dcrowell Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_thermal_init.C,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -49,6 +49,8 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//   1.17  | pardeik  |19-NOV-14| Use MRW attribute for SC address map for ISDIMMs
+//   1.16  | pardeik  |06-FEB-14| removed string in trace statement
 //   1.15  | pardeik  |24-FEB-14| added support for ATTR_MRW_CDIMM_SPARE_I2C_TEMP_SENSOR_ENABLE
 //   1.14  | pardeik  |12-FEB-14| changed CONFIG_INTERVAL_TIMER from 5 to 15 to 
 //   1.13  | pardeik  |30-JAN-14| workaround for SW243504 (enable sensors on master
@@ -120,8 +122,7 @@ fapi::ReturnCode mss_thermal_init(const fapi::Target & i_target)
       fapi::ReturnCode l_rc;
       uint32_t l_ecmd_rc = 0;
 
-      const char *procedure_name = "mss_thermal_init";
-      FAPI_INF("*** Running %s ***", procedure_name);
+      FAPI_INF("*** Running mss_thermal_init ***");
 
       // Constant declaration
       const uint8_t l_NUM_MBAS = 2;                                     // Number of MBAs per Centaur
@@ -150,7 +151,6 @@ fapi::ReturnCode mss_thermal_init(const fapi::Target & i_target)
       const uint32_t I2C_SETUP_LOWER_HALF = 0x05000000;
       const uint32_t ACT_MASK_UPPER_HALF = 0x00018000;
       const uint32_t ACT_MASK_LOWER_HALF = 0x00000000;
-      const uint32_t SENSOR_ADDR_MAP_ISDIMM = 0x01234567;
 // OCC polls cacheline every 2 ms (could vary from this, as seen on scope)
 // For I2C bus at 50kHz (9.6 ms max to read 8 sensors), use interval of 15 for margin and to prevent stall errors when 8 sensors are enabled to be read
       const uint32_t CONFIG_INTERVAL_TIMER = 15;
@@ -176,6 +176,7 @@ fapi::ReturnCode mss_thermal_init(const fapi::Target & i_target)
       uint8_t l_sensor_map_mask;
       uint8_t l_master_i2c_temp_sensor_enable;
       uint8_t l_spare_i2c_temp_sensor_enable;
+      uint32_t l_dimm_sensor_cache_addr_map = 0;
 
 //********************************************
 // Centaur internal temperature polling setup 
@@ -237,6 +238,15 @@ fapi::ReturnCode mss_thermal_init(const fapi::Target & i_target)
       l_rc = fapiGetChildChiplets(i_target, fapi::TARGET_TYPE_MBA_CHIPLET, l_target_mba_array);
       if (l_rc) return l_rc;
 
+      // need to clear out the array since it could be sparsely filled
+      //  in the ISDIMM case
+      for( size_t i = 0;
+           i < (sizeof(l_custom_dimm)/sizeof(l_custom_dimm[0]));
+           i++ )
+      {
+          l_custom_dimm[i] = fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_NO;
+      }
+
       for (uint8_t mba_index = 0; mba_index < l_target_mba_array.size(); mba_index++){
          l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_target_mba_array[mba_index], l_mba_pos);
 	 if (l_rc) return l_rc;
@@ -264,6 +274,12 @@ fapi::ReturnCode mss_thermal_init(const fapi::Target & i_target)
 	  l_rc = FAPI_ATTR_GET(ATTR_MRW_CDIMM_SPARE_I2C_TEMP_SENSOR_ENABLE, NULL, l_spare_i2c_temp_sensor_enable);
 	  if (l_rc) return l_rc;
       }
+      else
+      {
+	  // sensor cache address map for non custom dimm temperature sensors (which i2c bus and i2c address they are)
+	  l_rc = FAPI_ATTR_GET(ATTR_MRW_MEM_SENSOR_CACHE_ADDR_MAP, NULL, l_dimm_sensor_cache_addr_map);
+	  if (l_rc) return l_rc;
+      }
 
       // Configure Centaur Thermal Cache
 
@@ -492,7 +508,7 @@ fapi::ReturnCode mss_thermal_init(const fapi::Target & i_target)
 	    }
 	    l_iterator++;
 	 }
-	 l_ecmd_rc |= l_data_scac_addrmap.insert(SENSOR_ADDR_MAP_ISDIMM, 0, 32, 0);
+	 l_ecmd_rc |= l_data_scac_addrmap.insert(l_dimm_sensor_cache_addr_map, 0, 32, 0);
 	 if(l_ecmd_rc) {
 	     l_rc.setEcmdError(l_ecmd_rc);
 	     return l_rc;
@@ -619,7 +635,7 @@ fapi::ReturnCode mss_thermal_init(const fapi::Target & i_target)
 	  }
       }
 
-      FAPI_INF("*** %s COMPLETE ***", procedure_name);
+      FAPI_INF("*** mss_thermal_init COMPLETE ***");
       return l_rc;
 
    } //end mss_thermal_init
diff --git a/src/usr/hwpf/hwp/memory_attributes.xml b/src/usr/hwpf/hwp/memory_attributes.xml
index 99fffa5ce..270b155af 100644
--- a/src/usr/hwpf/hwp/memory_attributes.xml
+++ b/src/usr/hwpf/hwp/memory_attributes.xml
@@ -5,7 +5,7 @@
 <!--                                                                        -->
 <!-- OpenPOWER HostBoot Project                                             -->
 <!--                                                                        -->
-<!-- Contributors Listed Below - COPYRIGHT 2012,2014                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2012,2015                        -->
 <!-- [+] International Business Machines Corp.                              -->
 <!--                                                                        -->
 <!--                                                                        -->
@@ -23,7 +23,7 @@
 <!--                                                                        -->
 <!-- IBM_PROLOG_END_TAG                                                     -->
 <attributes>
-<!-- $Id: memory_attributes.xml,v 1.138 2014/11/04 21:34:12 jdsloat Exp $ -->
+<!-- $Id: memory_attributes.xml,v 1.139 2014/11/18 17:35:29 jdsloat Exp $ -->
 <!-- DO NOT EDIT THIS FILE DIRECTLY PLEASE UPDATE THE ODS FILE AND FOLLOW THE INSTRUCTION TAB -->
 <!-- PLEASE SEE MARK BELLOWS (BELLOWS.IBM.COM) OR OTHERS ON MEMORY TEAM FOR HELP -->
 <!-- *********************************************************************** -->
@@ -2886,6 +2886,15 @@ Will be set at an MBA level with one policy to be used</description>
     <odmVisable/>
 </attribute>  
 
+<attribute>
+    <id>ATTR_MRW_MEM_SENSOR_CACHE_ADDR_MAP</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Machine Readable Workbook value detailing the wiring of the 8 dimm temperature sensors for non custom dimms, in DIMM A0,A1,B0,B1,C0,C1,D0,D1 order. One nibble per sensor where bit0 (MSB) is the i2c bus the sensor is attached to (0 for master, 1 for spare) and bits 1:3 are for A2,A1,A0 of the sensor i2c address (where A2 is MSB)</description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
 <!-- DO NOT EDIT THIS FILE DIRECTLY PLEASE UPDATE THE ODS FILE AND FOLLOW THE INSTRUCTION TAB -->
 <!-- PLEASE SEE MARK BELLOWS (BELLOWS.IBM.COM) OR OTHERS ON MEMORY TEAM FOR HELP -->
 </attributes>
diff --git a/src/usr/targeting/common/genHwsvMrwXml.pl b/src/usr/targeting/common/genHwsvMrwXml.pl
index 9c9320595..42a98c0a4 100755
--- a/src/usr/targeting/common/genHwsvMrwXml.pl
+++ b/src/usr/targeting/common/genHwsvMrwXml.pl
@@ -227,7 +227,9 @@ push @systemAttr,
         $reqPol->{'cdimm_master_i2c_temp_sensor_enable'},
     "MRW_CDIMM_SPARE_I2C_TEMP_SENSOR_ENABLE",
         $reqPol->{'cdimm_spare_i2c_temp_sensor_enable'},
-    "PM_SYSTEM_IVRMS_ENABLED", $reqPol->{'pm_system_ivrms_enabled'},
+    "MRW_MEM_SENSOR_CACHE_ADDR_MAP",
+        $reqPol->{'mem_sensor_cache_addr_map'},
+     "PM_SYSTEM_IVRMS_ENABLED", $reqPol->{'pm_system_ivrms_enabled'},
     "PM_SYSTEM_IVRM_VPD_MIN_LEVEL", $reqPol->{'pm_system_ivrm_vpd_min_level'},
     "MRW_ENHANCED_GROUPING_NO_MIRRORING", $reqPol->{'mcs_enhanced_grouping_no_mirroring'},
     "MRW_STRICT_MBA_PLUG_RULE_CHECKING", $reqPol->{'strict_mba_plug_rule_checking'},
diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml
index 14bcf403c..dfaba53a9 100644
--- a/src/usr/targeting/common/xmltohb/attribute_types.xml
+++ b/src/usr/targeting/common/xmltohb/attribute_types.xml
@@ -11973,6 +11973,27 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript
 </attribute>
 
 <attribute>
+    <id>MRW_MEM_SENSOR_CACHE_ADDR_MAP</id>
+    <description>Machine Readable Workbook value detailing the wiring of the
+                 8 dimm temperature sensors for non custom dimms, in DIMM A0,
+                 A1,B0,B1,C0,C1,D0,D1 order. One nibble per sensor where
+                 bit0 (MSB) is the i2c bus the sensor is attached to
+                 (0 for master, 1 for spare) and bits 1:3 are for A2,A1,A0
+                 of the sensor i2c address (where A2 is MSB)
+    </description>
+    <simpleType>
+        <uint32_t>
+        </uint32_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MRW_MEM_SENSOR_CACHE_ADDR_MAP</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
     <id>CDIMM_SENSOR_MAP_PRIMARY</id>
     <description>
         Custom DIMM Sensor Map for Primary I2C Port (1 byte of data):
diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml
index ed44a82d8..c9e5c92ce 100644
--- a/src/usr/targeting/common/xmltohb/target_types.xml
+++ b/src/usr/targeting/common/xmltohb/target_types.xml
@@ -128,6 +128,8 @@
     <attribute><id>MRW_POWER_CONTROL_REQUESTED</id></attribute>
     <attribute><id>MRW_DDR3_VDDR_MAX_LIMIT</id></attribute>
     <attribute><id>MRW_DDR4_VDDR_MAX_LIMIT</id></attribute>
+    <attribute><id>MRW_MEM_SENSOR_CACHE_ADDR_MAP</id></attribute>
+
     <!-- Start pm_plat_attributes.xml -->
     <attribute><id>PM_EXTERNAL_VRM_STEPSIZE</id></attribute>
     <attribute><id>PM_EXTERNAL_VRM_STEPDELAY</id></attribute>