diff options
| author | Mike Jones <mjjones@us.ibm.com> | 2012-07-03 11:12:18 -0500 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2012-07-09 16:48:41 -0500 |
| commit | ddcb6d59a879539c52911b9e6d6c41e11146d7ae (patch) | |
| tree | 9e32f94d7ad8dfe0390a965814696bf441573a10 /src/usr | |
| parent | b6c438bc018f7102568b7c80927e3f9d77eec40a (diff) | |
| download | talos-hostboot-ddcb6d59a879539c52911b9e6d6c41e11146d7ae.tar.gz talos-hostboot-ddcb6d59a879539c52911b9e6d6c41e11146d7ae.zip | |
Add proc_revert_sbe_mcs_setup HWP to Hostboot
This was a late addition to the 07/15 milestone (Run Grub)
Change-Id: I5a72c83e1481207e47d5351a116174b180021ab6
RTC: 44247
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1289
Tested-by: Jenkins Server
Reviewed-by: Van H. Lee <vanlee@us.ibm.com>
Reviewed-by: CAMVAN T. NGUYEN <ctnguyen@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr')
| -rw-r--r-- | src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.C | 67 | ||||
| -rwxr-xr-x | src/usr/hwpf/hwp/include/cen_scom_addresses.H | 457 | ||||
| -rwxr-xr-x | src/usr/hwpf/hwp/include/common_scom_addresses.H | 277 | ||||
| -rw-r--r-- | src/usr/hwpf/hwp/include/fapi_sbe_common.H (renamed from src/usr/hwpf/hwp/build_winkle_images/proc_slw_build/fapi_sbe_common.H) | 0 | ||||
| -rw-r--r-- | src/usr/hwpf/hwp/include/fapi_sbe_common.h | 62 | ||||
| -rwxr-xr-x | src/usr/hwpf/hwp/include/p8_scom_addresses.H | 637 | ||||
| -rw-r--r-- | src/usr/hwpf/hwp/makefile | 3 | ||||
| -rw-r--r-- | src/usr/hwpf/hwp/nest_chiplets/makefile | 2 | ||||
| -rw-r--r-- | src/usr/hwpf/hwp/slave_sbe/makefile | 49 | ||||
| -rw-r--r-- | src/usr/hwpf/hwp/slave_sbe/proc_revert_sbe_mcs_setup/proc_revert_sbe_mcs_setup.C | 224 | ||||
| -rw-r--r-- | src/usr/hwpf/hwp/slave_sbe/proc_revert_sbe_mcs_setup/proc_revert_sbe_mcs_setup.H | 108 | ||||
| -rw-r--r-- | src/usr/hwpf/hwp/slave_sbe/slave_sbe.C | 107 | ||||
| -rw-r--r-- | src/usr/hwpf/hwp/slave_sbe/slave_sbe.H | 72 |
13 files changed, 1773 insertions, 292 deletions
diff --git a/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.C b/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.C index 60bd52146..e81be6161 100644 --- a/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.C +++ b/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.C @@ -1,26 +1,27 @@ -// IBM_PROLOG_BEGIN_TAG -// This is an automatically generated prolog. -// -// $Source: src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.C $ -// -// IBM CONFIDENTIAL -// -// COPYRIGHT International Business Machines Corp. 2012 -// -// p1 -// -// Object Code Only (OCO) source materials -// Licensed Internal Code Source Materials -// IBM HostBoot Licensed Internal Code -// -// The source code for this program is not published or other- -// wise divested of its trade secrets, irrespective of what has -// been deposited with the U.S. Copyright Office. -// -// Origin: 30 -// -// IBM_PROLOG_END -// $Id: proc_cen_framelock.C,v 1.5 2012/04/11 06:23:54 jmcgill Exp $ +/* IBM_PROLOG_BEGIN_TAG + * This is an automatically generated prolog. + * + * $Source: src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.C $ + * + * IBM CONFIDENTIAL + * + * COPYRIGHT International Business Machines Corp. 2012 + * + * p1 + * + * Object Code Only (OCO) source materials + * Licensed Internal Code Source Materials + * IBM HostBoot Licensed Internal Code + * + * The source code for this program is not published or other- + * wise divested of its trade secrets, irrespective of what has + * been deposited with the U.S. Copyright Office. + * + * Origin: 30 + * + * IBM_PROLOG_END_TAG + */ +// $Id: proc_cen_framelock.C,v 1.6 2012/06/01 02:47:07 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_cen_framelock.C,v $ //------------------------------------------------------------------------------ // *| @@ -156,11 +157,11 @@ fapi::ReturnCode proc_cen_framelock_clear_pu_mci_stat_reg( FAPI_DBG("proc_cen_framelock_clear_pu_mci_stat_reg: Start"); - rc = fapiPutScom(i_pu_target, MCI_STAT_0x0201184B, zero_data); + rc = fapiPutScom(i_pu_target, MCS_MCISTAT_0x0201184B, zero_data); if (rc) { - FAPI_ERR("proc_cen_framelock_clear_pu_mci_stat_reg: fapiPutScom error (MCI_STAT_0x0201184B)"); + FAPI_ERR("proc_cen_framelock_clear_pu_mci_stat_reg: fapiPutScom error (MCI_MCISTAT_0x0201184B)"); } return rc; @@ -182,11 +183,11 @@ fapi::ReturnCode proc_cen_framelock_get_pu_mci_stat_reg( FAPI_DBG("proc_cen_framelock_get_pu_mci_stat_reg: Start"); - rc = fapiGetScom(i_pu_target, MCI_STAT_0x0201184B, o_data); + rc = fapiGetScom(i_pu_target, MCS_MCISTAT_0x0201184B, o_data); if (rc) { - FAPI_ERR("proc_cen_framelock_get_pu_mci_stat_reg: fapiGetScom error (MCI_STAT_0x0201184B)"); + FAPI_ERR("proc_cen_framelock_get_pu_mci_stat_reg: fapiGetScom error (MCS_MCISTAT_0x0201184B)"); } return rc; } @@ -206,11 +207,11 @@ fapi::ReturnCode proc_cen_framelock_clear_pu_mci_fir_reg( FAPI_DBG("proc_cen_framelock_clear_pu_mci_fir_reg: Start"); - rc = fapiPutScom(i_pu_target, MCI_FIR_0x02011840, zero_data); + rc = fapiPutScom(i_pu_target, MCS_MCIFIR_0x02011840, zero_data); if (rc) { - FAPI_ERR("proc_cen_framelock_clear_pu_mci_fir_reg: fapiPutScom error (MCI_FIR_0x02011840)"); + FAPI_ERR("proc_cen_framelock_clear_pu_mci_fir_reg: fapiPutScom error (MCS_MCIFIR_0x02011840)"); } return rc; @@ -232,11 +233,11 @@ fapi::ReturnCode proc_cen_framelock_get_pu_mci_fir_reg( FAPI_DBG("proc_cen_framelock_get_pu_mci_fir_reg: Start"); - rc = fapiGetScom(i_pu_target, MCI_FIR_0x02011840, o_data); + rc = fapiGetScom(i_pu_target, MCS_MCIFIR_0x02011840, o_data); if (rc) { - FAPI_ERR("proc_cen_framelock_get_pu_mci_fir_reg: fapiGetScom error (MCI_FIR_0x02011840)"); + FAPI_ERR("proc_cen_framelock_get_pu_mci_fir_reg: fapiGetScom error (MCS_MCIFIR_0x02011840)"); } return rc; @@ -285,11 +286,11 @@ fapi::ReturnCode proc_cen_framelock_set_pu_mci_cfg_reg( FAPI_DBG("proc_cen_framelock_set_pu_mci_cfg_reg: Start"); - rc = fapiPutScomUnderMask(i_pu_target, MCI_CFG_0x0201184A, i_data, i_mask); + rc = fapiPutScomUnderMask(i_pu_target, MCS_MCICFG_0x0201184A, i_data, i_mask); if (rc) { - FAPI_ERR("proc_cen_framelock_set_pu_mci_cfg_reg: fapiPutScomUnderMask error (MCI_CFG_0x0201184A)"); + FAPI_ERR("proc_cen_framelock_set_pu_mci_cfg_reg: fapiPutScomUnderMask error (MCS_MCICFG_0x0201184A)"); } return rc; diff --git a/src/usr/hwpf/hwp/include/cen_scom_addresses.H b/src/usr/hwpf/hwp/include/cen_scom_addresses.H index 263bcc61e..cfb40a942 100755 --- a/src/usr/hwpf/hwp/include/cen_scom_addresses.H +++ b/src/usr/hwpf/hwp/include/cen_scom_addresses.H @@ -1,26 +1,27 @@ -// IBM_PROLOG_BEGIN_TAG -// This is an automatically generated prolog. -// -// $Source: src/usr/hwpf/hwp/include/cen_scom_addresses.H $ -// -// IBM CONFIDENTIAL -// -// COPYRIGHT International Business Machines Corp. 2012 -// -// p1 -// -// Object Code Only (OCO) source materials -// Licensed Internal Code Source Materials -// IBM HostBoot Licensed Internal Code -// -// The source code for this program is not published or other- -// wise divested of its trade secrets, irrespective of what has -// been deposited with the U.S. Copyright Office. -// -// Origin: 30 -// -// IBM_PROLOG_END -// $Id: cen_scom_addresses.H,v 1.15 2012/03/06 16:40:00 divyakum Exp $ +/* IBM_PROLOG_BEGIN_TAG + * This is an automatically generated prolog. + * + * $Source: src/usr/hwpf/hwp/include/cen_scom_addresses.H $ + * + * IBM CONFIDENTIAL + * + * COPYRIGHT International Business Machines Corp. 2012 + * + * p1 + * + * Object Code Only (OCO) source materials + * Licensed Internal Code Source Materials + * IBM HostBoot Licensed Internal Code + * + * The source code for this program is not published or other- + * wise divested of its trade secrets, irrespective of what has + * been deposited with the U.S. Copyright Office. + * + * Origin: 30 + * + * IBM_PROLOG_END_TAG + */ +// $Id: cen_scom_addresses.H,v 1.22 2012/06/18 01:58:44 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/cen_scom_addresses.H,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -44,7 +45,11 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- -// | | | +// | | | +// 1.22 | jmcgill |17-Jun-12| Added trace related SCOM addresses +// 1.21 | gollub |23-May-12| Added regs needed for mss_maint_cmds +// 1.20 | jdsloat |17-May-12| Added MBA/MBS level PM, REF register addresses +// 1.19 | gollub |25-Apr-12| Added MBS ECC regs // 1.15 | divyakum |06-Mar-12| Added calibration status regs // 1.14 | divyakum |22-Feb-12| Added CALIBRATION registers. // | | | Added Change history table @@ -120,7 +125,7 @@ // #include "common_scom_addresses.H" -#include "fapi_sbe_common.h" +#include "fapi_sbe_common.H" /******************************************************************************/ @@ -142,6 +147,8 @@ CONST_UINT64_T( CEN_WRITE_ARRAY_REPAIR_CMD_0x00050002, ULL(0x00050002) ); CONST_UINT64_T( CEN_READ_ARRAY_REPAIR_STATUS_0x00050003, ULL(0x00050003) ); CONST_UINT64_T( CEN_READ_ECC_TRAP_REGISTER_0x00050004, ULL(0x00050004) ); +CONST_UINT64_T( TP_TRACE_DATA_HI_0x01010440 , ULL(0x01010440) ); +CONST_UINT64_T( TP_TRACE_DATA_LO_0x01010441 , ULL(0x01010441) ); /******************************************************************************/ /******************************* NEST CHIPLET *******************************/ @@ -151,10 +158,23 @@ CONST_UINT64_T( CEN_READ_ECC_TRAP_REGISTER_0x00050004, ULL(0x00050004) ); // MBU //------------------------------------------------------------------------------ // MBI -CONST_UINT64_T( MBI_FIR_0x02010800 , ULL(0x02010800) ); -CONST_UINT64_T( MBI_CFG_0x0201080A , ULL(0x0201080A) ); -CONST_UINT64_T( MBI_STAT_0x0201080B , ULL(0x0201080B) ); +CONST_UINT64_T( MBI_FIR_0x02010800 , ULL(0x02010800) ); +CONST_UINT64_T( MBI_CFG_0x0201080A , ULL(0x0201080A) ); +CONST_UINT64_T( MBI_STAT_0x0201080B , ULL(0x0201080B) ); + +CONST_UINT64_T( NEST_TRACE_DATA_HI_MBI_0x02010C40 , ULL(0x02010C40) ); +CONST_UINT64_T( NEST_TRACE_DATA_LO_MBI_0x02010C41 , ULL(0x02010C41) ); +// MBS +CONST_UINT64_T( MBSSQ_0x02011417 , ULL(0x02011417) ); + +CONST_UINT64_T( NEST_TRACE_DATA_HI_MBS1_0x02011880 , ULL(0x02011880) ); +CONST_UINT64_T( NEST_TRACE_DATA_LO_MBS1_0x02011881 , ULL(0x02011881) ); +CONST_UINT64_T( NEST_TRACE_DATA_HI_MBS2_0x020118C0 , ULL(0x020118C0) ); +CONST_UINT64_T( NEST_TRACE_DATA_LO_MBS2_0x020118C1 , ULL(0x020118C1) ); +// MBA +CONST_UINT64_T( MBA01_REF0Q_0x03010432 , ULL(0x03010432) ); +CONST_UINT64_T( MBA01_PM0Q_0x03010434 , ULL(0x03010434) ); /******************************************************************************/ /****************************** MEM CHIPLET *********************************/ @@ -181,6 +201,14 @@ CONST_UINT64_T( MEM_MBA01_CCS_MODEQ_0x030106A7 , ULL(0x030106A7) ); CONST_UINT64_T( MEM_MBA23_CCS_MODEQ_0x03010EA7 , ULL(0x03010EA7) ); //------------------------------------------------------------------------------ +// MEM TRACE +//------------------------------------------------------------------------------ +CONST_UINT64_T( MEM_TRACE_DATA_HI_MBA01_0x03010880 , ULL(0x03010880) ); +CONST_UINT64_T( MEM_TRACE_DATA_LO_MBA01_0x03010881 , ULL(0x03010881) ); +CONST_UINT64_T( MEM_TRACE_DATA_HI_MBA23_0x030110C0 , ULL(0x030110C0) ); +CONST_UINT64_T( MEM_TRACE_DATA_LO_MBA23_0x030110C1 , ULL(0x030110C1) ); + +//------------------------------------------------------------------------------ // MEM CLOCK CONTROL //------------------------------------------------------------------------------ CONST_UINT64_T( MEM_OPCG_CNTL0_0x03030002 , ULL(0x03030002) ); @@ -232,148 +260,360 @@ CONST_UINT64_T( MEM_GP3_OR_0x030F0014 , ULL(0x030F0014) ); //------------------------------------------------------------------------------ // MEM CHIPLET INDIRECT SCOM ADDRESSES (DPHY REGISTERS) //------------------------------------------------------------------------------ +// Note - on March 30,2012, at the request of the GFW team, I removed all the DPHY23 addresses that were listed below. +// These adddresses should not be needed because the procedures are written using DPHY01 as the target and +// the platform translates the address for DPHY23. +// If you should need these dphy23 address for some reason, I have saved a copy of them here: +// /afs/rchland.ibm.com/usr5/mfred/vbu_files/cen_scom_addresses.H.dphy23 Mark Fredrickson + CONST_UINT64_T( DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_0_0x800000070301143F, ULL(0x800000070301143F) ); CONST_UINT64_T( DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_0_0x800100070301143F, ULL(0x800100070301143F) ); -CONST_UINT64_T( DPHY23_DDRPHY_DP18_SYSCLK_PR_P0_0_0x800000070301183F, ULL(0x800000070301183F) ); -CONST_UINT64_T( DPHY23_DDRPHY_DP18_SYSCLK_PR_P1_0_0x800100070301183F, ULL(0x800100070301183F) ); CONST_UINT64_T( DPHY01_DDRPHY_DP18_PLL_CONFIG0_P0_0_0x800000760301143F, ULL(0x800000760301143F) ); CONST_UINT64_T( DPHY01_DDRPHY_DP18_PLL_CONFIG0_P1_0_0x800100760301143F, ULL(0x800100760301143F) ); -CONST_UINT64_T( DPHY23_DDRPHY_DP18_PLL_CONFIG0_P0_0_0x800000760301183F, ULL(0x800000760301183F) ); -CONST_UINT64_T( DPHY23_DDRPHY_DP18_PLL_CONFIG0_P1_0_0x800100760301183F, ULL(0x800100760301183F) ); CONST_UINT64_T( DPHY01_DDRPHY_DP18_PLL_CONFIG1_P0_0_0x800000770301143F, ULL(0x800000770301143F) ); CONST_UINT64_T( DPHY01_DDRPHY_DP18_PLL_CONFIG1_P1_0_0x800100770301143F, ULL(0x800100770301143F) ); -CONST_UINT64_T( DPHY23_DDRPHY_DP18_PLL_CONFIG1_P0_0_0x800000770301183F, ULL(0x800000770301183F) ); -CONST_UINT64_T( DPHY23_DDRPHY_DP18_PLL_CONFIG1_P1_0_0x800100770301183F, ULL(0x800100770301183F) ); CONST_UINT64_T( DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_1_0x800004070301143F, ULL(0x800004070301143F) ); CONST_UINT64_T( DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_1_0x800104070301143F, ULL(0x800104070301143F) ); -CONST_UINT64_T( DPHY23_DDRPHY_DP18_SYSCLK_PR_P0_1_0x800004070301183F, ULL(0x800004070301183F) ); -CONST_UINT64_T( DPHY23_DDRPHY_DP18_SYSCLK_PR_P1_1_0x800104070301183F, ULL(0x800104070301183F) ); CONST_UINT64_T( DPHY01_DDRPHY_DP18_PLL_CONFIG0_P0_1_0x800004760301143F, ULL(0x800004760301143F) ); CONST_UINT64_T( DPHY01_DDRPHY_DP18_PLL_CONFIG0_P1_1_0x800104760301143F, ULL(0x800104760301143F) ); -CONST_UINT64_T( DPHY23_DDRPHY_DP18_PLL_CONFIG0_P0_1_0x800004760301183F, ULL(0x800004760301183F) ); -CONST_UINT64_T( DPHY23_DDRPHY_DP18_PLL_CONFIG0_P1_1_0x800104760301183F, ULL(0x800104760301183F) ); CONST_UINT64_T( DPHY01_DDRPHY_DP18_PLL_CONFIG1_P0_1_0x800004770301143F, ULL(0x800004770301143F) ); CONST_UINT64_T( DPHY01_DDRPHY_DP18_PLL_CONFIG1_P1_1_0x800104770301143F, ULL(0x800104770301143F) ); -CONST_UINT64_T( DPHY23_DDRPHY_DP18_PLL_CONFIG1_P0_1_0x800004770301183F, ULL(0x800004770301183F) ); -CONST_UINT64_T( DPHY23_DDRPHY_DP18_PLL_CONFIG1_P1_1_0x800104770301183F, ULL(0x800104770301183F) ); CONST_UINT64_T( DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_2_0x800008070301143F, ULL(0x800008070301143F) ); CONST_UINT64_T( DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_2_0x800108070301143F, ULL(0x800108070301143F) ); -CONST_UINT64_T( DPHY23_DDRPHY_DP18_SYSCLK_PR_P0_2_0x800008070301183F, ULL(0x800008070301183F) ); -CONST_UINT64_T( DPHY23_DDRPHY_DP18_SYSCLK_PR_P1_2_0x800108070301183F, ULL(0x800108070301183F) ); CONST_UINT64_T( DPHY01_DDRPHY_DP18_PLL_CONFIG0_P0_2_0x800008760301143F, ULL(0x800008760301143F) ); CONST_UINT64_T( DPHY01_DDRPHY_DP18_PLL_CONFIG0_P1_2_0x800108760301143F, ULL(0x800108760301143F) ); -CONST_UINT64_T( DPHY23_DDRPHY_DP18_PLL_CONFIG0_P0_2_0x800008760301183F, ULL(0x800008760301183F) ); -CONST_UINT64_T( DPHY23_DDRPHY_DP18_PLL_CONFIG0_P1_2_0x800108760301183F, ULL(0x800108760301183F) ); CONST_UINT64_T( DPHY01_DDRPHY_DP18_PLL_CONFIG1_P0_2_0x800008770301143F, ULL(0x800008770301143F) ); CONST_UINT64_T( DPHY01_DDRPHY_DP18_PLL_CONFIG1_P1_2_0x800108770301143F, ULL(0x800108770301143F) ); -CONST_UINT64_T( DPHY23_DDRPHY_DP18_PLL_CONFIG1_P0_2_0x800008770301183F, ULL(0x800008770301183F) ); -CONST_UINT64_T( DPHY23_DDRPHY_DP18_PLL_CONFIG1_P1_2_0x800108770301183F, ULL(0x800108770301183F) ); CONST_UINT64_T( DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_3_0x80000C070301143F, ULL(0x80000C070301143F) ); CONST_UINT64_T( DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_3_0x80010C070301143F, ULL(0x80010C070301143F) ); -CONST_UINT64_T( DPHY23_DDRPHY_DP18_SYSCLK_PR_P0_3_0x80000C070301183F, ULL(0x80000C070301183F) ); -CONST_UINT64_T( DPHY23_DDRPHY_DP18_SYSCLK_PR_P1_3_0x80010C070301183F, ULL(0x80010C070301183F) ); CONST_UINT64_T( DPHY01_DDRPHY_DP18_PLL_CONFIG0_P0_3_0x80000C760301143F, ULL(0x80000C760301143F) ); CONST_UINT64_T( DPHY01_DDRPHY_DP18_PLL_CONFIG0_P1_3_0x80010C760301143F, ULL(0x80010C760301143F) ); -CONST_UINT64_T( DPHY23_DDRPHY_DP18_PLL_CONFIG0_P0_3_0x80000C760301183F, ULL(0x80000C760301183F) ); -CONST_UINT64_T( DPHY23_DDRPHY_DP18_PLL_CONFIG0_P1_3_0x80010C760301183F, ULL(0x80010C760301183F) ); CONST_UINT64_T( DPHY01_DDRPHY_DP18_PLL_CONFIG1_P0_3_0x80000C770301143F, ULL(0x80000C770301143F) ); CONST_UINT64_T( DPHY01_DDRPHY_DP18_PLL_CONFIG1_P1_3_0x80010C770301143F, ULL(0x80010C770301143F) ); -CONST_UINT64_T( DPHY23_DDRPHY_DP18_PLL_CONFIG1_P0_3_0x80000C770301183F, ULL(0x80000C770301183F) ); -CONST_UINT64_T( DPHY23_DDRPHY_DP18_PLL_CONFIG1_P1_3_0x80010C770301183F, ULL(0x80010C770301183F) ); CONST_UINT64_T( DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_4_0x800010070301143F, ULL(0x800010070301143F) ); CONST_UINT64_T( DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_4_0x800110070301143F, ULL(0x800110070301143F) ); -CONST_UINT64_T( DPHY23_DDRPHY_DP18_SYSCLK_PR_P0_4_0x800010070301183F, ULL(0x800010070301183F) ); -CONST_UINT64_T( DPHY23_DDRPHY_DP18_SYSCLK_PR_P1_4_0x800110070301183F, ULL(0x800110070301183F) ); CONST_UINT64_T( DPHY01_DDRPHY_DP18_PLL_CONFIG0_P0_4_0x800010760301143F, ULL(0x800010760301143F) ); CONST_UINT64_T( DPHY01_DDRPHY_DP18_PLL_CONFIG0_P1_4_0x800110760301143F, ULL(0x800110760301143F) ); -CONST_UINT64_T( DPHY23_DDRPHY_DP18_PLL_CONFIG0_P0_4_0x800010760301183F, ULL(0x800010760301183F) ); -CONST_UINT64_T( DPHY23_DDRPHY_DP18_PLL_CONFIG0_P1_4_0x800110760301183F, ULL(0x800110760301183F) ); CONST_UINT64_T( DPHY01_DDRPHY_DP18_PLL_CONFIG1_P0_4_0x800010770301143F, ULL(0x800010770301143F) ); CONST_UINT64_T( DPHY01_DDRPHY_DP18_PLL_CONFIG1_P1_4_0x800110770301143F, ULL(0x800110770301143F) ); -CONST_UINT64_T( DPHY23_DDRPHY_DP18_PLL_CONFIG1_P0_4_0x800010770301183F, ULL(0x800010770301183F) ); -CONST_UINT64_T( DPHY23_DDRPHY_DP18_PLL_CONFIG1_P1_4_0x800110770301183F, ULL(0x800110770301183F) ); CONST_UINT64_T( DPHY01_DDRPHY_ADR_PLL_VREG_CONFIG_0_P0_ADR32S0_0x800080300301143F, ULL(0x800080300301143F) ); CONST_UINT64_T( DPHY01_DDRPHY_ADR_PLL_VREG_CONFIG_0_P1_ADR32S0_0x800180300301143F, ULL(0x800180300301143F) ); -CONST_UINT64_T( DPHY23_DDRPHY_ADR_PLL_VREG_CONFIG_0_P0_ADR32S0_0x800080300301183F, ULL(0x800080300301183F) ); -CONST_UINT64_T( DPHY23_DDRPHY_ADR_PLL_VREG_CONFIG_0_P1_ADR32S0_0x800180300301183F, ULL(0x800180300301183F) ); CONST_UINT64_T( DPHY01_DDRPHY_ADR_PLL_VREG_CONFIG_1_P0_ADR32S0_0x800080310301143F, ULL(0x800080310301143F) ); CONST_UINT64_T( DPHY01_DDRPHY_ADR_PLL_VREG_CONFIG_1_P1_ADR32S0_0x800180310301143F, ULL(0x800180310301143F) ); -CONST_UINT64_T( DPHY23_DDRPHY_ADR_PLL_VREG_CONFIG_1_P0_ADR32S0_0x800080310301183F, ULL(0x800080310301183F) ); -CONST_UINT64_T( DPHY23_DDRPHY_ADR_PLL_VREG_CONFIG_1_P1_ADR32S0_0x800180310301183F, ULL(0x800180310301183F) ); CONST_UINT64_T( DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_0x800080320301143F, ULL(0x800080320301143F) ); CONST_UINT64_T( DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S0_0x800180320301143F, ULL(0x800180320301143F) ); -CONST_UINT64_T( DPHY23_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_0x800080320301183F, ULL(0x800080320301183F) ); -CONST_UINT64_T( DPHY23_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S0_0x800180320301183F, ULL(0x800180320301183F) ); CONST_UINT64_T( DPHY01_DDRPHY_ADR_PLL_VREG_CONFIG_0_P0_ADR32S1_0x800084300301143F, ULL(0x800084300301143F) ); CONST_UINT64_T( DPHY01_DDRPHY_ADR_PLL_VREG_CONFIG_0_P1_ADR32S1_0x800184300301143F, ULL(0x800184300301143F) ); -CONST_UINT64_T( DPHY23_DDRPHY_ADR_PLL_VREG_CONFIG_0_P0_ADR32S1_0x800084300301183F, ULL(0x800084300301183F) ); -CONST_UINT64_T( DPHY23_DDRPHY_ADR_PLL_VREG_CONFIG_0_P1_ADR32S1_0x800184300301183F, ULL(0x800184300301183F) ); CONST_UINT64_T( DPHY01_DDRPHY_ADR_PLL_VREG_CONFIG_1_P0_ADR32S1_0x800084310301143F, ULL(0x800084310301143F) ); CONST_UINT64_T( DPHY01_DDRPHY_ADR_PLL_VREG_CONFIG_1_P1_ADR32S1_0x800184310301143F, ULL(0x800184310301143F) ); -CONST_UINT64_T( DPHY23_DDRPHY_ADR_PLL_VREG_CONFIG_1_P0_ADR32S1_0x800084310301183F, ULL(0x800084310301183F) ); -CONST_UINT64_T( DPHY23_DDRPHY_ADR_PLL_VREG_CONFIG_1_P1_ADR32S1_0x800184310301183F, ULL(0x800184310301183F) ); CONST_UINT64_T( DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_0x800084320301143F, ULL(0x800084320301143F) ); CONST_UINT64_T( DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1_0x800184320301143F, ULL(0x800184320301143F) ); -CONST_UINT64_T( DPHY23_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_0x800084320301183F, ULL(0x800084320301183F) ); -CONST_UINT64_T( DPHY23_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1_0x800184320301183F, ULL(0x800184320301183F) ); CONST_UINT64_T( DPHY01_DDRPHY_PC_DP18_PLL_LOCK_STATUS_P0_0x8000C0000301143F, ULL(0x8000C0000301143F) ); CONST_UINT64_T( DPHY01_DDRPHY_PC_DP18_PLL_LOCK_STATUS_P1_0x8001C0000301143F, ULL(0x8001C0000301143F) ); -CONST_UINT64_T( DPHY23_DDRPHY_PC_DP18_PLL_LOCK_STATUS_P0_0x8000C0000301183F, ULL(0x8000C0000301183F) ); -CONST_UINT64_T( DPHY23_DDRPHY_PC_DP18_PLL_LOCK_STATUS_P1_0x8001C0000301183F, ULL(0x8001C0000301183F) ); CONST_UINT64_T( DPHY01_DDRPHY_PC_AD32S_PLL_LOCK_STATUS_P0_0x8000C0010301143F, ULL(0x8000C0010301143F) ); CONST_UINT64_T( DPHY01_DDRPHY_PC_AD32S_PLL_LOCK_STATUS_P1_0x8001C0010301143F, ULL(0x8001C0010301143F) ); -CONST_UINT64_T( DPHY23_DDRPHY_PC_AD32S_PLL_LOCK_STATUS_P0_0x8000C0010301183F, ULL(0x8000C0010301183F) ); -CONST_UINT64_T( DPHY23_DDRPHY_PC_AD32S_PLL_LOCK_STATUS_P1_0x8001C0010301183F, ULL(0x8001C0010301183F) ); CONST_UINT64_T( DPHY01_DDRPHY_PC_CONFIG0_P0_0x8000C00C0301143F, ULL(0x8000C00C0301143F) ); CONST_UINT64_T( DPHY01_DDRPHY_PC_CONFIG0_P1_0x8001C00C0301143F, ULL(0x8001C00C0301143F) ); -CONST_UINT64_T( DPHY23_DDRPHY_PC_CONFIG0_P0_0x8000C00C0301183F, ULL(0x8000C00C0301183F) ); -CONST_UINT64_T( DPHY23_DDRPHY_PC_CONFIG0_P1_0x8001C00C0301183F, ULL(0x8001C00C0301183F) ); CONST_UINT64_T( DPHY01_DDRPHY_PC_RESETS_P0_0x8000C00E0301143F, ULL(0x8000C00E0301143F) ); CONST_UINT64_T( DPHY01_DDRPHY_PC_RESETS_P1_0x8001C00E0301143F, ULL(0x8001C00E0301143F) ); -CONST_UINT64_T( DPHY23_DDRPHY_PC_RESETS_P0_0x8000C00E0301183F, ULL(0x8000C00E0301183F) ); -CONST_UINT64_T( DPHY23_DDRPHY_PC_RESETS_P1_0x8001C00E0301183F, ULL(0x8001C00E0301183F) ); CONST_UINT64_T( DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_0x8000C0140301143F, ULL(0x8000C0140301143F) ); CONST_UINT64_T( DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P1_0x8001C0140301143F, ULL(0x8001C0140301143F) ); -CONST_UINT64_T( DPHY23_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_0x8000C0140301183F, ULL(0x8000C0140301183F) ); -CONST_UINT64_T( DPHY23_DDRPHY_PC_IO_PVT_FET_CONTROL_P1_0x8001C0140301183F, ULL(0x8001C0140301183F) ); //------------------------------------------------------------------------------ // CALIBRATION SCOM ADDRESSES (DPHY REGISTERS) //------------------------------------------------------------------------------ CONST_UINT64_T( DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P0_0x8000C0160301143F, ULL(0x8000C0160301143F) ); CONST_UINT64_T( DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P1_0x8001C0160301143F, ULL(0x8001C0160301143F) ); -CONST_UINT64_T( DPHY23_DDRPHY_PC_INIT_CAL_CONFIG0_P0_0x8000C0160301183F, ULL(0x8000C0160301183F) ); -CONST_UINT64_T( DPHY23_DDRPHY_PC_INIT_CAL_CONFIG0_P1_0x8001C0160301183F, ULL(0x8000C0160301183F) ); -CONST_UINT64_T( DPHY01_DDRPHY_PC_INIT_CAL_CONFIG1_P0_0x8000C0170301143F, ULL(0x8000C0160301143F) ); -CONST_UINT64_T( DPHY01_DDRPHY_PC_INIT_CAL_CONFIG1_P1_0x8001C0170301143F, ULL(0x8001C0160301143F) ); -CONST_UINT64_T( DPHY23_DDRPHY_PC_INIT_CAL_CONFIG1_P0_0x8000C0170301183F, ULL(0x8000C0160301183F) ); -CONST_UINT64_T( DPHY23_DDRPHY_PC_INIT_CAL_CONFIG1_P1_0x8001C0170301183F, ULL(0x8000C0160301183F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_INIT_CAL_CONFIG1_P0_0x8000C0170301143F, ULL(0x8000C0170301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_PC_INIT_CAL_CONFIG1_P1_0x8001C0170301143F, ULL(0x8001C0170301143F) ); CONST_UINT64_T( DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P0_0x8000C0190301143F, ULL(0x8000C0190301143F) ); CONST_UINT64_T( DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P1_0x8001C0190301143F, ULL(0x8001C0190301143F) ); -CONST_UINT64_T( DPHY23_DDRPHY_PC_INIT_CAL_STATUS_P0_0x8000C0190301183F, ULL(0x8000C0190301183F) ); -CONST_UINT64_T( DPHY23_DDRPHY_PC_INIT_CAL_STATUS_P1_0x8001C0190301183F, ULL(0x8001C0190301183F) ); CONST_UINT64_T( DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P0_0x8000C0180301143F, ULL(0x8000C0180301143F) ); CONST_UINT64_T( DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P1_0x8001C0180301143F, ULL(0x8001C0180301143F) ); -CONST_UINT64_T( DPHY23_DDRPHY_PC_INIT_CAL_ERROR_P0_0x8000C0180301183F, ULL(0x8000C0180301183F) ); -CONST_UINT64_T( DPHY23_DDRPHY_PC_INIT_CAL_ERROR_P1_0x8001C0180301183F, ULL(0x8001C0180301183F) ); CONST_UINT64_T( DPHY01_DDRPHY_PC_INIT_CAL_MASK_P0_0x8000C01A0301143F, ULL(0x8000C01A0301143F) ); CONST_UINT64_T( DPHY01_DDRPHY_PC_INIT_CAL_MASK_P1_0x8001C01A0301143F, ULL(0x8001C01A0301143F) ); -CONST_UINT64_T( DPHY23_DDRPHY_PC_INIT_CAL_MASK_P0_0x8000C01A0301183F, ULL(0x8000C01A0301183F) ); -CONST_UINT64_T( DPHY23_DDRPHY_PC_INIT_CAL_MASK_P1_0x8001C01A0301183F, ULL(0x8001C01A0301183F) ); CONST_UINT64_T( DPHY01_DDRPHY_PC_PER_CAL_CONFIG_P0_0x8000C00B0301143F, ULL(0x8000C00B0301143F) ); CONST_UINT64_T( DPHY01_DDRPHY_PC_PER_CAL_CONFIG_P1_0x8001C00B0301143F, ULL(0x8001C00B0301143F) ); -CONST_UINT64_T( DPHY23_DDRPHY_PC_PER_CAL_CONFIG_P0_0x8000C00B0301183F, ULL(0x8000C00B0301183F) ); -CONST_UINT64_T( DPHY23_DDRPHY_PC_PER_CAL_CONFIG_P1_0x8001C00B0301183F, ULL(0x8001C00B0301183F) ); CONST_UINT64_T( DPHY01_DDRPHY_PC_PER_ZCAL_CONFIG_P0_0x8000C00F0301143F, ULL(0x8000C00F0301143F) ); CONST_UINT64_T( DPHY01_DDRPHY_PC_PER_ZCAL_CONFIG_P1_0x8001C00F0301143F, ULL(0x8001C00F0301143F) ); -CONST_UINT64_T( DPHY23_DDRPHY_PC_PER_ZCAL_CONFIG_P0_0x8000C00F0301183F, ULL(0x8000C00F0301183F) ); -CONST_UINT64_T( DPHY23_DDRPHY_PC_PER_ZCAL_CONFIG_P1_0x8001C00F0301183F, ULL(0x8001C00F0301183F) ); + +//------------------------------------------------------------------------------ +// MBA Fault Isolation Register +//------------------------------------------------------------------------------ +CONST_UINT64_T( MBA01_MBAFIRQ_0x03010600 , ULL(0x03010600) ); + +//------------------------------------------------------------------------------ +// MBA Maintenance Command Type Register +//------------------------------------------------------------------------------ +CONST_UINT64_T( MBA01_MBMCTQ_0x0301060A , ULL(0x0301060A) ); + +//------------------------------------------------------------------------------ +// MBA Maintenance Command Control Register +//------------------------------------------------------------------------------ +CONST_UINT64_T( MBA01_MBMCCQ_0x0301060B , ULL(0x0301060B) ); + +//------------------------------------------------------------------------------ +// MBA Maintenance Command Status Register +//------------------------------------------------------------------------------ +CONST_UINT64_T( MBA01_MBMSRQ_0x0301060C , ULL(0x0301060C) ); + +//------------------------------------------------------------------------------ +// MBA Maintenance Command Address Register +//------------------------------------------------------------------------------ +CONST_UINT64_T( MBA01_MBMACAQ_0x0301060D , ULL(0x0301060D) ); + +//------------------------------------------------------------------------------ +// MBA Maintenance Command End Address Register +//------------------------------------------------------------------------------ +CONST_UINT64_T( MBA01_MBMEAQ_0x0301060E , ULL(0x0301060E) ); + +//------------------------------------------------------------------------------ +// MBA Memory Scrub/Read Control Register +//------------------------------------------------------------------------------ +CONST_UINT64_T( MBA01_MBASCTLQ_0x0301060F , ULL(0x0301060F) ); + +//------------------------------------------------------------------------------ +// MBA Error Control Register +//------------------------------------------------------------------------------ +CONST_UINT64_T( MBA01_MBECTLQ_0x03010610 , ULL(0x03010610) ); + +//------------------------------------------------------------------------------ +// MBA Special Attention Register +//------------------------------------------------------------------------------ +CONST_UINT64_T( MBA01_MBSPAQ_0x03010611 , ULL(0x03010611) ); + +//------------------------------------------------------------------------------ +// MBA Maint Read Buffers corresponding to ports 0/1 +//------------------------------------------------------------------------------ + +CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF0_DATA0_0x03010655 , ULL(0x03010655) ); +CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF0_DATA1_0x03010656 , ULL(0x03010656) ); +CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF0_DATA2_0x03010657 , ULL(0x03010657) ); +CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF0_DATA3_0x03010658 , ULL(0x03010658) ); + +CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF1_DATA0_0x03010665 , ULL(0x03010665) ); +CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF1_DATA1_0x03010666 , ULL(0x03010666) ); +CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF1_DATA2_0x03010667 , ULL(0x03010667) ); +CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF1_DATA3_0x03010668 , ULL(0x03010668) ); + +CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF2_DATA0_0x03010675 , ULL(0x03010675) ); +CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF2_DATA1_0x03010676 , ULL(0x03010676) ); +CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF2_DATA2_0x03010677 , ULL(0x03010677) ); +CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF2_DATA3_0x03010678 , ULL(0x03010678) ); + +CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF3_DATA0_0x03010685 , ULL(0x03010685) ); +CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF3_DATA1_0x03010686 , ULL(0x03010686) ); +CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF3_DATA2_0x03010687 , ULL(0x03010687) ); +CONST_UINT64_T( MAINT0_MBA_MAINT_BUFF3_DATA3_0x03010688 , ULL(0x03010688) ); + +//------------------------------------------------------------------------------ +// MBA Write Bit Steer Control Registers +//------------------------------------------------------------------------------ +CONST_UINT64_T( MBA01_MBABS0_0x03010440 , ULL(0x03010440) ); +CONST_UINT64_T( MBA01_MBABS1_0x03010441 , ULL(0x03010441) ); +CONST_UINT64_T( MBA01_MBABS2_0x03010442 , ULL(0x03010442) ); +CONST_UINT64_T( MBA01_MBABS3_0x03010443 , ULL(0x03010443) ); +CONST_UINT64_T( MBA01_MBABS4_0x03010444 , ULL(0x03010444) ); +CONST_UINT64_T( MBA01_MBABS5_0x03010445 , ULL(0x03010445) ); +CONST_UINT64_T( MBA01_MBABS6_0x03010446 , ULL(0x03010446) ); +CONST_UINT64_T( MBA01_MBABS7_0x03010447 , ULL(0x03010447) ); + +//------------------------------------------------------------------------------ +// MBA CAL FIR Register +//------------------------------------------------------------------------------ +CONST_UINT64_T( MBA01_MBACALFIR_0x03010400 , ULL(0x03010400) ); + +//------------------------------------------------------------------------------ +// MBA WRD Mode Register +//------------------------------------------------------------------------------ +CONST_UINT64_T( MBA01_MBA_WRD_MODE_0x03010429 , ULL(0x03010429) ); + + + + + +//------------------------------------------------------------------------------ +// Address Translate Control Registers +//------------------------------------------------------------------------------ +CONST_UINT64_T( MBAXCR01Q_0x0201140B , ULL(0x0201140B) ); +CONST_UINT64_T( MBAXCR23Q_0x0201140C , ULL(0x0201140C) ); + +//------------------------------------------------------------------------------ +// MBS ECC Decoder FIR Registers +//------------------------------------------------------------------------------ +CONST_UINT64_T( MBS_ECC0_MBECCFIR_0x02011440 , ULL(0x02011440) ); +CONST_UINT64_T( MBS_ECC1_MBECCFIR_0x02011480 , ULL(0x02011480) ); + +//------------------------------------------------------------------------------ +// MBS Memory ECC Mark Store Registers +//------------------------------------------------------------------------------ +CONST_UINT64_T( MBS_ECC0_MBMS0_0x0201144B , ULL(0x0201144B) ); +CONST_UINT64_T( MBS_ECC0_MBMS1_0x0201144C , ULL(0x0201144C) ); +CONST_UINT64_T( MBS_ECC0_MBMS2_0x0201144D , ULL(0x0201144D) ); +CONST_UINT64_T( MBS_ECC0_MBMS3_0x0201144E , ULL(0x0201144E) ); +CONST_UINT64_T( MBS_ECC0_MBMS4_0x0201144F , ULL(0x0201144F) ); +CONST_UINT64_T( MBS_ECC0_MBMS5_0x02011450 , ULL(0x02011450) ); +CONST_UINT64_T( MBS_ECC0_MBMS6_0x02011451 , ULL(0x02011451) ); +CONST_UINT64_T( MBS_ECC0_MBMS7_0x02011452 , ULL(0x02011452) ); + +CONST_UINT64_T( MBS_ECC1_MBMS0_0x0201148B , ULL(0x0201148B) ); +CONST_UINT64_T( MBS_ECC1_MBMS1_0x0201148C , ULL(0x0201148C) ); +CONST_UINT64_T( MBS_ECC1_MBMS2_0x0201148D , ULL(0x0201148D) ); +CONST_UINT64_T( MBS_ECC1_MBMS3_0x0201148E , ULL(0x0201148E) ); +CONST_UINT64_T( MBS_ECC1_MBMS4_0x0201148F , ULL(0x0201148F) ); +CONST_UINT64_T( MBS_ECC1_MBMS5_0x02011490 , ULL(0x02011490) ); +CONST_UINT64_T( MBS_ECC1_MBMS6_0x02011491 , ULL(0x02011491) ); +CONST_UINT64_T( MBS_ECC1_MBMS7_0x02011492 , ULL(0x02011492) ); + +//------------------------------------------------------------------------------ +// MBS Read Bit Steer Control Registers +//------------------------------------------------------------------------------ +CONST_UINT64_T( MBS_ECC0_MBSBS0_0x0201145E , ULL(0x0201145E) ); +CONST_UINT64_T( MBS_ECC0_MBSBS1_0x0201145F , ULL(0x0201145F) ); +CONST_UINT64_T( MBS_ECC0_MBSBS2_0x02011460 , ULL(0x02011460) ); +CONST_UINT64_T( MBS_ECC0_MBSBS3_0x02011461 , ULL(0x02011461) ); +CONST_UINT64_T( MBS_ECC0_MBSBS4_0x02011462 , ULL(0x02011462) ); +CONST_UINT64_T( MBS_ECC0_MBSBS5_0x02011463 , ULL(0x02011463) ); +CONST_UINT64_T( MBS_ECC0_MBSBS6_0x02011464 , ULL(0x02011464) ); +CONST_UINT64_T( MBS_ECC0_MBSBS7_0x02011465 , ULL(0x02011465) ); + +CONST_UINT64_T( MBS_ECC1_MBSBS0_0x0201149E , ULL(0x0201149E) ); +CONST_UINT64_T( MBS_ECC1_MBSBS1_0x0201149F , ULL(0x0201149F) ); +CONST_UINT64_T( MBS_ECC1_MBSBS2_0x020114A0 , ULL(0x020114A0) ); +CONST_UINT64_T( MBS_ECC1_MBSBS3_0x020114A1 , ULL(0x020114A1) ); +CONST_UINT64_T( MBS_ECC1_MBSBS4_0x020114A2 , ULL(0x020114A2) ); +CONST_UINT64_T( MBS_ECC1_MBSBS5_0x020114A3 , ULL(0x020114A3) ); +CONST_UINT64_T( MBS_ECC1_MBSBS6_0x020114A4 , ULL(0x020114A4) ); +CONST_UINT64_T( MBS_ECC1_MBSBS7_0x020114A5 , ULL(0x020114A5) ); + + +//------------------------------------------------------------------------------ +// MBS Maint Write Buffers corresponding to ports 0/1 +//------------------------------------------------------------------------------ + +// Maint Write Buffer 0 +CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF0_DATA0_0x0201160A , ULL(0x0201160A) ); +CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF0_DATA1_0x0201160B , ULL(0x0201160B) ); +CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF0_DATA2_0x0201160C , ULL(0x0201160C) ); +CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF0_DATA3_0x0201160D , ULL(0x0201160D) ); + +CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF0_DATA_ECC0_0x02011612 , ULL(0x02011612) ); +CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF0_DATA_ECC1_0x02011613 , ULL(0x02011613) ); +CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF0_DATA_ECC2_0x02011614 , ULL(0x02011614) ); +CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF0_DATA_ECC3_0x02011615 , ULL(0x02011615) ); + +// Maint Write Buffer 1 +CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF1_DATA0_0x0201161A , ULL(0x0201161A) ); +CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF1_DATA1_0x0201161B , ULL(0x0201161B) ); +CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF1_DATA2_0x0201161C , ULL(0x0201161C) ); +CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF1_DATA3_0x0201161D , ULL(0x0201161D) ); + +CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF1_DATA_ECC0_0x02011622 , ULL(0x02011622) ); +CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF1_DATA_ECC1_0x02011623 , ULL(0x02011623) ); +CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF1_DATA_ECC2_0x02011624 , ULL(0x02011624) ); +CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF1_DATA_ECC3_0x02011625 , ULL(0x02011625) ); + +// Maint Write Buffer 2 +CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF2_DATA0_0x0201162A , ULL(0x0201162A) ); +CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF2_DATA1_0x0201162B , ULL(0x0201162B) ); +CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF2_DATA2_0x0201162C , ULL(0x0201162C) ); +CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF2_DATA3_0x0201162D , ULL(0x0201162D) ); + +CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF2_DATA_ECC0_0x02011632 , ULL(0x02011632) ); +CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF2_DATA_ECC1_0x02011633 , ULL(0x02011633) ); +CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF2_DATA_ECC2_0x02011634 , ULL(0x02011634) ); +CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF2_DATA_ECC3_0x02011635 , ULL(0x02011635) ); + +// Maint Write Buffer 3 +CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF3_DATA0_0x0201163A , ULL(0x0201163A) ); +CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF3_DATA1_0x0201163B , ULL(0x0201163B) ); +CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF3_DATA2_0x0201163C , ULL(0x0201163C) ); +CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF3_DATA3_0x0201163D , ULL(0x0201163D) ); + +CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF3_DATA_ECC0_0x02011642 , ULL(0x02011642) ); +CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF3_DATA_ECC1_0x02011643 , ULL(0x02011643) ); +CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF3_DATA_ECC2_0x02011644 , ULL(0x02011644) ); +CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF3_DATA_ECC3_0x02011645 , ULL(0x02011645) ); + +// Maint Write Buffer 65th Byte +CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF_65TH_BYTE_64B_ECC0_0x0201164A , ULL(0x0201164A) ); +CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF_65TH_BYTE_64B_ECC1_0x0201164B , ULL(0x0201164B) ); +CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF_65TH_BYTE_64B_ECC2_0x0201164C , ULL(0x0201164C) ); +CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF_65TH_BYTE_64B_ECC3_0x0201164D , ULL(0x0201164D) ); + + +//------------------------------------------------------------------------------ +// MBS Maint Write Buffers corresponding to ports 2/3 +//------------------------------------------------------------------------------ + +// Maint Write Buffer 0 +CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF0_DATA0_0x0201170A , ULL(0x0201170A) ); +CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF0_DATA1_0x0201170B , ULL(0x0201170B) ); +CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF0_DATA2_0x0201170C , ULL(0x0201170C) ); +CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF0_DATA3_0x0201170D , ULL(0x0201170D) ); + +CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF0_DATA_ECC0_0x02011712 , ULL(0x02011712) ); +CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF0_DATA_ECC1_0x02011713 , ULL(0x02011713) ); +CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF0_DATA_ECC2_0x02011714 , ULL(0x02011714) ); +CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF0_DATA_ECC3_0x02011715 , ULL(0x02011715) ); + +// Maint Write Buffer 1 +CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF1_DATA0_0x0201171A , ULL(0x0201171A) ); +CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF1_DATA1_0x0201171B , ULL(0x0201171B) ); +CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF1_DATA2_0x0201171C , ULL(0x0201171C) ); +CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF1_DATA3_0x0201171D , ULL(0x0201171D) ); + +CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF1_DATA_ECC0_0x02011722 , ULL(0x02011722) ); +CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF1_DATA_ECC1_0x02011723 , ULL(0x02011723) ); +CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF1_DATA_ECC2_0x02011724 , ULL(0x02011724) ); +CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF1_DATA_ECC3_0x02011725 , ULL(0x02011725) ); + +// Maint Write Buffer 2 +CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF2_DATA0_0x0201172A , ULL(0x0201172A) ); +CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF2_DATA1_0x0201172B , ULL(0x0201172B) ); +CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF2_DATA2_0x0201172C , ULL(0x0201172C) ); +CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF2_DATA3_0x0201172D , ULL(0x0201172D) ); + +CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF2_DATA_ECC0_0x02011732 , ULL(0x02011732) ); +CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF2_DATA_ECC1_0x02011733 , ULL(0x02011733) ); +CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF2_DATA_ECC2_0x02011734 , ULL(0x02011734) ); +CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF2_DATA_ECC3_0x02011735 , ULL(0x02011735) ); + +// Maint Write Buffer 3 +CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF3_DATA0_0x0201173A , ULL(0x0201173A) ); +CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF3_DATA1_0x0201173B , ULL(0x0201173B) ); +CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF3_DATA2_0x0201173C , ULL(0x0201173C) ); +CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF3_DATA3_0x0201173D , ULL(0x0201173D) ); + +CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF3_DATA_ECC0_0x02011742 , ULL(0x02011742) ); +CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF3_DATA_ECC1_0x02011743 , ULL(0x02011743) ); +CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF3_DATA_ECC2_0x02011744 , ULL(0x02011744) ); +CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF3_DATA_ECC3_0x02011745 , ULL(0x02011745) ); + +// Maint Write Buffer 65th Byte +CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF_65TH_BYTE_64B_ECC0_0x0201174A , ULL(0x0201174A) ); +CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF_65TH_BYTE_64B_ECC1_0x0201174B , ULL(0x0201174B) ); +CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF_65TH_BYTE_64B_ECC2_0x0201174C , ULL(0x0201174C) ); +CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF_65TH_BYTE_64B_ECC3_0x0201174D , ULL(0x0201174D) ); + +//------------------------------------------------------------------------------ +// MBS Memory ECC Control Registers +//------------------------------------------------------------------------------ +CONST_UINT64_T( MBS_ECC0_MBSECCQ_0x0201144A , ULL(0x0201144A) ); +CONST_UINT64_T( MBS_ECC1_MBSECCQ_0x0201148A , ULL(0x0201148A) ); + +//------------------------------------------------------------------------------ +// MBS Memory Scrub/Read Error Threshold Registers +//------------------------------------------------------------------------------ +CONST_UINT64_T( MBS01_MBSTRQ_0x02011655 , ULL(02011655) ); +CONST_UINT64_T( MBS23_MBSTRQ_0x02011755 , ULL(02011755) ); + /******************************************************************************/ @@ -396,6 +636,31 @@ This section is automatically updated by CVS when you check in this file. Be sure to create CVS comments when you commit so that they can be included here. $Log: cen_scom_addresses.H,v $ +Revision 1.22 2012/06/18 01:58:44 jmcgill +added trace related SCOM addresses + +Revision 1.21 2012/05/23 15:54:03 gollub + +Added regs needed for mss_maint_cmds. + +Revision 1.20 2012/05/17 21:55:05 jdsloat +Added MBA/MBS level PM, REF register addresses + +Revision 1.19 2012/04/25 22:28:06 gollub +Added MBS ECC regs + +Revision 1.18 2012/04/16 23:56:39 bcbrock +Corrected problems related to C/C++ and 32-bit/64-bit portability and Host +Boot after initial review by FW team. + +o Renamed fapi_sbe_common.h to fapi_sbe_common.H + +Revision 1.17 2012/03/30 19:59:23 mfred +removing dphy23 addresses completely. Should not be needed. + +Revision 1.16 2012/03/30 19:29:44 mfred +Fix some DPHY23 addresses and comment out all the DPHY23 addresses. Should not be needed. + Revision 1.15 2012/03/06 16:40:00 divyakum Added calibration status regs diff --git a/src/usr/hwpf/hwp/include/common_scom_addresses.H b/src/usr/hwpf/hwp/include/common_scom_addresses.H index f7ca02897..7edeb8da2 100755 --- a/src/usr/hwpf/hwp/include/common_scom_addresses.H +++ b/src/usr/hwpf/hwp/include/common_scom_addresses.H @@ -1,26 +1,27 @@ -// IBM_PROLOG_BEGIN_TAG -// This is an automatically generated prolog. -// -// $Source: src/usr/HWPs/common_scom_addresses.H $ -// -// IBM CONFIDENTIAL -// -// COPYRIGHT International Business Machines Corp. 2012 -// -// p1 -// -// Object Code Only (OCO) source materials -// Licensed Internal Code Source Materials -// IBM HostBoot Licensed Internal Code -// -// The source code for this program is not published or other- -// wise divested of its trade secrets, irrespective of what has -// been deposited with the U.S. Copyright Office. -// -// Origin: 30 -// -// IBM_PROLOG_END -// $Id: common_scom_addresses.H,v 1.1 2012/01/06 22:21:10 jmcgill Exp $ +/* IBM_PROLOG_BEGIN_TAG + * This is an automatically generated prolog. + * + * $Source: src/usr/hwpf/hwp/include/common_scom_addresses.H $ + * + * IBM CONFIDENTIAL + * + * COPYRIGHT International Business Machines Corp. 2012 + * + * p1 + * + * Object Code Only (OCO) source materials + * Licensed Internal Code Source Materials + * IBM HostBoot Licensed Internal Code + * + * The source code for this program is not published or other- + * wise divested of its trade secrets, irrespective of what has + * been deposited with the U.S. Copyright Office. + * + * Origin: 30 + * + * IBM_PROLOG_END_TAG + */ +// $Id: common_scom_addresses.H,v 1.18 2012/06/25 17:52:34 bcbrock Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/common_scom_addresses.H,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -95,7 +96,7 @@ // if the multicast bit is set // -#include "fapi_sbe_common.h" +#include "fapi_sbe_common.H" /******************************************************************************/ @@ -105,6 +106,7 @@ CONST_UINT64_T( STBY_CHIPLET_0x00000000 , ULL(0x00000000) ); CONST_UINT64_T( TP_CHIPLET_0x01000000 , ULL(0x01000000) ); CONST_UINT64_T( NEST_CHIPLET_0x02000000 , ULL(0x02000000) ); +CONST_UINT64_T( XBUS_CHIPLET_0x04000000 , ULL(0x04000000) ); /******************************************************************************/ @@ -128,10 +130,13 @@ CONST_UINT64_T( GENERIC_OPCG_CNTL0_0x00030002 , ULL(0x00030002) ); CONST_UINT64_T( GENERIC_OPCG_CNTL1_0x00030003 , ULL(0x00030003) ); CONST_UINT64_T( GENERIC_OPCG_CNTL2_0x00030004 , ULL(0x00030004) ); CONST_UINT64_T( GENERIC_OPCG_CNTL3_0x00030005 , ULL(0x00030005) ); +CONST_UINT64_T( GENERIC_CLK_SYNC_CONFIG_0x00030000 , ULL(0x00030000) ); CONST_UINT64_T( GENERIC_CLK_REGION_0x00030006 , ULL(0x00030006) ); CONST_UINT64_T( GENERIC_CLK_SCANSEL_0x00030007 , ULL(0x00030007) ); CONST_UINT64_T( GENERIC_CLK_STATUS_0x00030008 , ULL(0x00030008) ); CONST_UINT64_T( GENERIC_CLK_SCANDATA0_0x00038000 , ULL(0x00038000) ); +CONST_UINT64_T( GENERIC_CLK_SCAN_UPDATEDR_0x0003A000 , ULL(0x0003A000) ); +CONST_UINT64_T( GENERIC_CLK_SCAN_CAPTUREDR_0x0003C000 , ULL(0x0003C000) ); //------------------------------------------------------------------------------ // GENERIC FIR @@ -195,6 +200,7 @@ CONST_UINT32_T( CFAM_FSI_GP4_0x00001013 , ULL(0x00001013) ); CONST_UINT32_T( CFAM_FSI_GP5_0x00001014 , ULL(0x00001014) ); CONST_UINT32_T( CFAM_FSI_GP6_0x00001015 , ULL(0x00001015) ); CONST_UINT32_T( CFAM_FSI_GP7_0x00001016 , ULL(0x00001016) ); +CONST_UINT32_T( CFAM_FSI_GP8_0x00001017 , ULL(0x00001017) ); CONST_UINT32_T( CFAM_FSI_GP3_MIRROR_0x0000101B , ULL(0x0000101B) ); //------------------------------------------------------------------------------ @@ -202,6 +208,14 @@ CONST_UINT32_T( CFAM_FSI_GP3_MIRROR_0x0000101B , ULL(0x0000101B) ); //------------------------------------------------------------------------------ CONST_UINT64_T( OTPROM_0x00010000 , ULL(0x00010000) ); + +//------------------------------------------------------------------------------ +// PIBMEM +//------------------------------------------------------------------------------ + +CONST_UINT64_T( PIBMEM_REPAIR_0x00088007 , ULL(0x00088007) ); + + //------------------------------------------------------------------------------ // MFSI0 //------------------------------------------------------------------------------ @@ -230,10 +244,19 @@ CONST_UINT64_T( MBOX_FSIGP4_0x00050013 , ULL(0x00050013) ); CONST_UINT64_T( MBOX_FSIGP5_0x00050014 , ULL(0x00050014) ); CONST_UINT64_T( MBOX_FSIGP6_0x00050015 , ULL(0x00050015) ); CONST_UINT64_T( MBOX_FSIGP7_0x00050016 , ULL(0x00050016) ); +CONST_UINT64_T( MBOX_FSIGP8_0x00050017 , ULL(0x00050017) ); CONST_UINT64_T( MBOX_OSC_S1_0x00050019 , ULL(0x00050019) ); CONST_UINT64_T( MBOX_OSC_S2_0x0005001A , ULL(0x0005001A) ); CONST_UINT64_T( MBOX_GP3MIR_0x0005001B , ULL(0x0005001B) ); CONST_UINT64_T( MBOX_SBEVITAL_0x0005001C , ULL(0x0005001C) ); +CONST_UINT64_T( MBOX_SCRATCH_REG0_0x00050038 , ULL(0x00050038) ); +CONST_UINT64_T( MBOX_SCRATCH_REG1_0x00050039 , ULL(0x00050039) ); + +//------------------------------------------------------------------------------ +// TP ADDITIONAL REGISTER +//------------------------------------------------------------------------------ +CONST_UINT64_T( TP_PLL_LOCK_0x010F0019 , ULL(0x010F0019) ); + //------------------------------------------------------------------------------ // I2C MASTER (MEMS0) @@ -243,6 +266,8 @@ CONST_UINT64_T( I2CMS_MEMS0_RESET_0x000A0001 , ULL(0x000A0001) ); CONST_UINT64_T( I2CMS_MEMS0_STATUS_0x000A0002 , ULL(0x000A0002) ); CONST_UINT64_T( I2CMS_MEMS0_DATA_0x000A0003 , ULL(0x000A0003) ); CONST_UINT64_T( I2CMS_MEMS0_COMMAND_0x000A0005 , ULL(0x000A0005) ); +CONST_UINT64_T( I2CMS_MEMS0_MODE_0x000A0006 , ULL(0x000A0006) ); +CONST_UINT64_T( I2CMS_MEMS0_STATUS_0x000A000B , ULL(0x000A000B) ); //------------------------------------------------------------------------------ // PCB MASTER @@ -271,6 +296,12 @@ CONST_UINT64_T( TP_GP4_OR_0x01000007 , ULL(0x01000007) ); CONST_UINT64_T( TP_SCOM_0x01010000 , ULL(0x01010000) ); //------------------------------------------------------------------------------ +// TP TRACE +//------------------------------------------------------------------------------ +CONST_UINT64_T( TP_TRACE_DATA_HI_0x01010400 , ULL(0x01010400) ); +CONST_UINT64_T( TP_TRACE_DATA_LO_0x01010401 , ULL(0x01010401) ); + +//------------------------------------------------------------------------------ // TP ITR //------------------------------------------------------------------------------ CONST_UINT64_T( TP_OSC_MSK_0x0102001A , ULL(0x0102001A) ); @@ -283,6 +314,7 @@ CONST_UINT64_T( TP_OPCG_CNTL1_0x01030003 , ULL(0x01030003) ); CONST_UINT64_T( TP_OPCG_CNTL2_0x01030004 , ULL(0x01030004) ); CONST_UINT64_T( TP_OPCG_CNTL3_0x01030005 , ULL(0x01030005) ); CONST_UINT64_T( TP_CLK_REGION_0x01030006 , ULL(0x01030006) ); + CONST_UINT64_T( TP_CLK_SCANSEL_0x01030007 , ULL(0x01030007) ); CONST_UINT64_T( TP_CLK_STATUS_0x01030008 , ULL(0x01030008) ); @@ -325,6 +357,7 @@ CONST_UINT64_T( TP_MCGR4_0x010F0004 , ULL(0x010F0004) ); //------------------------------------------------------------------------------ CONST_UINT64_T( TP_HANG_P1_0x010F0021 , ULL(0x010F0021) ); // PRV: setup hang pulse register0 CONST_UINT64_T( TP_HANG_P2_0x010F0022 , ULL(0x010F0022) ); // PRV: setup hang pulse register1 +CONST_UINT64_T( TP_HANG_P6_0x010F0026 , ULL(0x010F0026) ); // PRV: setup hang pulse register6 CONST_UINT64_T( TP_HANG_PRE_0x010F0028 , ULL(0x010F0028) ); // PRV: setup hang precounter (HEX:01) @@ -403,21 +436,138 @@ CONST_UINT64_T( NEST_HANG_P4_0x020F0024 , ULL(0x020F0024) ); / CONST_UINT64_T( NEST_HANG_PRE_0x020F0028 , ULL(0x020F0028) ); // NEST (PB): setup hang precounter (HEX:01) +/******************************************************************************/ +/********* MULTICAST REGISTER DEFINITIONS FOR PERVASIVE INITs ****************/ +/******************************************************************************/ + +CONST_UINT64_T( READ_ALL_GP0_0x43000000 , ULL(0x43000000) ); // all GP0 but not PRV +CONST_UINT64_T( WRITE_ALL_GP0_0x6B000000 , ULL(0x6B000000) ); // all GP0 but not PRV +CONST_UINT64_T( WRITE_ALL_GP0_AND_0x6B000004 , ULL(0x6B000004) ); // all GP0 AND but not PRV +CONST_UINT64_T( WRITE_ALL_GP0_OR_0x6B000005 , ULL(0x6B000005) ); // all GP0 OR but not PRV + +CONST_UINT64_T( READ_ALL_GP1_AND_0x4B000001 , ULL(0x4B000001) ); // and all GP1 but not PRV + +CONST_UINT64_T( WRITE_EX_GP3_AND_0x690F0013 , ULL(0x690F0013) ); // and all EX GP3 + +CONST_UINT64_T( WRITE_ALL_CLK_REGION_0x6B030006 , ULL(0x6B030006) ); // all GP3 but not PRV + +CONST_UINT64_T( READ_ALL_OPCG_CNTL0_0x43030002 , ULL(0x43030002) ); // all EX OPCG0 +CONST_UINT64_T( WRITE_ALL_OPCG_CNTL0_0x6B030002 , ULL(0x6B030002) ); // all EX OPCG0 + +CONST_UINT64_T( READ_ALL_OPCG_CNTL2_0x43030004 , ULL(0x43030004) ); // all OPCG2 but not PRV +CONST_UINT64_T( WRITE_ALL_OPCG_CNTL2_0x6B030004 , ULL(0x6B030004) ); // all OPCG2 but not PRV + +CONST_UINT64_T( READ_ALL_FUNC_GP3_0x430F0012 , ULL(0x430F0012) ); // all GP3 but not PRV + +CONST_UINT64_T( SLAVE_PCB_ERR_0x6B0F001F , ULL(0x6B0F001F) ); + + +CONST_UINT64_T( READ_OR_ALL_FUNC_GP0_0x43000000 , ULL(0x43000000) ); // group3: all except PRV: GP0 +CONST_UINT64_T( READ_OR_ALL_FUNC_GP1_0x43000001 , ULL(0x43000001) ); // group3: all except PRV: GP1 +CONST_UINT64_T( READ_OR_ALL_FUNC_GP2_0x43000002 , ULL(0x43000002) ); // group3: all except PRV: GP2 +CONST_UINT64_T( READ_OR_ALL_FUNC_GP4_0x43000003 , ULL(0x43000003) ); // group3: all except PRV: GP4 +CONST_UINT64_T( READ_OR_ALL_FUNC_OPCG_CNTL0_0x43030002 , ULL(0x43030002) ); // group3: all except PRV: OPCG_CNTL0 +CONST_UINT64_T( READ_OR_ALL_FUNC_OPCG_CNTL1_0x43030003 , ULL(0x43030003) ); // group3: all except PRV: OPCG_CNTL1 +CONST_UINT64_T( READ_OR_ALL_FUNC_OPCG_CNTL2_0x43030004 , ULL(0x43030004) ); // group3: all except PRV: OPCG_CNTL2 +CONST_UINT64_T( READ_OR_ALL_FUNC_OPCG_CNTL3_0x43030005 , ULL(0x43030005) ); // group3: all except PRV: OPCG_CNTL3 +CONST_UINT64_T( READ_OR_ALL_FUNC_CLK_REGION_0x43030006 , ULL(0x43030006) ); // group3: all except PRV: CLK_REGION +CONST_UINT64_T( READ_OR_ALL_FUNC_CLK_SCANSEL_0x43030007 , ULL(0x43030007) ); // group3: all except PRV: CLK_SCANSEL +CONST_UINT64_T( READ_OR_ALL_FUNC_CLK_STATUS_0x43030008 , ULL(0x43030008) ); // group3: all except PRV: CLK_STATUS +CONST_UINT64_T( READ_OR_ALL_FUNC_GP3_0x430F0012 , ULL(0x430F0012) ); // group3: all except PRV: GP3 +CONST_UINT64_T( READ_OR_ALL_PCB_SLAVE_ERRREG_0x430F001F , ULL(0x430F001F) ); // group3: all except PRV: + +CONST_UINT64_T( READ_AND_ALL_FUNC_GP0_0x4B000000 , ULL(0x4B000000) ); // group3: all except PRV: GP0 +CONST_UINT64_T( READ_AND_ALL_FUNC_GP1_0x4B000001 , ULL(0x4B000001) ); // group3: all except PRV: GP1 +CONST_UINT64_T( READ_AND_ALL_FUNC_GP2_0x4B000002 , ULL(0x4B000002) ); // group3: all except PRV: GP2 +CONST_UINT64_T( READ_AND_ALL_FUNC_GP4_0x4B000003 , ULL(0x4B000003) ); // group3: all except PRV: GP4 +CONST_UINT64_T( READ_AND_ALL_FUNC_OPCG_CNTL0_0x4B030002 , ULL(0x4B030002) ); // group3: all except PRV: OPCG_CNTL0 +CONST_UINT64_T( READ_AND_ALL_FUNC_OPCG_CNTL1_0x4B030003 , ULL(0x4B030003) ); // group3: all except PRV: OPCG_CNTL1 +CONST_UINT64_T( READ_AND_ALL_FUNC_OPCG_CNTL2_0x4B030004 , ULL(0x4B030004) ); // group3: all except PRV: OPCG_CNTL2 +CONST_UINT64_T( READ_AND_ALL_FUNC_OPCG_CNTL3_0x4B030005 , ULL(0x4B030005) ); // group3: all except PRV: OPCG_CNTL3 +CONST_UINT64_T( READ_AND_ALL_FUNC_CLK_REGION_0x4B030006 , ULL(0x4B030006) ); // group3: all except PRV: CLK_REGION +CONST_UINT64_T( READ_AND_ALL_FUNC_CLK_SCANSEL_0x4B030007 , ULL(0x4B030007) ); // group3: all except PRV: CLK_SCANSEL +CONST_UINT64_T( READ_AND_ALL_FUNC_CLK_STATUS_0x4B030008 , ULL(0x4B030008) ); // group3: all except PRV: CLK_STATUS +CONST_UINT64_T( READ_AND_ALL_FUNC_GP3_0x4B0F0012 , ULL(0x4B0F0012) ); // group3: all except PRV: GP3 +CONST_UINT64_T( READ_AND_ALL_PCB_SLAVE_ERRREG_0x4B0F001F , ULL(0x4B0F001F) ); // group3: all except PRV: + +CONST_UINT64_T( READ_ALL_PCB_SLAVE_ATTN_INT_0x500F001A , ULL(0x500F001A) ); // group0: all chiplets +CONST_UINT64_T( READ_ALL_PCB_SLAVE_RECOV_INT_0x500F001B , ULL(0x500F001B) ); // group0: all chiplets +CONST_UINT64_T( READ_ALL_PCB_SLAVE_XSTOP_INT_0x500F001C , ULL(0x500F001C) ); // group0: all chiplets + +CONST_UINT64_T( WRITE_ALL_FUNC_GP0_0x6B000000 , ULL(0x6B000000) ); // group3: all except PRV: GP0 +CONST_UINT64_T( WRITE_ALL_FUNC_GP1_0x6B000001 , ULL(0x6B000001) ); // group3: all except PRV: GP1 +CONST_UINT64_T( WRITE_ALL_FUNC_GP2_0x6B000002 , ULL(0x6B000002) ); // group3: all except PRV: GP2 +CONST_UINT64_T( WRITE_ALL_FUNC_GP4_0x6B000003 , ULL(0x6B000003) ); // group3: all except PRV: GP4 +CONST_UINT64_T( WRITE_ALL_FUNC_GP0_AND_0x6B000004 , ULL(0x6B000004) ); // group3: all except PRV: GP0 AND (for clearing bits) +CONST_UINT64_T( WRITE_ALL_FUNC_GP0_OR_0x6B000005 , ULL(0x6B000005) ); // group3: all except PRV: GP0 OR (for setting bits) +CONST_UINT64_T( WRITE_ALL_FUNC_GP4_AND_0x6B000006 , ULL(0x6B000006) ); // group3: all except PRV: GP4 AND (for clearing bits) +CONST_UINT64_T( WRITE_ALL_FUNC_GP4_OR_0x6B000007 , ULL(0x6B000007) ); // group3: all except PRV: GP4 OR (for setting bits) +CONST_UINT64_T( WRITE_ALL_FUNC_OPCG_CNTL0_0x6B030002 , ULL(0x6B030002) ); // group3: all except PRV: OPCG_CNTL0 +CONST_UINT64_T( WRITE_ALL_FUNC_OPCG_CNTL1_0x6B030003 , ULL(0x6B030003) ); // group3: all except PRV: OPCG_CNTL1 +CONST_UINT64_T( WRITE_ALL_FUNC_OPCG_CNTL2_0x6B030004 , ULL(0x6B030004) ); // group3: all except PRV: OPCG_CNTL2 +CONST_UINT64_T( WRITE_ALL_FUNC_OPCG_CNTL3_0x6B030005 , ULL(0x6B030005) ); // group3: all except PRV: OPCG_CNTL3 +CONST_UINT64_T( WRITE_ALL_FUNC_CLK_REGION_0x6B030006 , ULL(0x6B030006) ); // group3: all except PRV: CLK_REGION +CONST_UINT64_T( WRITE_ALL_FUNC_CLK_SCANSEL_0x6B030007 , ULL(0x6B030007) ); // group3: all except PRV: CLK_SCANSEL +CONST_UINT64_T( WRITE_ALL_FUNC_CLK_STATUS_0x6B030008 , ULL(0x6B030008) ); // group3: all except PRV: CLK_STATUS +CONST_UINT64_T( WRITE_ALL_FUNC_GP3_0x6B0F0012 , ULL(0x6B0F0012) ); // group3: all except PRV: GP3 +CONST_UINT64_T( WRITE_ALL_FUNC_GP3_AND_0x6B0F0013 , ULL(0x6B0F0013) ); // group3: all except PRV: GP3 AND (for clearing bits) +CONST_UINT64_T( WRITE_ALL_FUNC_GP3_OR_0x6B0F0014 , ULL(0x6B0F0014) ); // group3: all except PRV: GP3 OR (for setting bits) +CONST_UINT64_T( WRITE_ALL_PCB_SLAVE_ERRREG_0x6B0F001F , ULL(0x6B0F001F) ); // group3: all except PRV: + + //******************************************************************************/ //********* ADDRESS PREFIXES FOR SUBROUTINE SCAN0_MODULE CALLS ****************/ //******************************************************************************/ -CONST_UINT64_T( SCAN_ALLSCANEXVITAL, ULL(0x0FF00FFE00000000) ); -CONST_UINT64_T( SCAN_ALLSCANEXPRV, ULL(0x0FF00DCE00000000) ); -CONST_UINT64_T( SCAN_GPTR_TIME_REP, ULL(0x0FF0023000000000) ); -CONST_UINT64_T( SCAN_TIME_REP, ULL(0x0CF0003000000000) ); -CONST_UINT8_T( SCAN_CHIPLET_TP, ULL(0x01) ); -CONST_UINT8_T( SCAN_CHIPLET_NEST, ULL(0x02) ); -CONST_UINT8_T( SCAN_CHIPLET_MEM, ULL(0x03) ); -CONST_UINT8_T( SCAN_CHIPLET_ALL, ULL(0x69) ); -CONST_UINT8_T( SCAN_CHIPLET_GROUP3, ULL(0x6B) ); + +CONST_UINT64_T( SCAN_ALLREGIONEXVITAL, ULL(0x0FF00E0000000000) ); +CONST_UINT64_T( SCAN_CLK_ALL, ULL(0x0FF00E0000000000) ); +CONST_UINT64_T( SCAN_CLK_ALLEXDPLL, ULL(0x0FE00E0000000000) ); +CONST_UINT64_T( SCAN_CLK_CORE_ONLY, ULL(0x06000E0000000000) ); +CONST_UINT64_T( SCAN_ALLSCANEXVITAL, ULL(0x0FF00DCE00000000) ); // Looking to be deprecated +CONST_UINT64_T( SCAN_ALLSCANEXPRV, ULL(0x0FF00DCE00000000) ); // Looking to be deprecated +CONST_UINT64_T( SCAN_ALL_BUT_GPTRTIMEREP, ULL(0x0FF00DCE00000000) ); +CONST_UINT64_T( SCAN_ALL_BUT_VITALDPLLGPTRTIME, ULL(0x0FE00DCE00000000) ); +CONST_UINT64_T( SCAN_GPTR_TIME_REP, ULL(0x0FF0023000000000) ); +CONST_UINT64_T( SCAN_TIME_REP, ULL(0x0CF0003000000000) ); + +CONST_UINT64_T( SCAN_CORE_ALL, ULL(0x06000FFE00000000) ); +CONST_UINT64_T( SCAN_CORE_ALL_BUT_GPTRTIMEREP, ULL(0x06000DCE00000000) ); +CONST_UINT64_T( SCAN_CORE_GPTR_TIME_REP, ULL(0x0600023000000000) ); +CONST_UINT64_T( SCAN_CORE_TIME_REP, ULL(0x0600003000000000) ); + + + + +CONST_UINT8_T( SCAN_CHIPLET_TP, ULL(0x01) ); +CONST_UINT8_T( SCAN_CHIPLET_NEST, ULL(0x02) ); +CONST_UINT8_T( SCAN_CHIPLET_MEM, ULL(0x03) ); +CONST_UINT8_T( SCAN_CHIPLET_ALL, ULL(0x68) ); +CONST_UINT8_T( SCAN_CHIPLET_GROUP1, ULL(0x69) ); +CONST_UINT8_T( SCAN_CHIPLET_GROUP3, ULL(0x6B) ); + +/* This content is old but will let R. Koester remove it formally +CONST_UINT64_T( SCAN_ALLREGIONEXVITAL, ULL(0x0FF00E0000000000) ); +// next line was wrong based on a documentation error, do we need this option at all? +// use OPTION 3 instead rkoester 05/23/12 +// CONST_UINT64_T( SCAN_ALLSCANEXVITAL, ULL(0x0FF00FFE00000000) ); +CONST_UINT64_T( SCAN_ALLSCANEXVITAL, ULL(0x0FF00DCE00000000) ); +CONST_UINT64_T( SCAN_ALLSCANEXPRV, ULL(0x0FF00DCE00000000) ); +// next line is a suggestion from Johannes, I need to discuss this with PRV design first: +// this would exclude a scan region for PRV, which probably does not serve chiplet init correctly +// rkoester 05/23/12 +// CONST_UINT64_T( SCAN_ALLSCANEXPRV, ULL(0x07F00DCE00000000) ); +*/ + +CONST_UINT8_T( READ_OR_ALL_CHIPLETS, ULL(0x40) ); // group 0: all chiplets +CONST_UINT8_T( READ_OR_ALL_FUNC_CHIPLETS, ULL(0x43) ); // group 3: all functional chiplets +// CONST_UINT8_T( READ_AND_ALL_CHIPLETS, ULL(0x48) ); // group 0: all chiplets +CONST_UINT8_T( READ_AND_ALL_FUNC_CHIPLETS, ULL(0x4B) ); // group 3: all functional chiplets +CONST_UINT8_T( WRITE_ALL_CHIPLETS, ULL(0x68) ); // group 0: all chiplets +CONST_UINT8_T( WRITE_ALL_FUNC_CHIPLETS, ULL(0x6B) ); // group 3: all functional chiplets + #endif @@ -427,6 +577,67 @@ This section is automatically updated by CVS when you check in this file. Be sure to create CVS comments when you commit so that they can be included here. $Log: common_scom_addresses.H,v $ +Revision 1.18 2012/06/25 17:52:34 bcbrock +Modified proc_sbe_decompress_scan.S: 1) Removed comments and code related to +the "polling" protocol. 2) Added a final SCOM to always issue a "setpulse" +after acanning. + +Revision 1.17 2012/06/20 14:49:29 rkoester +add plllock register + +Revision 1.16 2012/06/17 20:25:57 jmcgill +update trace SCOM addresses + +Revision 1.15 2012/06/14 14:21:03 koenig +Added MBOX scratch and I2CMS status - AK + +Revision 1.14 2012/06/11 16:14:56 rkoester +FSI GP8 CFAM address added + +Revision 1.13 2012/06/05 17:05:41 mfred +Added constants for reading PCB interrupt regs. + +Revision 1.12 2012/05/31 12:15:24 stillgs +Update constant names for (ex) scan0 routines that do real scanning + +Revision 1.11 2012/05/23 17:03:25 rkoester +scan0 vectors for scan0 module modified, Option 1 wrong + +Revision 1.10 2012/04/27 15:08:29 koenig +Added GENERIC_CLK_SYNC - AK + +Revision 1.9 2012/04/19 22:05:35 koenig +Added AND write to EX MCGR GP3 - AK + +Revision 1.8 2012/04/16 23:55:34 bcbrock +Corrected problems related to C/C++ and 32-bit/64-bit portability and Host +Boot after initial review by FW team. + +o Renamed fapi_sbe_common.h to fapi_sbe_common.H +o Renamed p8_scan_compression.[ch] to .[CH] since these are for use by C++ + procedures only (no requirement to execute on OCC). +o Modified sbe_xip_image.c to use the C99 standard way to print uint64_t + variables. +o Added __cplusplus guards to sbe_xip_image.h + +Revision 1.7 2012/04/04 11:41:15 koenig +Added TP hangcounter 6 and MBOX_FSIGP8 + +Revision 1.6 2012/03/26 15:16:52 stillgs +Added SCAN_CORE_ALL, SCAN_CORE_GPTR_TIME_REP, SCAN_CORE_TIME_REP constants for use by Sleep Exit + +Revision 1.5 2012/02/10 23:09:50 jmcgill +add trace array addresses + +Revision 1.4 2012/01/30 10:07:53 gweber +changed SCAN_CHIPLET_ALL to 0x68 + +Revision 1.3 2012/01/27 09:36:42 koenig +Added a region vector for scan0 module + +Revision 1.2 2012/01/24 21:59:39 mfred +Moved common multicast address constants to common_scom_accresses.H + Revision 1.1 2012/01/06 22:21:10 jmcgill initial release diff --git a/src/usr/hwpf/hwp/build_winkle_images/proc_slw_build/fapi_sbe_common.H b/src/usr/hwpf/hwp/include/fapi_sbe_common.H index 24868bb52..24868bb52 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/proc_slw_build/fapi_sbe_common.H +++ b/src/usr/hwpf/hwp/include/fapi_sbe_common.H diff --git a/src/usr/hwpf/hwp/include/fapi_sbe_common.h b/src/usr/hwpf/hwp/include/fapi_sbe_common.h deleted file mode 100644 index 2ad5b7bda..000000000 --- a/src/usr/hwpf/hwp/include/fapi_sbe_common.h +++ /dev/null @@ -1,62 +0,0 @@ -// IBM_PROLOG_BEGIN_TAG -// This is an automatically generated prolog. -// -// $Source: src/usr/HWPs/dmi_training/fapi_sbe_common.h $ -// -// IBM CONFIDENTIAL -// -// COPYRIGHT International Business Machines Corp. 2012 -// -// p1 -// -// Object Code Only (OCO) source materials -// Licensed Internal Code Source Materials -// IBM HostBoot Licensed Internal Code -// -// The source code for this program is not published or other- -// wise divested of its trade secrets, irrespective of what has -// been deposited with the U.S. Copyright Office. -// -// Origin: 30 -// -// IBM_PROLOG_END -#ifndef __FAPI_SBE_COMMON_H -#define __FAPI_SBE_COMMON_H - -// $Id: fapi_sbe_common.h,v 1.1 2011/07/06 04:06:49 bcbrock Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/fapi_sbe_common.h,v $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2011 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//------------------------------------------------------------------------------ -// *! OWNER NAME : Email: - -/// \file fapi_sbe_common.h -/// \brief Definitions common to FAPI and SBE procedures -/// -/// Several preprocessor macros are required to have different definitions in -/// traditional C, C++ and SBE assembly procedures. These common forms are -/// collected here. - -#ifdef __ASSEMBLER__ - -#define CONST_UINT8_T(name, expr) .set name, (expr) -#define CONST_UINT32_T(name, expr) .set name, (expr) -#define CONST_UINT64_T(name, expr) .set name, (expr) - -#define ULL(x) x - -#else - -#include <stdint.h> - -#define CONST_UINT8_T(name, expr) const uint8_t name = (expr); -#define CONST_UINT32_T(name, expr) const uint32_t name = (expr); -#define CONST_UINT64_T(name, expr) const uint64_t name = (expr); - -#define ULL(x) x##ull - -#endif // __ASSEMBLER__ - -#endif // __FAPI_SBE_COMMON_H diff --git a/src/usr/hwpf/hwp/include/p8_scom_addresses.H b/src/usr/hwpf/hwp/include/p8_scom_addresses.H index 17b672b30..96875564b 100755 --- a/src/usr/hwpf/hwp/include/p8_scom_addresses.H +++ b/src/usr/hwpf/hwp/include/p8_scom_addresses.H @@ -1,26 +1,27 @@ -// IBM_PROLOG_BEGIN_TAG -// This is an automatically generated prolog. -// -// $Source: src/usr/HWPs/dmi_training/p8_scom_addresses.H $ -// -// IBM CONFIDENTIAL -// -// COPYRIGHT International Business Machines Corp. 2012 -// -// p1 -// -// Object Code Only (OCO) source materials -// Licensed Internal Code Source Materials -// IBM HostBoot Licensed Internal Code -// -// The source code for this program is not published or other- -// wise divested of its trade secrets, irrespective of what has -// been deposited with the U.S. Copyright Office. -// -// Origin: 30 -// -// IBM_PROLOG_END -// $Id: p8_scom_addresses.H,v 1.50 2012/01/06 22:20:53 jmcgill Exp $ +/* IBM_PROLOG_BEGIN_TAG + * This is an automatically generated prolog. + * + * $Source: src/usr/hwpf/hwp/include/p8_scom_addresses.H $ + * + * IBM CONFIDENTIAL + * + * COPYRIGHT International Business Machines Corp. 2012 + * + * p1 + * + * Object Code Only (OCO) source materials + * Licensed Internal Code Source Materials + * IBM HostBoot Licensed Internal Code + * + * The source code for this program is not published or other- + * wise divested of its trade secrets, irrespective of what has + * been deposited with the U.S. Copyright Office. + * + * Origin: 30 + * + * IBM_PROLOG_END_TAG + */ +// $Id: p8_scom_addresses.H,v 1.82 2012/06/27 07:43:32 rkoester Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/p8_scom_addresses.H,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -96,7 +97,7 @@ // #include "common_scom_addresses.H" -#include "fapi_sbe_common.h" +#include "fapi_sbe_common.H" /******************************************************************************/ /********************************** CHIPLET *********************************/ @@ -131,6 +132,12 @@ CONST_UINT64_T( ALL_CORES_WRITE_0x6A000000 , ULL(0x6A000000) ); /******************************************************************************/ //------------------------------------------------------------------------------ +// OTPROM +//------------------------------------------------------------------------------ +CONST_UINT64_T( ECID_PART_0_0x00018000 , ULL(0x00018000) ); +CONST_UINT64_T( ECID_PART_1_0x00018001 , ULL(0x00018001) ); + +//------------------------------------------------------------------------------ // PORE-GPE0 //------------------------------------------------------------------------------ CONST_UINT64_T( PORE_GPE0_0x00060000 , ULL(0x00060000) ); @@ -226,6 +233,7 @@ CONST_UINT64_T( PORE_SLW_I2C_E2_PARAM_0x00068019 , ULL(0x00068019) ); //------------------------------------------------------------------------------ // OCC/OCB //------------------------------------------------------------------------------ + CONST_UINT64_T( OCC_CONTROL_0x0006B000 , ULL(0x0006B000) ); CONST_UINT64_T( OCC_CONTROL_AND_0x0006B001 , ULL(0x0006B001) ); CONST_UINT64_T( OCC_CONTROL_OR_0x0006B002 , ULL(0x0006B002) ); @@ -237,27 +245,125 @@ CONST_UINT64_T( OCB0_STATUS_CONTROL_AND_0x0006B012 , ULL(0x0006B012) ); CONST_UINT64_T( OCB0_STATUS_CONTROL_OR_0x0006B013 , ULL(0x0006B013) ); CONST_UINT64_T( OCB0_ERROR_STATUS_0x0006B014 , ULL(0x0006B014) ); CONST_UINT64_T( OCB0_DATA_0x0006B015 , ULL(0x0006B015) ); +CONST_UINT64_T( OCB0_PULL_BASE_0x0006A200 , ULL(0x0006A200) ); +CONST_UINT64_T( OCB0_PULL_STATUS_CONTROL_0x0006A201 , ULL(0x0006A201) ); +CONST_UINT64_T( OCB0_PUSH_BASE_0x0006A203 , ULL(0x0006A203) ); +CONST_UINT64_T( OCB0_PUSH_STATUS_CONTROL_0x0006A204 , ULL(0x0006A204) ); +CONST_UINT64_T( OCB0_STREAM_ERR_STATUS_0x0006A206 , ULL(0x0006A206) ); +CONST_UINT64_T( OCB0_UNTRUSTED_CONTROL_0x0006A207 , ULL(0x0006A207) ); +CONST_UINT64_T( OCB0_LIN_WINDOW_CONTROL_0x0006A208 , ULL(0x0006A208) ); +CONST_UINT64_T( OCB0_LIN_WINDOW_BASE_0x0006A20C , ULL(0x0006A20C) ); CONST_UINT64_T( OCB1_ADDRESS_0x0006B030 , ULL(0x0006B030) ); CONST_UINT64_T( OCB1_STATUS_CONTROL_0x0006B031 , ULL(0x0006B031) ); CONST_UINT64_T( OCB1_STATUS_CONTROL_AND_0x0006B032 , ULL(0x0006B032) ); -CONST_UINT64_T( OCB1_STATUS_CONTROL_OR_0x0006B032 , ULL(0x0006B033) ); +CONST_UINT64_T( OCB1_STATUS_CONTROL_OR_0x0006B033 , ULL(0x0006B033) ); CONST_UINT64_T( OCB1_ERROR_STATUS_0x0006B034 , ULL(0x0006B034) ); CONST_UINT64_T( OCB1_DATA_0x0006B035 , ULL(0x0006B035) ); +CONST_UINT64_T( OCB1_PULL_BASE_0x0006A210 , ULL(0x0006A210) ); +CONST_UINT64_T( OCB1_PULL_STATUS_CONTROL_0x0006A211 , ULL(0x0006A211) ); +CONST_UINT64_T( OCB1_PUSH_BASE_0x0006A213 , ULL(0x0006A213) ); +CONST_UINT64_T( OCB1_PUSH_STATUS_CONTROL_0x0006A214 , ULL(0x0006A214) ); +CONST_UINT64_T( OCB1_STREAM_ERR_STATUS_0x0006A216 , ULL(0x0006A216) ); +CONST_UINT64_T( OCB1_UNTRUSTED_CONTROL_0x0006A217 , ULL(0x0006A217) ); +CONST_UINT64_T( OCB1_LIN_WINDOW_CONTROL_0x0006A218 , ULL(0x0006A218) ); +CONST_UINT64_T( OCB1_LIN_WINDOW_BASE_0x0006A21C , ULL(0x0006A21C) ); CONST_UINT64_T( OCB2_ADDRESS_0x0006B050 , ULL(0x0006B050) ); CONST_UINT64_T( OCB2_STATUS_CONTROL_0x0006B051 , ULL(0x0006B051) ); CONST_UINT64_T( OCB2_STATUS_CONTROL_AND_0x0006B052 , ULL(0x0006B052) ); -CONST_UINT64_T( OCB2_STATUS_CONTROL_OR_0x0006B052 , ULL(0x0006B053) ); +CONST_UINT64_T( OCB2_STATUS_CONTROL_OR_0x0006B053 , ULL(0x0006B053) ); CONST_UINT64_T( OCB2_ERROR_STATUS_0x0006B054 , ULL(0x0006B054) ); CONST_UINT64_T( OCB2_DATA_0x0006B055 , ULL(0x0006B055) ); +CONST_UINT64_T( OCB2_PULL_BASE_0x0006A220 , ULL(0x0006A220) ); +CONST_UINT64_T( OCB2_PULL_STATUS_CONTROL_0x0006A221 , ULL(0x0006A221) ); +CONST_UINT64_T( OCB2_PUSH_BASE_0x0006A223 , ULL(0x0006A223) ); +CONST_UINT64_T( OCB2_PUSH_STATUS_CONTROL_0x0006A224 , ULL(0x0006A224) ); +CONST_UINT64_T( OCB2_STREAM_ERR_STATUS_0x0006A226 , ULL(0x0006A226) ); +CONST_UINT64_T( OCB2_UNTRUSTED_CONTROL_0x0006A227 , ULL(0x0006A227) ); +CONST_UINT64_T( OCB2_LIN_WINDOW_CONTROL_0x0006A228 , ULL(0x0006A228) ); +CONST_UINT64_T( OCB2_LIN_WINDOW_BASE_0x0006A22C , ULL(0x0006A22C) ); CONST_UINT64_T( OCB3_ADDRESS_0x0006B070 , ULL(0x0006B070) ); CONST_UINT64_T( OCB3_STATUS_CONTROL_0x0006B071 , ULL(0x0006B071) ); CONST_UINT64_T( OCB3_STATUS_CONTROL_AND_0x0006B072 , ULL(0x0006B072) ); -CONST_UINT64_T( OCB3_STATUS_CONTROL_OR_0x0006B072 , ULL(0x0006B073) ); +CONST_UINT64_T( OCB3_STATUS_CONTROL_OR_0x0006B073 , ULL(0x0006B073) ); CONST_UINT64_T( OCB3_ERROR_STATUS_0x0006B074 , ULL(0x0006B074) ); CONST_UINT64_T( OCB3_DATA_0x0006B075 , ULL(0x0006B075) ); +CONST_UINT64_T( OCB3_PULL_BASE_0x0006A230 , ULL(0x0006A230) ); +CONST_UINT64_T( OCB3_PULL_STATUS_CONTROL_0x0006A231 , ULL(0x0006A231) ); +CONST_UINT64_T( OCB3_PUSH_BASE_0x0006A233 , ULL(0x0006A233) ); +CONST_UINT64_T( OCB3_PUSH_STATUS_CONTROL_0x0006A234 , ULL(0x0006A234) ); +CONST_UINT64_T( OCB3_STREAM_ERR_STATUS_0x0006A236 , ULL(0x0006A236) ); +CONST_UINT64_T( OCB3_UNTRUSTED_CONTROL_0x0006A237 , ULL(0x0006A237) ); +CONST_UINT64_T( OCB3_LIN_WINDOW_CONTROL_0x0006A238 , ULL(0x0006A238) ); +CONST_UINT64_T( OCB3_LIN_WINDOW_BASE_0x0006A23C , ULL(0x0006A23C) ); + +// sram registers +CONST_UINT64_T( OCC_SRAM_BOOT_VEC0_0x00066004 , ULL(0x00066004) ); +CONST_UINT64_T( OCC_SRAM_BOOT_VEC1_0x00066005 , ULL(0x00066005) ); +CONST_UINT64_T( OCC_SRAM_BOOT_VEC2_0x00066006 , ULL(0x00066006) ); +CONST_UINT64_T( OCC_SRAM_BOOT_VEC3_0x00066007 , ULL(0x00066007) ); + +//------------------------------------------------------------------------------ +// PMC +//------------------------------------------------------------------------------ +// todo: the full set needs to be added. The ones below are for SLW at this time + +// PIB Space Addresses + + +CONST_UINT64_T( PMC_SPIV_CTRL_REG0A_0x00062040 , ULL(0x00062040) ); +CONST_UINT64_T( PMC_SPIV_CTRL_REG0B_0x00062041 , ULL(0x00062041) ); +CONST_UINT64_T( PMC_SPIV_CTRL_REG1_0x00062042 , ULL(0x00062042) ); +CONST_UINT64_T( PMC_SPIV_CTRL_REG2_0x00062043 , ULL(0x00062043) ); +CONST_UINT64_T( PMC_SPIV_CTRL_REG3_0x00062044 , ULL(0x00062044) ); +CONST_UINT64_T( PMC_SPIV_CTRL_REG4_0x00062045 , ULL(0x00062045) ); +CONST_UINT64_T( PMC_SPIV_STATUS_REG_0x00062046 , ULL(0x00062046) ); +CONST_UINT64_T( PMC_SPIV_COMMAND_REG_0x00062047 , ULL(0x00062047) ); + + +CONST_UINT64_T( PMC_O2S_CTRL_REG0A_0x00062050 , ULL(0x00062050) ); +CONST_UINT64_T( PMC_O2S_CTRL_REG0B_0x00062051 , ULL(0x00062051) ); +CONST_UINT64_T( PMC_O2S_CTRL_REG1_0x00062052 , ULL(0x00062052) ); +CONST_UINT64_T( PMC_O2S_CTRL_REG2_0x00062053 , ULL(0x00062053) ); +CONST_UINT64_T( PMC_O2S_CTRL_REG4_0x00062055 , ULL(0x00062055) ); +CONST_UINT64_T( PMC_O2S_STATUS_REG_0x00062056 , ULL(0x00062056) ); +CONST_UINT64_T( PMC_O2S_COMMAND_REG_0x00062057 , ULL(0x00062057) ); +CONST_UINT64_T( PMC_O2S_WDATA_REG_0x00062058 , ULL(0x00062058) ); +CONST_UINT64_T( PMC_O2S_RDATA_REG_0x00062059 , ULL(0x00062059) ); + +CONST_UINT64_T( PMC_PORE_REQ_STAT_REG_0x00062090 , ULL(0x00062090) ); +CONST_UINT64_T( PMC_MODE_REG_0x00062000 , ULL(0x00062000) ); + + + + +CONST_UINT64_T( SPIPSS_ADC_CTRL_REG0_0x00070000 , ULL(0x00070000) ); +CONST_UINT64_T( SPIPSS_ADC_CTRL_REG1_0x00070001 , ULL(0x00070001) ); +CONST_UINT64_T( SPIPSS_ADC_CTRL_REG2_0x00070002 , ULL(0x00070002) ); +CONST_UINT64_T( SPIPSS_ADC_STATUS_REG_0x00070003 , ULL(0x00070003) ); +CONST_UINT64_T( SPIPSS_ADC_CMD_REG_0x00070004 , ULL(0x00070004) ); +CONST_UINT64_T( SPIPSS_ADC_WDATA_REG_0x00070010 , ULL(0x00070010) ); +CONST_UINT64_T( SPIPSS_ADC_RDATA_REG0_0x00070020 , ULL(0x00070020) ); +CONST_UINT64_T( SPIPSS_ADC_RDATA_REG1_0x00070021 , ULL(0x00070021) ); +CONST_UINT64_T( SPIPSS_ADC_RDATA_REG2_0x00070022 , ULL(0x00070022) ); +CONST_UINT64_T( SPIPSS_ADC_RDATA_REG3_0x00070023 , ULL(0x00070023) ); +CONST_UINT64_T( SPIPSS_100NS_REG_0x00070028 , ULL(0x00070028) ); +CONST_UINT64_T( SPIPSS_P2S_CTRL_REG0_0x00070040 , ULL(0x00070040) ); +CONST_UINT64_T( SPIPSS_P2S_CTRL_REG1_0x00070041 , ULL(0x00070041) ); +CONST_UINT64_T( SPIPSS_P2S_CTRL_REG2_0x00070042 , ULL(0x00070042) ); +CONST_UINT64_T( SPIPSS_P2S_STATUS_REG_0x00070043 , ULL(0x00070043) ); +CONST_UINT64_T( SPIPSS_P2S_COMMAND_REG_0x00070044 , ULL(0x00070044) ); +CONST_UINT64_T( SPIPSS_P2S_WDATA_REG_0x00070050 , ULL(0x00070050) ); +CONST_UINT64_T( SPIPSS_P2S_RDATA_REG_0x00070060 , ULL(0x00070060) ); +CONST_UINT64_T( SPIPSS_ADC_RESET_REGISTER_0x00070005 , ULL(0x00070005) ); +CONST_UINT64_T( SPIPSS_P2S_RESET_REGISTER_0x00070045 , ULL(0x00070045) ); + + +// OCI Space Addresses +CONST_UINT32_T( OCI_PMC_PORE_REQ_STAT_REG_0x40010480 , ULL(0x40010480) ); + //------------------------------------------------------------------------------ // SPIADC @@ -269,6 +375,15 @@ CONST_UINT64_T( SPIADC_0x00070000 , ULL(0x00070000) ); //------------------------------------------------------------------------------ CONST_UINT64_T( PIBMEM0_0x00080000 , ULL(0x00080000) ); +CONST_UINT64_T( PIBMEM_CONTROL_0x00088000 , ULL(0x00088000) ); +CONST_UINT64_T( PIBMEM_ADDRESS_0x00088001 , ULL(0x00088001) ); +CONST_UINT64_T( PIBMEM_DATA_0x00088002 , ULL(0x00088002) ); +CONST_UINT64_T( PIBMEM_DATA_INC_0x00088003 , ULL(0x00088003) ); +CONST_UINT64_T( PIBMEM_DATA_DEC_0x00088004 , ULL(0x00088004) ); +CONST_UINT64_T( PIBMEM_STATUS_0x00088005 , ULL(0x00088005) ); +CONST_UINT64_T( PIBMEM_RESET_0x00088006 , ULL(0x00088006) ); +CONST_UINT64_T( PIBMEM_REPAIR_LOAD_0x00088007 , ULL(0x00088007) ); + //------------------------------------------------------------------------------ // I2C MASTER (MEMS1) //------------------------------------------------------------------------------ @@ -359,16 +474,43 @@ CONST_UINT64_T( PORE_SBE_I2C_E2_PARAM_0x000E0019 , ULL(0x000E0019) ); //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ +// NEST TRACE +//------------------------------------------------------------------------------ +CONST_UINT64_T( NEST_TRACE_DATA_HI_PB_T1_0x02010440 , ULL(0x02010440) ); +CONST_UINT64_T( NEST_TRACE_DATA_LO_PB_T1_0x02010441 , ULL(0x02010441) ); +CONST_UINT64_T( NEST_TRACE_DATA_HI_PB_T2_0x02010480 , ULL(0x02010480) ); +CONST_UINT64_T( NEST_TRACE_DATA_LO_PB_T2_0x02010481 , ULL(0x02010481) ); +CONST_UINT64_T( NEST_TRACE_DATA_HI_PB_T3_0x020104C0 , ULL(0x020104C0) ); +CONST_UINT64_T( NEST_TRACE_DATA_LO_PB_T3_0x020104C1 , ULL(0x020104C1) ); +CONST_UINT64_T( NEST_TRACE_DATA_HI_PB_T4_0x02010500 , ULL(0x02010500) ); +CONST_UINT64_T( NEST_TRACE_DATA_LO_PB_T4_0x02010501 , ULL(0x02010501) ); +CONST_UINT64_T( NEST_TRACE_DATA_HI_PB_T5_0x02010540 , ULL(0x02010540) ); +CONST_UINT64_T( NEST_TRACE_DATA_LO_PB_T5_0x02010541 , ULL(0x02010541) ); +CONST_UINT64_T( NEST_TRACE_DATA_HI_PB_T6_0x02010580 , ULL(0x02010580) ); +CONST_UINT64_T( NEST_TRACE_DATA_LO_PB_T6_0x02010581 , ULL(0x02010581) ); +CONST_UINT64_T( NEST_TRACE_DATA_HI_PB_T7_0x020105C0 , ULL(0x020105C0) ); +CONST_UINT64_T( NEST_TRACE_DATA_LO_PB_T7_0x020105C1 , ULL(0x020105C1) ); +CONST_UINT64_T( NEST_TRACE_DATA_HI_PB_T8_0x02010600 , ULL(0x02010600) ); +CONST_UINT64_T( NEST_TRACE_DATA_LO_PB_T8_0x02010601 , ULL(0x02010601) ); +CONST_UINT64_T( NEST_TRACE_DATA_HI_PB_T9_0x02010640 , ULL(0x02010640) ); +CONST_UINT64_T( NEST_TRACE_DATA_LO_PB_T9_0x02010641 , ULL(0x02010641) ); +CONST_UINT64_T( NEST_TRACE_DATA_HI_NX_0x02010A00 , ULL(0x02010A00) ); +CONST_UINT64_T( NEST_TRACE_DATA_LO_NX_0x02010A01 , ULL(0x02010A01) ); + +//------------------------------------------------------------------------------ // POWERBUS ACCESS BRIDGE (PBA) //------------------------------------------------------------------------------ +CONST_UINT64_T( PBA_CC_SYNC_CONF_0x02030000 , ULL(0x02030000) ); + CONST_UINT64_T( PBA_FIR_0x02010840 , ULL(0x02010840) ); CONST_UINT64_T( PBA_FIR_AND_0x02010841 , ULL(0x02010841) ); CONST_UINT64_T( PBA_FIR_OR_0x02010842 , ULL(0x02010842) ); -CONST_UINT64_T( PBA_FIR_ACTION0_0x02010843 , ULL(0x02010843) ); -CONST_UINT64_T( PBA_FIR_ACTION1_0x02010844 , ULL(0x02010844) ); -CONST_UINT64_T( PBA_FIR_MASK_0x02010846 , ULL(0x02010846) ); -CONST_UINT64_T( PBA_FIR_MASK_AND_0x02010847 , ULL(0x02010847) ); -CONST_UINT64_T( PBA_FIR_MASK_OR_0x02010848 , ULL(0x02010848) ); +CONST_UINT64_T( PBA_FIR_MASK_0x02010843 , ULL(0x02010843) ); +CONST_UINT64_T( PBA_FIR_MASK_AND_0x02010844 , ULL(0x02010844) ); +CONST_UINT64_T( PBA_FIR_MASK_OR_0x02010845 , ULL(0x02010845) ); +CONST_UINT64_T( PBA_FIR_ACTION0_0x02010846 , ULL(0x02010846) ); +CONST_UINT64_T( PBA_FIR_ACTION1_0x02010847 , ULL(0x02010847) ); + CONST_UINT64_T( PBA_OCC_ACTION_0x0201084A , ULL(0x0201084A) ); CONST_UINT64_T( PBA_CONFIG_0x0201084B , ULL(0x0201084B) ); CONST_UINT64_T( PBA_ERR_RPT0_0x0201084C , ULL(0x0201084C) ); @@ -417,6 +559,21 @@ CONST_UINT64_T( PBA_BARMSK3_0x02013F07 , ULL(0x02013F07) ); CONST_UINT64_T( PBA_TRUSTMODE_0x02013F08 , ULL(0x02013F08) ); //------------------------------------------------------------------------------ +// PSI +//------------------------------------------------------------------------------ +CONST_UINT64_T( PSI_BRIDGE_BAR_0x0201090A , ULL(0x0201090A) ); +CONST_UINT64_T( PSI_FSP_BAR_0x0201090B , ULL(0x0201090B) ); +CONST_UINT64_T( PSI_FSP_MMR_0x0201090C , ULL(0x0201090C) ); +CONST_UINT64_T( PSI_BRIDGE_STATUS_CTL_0x0201090E , ULL(0x0201090E) ); + +//------------------------------------------------------------------------------ +// INTERRUPT CONTROL PRESENTER (ICP) +//------------------------------------------------------------------------------ +CONST_UINT64_T( ICP_BAR_0x020109CA , ULL(0x020109CA) ); +CONST_UINT64_T( ICP_INTR_INJECT_0x020109CC , ULL(0x020109CC) ); + + +//------------------------------------------------------------------------------ // NEST PB EH //------------------------------------------------------------------------------ // registers with multiple physical/shadow copies (all must be configured consistently) @@ -518,14 +675,26 @@ CONST_UINT64_T( PB_RAS_FIR_MASK_AND_0x02010C70 , ULL(0x02010C70) ); CONST_UINT64_T( PB_RAS_FIR_MASK_OR_0x02010C71 , ULL(0x02010C71) ); CONST_UINT64_T( PB_RAS_FIR_ACTION0_0x02010C72 , ULL(0x02010C72) ); CONST_UINT64_T( PB_RAS_FIR_ACTION1_0x02010C73 , ULL(0x02010C73) ); +//------------------------------------------------------------------------------ +// PLL LOCK +//------------------------------------------------------------------------------ +// PLL lock information +CONST_UINT64_T( PB_PLLLOCKREG_0x020F0019 , ULL(0x020F0019) ); //------------------------------------------------------------------------------ // MCS //------------------------------------------------------------------------------ -// MCI -CONST_UINT64_T( MCI_FIR_0x02011840 , ULL(0x02011840) ); -CONST_UINT64_T( MCI_CFG_0x0201184A , ULL(0x0201184A) ); -CONST_UINT64_T( MCI_STAT_0x0201184B , ULL(0x0201184B) ); +CONST_UINT64_T( MCS_MCFGP_0x02011800 , ULL(0x02011800) ); + +CONST_UINT64_T( MCS_MCIFIR_0x02011840 , ULL(0x02011840) ); +CONST_UINT64_T( MCS_MCIFIR_AND_0x02011841 , ULL(0x02011841) ); +CONST_UINT64_T( MCS_MCIFIR_OR_0x02011842 , ULL(0x02011842) ); +CONST_UINT64_T( MCS_MCIFIRMASK_0x02011843 , ULL(0x02011843) ); +CONST_UINT64_T( MCS_MCIFIRMASK_AND_0x02011844 , ULL(0x02011844) ); +CONST_UINT64_T( MCS_MCIFIRMASK_OR_0x02011845 , ULL(0x02011845) ); + +CONST_UINT64_T( MCS_MCICFG_0x0201184A , ULL(0x0201184A) ); +CONST_UINT64_T( MCS_MCISTAT_0x0201184B , ULL(0x0201184B) ); //------------------------------------------------------------------------------ // NEST Alter-Diplay Unit (ADU) @@ -534,8 +703,88 @@ CONST_UINT64_T( ADU_CONTROL_0x02020000 , ULL(0x02020000) ); CONST_UINT64_T( ADU_COMMAND_0x02020001 , ULL(0x02020001) ); CONST_UINT64_T( ADU_STATUS_0x02020002 , ULL(0x02020002) ); CONST_UINT64_T( ADU_DATA_0x02020003 , ULL(0x02020003) ); +CONST_UINT64_T( ADU_XSCOM_BASE_0x02020005 , ULL(0x02020005) ); CONST_UINT64_T( ADU_FORCE_ECC_0x02020010 , ULL(0x02020010) ); CONST_UINT64_T( ADU_PMISC_MODE_0x0202000B , ULL(0x0202000B) ); +CONST_UINT64_T( ADU_UNTRUSTED_BAR_0x02020015 , ULL(0x02020015) ); +CONST_UINT64_T( ADU_UNTRUSTED_BAR_MASK_0x02020016 , ULL(0x02020016) ); + +//------------------------------------------------------------------------------ +// PCIe +//------------------------------------------------------------------------------ +CONST_UINT64_T( PCIE0_NODAL_BAR0_0x02012010 , ULL(0x02012010) ); +CONST_UINT64_T( PCIE0_NODAL_BAR1_0x02012011 , ULL(0x02012011) ); +CONST_UINT64_T( PCIE0_GROUP_BAR0_0x02012012 , ULL(0x02012012) ); +CONST_UINT64_T( PCIE0_GROUP_BAR1_0x02012013 , ULL(0x02012013) ); +CONST_UINT64_T( PCIE0_NEAR_BAR_F0_0x02012014 , ULL(0x02012014) ); +CONST_UINT64_T( PCIE0_FAR_BAR_F0_0x02012015 , ULL(0x02012015) ); +CONST_UINT64_T( PCIE0_NEAR_BAR_F1_0x02012016 , ULL(0x02012016) ); +CONST_UINT64_T( PCIE0_FAR_BAR_F1_0x02012017 , ULL(0x02012017) ); +CONST_UINT64_T( PCIE0_IO_BAR0_0x02012040 , ULL(0x02012040) ); +CONST_UINT64_T( PCIE0_IO_BAR1_0x02012041 , ULL(0x02012041) ); +CONST_UINT64_T( PCIE0_IO_BAR2_0x02012042 , ULL(0x02012042) ); +CONST_UINT64_T( PCIE0_IO_MASK0_0x02012043 , ULL(0x02012043) ); +CONST_UINT64_T( PCIE0_IO_MASK1_0x02012044 , ULL(0x02012044) ); +CONST_UINT64_T( PCIE0_IO_BAR_EN_0x02012045 , ULL(0x02012045) ); + +CONST_UINT64_T( PCIE1_NODAL_BAR0_0x02012410 , ULL(0x02012410) ); +CONST_UINT64_T( PCIE1_NODAL_BAR1_0x02012411 , ULL(0x02012411) ); +CONST_UINT64_T( PCIE1_GROUP_BAR0_0x02012412 , ULL(0x02012412) ); +CONST_UINT64_T( PCIE1_GROUP_BAR1_0x02012413 , ULL(0x02012413) ); +CONST_UINT64_T( PCIE1_NEAR_BAR_F0_0x02012414 , ULL(0x02012414) ); +CONST_UINT64_T( PCIE1_FAR_BAR_F0_0x02012415 , ULL(0x02012415) ); +CONST_UINT64_T( PCIE1_NEAR_BAR_F1_0x02012416 , ULL(0x02012416) ); +CONST_UINT64_T( PCIE1_FAR_BAR_F1_0x02012417 , ULL(0x02012417) ); +CONST_UINT64_T( PCIE1_IO_BAR0_0x02012440 , ULL(0x02012440) ); +CONST_UINT64_T( PCIE1_IO_BAR1_0x02012441 , ULL(0x02012441) ); +CONST_UINT64_T( PCIE1_IO_BAR2_0x02012442 , ULL(0x02012442) ); +CONST_UINT64_T( PCIE1_IO_MASK0_0x02012443 , ULL(0x02012443) ); +CONST_UINT64_T( PCIE1_IO_MASK1_0x02012444 , ULL(0x02012444) ); +CONST_UINT64_T( PCIE1_IO_BAR_EN_0x02012445 , ULL(0x02012445) ); + +CONST_UINT64_T( PCIE2_NODAL_BAR0_0x02012810 , ULL(0x02012810) ); +CONST_UINT64_T( PCIE2_NODAL_BAR1_0x02012811 , ULL(0x02012811) ); +CONST_UINT64_T( PCIE2_GROUP_BAR0_0x02012812 , ULL(0x02012812) ); +CONST_UINT64_T( PCIE2_GROUP_BAR1_0x02012813 , ULL(0x02012813) ); +CONST_UINT64_T( PCIE2_NEAR_BAR_F0_0x02012814 , ULL(0x02012814) ); +CONST_UINT64_T( PCIE2_FAR_BAR_F0_0x02012815 , ULL(0x02012815) ); +CONST_UINT64_T( PCIE2_NEAR_BAR_F1_0x02012816 , ULL(0x02012816) ); +CONST_UINT64_T( PCIE2_FAR_BAR_F1_0x02012817 , ULL(0x02012817) ); +CONST_UINT64_T( PCIE2_IO_BAR0_0x02012840 , ULL(0x02012840) ); +CONST_UINT64_T( PCIE2_IO_BAR1_0x02012841 , ULL(0x02012841) ); +CONST_UINT64_T( PCIE2_IO_BAR2_0x02012842 , ULL(0x02012842) ); +CONST_UINT64_T( PCIE2_IO_MASK0_0x02012843 , ULL(0x02012843) ); +CONST_UINT64_T( PCIE2_IO_MASK1_0x02012844 , ULL(0x02012844) ); +CONST_UINT64_T( PCIE2_IO_BAR_EN_0x02012845 , ULL(0x02012845) ); + +//------------------------------------------------------------------------------ +// NX +//------------------------------------------------------------------------------ +CONST_UINT64_T( NX_APC_NODAL_BAR0_0x0201302D , ULL(0x0201302D) ); +CONST_UINT64_T( NX_APC_NODAL_BAR1_0x0201302E , ULL(0x0201302E) ); +CONST_UINT64_T( NX_APC_GROUP_BAR0_0x0201302F , ULL(0x0201302F) ); +CONST_UINT64_T( NX_APC_GROUP_BAR1_0x02013030 , ULL(0x02013030) ); +CONST_UINT64_T( NX_APC_NEAR_BAR_F0_0x02013031 , ULL(0x02013031) ); +CONST_UINT64_T( NX_APC_FAR_BAR_F0_0x02013032 , ULL(0x02013032) ); +CONST_UINT64_T( NX_APC_NEAR_BAR_F1_0x02013033 , ULL(0x02013033) ); +CONST_UINT64_T( NX_APC_FAR_BAR_F1_0x02013034 , ULL(0x02013034) ); +CONST_UINT64_T( NX_MMIO_BAR_0x0201308D , ULL(0x0201308D) ); +CONST_UINT64_T( NX_NODAL_BAR0_0x02013095 , ULL(0x02013095) ); +CONST_UINT64_T( NX_NODAL_BAR1_0x02013096 , ULL(0x02013096) ); +CONST_UINT64_T( NX_GROUP_BAR0_0x02013097 , ULL(0x02013097) ); +CONST_UINT64_T( NX_GROUP_BAR1_0x02013098 , ULL(0x02013098) ); +CONST_UINT64_T( NX_NEAR_BAR_F0_0x02013099 , ULL(0x02013099) ); +CONST_UINT64_T( NX_FAR_BAR_F0_0x0201309A , ULL(0x0201309A) ); +CONST_UINT64_T( NX_NEAR_BAR_F1_0x0201309B , ULL(0x0201309B) ); +CONST_UINT64_T( NX_FAR_BAR_F1_0x0201309C , ULL(0x0201309C) ); + +//------------------------------------------------------------------------------ +// MCD +//------------------------------------------------------------------------------ +CONST_UINT64_T( MCD_CN00_0x0201340C , ULL(0x0201340C) ); +CONST_UINT64_T( MCD_CN01_0x0201340D , ULL(0x0201340D) ); +CONST_UINT64_T( MCD_CN10_0x0201340E , ULL(0x0201340E) ); +CONST_UINT64_T( MCD_CN11_0x0201340F , ULL(0x0201340F) ); /******************************************************************************/ @@ -563,6 +812,14 @@ CONST_UINT64_T( X_GP2_0x04000002 , ULL(0x04000002) ); CONST_UINT64_T( X_SCOM_0x04010000 , ULL(0x04010000) ); //------------------------------------------------------------------------------ +// X-BUS TRACE +//------------------------------------------------------------------------------ +CONST_UINT64_T( X_TRACE_DATA_HI_T0_0x04010400 , ULL(0x04010400) ); +CONST_UINT64_T( X_TRACE_DATA_LO_T0_0x04010401 , ULL(0x04010401) ); +CONST_UINT64_T( X_TRACE_DATA_HI_T1_0x04010800 , ULL(0x04010800) ); +CONST_UINT64_T( X_TRACE_DATA_LO_T1_0x04010801 , ULL(0x04010801) ); + +//------------------------------------------------------------------------------ // X-BUS CLOCK CONTROL //------------------------------------------------------------------------------ CONST_UINT64_T( X_OPCG_CNTL0_0x04030002 , ULL(0x04030002) ); @@ -613,6 +870,8 @@ CONST_UINT64_T( X_GP0_OR_0x04000005 , ULL(0x04000005) ); CONST_UINT64_T( X_GP3_0x040F0012 , ULL(0x040F0012) ); CONST_UINT64_T( X_GP3_AND_0x040F0013 , ULL(0x040F0013) ); CONST_UINT64_T( X_GP3_OR_0x040F0014 , ULL(0x040F0014) ); +// PLL lock information +CONST_UINT64_T( X_PLLLOCKREG_0x040F0019 , ULL(0x040F0019) ); //------------------------------------------------------------------------------ // X-BUS HANG DETECTION @@ -645,6 +904,12 @@ CONST_UINT64_T( A_GP2_0x08000002 , ULL(0x08000002) ); CONST_UINT64_T( A_SCOM_0x08010000 , ULL(0x08010000) ); //------------------------------------------------------------------------------ +// A-BUS TRACE +//------------------------------------------------------------------------------ +CONST_UINT64_T( A_TRACE_DATA_HI_0x08010400 , ULL(0x08010400) ); +CONST_UINT64_T( A_TRACE_DATA_LO_0x08010401 , ULL(0x08010401) ); + +//------------------------------------------------------------------------------ // A-BUS CLOCK CONTROL //------------------------------------------------------------------------------ CONST_UINT64_T( A_OPCG_CNTL0_0x08030002 , ULL(0x08030002) ); @@ -676,6 +941,12 @@ CONST_UINT64_T( A_PERV_LFIR_ACT0_0x08040010 , ULL(0x08040010) ); CONST_UINT64_T( A_PERV_LFIR_ACT1_0x08040011 , ULL(0x08040011) ); //------------------------------------------------------------------------------ +// PLL LOCK +//------------------------------------------------------------------------------ +// PLL lock information +CONST_UINT64_T( A_PLLLOCKREG_0x080F0019 , ULL(0x080F0019) ); + +//------------------------------------------------------------------------------ // A-BUS THERMAL //------------------------------------------------------------------------------ CONST_UINT64_T( A_THERM_0x08050000 , ULL(0x08050000) ); @@ -718,6 +989,9 @@ CONST_UINT64_T( PCIE_GP0_0x09000000 , ULL(0x09000000) ); CONST_UINT64_T( PCIE_GP1_0x09000001 , ULL(0x09000001) ); CONST_UINT64_T( PCIE_GP2_0x09000002 , ULL(0x09000002) ); +CONST_UINT64_T( PCIE_GP0_AND_0x09000004 , ULL(0x09000004) ); +CONST_UINT64_T( PCIE_GP0_OR_0x09000005 , ULL(0x09000005) ); + //------------------------------------------------------------------------------ // PCIE-BUS SCOM // ring 1 = trace @@ -733,6 +1007,19 @@ CONST_UINT64_T( PCIE_GP2_0x09000002 , ULL(0x09000002) ); CONST_UINT64_T( PCIE_SCOM_0x09010000 , ULL(0x09010000) ); //------------------------------------------------------------------------------ +// PCIE-BUS TRACE +//------------------------------------------------------------------------------ +CONST_UINT64_T( PCIE_TRACE_DATA_HI_0x09010400 , ULL(0x09010400) ); +CONST_UINT64_T( PCIE_TRACE_DATA_LO_0x09010401 , ULL(0x09010401) ); + +//------------------------------------------------------------------------------ +// PCIE-BUS BARS +//------------------------------------------------------------------------------ +CONST_UINT64_T( PCIE0_ASB_BAR_0x0901200B , ULL(0x0901200B) ); +CONST_UINT64_T( PCIE1_ASB_BAR_0x0901240B , ULL(0x0901240B) ); +CONST_UINT64_T( PCIE2_ASB_BAR_0x0901280B , ULL(0x0901280B) ); + +//------------------------------------------------------------------------------ // PCIE-BUS CLOCK CONTROL //------------------------------------------------------------------------------ CONST_UINT64_T( PCIE_OPCG_CNTL0_0x09030002 , ULL(0x09030002) ); @@ -764,6 +1051,12 @@ CONST_UINT64_T( PCIE_PERV_LFIR_ACT0_0x09040010 , ULL(0x09040010) ); CONST_UINT64_T( PCIE_PERV_LFIR_ACT1_0x09040011 , ULL(0x09040011) ); //------------------------------------------------------------------------------ +// PLL LOCK +//------------------------------------------------------------------------------ +// PLL lock information +CONST_UINT64_T( PCIE_PLLLOCKREG_0x090F0019 , ULL(0x090F0019) ); + +//------------------------------------------------------------------------------ // PCIE-BUS THERMAL //------------------------------------------------------------------------------ CONST_UINT64_T( PCIE_THERM_0x09050000 , ULL(0x09050000) ); @@ -820,6 +1113,8 @@ CONST_UINT64_T( EX15_CHIPLET_0x1F000000 , ULL(0x1F000000) ); // EX GPIO //------------------------------------------------------------------------------ CONST_UINT64_T( EX_GP0_0x10000000 , ULL(0x10000000) ); +CONST_UINT64_T( EX_GP0_AND_0x10000004 , ULL(0x10000004) ); +CONST_UINT64_T( EX_GP0_OR_0x10000005 , ULL(0x10000005) ); CONST_UINT64_T( EX_GP1_0x10000001 , ULL(0x10000001) ); CONST_UINT64_T( EX_GP2_0x10000002 , ULL(0x10000002) ); @@ -836,18 +1131,41 @@ CONST_UINT64_T( EX_GP2_0x10000002 , ULL(0x10000002) ); // ring 12 = PC // ring 15 = PC sec //------------------------------------------------------------------------------ -//ECO Trace -CONST_UINT64_T( EX_ECO_TRACE0_0x10010400 , ULL(0x10010400) ); -CONST_UINT64_T( EX_ECO_TRACE1_0x10010401 , ULL(0x10010401) ); //L3 CONST_UINT64_T( EX_L3_MODE_REG1_0x1001080A , ULL(0x1001080A) ); CONST_UINT64_T( EX_L3_MODE_REG0_0x1001082B , ULL(0x1001082B) ); //L2 +CONST_UINT64_T( EX_L2_FIR_REG_0x10012800 , ULL(0x10012800) ); +CONST_UINT64_T( EX_L2_CERRS_REG0_0x10012815 , ULL(0x10012815) ); +CONST_UINT64_T( EX_L2_CERRS_REG1_0x10012816 , ULL(0x10012816) ); CONST_UINT64_T( EX_L2_MODE_REG0_0x1001280A , ULL(0x1001280A) ); CONST_UINT64_T( EX_L2_PURGE_CMD_PRD_0x1001280E , ULL(0x1001280E) ); CONST_UINT64_T( EX_L2_PURGE_CMD_PHYP_0x1001280F , ULL(0x1001280F) ); //------------------------------------------------------------------------------ +// EX/CORE TRACE +//------------------------------------------------------------------------------ +CONST_UINT64_T( EX_TRACE_DATA_HI_ECO_0x10010400 , ULL(0x10010400) ); +CONST_UINT64_T( EX_TRACE_DATA_LO_ECO_0x10010401 , ULL(0x10010401) ); +CONST_UINT64_T( EX_TRACE_DATA_HI_L2_T0_0x10012000 , ULL(0x10012000) ); +CONST_UINT64_T( EX_TRACE_DATA_LO_L2_T0_0x10012001 , ULL(0x10012001) ); +CONST_UINT64_T( EX_TRACE_DATA_HI_L2_T1_0x10012400 , ULL(0x10012400) ); +CONST_UINT64_T( EX_TRACE_DATA_LO_L2_T1_0x10012401 , ULL(0x10012401) ); +CONST_UINT64_T( EX_TRACE_DATA_HI_CORE_T0_0x10012C00 , ULL(0x10012C00) ); +CONST_UINT64_T( EX_TRACE_DATA_LO_CORE_T0_0x10012C01 , ULL(0x10012C01) ); +CONST_UINT64_T( EX_TRACE_DATA_HI_CORE_T1_0x10012C40 , ULL(0x10012C40) ); +CONST_UINT64_T( EX_TRACE_DATA_LO_CORE_T1_0x10012C41 , ULL(0x10012C41) ); +CONST_UINT64_T( EX_TRACE_DATA_HI_CORE_T2_0x10012C80 , ULL(0x10012C80) ); +CONST_UINT64_T( EX_TRACE_DATA_LO_CORE_T2_0x10012C81 , ULL(0x10012C81) ); +CONST_UINT64_T( EX_TRACE_DATA_HI_CORE_T3_0x10012CC0 , ULL(0x10012CC0) ); +CONST_UINT64_T( EX_TRACE_DATA_LO_CORE_T3_0x10012CC1 , ULL(0x10012CC1) ); +CONST_UINT64_T( EX_TRACE_DATA_HI_CORE_T4_0x10012D00 , ULL(0x10012D00) ); +CONST_UINT64_T( EX_TRACE_DATA_LO_CORE_T4_0x10012D01 , ULL(0x10012D01) ); +CONST_UINT64_T( EX_TRACE_DATA_HI_CORE_T5_0x10012D40 , ULL(0x10012D40) ); +CONST_UINT64_T( EX_TRACE_DATA_LO_CORE_T5_0x10012D41 , ULL(0x10012D41) ); +CONST_UINT64_T( EX_CORE_DIRECT_DEBUG_CTL_0x100132AF , ULL(0x100132AF) ); + +//------------------------------------------------------------------------------ // EX/CORE PERVASIVE THREAD CONTROLS // (chiplet/core set by P0 register) //------------------------------------------------------------------------------ @@ -861,6 +1179,16 @@ CONST_UINT64_T( EX_PERV_TCTL5_DIRECT_0x10013050 , ULL(0x10013050) ); CONST_UINT64_T( EX_PERV_TCTL6_DIRECT_0x10013060 , ULL(0x10013060) ); CONST_UINT64_T( EX_PERV_TCTL7_DIRECT_0x10013070 , ULL(0x10013070) ); +// TCTL RAS Mode (for each thread) +CONST_UINT64_T( EX_PERV_TCTL0_R_MODE_0x10013001 , ULL(0x10013001) ); +CONST_UINT64_T( EX_PERV_TCTL1_R_MODE_0x10013011 , ULL(0x10013011) ); +CONST_UINT64_T( EX_PERV_TCTL2_R_MODE_0x10013021 , ULL(0x10013021) ); +CONST_UINT64_T( EX_PERV_TCTL3_R_MODE_0x10013031 , ULL(0x10013031) ); +CONST_UINT64_T( EX_PERV_TCTL4_R_MODE_0x10013041 , ULL(0x10013041) ); +CONST_UINT64_T( EX_PERV_TCTL5_R_MODE_0x10013051 , ULL(0x10013051) ); +CONST_UINT64_T( EX_PERV_TCTL6_R_MODE_0x10013061 , ULL(0x10013061) ); +CONST_UINT64_T( EX_PERV_TCTL7_R_MODE_0x10013071 , ULL(0x10013071) ); + // TCTL RAS Status (for each thread) CONST_UINT64_T( EX_PERV_TCTL0_R_STAT_0x10013002 , ULL(0x10013002) ); CONST_UINT64_T( EX_PERV_TCTL1_R_STAT_0x10013012 , ULL(0x10013012) ); @@ -871,10 +1199,41 @@ CONST_UINT64_T( EX_PERV_TCTL5_R_STAT_0x10013052 , ULL(0x10013052) ); CONST_UINT64_T( EX_PERV_TCTL6_R_STAT_0x10013062 , ULL(0x10013062) ); CONST_UINT64_T( EX_PERV_TCTL7_R_STAT_0x10013072 , ULL(0x10013072) ); +// Thread Active Status +CONST_UINT64_T( EX_PERV_THREAD_ACTIVE_0x1001310E , ULL(0x1001310E) ); + +// RAM Registers +CONST_UINT64_T( EX_PERV_RAM_MODE_0x10013C00 , ULL(0x10013C00) ); +CONST_UINT64_T( EX_PERV_RAM_CTRL_0x10013C01 , ULL(0x10013C01) ); +CONST_UINT64_T( EX_PERV_RAM_STAT_0x10013C02 , ULL(0x10013C02) ); + +// SPRC/SPRD/Scratch +CONST_UINT64_T( EX_PERV_L0_SCOM_SPRC_10013280 , ULL(0x10013280) ); +CONST_UINT64_T( EX_PERV_SPR_MODE_10013281 , ULL(0x10013281) ); +CONST_UINT64_T( EX_PERV_SCRATCH0_10013283 , ULL(0x10013283) ); +CONST_UINT64_T( EX_PERV_SCRATCH1_10013284 , ULL(0x10013284) ); +CONST_UINT64_T( EX_PERV_SCRATCH2_10013285 , ULL(0x10013285) ); +CONST_UINT64_T( EX_PERV_SCRATCH3_10013286 , ULL(0x10013286) ); +CONST_UINT64_T( EX_PERV_SCRATCH4_10013287 , ULL(0x10013287) ); +CONST_UINT64_T( EX_PERV_SCRATCH5_10013288 , ULL(0x10013288) ); +CONST_UINT64_T( EX_PERV_SCRATCH6_10013289 , ULL(0x10013289) ); +CONST_UINT64_T( EX_PERV_SCRATCH7_1001328A , ULL(0x1001328A) ); + //------------------------------------------------------------------------------ // EX OHA //------------------------------------------------------------------------------ CONST_UINT64_T( EX_SCOM_0x10020000 , ULL(0x10020000) ); +CONST_UINT64_T( EX_OHA_ACTIVITY_SAMPLE_MODE_REG_RWx10020000 , ULL(0x10020000) ); +CONST_UINT64_T( EX_OHA_LOW_ACTIVITY_DETECT_MODE_REG_RWx10020003 , ULL(0x10020003) ); +CONST_UINT64_T( EX_OHA_PROXY_REG_0x10020006 , ULL(0x10020006) ); +CONST_UINT64_T( EX_OHA_PROXY_LEGACY_REG_0x10020007 , ULL(0x10020007) ); +CONST_UINT64_T( EX_OHA_SKITTER_CTRL_MODE_REG_0x10020008 , ULL(0x10020008) ); +CONST_UINT64_T( EX_OHA_CPM_CTRL_REG_0x1002000A , ULL(0x1002000A) ); +CONST_UINT64_T( EX_OHA_RO_STATUS_REG_0x1002000B , ULL(0x1002000B) ); +CONST_UINT64_T( EX_OHA_MODE_REG_RWx1002000D , ULL(0x1002000D) ); +CONST_UINT64_T( EX_OHA_ERROR_ERROR_MASK_REG_RWx1002000E , ULL(0x1002000E) ); +CONST_UINT64_T( EX_OHA_ARCH_IDLE_STATE_REG_RWx10020011 , ULL(0x10020011) ); +CONST_UINT64_T( EX_OHA_AISS_IO_REG_0x10020014 , ULL(0x10020014) ); //------------------------------------------------------------------------------ // EX CLOCK CONTROL @@ -916,19 +1275,21 @@ CONST_UINT64_T( EX_THERM_0x10050000 , ULL(0x10050000) ); // EX PCB SLAVE //------------------------------------------------------------------------------ //Generic names (need to add in (cuTarget.chipUnitNum * 0x01000000)) when being used +// special wakeup registers +CONST_UINT64_T( PM_SPECIAL_WKUP_FSP_0x100F010B , ULL(0x100F010B) ); +CONST_UINT64_T( PM_SPECIAL_WKUP_OCC_0x100F010C , ULL(0x100F010C) ); +CONST_UINT64_T( PM_SPECIAL_WKUP_PHYP_0x100F010D , ULL(0x100F010D) ); + //Multicast Group Registers CONST_UINT64_T( EX_MCGR1_0x100F0001 , ULL(0x100F0001) ); CONST_UINT64_T( EX_MCGR2_0x100F0002 , ULL(0x100F0002) ); CONST_UINT64_T( EX_MCGR3_0x100F0003 , ULL(0x100F0003) ); CONST_UINT64_T( EX_MCGR4_0x100F0004 , ULL(0x100F0004) ); + //GP3 Register CONST_UINT64_T( EX_GP3_0x100F0012 , ULL(0x100F0012) ); CONST_UINT64_T( EX_GP3_AND_0x100F0013 , ULL(0x100F0013) ); CONST_UINT64_T( EX_GP3_OR_0x100F0014 , ULL(0x100F0014) ); -//PMGP0 Register -CONST_UINT64_T( EX_PMGP0_0x100F0100 , ULL(0x100F0100) ); -CONST_UINT64_T( EX_PMGP0_AND_0x100F0101 , ULL(0x100F0101) ); -CONST_UINT64_T( EX_PMGP0_OR_0x100F0102 , ULL(0x100F0102) ); //Chiplet specific names (probably won't ever be used) CONST_UINT64_T( EX00_GP3_0x100F0012 , ULL(0x100F0012) ); @@ -999,35 +1360,81 @@ CONST_UINT64_T( EX15_GP3_OR_0x1F0F0014 , ULL(0x1F0F0014) ); // EX PCB SLAVE PM //------------------------------------------------------------------------------ //Generic names (need to add in (cuTarget.chipUnitNum * 0x01000000)) when being used +//PMGP0 Register +CONST_UINT64_T( EX_PMGP0_0x100F0100 , ULL(0x100F0100) ); +CONST_UINT64_T( EX_PMGP0_AND_0x100F0101 , ULL(0x100F0101) ); +CONST_UINT64_T( EX_PMGP0_OR_0x100F0102 , ULL(0x100F0102) ); +//PMGP1 Register +CONST_UINT64_T( EX_PMGP1_0x100F0103 , ULL(0x100F0103) ); +CONST_UINT64_T( EX_PMGP1_AND_0x100F0104 , ULL(0x100F0104) ); +CONST_UINT64_T( EX_PMGP1_OR_0x100F0105 , ULL(0x100F0105) ); + +CONST_UINT64_T( EX_PFET_CTL_REG_0x100F0106 , ULL(0x100F0106) ); +CONST_UINT64_T( EX_PFET_STAT_REG_0x100F0107 , ULL(0x100F0107) ); +CONST_UINT64_T( EX_PFET_CTL_REG_0x100F010E , ULL(0x100F010E) ); + CONST_UINT64_T( EX_IDLEGOTO_0x100F0114 , ULL(0x100F0114) ); CONST_UINT64_T( EX_FREQCNTL_0x100F0151 , ULL(0x100F0151) ); +CONST_UINT64_T( EX_PMGP1_REG_0_RWXx100F0103 , ULL(0x100F0103) ); +CONST_UINT64_T( EX_PMGP1_REG_0_WANDx100F0104 , ULL(0x100F0104) ); +CONST_UINT64_T( EX_PMGP1_REG_0_WORx100F0105 , ULL(0x100F0105) ); +CONST_UINT64_T( EX_PFVddCntlStat_REG_0x100F0106 , ULL(0x100F0106) ); +CONST_UINT64_T( EX_PFVcsCntlStat_REG_0x100F010E , ULL(0x100F010E) ); +CONST_UINT64_T( EX_PMErrMask_REG_0x100F010A , ULL(0x100F010A) ); +CONST_UINT64_T( EX_PMSpcWkupFSP_REG_0x100F010B , ULL(0x100F010B) ); +CONST_UINT64_T( EX_PMSpcWkupOCC_REG_0x100F010C , ULL(0x100F010C) ); +CONST_UINT64_T( EX_PMSpcWkupPHYP_REG_0x100F010D , ULL(0x100F010D) ); +CONST_UINT64_T( EX_PMSTATEHISTPHYP_REG_0x100F0110 , ULL(0x100F0110) ); +CONST_UINT64_T( EX_PMSTATEHISTFSP_REG_0x100F0111 , ULL(0x100F0111) ); +CONST_UINT64_T( EX_PMSTATEHISTOCC_REG_0x100F0112 , ULL(0x100F0112) ); +CONST_UINT64_T( EX_PMSTATEHISTPERF_REG_0x100F0113 , ULL(0x100F0113) ); +CONST_UINT64_T( EX_IdleFSMGotoCmd_REG_0x100F0114 , ULL(0x100F0114) ); +CONST_UINT64_T( EX_CorePFPUDly_REG_0x100F012C , ULL(0x100F012C) ); +CONST_UINT64_T( EX_CorePFPDDly_REG_0x100F012D , ULL(0x100F012D) ); +CONST_UINT64_T( EX_CorePFVRET_REG_0x100F0130 , ULL(0x100F0130) ); +CONST_UINT64_T( EX_ECOPFPUDly_REG_0x100F014C , ULL(0x100F014C) ); +CONST_UINT64_T( EX_ECOPFPDDly_REG_0x100F014D , ULL(0x100F014D) ); +CONST_UINT64_T( EX_ECOPFVRET_REG_0x100F0150 , ULL(0x100F0150) ); +CONST_UINT64_T( EX_DPLL_CPM_PARM_REG_0x100F0152 , ULL(0x100F0152) ); +CONST_UINT64_T( EX_PCBS_POWER_MANAGEMENT_STATUS_REG_0x100F0153 , ULL(0x100F0153) ); //ROX +CONST_UINT64_T( EX_PCBS_iVRM_Control_Status_Reg_0x100F0154 , ULL(0x100F0154) ); +CONST_UINT64_T( EX_PCBS_iVRM_Value_Setting_Reg_0x100F0155 , ULL(0x100F0155) ); +CONST_UINT64_T( EX_PCBSPM_MODE_REG_0x100F0156 , ULL(0x100F0156) ); +CONST_UINT64_T( EX_PCBS_iVRM_PFETSTR_Sense_Reg_0x100F0157 , ULL(0x100F0157) ); +CONST_UINT64_T( EX_PCBS_Power_Management_Idle_Control_Reg_0x100F0158 , ULL(0x100F0158) ); +CONST_UINT64_T( EX_PCBS_Power_Management_Control_Reg_0x100F0159 , ULL(0x100F0159) ); +CONST_UINT64_T( EX_PCBS_PMC_VF_CTRL_REG_0x100F015A , ULL(0x100F015A) ); +CONST_UINT64_T( EX_PCBS_UNDERVOLTING_REG_0x100F015B , ULL(0x100F015B) ); +CONST_UINT64_T( EX_PCBS_Pstate_Index_Bound_Reg_0x100F015C , ULL(0x100F015C) ); +CONST_UINT64_T( EX_PCBS_Power_Management_Bounds_Reg_0x100F015D , ULL(0x100F015D) ); +CONST_UINT64_T( EX_PCBS_PSTATE_TABLE_CTRL_REG_0x100F015E , ULL(0x100F015E) ); +CONST_UINT64_T( EX_PCBS_PSTATE_TABLE_REG_0x100F015F , ULL(0x100F015F) ); +CONST_UINT64_T( EX_PCBS_Pstate_Step_Target_Register_0x100F0160 , ULL(0x100F0160) ); +CONST_UINT64_T( EX_PCBS_iVRM_VID_Control_Reg0_0x100F0162 , ULL(0x100F0162) ); +CONST_UINT64_T( EX_PCBS_iVRM_VID_Control_Reg1_0x100F0163 , ULL(0x100F0163) ); +CONST_UINT64_T( EX_PCBS_OCC_Heartbeat_Reg_0x100F0164 , ULL(0x100F0164) ); +CONST_UINT64_T( EX_PCBS_Resonant_Clock_Control_Reg0_0x100F0165 , ULL(0x100F0165) ); +CONST_UINT64_T( EX_PCBS_Resonant_Clock_Control_Reg1_0x100F0166 , ULL(0x100F0166) ); +CONST_UINT64_T( EX_PCBS_Resonant_Clock_Status_Reg_0x100F0167 , ULL(0x100F0167) ); +CONST_UINT64_T( EX_PCBS_Local_Pstate_Frequency_Target_Control_Register_0x100F0168 , ULL(0x100F0168) ); +CONST_UINT64_T( EX_PCBS_FSM_MONITOR2_REG_0x100F0171 , ULL(0x100F0171) ); + +//------------------------------------------------------------------------------ +// MULTICAST REGISTER DEFINITION +//------------------------------------------------------------------------------ +CONST_UINT64_T( EX_WRITE_ALL_EX_PMGP1_REG_0_RWx690F0103 , ULL(0x690F0103) ); // PM GP1 Multicast Group1 +CONST_UINT64_T( EX_WRITE_ALL_EX_PMGP1_REG_0_WANDx690F0104 , ULL(0x690F0104) ); // PM GP1 Multicast Group1 +CONST_UINT64_T( EX_WRITE_ALL_EX_PMGP1_REG_0_WORx690F0105 , ULL(0x690F0105) ); // PM GP1 Multicast Group1 +CONST_UINT64_T( EX_WRITE_ALL_PCBSPM_MODE_REG_0x690F0156 , ULL(0x690F0156) ); // PCBSLV Mode Multicast Group1 +CONST_UINT64_T( EX_WRITE_ALL_PCBS_Power_Management_Bounds_Reg_0x690F015D , ULL(0x690F015D) ); // PCBSLV PM Bounds Multicast Group1 + //******************************************************************************/ //********* MULTICAST REGISTER DEFINITIONS FOR PERVASIVE INITs ****************/ //******************************************************************************/ -CONST_UINT64_T( READ_ALL_GP0_0x43000000 , ULL(0x43000000) ); // all GP0 but not PRV -CONST_UINT64_T( WRITE_ALL_GP0_0x6B000000 , ULL(0x6B000000) ); // all GP0 but not PRV -CONST_UINT64_T( WRITE_ALL_GP0_AND_0x6B000004 , ULL(0x6B000004) ); // all GP0 AND but not PRV -CONST_UINT64_T( WRITE_ALL_GP0_OR_0x6B000005 , ULL(0x6B000005) ); // all GP0 OR but not PRV - -CONST_UINT64_T( READ_ALL_GP1_AND_0x4B000001 , ULL(0x4B000001) ); // and all GP1 but not PRV - -CONST_UINT64_T( WRITE_ALL_CLK_REGION_0x6B030006 , ULL(0x6B030006) ); // all GP3 but not PRV - -CONST_UINT64_T( READ_ALL_OPCG_CNTL0_0x43030002 , ULL(0x43030002) ); // all EX OPCG0 -CONST_UINT64_T( WRITE_ALL_OPCG_CNTL0_0x6B030002 , ULL(0x6B030002) ); // all EX OPCG0 - -CONST_UINT64_T( READ_ALL_OPCG_CNTL2_0x43030004 , ULL(0x43030004) ); // all OPCG2 but not PRV -CONST_UINT64_T( WRITE_ALL_OPCG_CNTL2_0x6B030004 , ULL(0x6B030004) ); // all OPCG2 but not PRV - -CONST_UINT64_T( READ_ALL_FUNC_GP3_0x430F0012 , ULL(0x430F0012) ); // all GP3 but not PRV -CONST_UINT64_T( WRITE_ALL_FUNC_GP3_0x6B0F0012 , ULL(0x6B0F0012) ); // all GP3 but not PRV -CONST_UINT64_T( WRITE_ALL_FUNC_GP3_AND_0x6B0F0013 , ULL(0x6B0F0013) ); // all GP3 but not PRV -CONST_UINT64_T( WRITE_ALL_FUNC_GP3_OR_0x6B0F0014 , ULL(0x6B0F0014) ); // all GP3 but not PRV - CONST_UINT64_T( WRITE_ALL_HPRE0_0x690F0020 , ULL(0x690F0020) ); // hang pulse register 0 CONST_UINT64_T( WRITE_ALL_HPRE1_0x690F0021 , ULL(0x690F0021) ); // hang pulse register 1 CONST_UINT64_T( WRITE_ALL_HPRE2_0x690F0022 , ULL(0x690F0022) ); // hang pulse register 2 @@ -1035,8 +1442,7 @@ CONST_UINT64_T( WRITE_ALL_HPCRE_0x690F0028 , ULL(0x690F0028) ); CONST_UINT64_T( WRITE_EX_PMGP0_AND_0x690F0101 , ULL(0x690F0101) ); // PM GP0 initialization -CONST_UINT64_T( SLAVE_PCB_ERR_0x6B0F001F , ULL(0x6B0F001F) ); - +// other multicast constants were moved to common_scom_addresses.H 1/24/2010 mfred #endif @@ -1047,6 +1453,107 @@ This section is automatically updated by CVS when you check in this file. Be sure to create CVS comments when you commit so that they can be included here. $Log: p8_scom_addresses.H,v $ +Revision 1.82 2012/06/27 07:43:32 rkoester +add remaining PLLLOCK register + +Revision 1.80 2012/06/20 14:49:32 rkoester +add plllock register + +Revision 1.79 2012/06/17 20:26:00 jmcgill +update trace SCOM addresses + +Revision 1.78 2012/06/17 19:00:37 jmcgill +add core direct debug control register + +Revision 1.77 2012/06/09 19:24:39 jmcgill +add ADU BAR registers + +Revision 1.76 2012/06/05 06:03:04 jmcgill +add ADU XSCOM BAR register + +Revision 1.75 2012/06/01 02:45:26 jmcgill +updates for MCS registers + +Revision 1.74 2012/05/30 12:28:52 kgungl +issues resolved: scom addresses for pba + +Revision 1.73 2012/05/23 16:31:18 karm +added EX core RAS_MODE + +Revision 1.72 2012/05/23 11:04:28 pchatnah +updating pss spivid spwkup registers + +Revision 1.71 2012/05/18 17:59:24 jmcgill +add addresses for proc_setup_bars + +Revision 1.70 2012/05/11 21:15:05 jeshua +Added EX_PCBS_FSM_MONITOR2_REG + +Revision 1.69 2012/05/08 13:31:46 karm +changes to RAM registers in EX PC unit + +Revision 1.68 2012/05/08 11:55:20 stillgs +Added some additional PCBS-PM addresses + +Revision 1.67 2012/05/03 21:36:59 karm +added core thread_active + +Revision 1.66 2012/05/02 21:37:42 jeshua +Added ECID_PART_0 and ECID_PART_1 + +Revision 1.65 2012/05/01 14:30:39 stillgs +Add additional OHA registers + +Revision 1.64 2012/04/27 14:48:20 rmaier +Added RESCLK_status_reg + +Revision 1.63 2012/04/26 22:47:18 karm +added EX_PERV registers for ram and thread ctrl + +Revision 1.62 2012/04/16 23:55:37 bcbrock +Corrected problems related to C/C++ and 32-bit/64-bit portability and Host +Boot after initial review by FW team. + +o Renamed fapi_sbe_common.h to fapi_sbe_common.H +o Renamed p8_scan_compression.[ch] to .[CH] since these are for use by C++ + procedures only (no requirement to execute on OCC). +o Modified sbe_xip_image.c to use the C99 standard way to print uint64_t + variables. +o Added __cplusplus guards to sbe_xip_image.h + +Revision 1.61 2012/04/09 22:35:14 jeshua +Added L2 FIR and CERR registers + +Revision 1.60 2012/03/21 08:15:53 rmaier +Added OHA_ARCH_IDLE_STATE_REG + +Revision 1.59 2012/03/14 11:50:03 stillgs +Added PMC O2S and SPIVID control regs for use by proc_pmc_init.C and proc_sbe_set_pvid.S + +Revision 1.58 2012/03/02 21:41:45 jimyac +added additional OCB Indirect Channel 0-3 Registers + +Revision 1.57 2012/03/01 16:09:20 rmaier +Added PCBS/OHA constants + +Revision 1.56 2012/02/29 22:57:24 bcbrock +Added PIBMEM control registers to p8_scom_addresses.H + +Revision 1.55 2012/02/10 23:09:52 jmcgill +add trace array addresses + +Revision 1.54 2012/01/30 16:08:40 jimyac +added OCC SRAM Boot Vector0-3 registers + +Revision 1.53 2012/01/30 15:59:43 jimyac +added ocb channel0-3 push & pull register and fixed typo in ocb addressed where address in variable name did not match actual address value + +Revision 1.52 2012/01/24 21:59:42 mfred +Moved common multicast address constants to common_scom_accresses.H + +Revision 1.51 2012/01/18 12:55:03 koenig +Added PBA clock sync reg + Revision 1.50 2012/01/06 22:20:53 jmcgill move shared/common addresses to common_scom_addresses.H, general cleanup diff --git a/src/usr/hwpf/hwp/makefile b/src/usr/hwpf/hwp/makefile index 4437d463a..10c52e219 100644 --- a/src/usr/hwpf/hwp/makefile +++ b/src/usr/hwpf/hwp/makefile @@ -44,7 +44,6 @@ SUBDIRS = dmi_training.d sbe_centaur_init.d mc_init.d \ dram_training.d activate_powerbus.d build_winkle_images.d \ core_activate.d dram_initialization.d edi_ei_initialization.d \ establish_system_smp.d load_payload.d bus_training.d \ - nest_chiplets.d start_payload.d \ - thread_activate.d + nest_chiplets.d start_payload.d thread_activate.d slave_sbe.d include ${ROOTPATH}/config.mk diff --git a/src/usr/hwpf/hwp/nest_chiplets/makefile b/src/usr/hwpf/hwp/nest_chiplets/makefile index 245b6ebae..a91e42c04 100644 --- a/src/usr/hwpf/hwp/nest_chiplets/makefile +++ b/src/usr/hwpf/hwp/nest_chiplets/makefile @@ -22,7 +22,7 @@ # IBM_PROLOG_END_TAG ROOTPATH = ../../../../.. -MODULE = start_clocks_on_nest_chiplets +MODULE = nest_chiplets ## support for Targeting and fapi EXTRAINCDIR += ${ROOTPATH}/src/include/usr/ecmddatabuffer diff --git a/src/usr/hwpf/hwp/slave_sbe/makefile b/src/usr/hwpf/hwp/slave_sbe/makefile new file mode 100644 index 000000000..6788d7d5c --- /dev/null +++ b/src/usr/hwpf/hwp/slave_sbe/makefile @@ -0,0 +1,49 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/hwpf/hwp/slave_sbe/makefile $ +# +# IBM CONFIDENTIAL +# +# COPYRIGHT International Business Machines Corp. 2012 +# +# p1 +# +# Object Code Only (OCO) source materials +# Licensed Internal Code Source Materials +# IBM HostBoot Licensed Internal Code +# +# The source code for this program is not published or other- +# wise divested of its trade secrets, irrespective of what has +# been deposited with the U.S. Copyright Office. +# +# Origin: 30 +# +# IBM_PROLOG_END_TAG +ROOTPATH = ../../../../.. + +MODULE = slave_sbe + +## support for Targeting and fapi +EXTRAINCDIR += ${ROOTPATH}/src/include/usr/ecmddatabuffer +EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/fapi +EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/plat +EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp + +## pointer to common HWP files +EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/include + +## Include sub dirs +## NOTE: add a new EXTRAINCDIR when you add a new HWP +EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/slave_sbe +EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/slave_sbe/proc_revert_sbe_mcs_setup + +## NOTE: add new object files when you add a new HWP +OBJS = slave_sbe.o \ + proc_revert_sbe_mcs_setup.o + +## NOTE: add a new directory onto the vpaths when you add a new HWP +VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/slave_sbe/proc_revert_sbe_mcs_setup + +include ${ROOTPATH}/config.mk + diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_revert_sbe_mcs_setup/proc_revert_sbe_mcs_setup.C b/src/usr/hwpf/hwp/slave_sbe/proc_revert_sbe_mcs_setup/proc_revert_sbe_mcs_setup.C new file mode 100644 index 000000000..af93f6006 --- /dev/null +++ b/src/usr/hwpf/hwp/slave_sbe/proc_revert_sbe_mcs_setup/proc_revert_sbe_mcs_setup.C @@ -0,0 +1,224 @@ +/* IBM_PROLOG_BEGIN_TAG + * This is an automatically generated prolog. + * + * $Source: src/usr/hwpf/hwp/slave_sbe/proc_revert_sbe_mcs_setup/proc_revert_sbe_mcs_setup.C $ + * + * IBM CONFIDENTIAL + * + * COPYRIGHT International Business Machines Corp. 2012 + * + * p1 + * + * Object Code Only (OCO) source materials + * Licensed Internal Code Source Materials + * IBM HostBoot Licensed Internal Code + * + * The source code for this program is not published or other- + * wise divested of its trade secrets, irrespective of what has + * been deposited with the U.S. Copyright Office. + * + * Origin: 30 + * + * IBM_PROLOG_END_TAG + */ +// $Id: proc_revert_sbe_mcs_setup.C,v 1.2 2012/06/29 06:15:33 jmcgill Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_revert_sbe_mcs_setup.C,v $ +//------------------------------------------------------------------------------ +// *| +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +// *| +// *! TITLE : proc_revert_sbe_mcs_setup.C +// *! DESCRIPTION : Revert MCS configuration applied by SBE (FAPI) +// *! +// *! OWNER NAME : Joe McGill Email: jmcgill@us.ibm.com +// *! +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include "proc_revert_sbe_mcs_setup.H" + +extern "C" +{ + +//------------------------------------------------------------------------------ +// Function definitions +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +// function: reset MCFGP BAR valid bit, base address and size fields to restore +// register flush state +// parameters: i_target => MCS chiplet target +// returns: FAPI_RC_SUCCESS if register write is successful, +// else failing return code +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_revert_sbe_mcs_setup_reset_mcfgp( + const fapi::Target& i_target) +{ + fapi::ReturnCode rc; + uint32_t rc_ecmd = 0x0; + ecmdDataBufferBase mcfgp_data(64); + ecmdDataBufferBase mcfgp_mask(64); + + // mark function entry + FAPI_DBG("proc_revert_sbe_mcs_setup_reset_mcfgp: Start"); + + do + { + // clear fields manipulated by SBE (to restore logic flush state) + rc_ecmd |= mcfgp_mask.setBit(MCFGP_VALID_BIT); + rc_ecmd |= mcfgp_mask.setBit( + MCFGP_UNITS_PER_GROUP_START_BIT, + (MCFGP_UNITS_PER_GROUP_END_BIT - + MCFGP_UNITS_PER_GROUP_START_BIT + 1)); + rc_ecmd |= mcfgp_mask.setBit( + MCFGP_GROUP_MEMBER_ID_START_BIT, + (MCFGP_GROUP_MEMBER_ID_END_BIT - + MCFGP_GROUP_MEMBER_ID_START_BIT + 1)); + rc_ecmd |= mcfgp_mask.setBit( + MCFGP_GROUP_SIZE_START_BIT, + (MCFGP_GROUP_SIZE_END_BIT - + MCFGP_GROUP_SIZE_START_BIT + 1)); + rc_ecmd |= mcfgp_mask.setBit(MCFGP_FASTPATH_ENABLE_BIT); + rc_ecmd |= mcfgp_mask.setBit( + MCFGP_GROUP_BASE_ADDR_START_BIT, + (MCFGP_GROUP_BASE_ADDR_END_BIT - + MCFGP_GROUP_BASE_ADDR_START_BIT + 1)); + + // check buffer manipulation return code + if (rc_ecmd) + { + FAPI_ERR("proc_revert_sbe_mcs_setup_reset_mcfgp: Error 0x%X setting up MCFGP mask data buffer", + rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } + + // write register + rc = fapiPutScomUnderMask(i_target, + MCS_MCFGP_0x02011800, + mcfgp_data, + mcfgp_mask); + if (!rc.ok()) + { + FAPI_ERR("proc_revert_sbe_mcs_setup_reset_mcfgp: fapiPutScomUnderMask error (MCS_MCFGP_0x02011800)"); + break; + } + } while(0); + + // mark function exit + FAPI_DBG("proc_revert_sbe_mcs_setup_reset_mcfgp: End"); + return rc; +} + + +//------------------------------------------------------------------------------ +// function: set MCI FIR Mask channel timeout bit, to restore register flush +// state +// parameters: i_target => MCS chiplet target +// returns: FAPI_RC_SUCCESS if register write is successful, +// else failing return code +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_revert_sbe_mcs_setup_reset_mcifirmask( + const fapi::Target& i_target) +{ + fapi::ReturnCode rc; + uint32_t rc_ecmd = 0x0; + ecmdDataBufferBase mcifirmask_or_data(64); + + // mark function entry + FAPI_DBG("proc_revert_sbe_mcs_setup_reset_mcifirmask: Start"); + + do + { + // set fields manipulated by SBE (to restore logic flush state) + rc_ecmd |= mcifirmask_or_data.setBit( + MCIFIR_CL_TIMEOUT_DUE_TO_CHANNEL_BIT); + + // check buffer manipulation return code + if (rc_ecmd) + { + FAPI_ERR("proc_revert_sbe_mcs_setup_reset_mcifirmask: Error 0x%X setting up MCI FIR Mask register data buffer", + rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } + + // write register + rc = fapiPutScom(i_target, + MCS_MCIFIRMASK_OR_0x02011845, + mcifirmask_or_data); + if (!rc.ok()) + { + FAPI_ERR("proc_revert_sbe_mcs_setup_reset_mcifirmask: fapiPutScom error (MCS_MCIFIRMASK_OR_0x02011845)"); + break; + } + } while(0); + + // mark function exit + FAPI_DBG("proc_revert_sbe_mcs_setup_reset_mcifirmask: End"); + return rc; +} + + +//------------------------------------------------------------------------------ +// function: proc_revert_sbe_mcs_setup HWP entry point +// NOTE: see comments above function prototype in header +//------------------------------------------------------------------------------ +fapi::ReturnCode proc_revert_sbe_mcs_setup( + const fapi::Target& i_target) +{ + fapi::ReturnCode rc; + + // vector to hold MCS chiplet targets + std::vector<fapi::Target> mcs_chiplets; + + // mark HWP entry + FAPI_IMP("proc_revert_sbe_mcs_setup: Entering ..."); + + do + { + // loop over all functional MCS chiplets, revert SBE configuration + // of BAR/FIR mask registers back to flush state + rc = fapiGetChildChiplets(i_target, + fapi::TARGET_TYPE_MCS_CHIPLET, + mcs_chiplets, + fapi::TARGET_STATE_FUNCTIONAL); + if (!rc.ok()) + { + FAPI_ERR("proc_revert_sbe_mcs_setup: Error from fapiGetChildChiplets"); + break; + } + + for (std::vector<fapi::Target>::iterator i = mcs_chiplets.begin(); + i != mcs_chiplets.end(); + i++) + { + rc = proc_revert_sbe_mcs_setup_reset_mcfgp(*i); + if (!rc.ok()) + { + FAPI_ERR("proc_revert_sbe_mcs_setup: Error from proc_revert_sbe_mcs_setup_reset_mcfgp"); + break; + } + + rc = proc_revert_sbe_mcs_setup_reset_mcifirmask(*i); + if (!rc.ok()) + { + FAPI_ERR("proc_revert_sbe_mcs_setup: Error from proc_revert_sbe_mcs_setup_reset_mcfgp"); + break; + } + } + } while(0); + + // log function exit + FAPI_IMP("proc_revert_sbe_mcs_setup: Exiting ..."); + return rc; +} + + +} // extern "C" diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_revert_sbe_mcs_setup/proc_revert_sbe_mcs_setup.H b/src/usr/hwpf/hwp/slave_sbe/proc_revert_sbe_mcs_setup/proc_revert_sbe_mcs_setup.H new file mode 100644 index 000000000..f2aeb162b --- /dev/null +++ b/src/usr/hwpf/hwp/slave_sbe/proc_revert_sbe_mcs_setup/proc_revert_sbe_mcs_setup.H @@ -0,0 +1,108 @@ +/* IBM_PROLOG_BEGIN_TAG + * This is an automatically generated prolog. + * + * $Source: src/usr/hwpf/hwp/slave_sbe/proc_revert_sbe_mcs_setup/proc_revert_sbe_mcs_setup.H $ + * + * IBM CONFIDENTIAL + * + * COPYRIGHT International Business Machines Corp. 2012 + * + * p1 + * + * Object Code Only (OCO) source materials + * Licensed Internal Code Source Materials + * IBM HostBoot Licensed Internal Code + * + * The source code for this program is not published or other- + * wise divested of its trade secrets, irrespective of what has + * been deposited with the U.S. Copyright Office. + * + * Origin: 30 + * + * IBM_PROLOG_END_TAG + */ +// $Id: proc_revert_sbe_mcs_setup.H,v 1.1 2012/06/05 07:03:39 jmcgill Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_revert_sbe_mcs_setup.H,v $ +//------------------------------------------------------------------------------ +// *| +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +// *| +// *! TITLE : proc_revert_sbe_mcs_setup.H +// *! DESCRIPTION : Revert MCS configuration applied by SBE (FAPI) +// *! +// *! OWNER NAME : Joe McGill Email: jmcgill@us.ibm.com +// *! +// *! ADDITIONAL COMMENTS: +// *! +// *! Disable MCS configuration written by SBE to enable initial phase of +// *! HBI execution (providing lpc_ack for dcbz prior to initialization +// *! of memory). Registers touched by SBE (MCFGP, MCIFIRMASK) will be +// *! reset to flush state by this procedure. +// *! +//------------------------------------------------------------------------------ + +#ifndef _PROC_REVERT_SBE_MCS_SETUP_H_ +#define _PROC_REVERT_SBE_MCS_SETUP_H_ + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ + +#include <vector> +#include <fapi.H> +#include "p8_scom_addresses.H" + + +//------------------------------------------------------------------------------ +// Constant definitions +//------------------------------------------------------------------------------ + +// MCFGP register constants +const uint32_t MCFGP_VALID_BIT = 0; +const uint32_t MCFGP_UNITS_PER_GROUP_START_BIT = 1; +const uint32_t MCFGP_UNITS_PER_GROUP_END_BIT = 3; +const uint32_t MCFGP_GROUP_MEMBER_ID_START_BIT = 4; +const uint32_t MCFGP_GROUP_MEMBER_ID_END_BIT = 8; +const uint32_t MCFGP_GROUP_SIZE_START_BIT = 11; +const uint32_t MCFGP_GROUP_SIZE_END_BIT = 23; +const uint32_t MCFGP_FASTPATH_ENABLE_BIT = 25; +const uint32_t MCFGP_GROUP_BASE_ADDR_START_BIT = 26; +const uint32_t MCFGP_GROUP_BASE_ADDR_END_BIT = 43; + +// MCIFIR register constants +const uint32_t MCIFIR_CL_TIMEOUT_DUE_TO_CHANNEL_BIT = 28; + + +//------------------------------------------------------------------------------ +// Structure definitions +//------------------------------------------------------------------------------ + +// function pointer typedef definition for HWP call support +typedef fapi::ReturnCode +(*proc_revert_sbe_mcs_setup_FP_t)(const fapi::Target&); + + +extern "C" +{ + +//------------------------------------------------------------------------------ +// Function prototypes +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// function: disable MCS configuration written by SBE to enable initial phase of +// HBI execution (providing lpc_ack for dcbz prior to initialization +// of memory) +// parameters: i_target => P8 master chip target +// returns: FAPI_RC_SUCCESS if all register writes are successful, +// else failing return code +fapi::ReturnCode proc_revert_sbe_mcs_setup( + const fapi::Target& i_target); + + +} // extern "C" + + +#endif // _PROC_REVERT_SBE_MCS_SETUP_H_ diff --git a/src/usr/hwpf/hwp/slave_sbe/slave_sbe.C b/src/usr/hwpf/hwp/slave_sbe/slave_sbe.C new file mode 100644 index 000000000..295898233 --- /dev/null +++ b/src/usr/hwpf/hwp/slave_sbe/slave_sbe.C @@ -0,0 +1,107 @@ +/* IBM_PROLOG_BEGIN_TAG + * This is an automatically generated prolog. + * + * $Source: src/usr/hwpf/hwp/slave_sbe/slave_sbe.C $ + * + * IBM CONFIDENTIAL + * + * COPYRIGHT International Business Machines Corp. 2012 + * + * p1 + * + * Object Code Only (OCO) source materials + * Licensed Internal Code Source Materials + * IBM HostBoot Licensed Internal Code + * + * The source code for this program is not published or other- + * wise divested of its trade secrets, irrespective of what has + * been deposited with the U.S. Copyright Office. + * + * Origin: 30 + * + * IBM_PROLOG_END_TAG + */ +/** + * @file slave_sbe.C + * + * Support file for IStep: slave_sbe + * Slave SBE + */ + +/******************************************************************************/ +// Includes +/******************************************************************************/ +#include <stdint.h> + +#include <trace/interface.H> +#include <initservice/taskargs.H> +#include <errl/errlentry.H> +#include <initservice/isteps_trace.H> + +// targeting support +#include <targeting/common/commontargeting.H> +#include <targeting/common/utilFilter.H> + +// fapi support +#include <fapi.H> +#include <fapiPlatHwpInvoker.H> + +#include "slave_sbe.H" +#include "proc_revert_sbe_mcs_setup/proc_revert_sbe_mcs_setup.H" + +namespace SLAVE_SBE +{ +// +// Wrapper function to call 6.8 : +// proc_revert_sbe_mcs_setup +// +void call_proc_revert_sbe_mcs_setup(void *io_pArgs) +{ + errlHndl_t l_errl = NULL; + + TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "call_proc_revert_sbe_mcs_setup entry" ); + + // TODO + // This currently fails on Simics because this touches a Murano chip + // register that doesn't exist in the Venice chip. When Simcs supports + // a Murano chip, this HWP can be executed. For now, just execute the + // HWP on VPO + TARGETING::Target * l_pSysTarget = NULL; + TARGETING::targetService().getTopLevelTarget(l_pSysTarget); + uint8_t l_vpoMode = l_pSysTarget->getAttr<TARGETING::ATTR_IS_SIMULATION>(); + if (!l_vpoMode) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "INFO : not executing proc_revert_sbe_mcs_setup until murano chip in Simics"); + } + else + { + TARGETING::Target* l_pProcTarget = NULL; + TARGETING::targetService().masterProcChipTargetHandle(l_pProcTarget); + + fapi::Target l_fapiProcTarget(fapi::TARGET_TYPE_PROC_CHIP, l_pProcTarget); + + // Invoke the HWP + FAPI_INVOKE_HWP(l_errl, proc_revert_sbe_mcs_setup, l_fapiProcTarget); + + if (l_errl) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR : failed executing proc_revert_sbe_mcs_setup returning error"); + } + else + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "SUCCESS : proc_revert_sbe_mcs_setup completed ok"); + } + } + + TRACDCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "call_proc_revert_sbe_mcs_setup exit"); + + // end task, returning any errorlogs to IStepDisp + task_end2(l_errl); +} + +} diff --git a/src/usr/hwpf/hwp/slave_sbe/slave_sbe.H b/src/usr/hwpf/hwp/slave_sbe/slave_sbe.H new file mode 100644 index 000000000..58800deff --- /dev/null +++ b/src/usr/hwpf/hwp/slave_sbe/slave_sbe.H @@ -0,0 +1,72 @@ +/* IBM_PROLOG_BEGIN_TAG + * This is an automatically generated prolog. + * + * $Source: src/usr/hwpf/hwp/slave_sbe/slave_sbe.H $ + * + * IBM CONFIDENTIAL + * + * COPYRIGHT International Business Machines Corp. 2012 + * + * p1 + * + * Object Code Only (OCO) source materials + * Licensed Internal Code Source Materials + * IBM HostBoot Licensed Internal Code + * + * The source code for this program is not published or other- + * wise divested of its trade secrets, irrespective of what has + * been deposited with the U.S. Copyright Office. + * + * Origin: 30 + * + * IBM_PROLOG_END_TAG + */ + +#ifndef __SLAVE_SBE_SLAVE_SBE_H +#define __SLAVE_SBE_SLAVE_SBE_H + +/** + * @file slave_sbe.H + * + * Slave SBE Isteps that invoke HWPs. + * + * Note that a number of IStep 6 substeps are done by Hostboot specific + * functions, this file is for the substeps that invoke HWPs + * + * All of the following routines are "named isteps" - they are invoked as + * tasks by the @ref IStepDispatcher. + * + */ + + /* @tag isteplist + * @docversion v1.05 (06/28/12) + * @istepname slave_sbe + * @istepnum 6 + * @istepdesc Slave SBE + * + * @{ + * @substepnum 8 + * @substepname proc_revert_sbe_mcs_setup + * @substepdesc : Clean up MCS Extent regs + * @target_sched serial + * @} + * + */ + +namespace SLAVE_SBE +{ + +/** + * @brief proc_revert_sbe_mcs_setup + * + * 6.8 : : Clean up MCS Extent regs + * + * param[in,out] - pointer to any arguments, usually NULL + * + * return none + */ +void call_proc_revert_sbe_mcs_setup(void *io_pArgs); + +}; // end namespace + +#endif |
