diff options
| author | Stephen Cprek <smcprek@us.ibm.com> | 2014-03-27 11:39:08 -0500 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2014-04-02 13:02:38 -0500 |
| commit | db64cceabdbb2767260e8dcf8f27014fd2bc8b99 (patch) | |
| tree | ef884dd8176e980c905e749cc6a4c65d0f48f950 /src/usr | |
| parent | 08b2a7d1c64a65cba7146f16180d42d6f9198700 (diff) | |
| download | talos-hostboot-db64cceabdbb2767260e8dcf8f27014fd2bc8b99.tar.gz talos-hostboot-db64cceabdbb2767260e8dcf8f27014fd2bc8b99.zip | |
Add missing SBE error files to HB - 820
Change-Id: I267a8e0130b3bbb80b2d15c7bd332deddef25c4e
CQ: SW254154
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/9967
Reviewed-by: Brian H. Horton <brianh@linux.ibm.com>
Tested-by: Jenkins Server
Reviewed-by: MATTHEW A. PLOETZ <maploetz@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr')
23 files changed, 2406 insertions, 18 deletions
diff --git a/src/usr/hwpf/hwp/proc_clock_control_registers.xml b/src/usr/hwpf/hwp/proc_clock_control_registers.xml new file mode 100644 index 000000000..71665d172 --- /dev/null +++ b/src/usr/hwpf/hwp/proc_clock_control_registers.xml @@ -0,0 +1,93 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/proc_clock_control_registers.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2014 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- $Id: proc_clock_control_registers.xml,v 1.1 2013/04/25 19:17:30 jeshua Exp $ --> +<!-- Definition of Clock control registers to collect on some errors --> +<hwpErrors> + <!-- TP chiplet --> + <registerFfdc> + <id>REG_FFDC_PROC_TP_CLOCK_CONTROLLER</id> + <scomRegister>TP_OPCG_CNTL0_0x01030002</scomRegister> + <scomRegister>TP_OPCG_CNTL1_0x01030003</scomRegister> + <scomRegister>TP_OPCG_CNTL2_0x01030004</scomRegister> + <scomRegister>TP_OPCG_CNTL3_0x01030005</scomRegister> + <scomRegister>TP_CLK_REGION_0x01030006</scomRegister> + <scomRegister>TP_CLK_SCANSEL_0x01030007</scomRegister> + <scomRegister>TP_CLK_STATUS_0x01030008</scomRegister> + </registerFfdc> + <!-- Nest chiplet --> + <registerFfdc> + <id>REG_FFDC_PROC_NEST_CLOCK_CONTROLLER</id> + <scomRegister>NEST_OPCG_CNTL0_0x02030002</scomRegister> + <scomRegister>NEST_OPCG_CNTL1_0x02030003</scomRegister> + <scomRegister>NEST_OPCG_CNTL2_0x02030004</scomRegister> + <scomRegister>NEST_OPCG_CNTL3_0x02030005</scomRegister> + <scomRegister>NEST_CLK_REGION_0x02030006</scomRegister> + <scomRegister>NEST_CLK_SCANSEL_0x02030007</scomRegister> + <scomRegister>NEST_CLK_STATUS_0x02030008</scomRegister> + </registerFfdc> + <!-- X Bus chiplet --> + <registerFfdc> + <id>REG_FFDC_PROC_XBUS_CLOCK_CONTROLLER</id> + <scomRegister>X_OPCG_CNTL0_0x04030002</scomRegister> + <scomRegister>X_OPCG_CNTL1_0x04030003</scomRegister> + <scomRegister>X_OPCG_CNTL2_0x04030004</scomRegister> + <scomRegister>X_OPCG_CNTL3_0x04030005</scomRegister> + <scomRegister>X_CLK_REGION_0x04030006</scomRegister> + <scomRegister>X_CLK_SCANSEL_0x04030007</scomRegister> + <scomRegister>X_CLK_STATUS_0x04030008</scomRegister> + </registerFfdc> + <!-- A Bus chiplet --> + <registerFfdc> + <id>REG_FFDC_PROC_ABUS_CLOCK_CONTROLLER</id> + <scomRegister>A_OPCG_CNTL0_0x08030002</scomRegister> + <scomRegister>A_OPCG_CNTL1_0x08030003</scomRegister> + <scomRegister>A_OPCG_CNTL2_0x08030004</scomRegister> + <scomRegister>A_OPCG_CNTL3_0x08030005</scomRegister> + <scomRegister>A_CLK_REGION_0x08030006</scomRegister> + <scomRegister>A_CLK_SCANSEL_0x08030007</scomRegister> + <scomRegister>A_CLK_STATUS_0x08030008</scomRegister> + </registerFfdc> + <!-- PCIE chiplet --> + <registerFfdc> + <id>REG_FFDC_PROC_PCIE_CLOCK_CONTROLLER</id> + <scomRegister>PCIE_OPCG_CNTL0_0x09030002</scomRegister> + <scomRegister>PCIE_OPCG_CNTL1_0x09030003</scomRegister> + <scomRegister>PCIE_OPCG_CNTL2_0x09030004</scomRegister> + <scomRegister>PCIE_OPCG_CNTL3_0x09030005</scomRegister> + <scomRegister>PCIE_CLK_REGION_0x09030006</scomRegister> + <scomRegister>PCIE_CLK_SCANSEL_0x09030007</scomRegister> + <scomRegister>PCIE_CLK_STATUS_0x09030008</scomRegister> + </registerFfdc> + <!-- EX chiplet --> + <registerFfdc> + <id>REG_FFDC_PROC_EX_CLOCK_CONTROLLER</id> + <scomRegister>EX_SYNC_CONFIG_0x10030000</scomRegister> + <scomRegister>EX_OPCG_CNTL0_0x10030002</scomRegister> + <scomRegister>EX_OPCG_CNTL1_0x10030003</scomRegister> + <scomRegister>EX_OPCG_CNTL2_0x10030004</scomRegister> + <scomRegister>EX_OPCG_CNTL3_0x10030005</scomRegister> + <scomRegister>EX_CLK_REGION_0x10030006</scomRegister> + <scomRegister>EX_CLK_SCANSEL_0x10030007</scomRegister> + <scomRegister>EX_CLK_STATUS_0x10030008</scomRegister> + </registerFfdc> +</hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_pibmem_registers.xml b/src/usr/hwpf/hwp/proc_pibmem_registers.xml new file mode 100644 index 000000000..066532d3f --- /dev/null +++ b/src/usr/hwpf/hwp/proc_pibmem_registers.xml @@ -0,0 +1,30 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/proc_pibmem_registers.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2014 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- $Id: proc_pibmem_registers.xml,v 1.1 2013/04/25 19:54:23 jeshua Exp $ --> +<!-- Definition of PIBMEM registers to collect on some errors --> +<hwpErrors> + <registerFfdc> + <id>REG_FFDC_PROC_PIBMEM_REGISTERS</id> + <scomRegister>PIBMEM_STATUS_0x00088005</scomRegister> + </registerFfdc> +</hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_check_master_errors.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_check_master_errors.xml new file mode 100644 index 000000000..f578cec8f --- /dev/null +++ b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_check_master_errors.xml @@ -0,0 +1,41 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_check_master_errors.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2014 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- $Id: proc_sbe_check_master_errors.xml,v 1.2 2013/06/21 14:38:48 jeshua Exp $ --> +<!-- Halt codes for proc_sbe_check_master --> +<hwpErrors> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_CHECK_MASTER_NO_VALID_MCS</rc> + <description> + Procedure: proc_sbe_check_master + Both MCL/MCR fences asserted, no functional MCS units are available for use. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <ffdc>NEST_GP0_0x02000000</ffdc> + <sbeError/> + </hwpError> +</hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_chiplet_init_errors.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_chiplet_init_errors.xml new file mode 100644 index 000000000..9efa50c6c --- /dev/null +++ b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_chiplet_init_errors.xml @@ -0,0 +1,68 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_chiplet_init_errors.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2014 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- $Id: proc_sbe_chiplet_init_errors.xml,v 1.2 2013/12/13 15:59:11 stillgs Exp $ --> +<!-- Halt codes for proc_sbe_chiplet_init.S --> +<hwpErrors> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_MPIPL_CLOCK_START_ERROR</rc> + <description> + Procedure: proc_sbe_chiplet_init.S + Check that clocks were started to allow AISS access for PCB Fencing failed + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_MPIPL_PBC_FENCE_TIMEOUT_ERROR</rc> + <description> + Procedure: proc_sbe_chiplet_init.S + Check that the PCB Fence was raised fOR MPIPL reset failed + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_MPIPL_SECURITY_UNLOCK_ERROR</rc> + <description> + Procedure: proc_sbe_chiplet_init.S + The security function failed to unlock for MPIPL restart + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> +</hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_decompress_scan_halt_codes.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_decompress_scan_halt_codes.xml new file mode 100644 index 000000000..4f1893bd1 --- /dev/null +++ b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_decompress_scan_halt_codes.xml @@ -0,0 +1,136 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_decompress_scan_halt_codes.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2014 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- $Id: proc_sbe_decompress_scan_halt_codes.xml,v 1.3 2013/06/21 22:46:29 jeshua Exp $ --> +<!-- Halt codes for proc_sbe_decompress_scan.S --> +<hwpErrors> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_SCAN_MULTICAST_TYPE_ERROR</rc> + <description> + Subroutine: proc_sbe_decompress_scan + The subroutine was given a chiplet Id that is a multicast chiplet, + however it is not a multicast WRITE type as required. The bad chiplet Id + will be found in P0 at the halt. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_SCAN_MAGIC_MISMATCH</rc> + <description> + Subroutine: proc_sbe_decompress_scan + The subroutine was passed a data structure whose magic number was + incorrect. The magic number of the data structure can be found in PORE + register D0. The most likely cause of this error is a problem with the + tool chain used to build the SBE IPL images. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_SCAN_HEADER_VERSION_ERROR</rc> + <description> + Subroutine: proc_sbe_decompress_scan + The subroutine was passed a data structure whose header version is + different from the one the code was expecting. The header version of the + data structure can be found in PORE register D0. The most likely cause of + this error is a problem with the tool chain used to build the SBE IPL + images. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_SCAN_DATA_SIZE_ERROR</rc> + <description> + Subroutine: proc_sbe_decompress_scan + Each scan data structure contains the total expected size of the + structure, however in this case the compressed scan string required + either more or less data than indicated in the header. The PORE register + D0 contains the number (signed) of excess doublewords. The most likely + cause of this error is a problem with the tool chain used to build the + SBE IPL images. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_SCAN_RING_LENGTH_ERROR</rc> + <description> + Subroutine: proc_sbe_decompress_scan + The number of bits scanned does not match the ring length stored in the + scan data header. The PORE register D0 contains the number (signed) of + excess bits. The most likely cause of this error is a problem with the + tool chain used to build the SBE IPL images. + </description> + <!-- JDS TODO - this FFDC should log the target chiplet + REG_FFDC_PROC_*_CLOCK_CONTROLLER registers as well --> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_SCAN_CHECKWORD_ERROR</rc> + <description> + Subroutine: proc_sbe_decompress_scan + The initial checkword did not rotate back into the scan data register at + the completion of the scan. The contents of the PORE D0 register have + been loaded with the received checkword, whose value may provide a clue + as to what happened. The expected value is 0xa5a55a5a00000000. This error + could be caused by broken hardware, or by any tool problem that would + misrepresent the length of the actual hardware scan ring. + </description> + <!-- JDS TODO - this FFDC should log the target chiplet + REG_FFDC_PROC_*_CLOCK_CONTROLLER registers as well --> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> +</hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_ex_dpll_setup_halt_codes.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_ex_dpll_setup_halt_codes.xml new file mode 100644 index 000000000..09488fdc7 --- /dev/null +++ b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_ex_dpll_setup_halt_codes.xml @@ -0,0 +1,43 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_ex_dpll_setup_halt_codes.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2014 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- $Id: proc_sbe_ex_dpll_setup_halt_codes.xml,v 1.2 2013/06/21 21:04:33 jeshua Exp $ --> +<!-- Halt codes for proc_sbe_ex_dpll_setup.S --> +<hwpErrors> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_DPLL_SETUP_NOLOCK</rc> + <description> + Procedure: proc_sbe_ex_dpll_setup + This error is signalled when the EX DPLL fails to lock after ~150us. + </description> + <!-- JDS TODO - this FFDC should probably only log the target engine + and should log something about the target EX --> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> +</hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_ex_startclocks_errors.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_ex_startclocks_errors.xml new file mode 100644 index 000000000..70b43de3b --- /dev/null +++ b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_ex_startclocks_errors.xml @@ -0,0 +1,56 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_ex_startclocks_errors.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2014 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- $Id: proc_sbe_ex_startclocks_errors.xml,v 1.1 2013/08/30 18:43:18 jeshua Exp $ --> +<!-- Error definitions for proc_sbe_ex_startclocks procedure --> +<hwpErrors> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_SBE_EX_STARTCLOCKS_CLOCKS_NOT_STARTED</rc> + <description> + Procedure: proc_sbe_ex_startclocks + After trying to start all of the EX clocks, some of the tholds were still high + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <!-- JDS TODO - add the clock status regs for the target EX here--> + <sbeError/> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_SBE_EX_STARTCLOCKS_CHIP_XSTOPPED</rc> + <description> + Procedure: proc_sbe_ex_startclocks + After starting the EX clocks the system was xstopped + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <!-- JDS TODO - collect the fir regs of the target EX here --> + <sbeError/> + </hwpError> +</hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_fabricinit_errors.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_fabricinit_errors.xml new file mode 100644 index 000000000..228fb9ddb --- /dev/null +++ b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_fabricinit_errors.xml @@ -0,0 +1,56 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_fabricinit_errors.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2014 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- $Id: proc_sbe_fabricinit_errors.xml,v 1.3 2013/06/21 18:50:20 jeshua Exp $ --> +<!-- Halt codes for proc_sbe_fabricinit --> +<hwpErrors> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_FABRICINIT_FBC_STOPPED_ERR</rc> + <description> + Procedure: proc_sbe_fabricinit + Fabric init sequence not attempted, fabric arbitration is stopped. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <ffdc>ADU_PMISC_MODE_0x0202000B</ffdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_FABRICINIT_ERR</rc> + <description> + Procedure: proc_sbe_fabricinit + Fabric init failed, or mismatch in expected ADU status. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <ffdc>ADU_STATUS_0x02020002</ffdc> + <sbeError/> + </hwpError> +</hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_instruct_start_errors.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_instruct_start_errors.xml new file mode 100644 index 000000000..46ab9f5de --- /dev/null +++ b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_instruct_start_errors.xml @@ -0,0 +1,77 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_instruct_start_errors.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2014 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- $Id: proc_sbe_instruct_start_errors.xml,v 1.4 2013/11/04 15:16:34 jeshua Exp $ --> +<!-- Halt codes for proc_sbe_instruct_start --> +<hwpErrors> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_INSTR_START_SPWU_FAILED</rc> + <description> + Procedure: proc_sbe_instruct_start + Special wakeup before starting instructions failed. + </description> + <!-- JDS TODO - this FFDC should probably only log the target engine + and should log something about the target EX --> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_INSTR_START_THREAD0_NOT_RUNNING</rc> + <description> + Procedure: proc_sbe_instruct_start + Thread 0 is still in nap/sleep/winkle after the instruct start + </description> + <!-- JDS TODO - this FFDC should probably only log the target engine + and should log something about the target EX --> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_INSTR_START_MAINT_MODE</rc> + <description> + Procedure: proc_sbe_instruct_start + Can't start instructions because the core is still in maintenance mode. + </description> + <!-- JDS TODO - this FFDC should probably only log the target engine + and should log something about the target EX --> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> +</hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_lco_loader_errors.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_lco_loader_errors.xml new file mode 100644 index 000000000..da301e85f --- /dev/null +++ b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_lco_loader_errors.xml @@ -0,0 +1,190 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_lco_loader_errors.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2014 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- $Id: proc_sbe_lco_loader_errors.xml,v 1.3 2013/06/21 19:15:05 jeshua Exp $ --> +<!-- Halt codes for proc_sbe_lco_loader --> +<hwpErrors> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_LCO_LOADER_MULTICAST_ERR</rc> + <description> + Procedure: proc_sbe_lco_loader + Attempted to execute procedure with cv_multicast option. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_LCO_LOADER_FBC_STOPPED_ERR</rc> + <description> + Procedure: proc_sbe_lco_loader + LCO load sequence not attempted, fabric arbitration is stopped. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <ffdc>ADU_PMISC_MODE_0x0202000B</ffdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_LCO_LOADER_IMAGE_SIZE_PAD_ERR</rc> + <description> + Procedure: proc_sbe_lco_loader + Image size is not evenly divisible by cacheline size. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <ffdc>OTPC_M_SECURITY_SWITCH_0x00010005</ffdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_LCO_LOADER_IMAGE_SIZE_OVERFLOW_ERR</rc> + <description> + Procedure: proc_sbe_lco_loader + Image size is larger than master chiplet cache size. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <ffdc>OTPC_M_SECURITY_SWITCH_0x00010005</ffdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_LCO_LOADER_IMAGE_WRAP_ERR</rc> + <description> + Procedure: proc_sbe_lco_loader + Combination of target base address and image size will wrap OCB address. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <ffdc>OTPC_M_SECURITY_SWITCH_0x00010005</ffdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_LCO_LOADER_IMAGE_ALIGN_ERR</rc> + <description> + Procedure: proc_sbe_lco_loader + Target base address is not cacheline aligned. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <ffdc>OTPC_M_SECURITY_SWITCH_0x00010005</ffdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_LCO_LOADER_PBA_RESET_ERR</rc> + <description> + Procedure: proc_sbe_lco_loader + PBA slave reset still in progress or buffer is busy. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <ffdc>PBA_SLVRST_0x00064001</ffdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_LCO_LOADER_OCB_STATUS_ERR</rc> + <description> + Procedure: proc_sbe_lco_loader + Unexpected state in OCB Status Control Register at end of write stream. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <ffdc>OCB3_STATUS_CONTROL_0x0006B071</ffdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_LCO_LOADER_PBA_FIR_ERR</rc> + <description> + Procedure: proc_sbe_lco_loader + Unexpected state in PBA FIR Register at end of write stream. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <ffdc>PBA_FIR_0x02010840</ffdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_LCO_LOADER_PBA_WBUF0_ERR</rc> + <description> + Procedure: proc_sbe_lco_loader + Unexpected state in PBA Write Buffer0 Register at end of write stream. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <ffdc>PBA_WBUFVAL0_0x02010858</ffdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_LCO_LOADER_PBA_WBUF1_ERR</rc> + <description> + Procedure: proc_sbe_lco_loader + Unexpected state in PBA Write Buffer1 Register at end of write stream. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <ffdc>PBA_WBUFVAL1_0x02010859</ffdc> + <sbeError/> + </hwpError> +</hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_npll_setup_errors.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_npll_setup_errors.xml new file mode 100644 index 000000000..050ede645 --- /dev/null +++ b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_npll_setup_errors.xml @@ -0,0 +1,77 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_npll_setup_errors.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2014 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- $Id: proc_sbe_npll_setup_errors.xml,v 1.4 2013/06/21 19:00:29 jeshua Exp $ --> +<!-- Halt codes for proc_sbe_npll_setup --> +<hwpErrors> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_NPLL_SETUP_CPFILT_NOLOCK</rc> + <description> + Procedure: proc_sbe_npll_setup + CP Filter PLL failed to lock. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <ffdc>TP_PLL_LOCK_0x010F0019</ffdc> + <ffdc>MBOX_FSIGP4_0x00050013</ffdc> + <ffdc>MBOX_FSIGP3_0x00050012</ffdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_NPLL_SETUP_EMFILT_NOLOCK</rc> + <description> + Procedure: proc_sbe_npll_setup + EM Filter PLL failed to lock. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <ffdc>TP_PLL_LOCK_0x010F0019</ffdc> + <ffdc>MBOX_FSIGP4_0x00050013</ffdc> + <ffdc>MBOX_FSIGP3_0x00050012</ffdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_NPLL_SETUP_XBUS_NOLOCK</rc> + <description> + Procedure: proc_sbe_npll_setup + X-Bus PLL failed to lock. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <ffdc>MBOX_FSIGP4_0x00050013</ffdc> + <ffdc>MBOX_GP3MIR_0x0005001B</ffdc> + <ffdc>X_PLLLOCKREG_0x040F0019</ffdc> + <sbeError/> + </hwpError> +</hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_pb_startclocks.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_pb_startclocks.xml new file mode 100644 index 000000000..b5a593ced --- /dev/null +++ b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_pb_startclocks.xml @@ -0,0 +1,41 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_pb_startclocks.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2014 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- $Id: proc_sbe_pb_startclocks.xml,v 1.2 2013/06/21 19:20:21 jeshua Exp $ --> +<!-- Halt codes for proc_sbe_pb_startclocks --> +<hwpErrors> + <!-- ******************************************************************** --> + <hwpError> + <rc>PROC_SBE_PB_START_CLOCK_ERROR</rc> + <description> + Procedure: proc_sbe_pb_startclocks + Failed to start clocks on PB chiplet. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_NEST_CLOCK_CONTROLLER</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> +</hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_pibmem_loader_halt_codes.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_pibmem_loader_halt_codes.xml new file mode 100644 index 000000000..cef6e0c55 --- /dev/null +++ b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_pibmem_loader_halt_codes.xml @@ -0,0 +1,106 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_pibmem_loader_halt_codes.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2014 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- $Id: proc_sbe_pibmem_loader_halt_codes.xml,v 1.2 2013/06/21 18:44:47 jeshua Exp $ --> +<!-- Halt codes for proc_sbe_pibmem_loader.S --> +<hwpErrors> + <hwpError> + <rc>RC_SBE_PIBMEM_PRE_ERROR</rc> + <description> + Procedure: proc_sbe_pibmem_loader + The PIBMEM either shows error status or is not in the idle state prior to + the execution of the procedure. The contents of the PIBMEM Status + Register are in D0 at the time of the halt. Resetting the PIBMEM prior + to running proc_sbe_pibmem_loader should clear up this error. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_PIBMEM_POST_ERROR</rc> + <description> + Procedure: proc_sbe_pibmem_loader + The PIBMEM either shows error status or is not in the idle state after + execution of the procedure. The contents of the PIBMEM Status Register + are in D0 at the time of the halt. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_PIBMEM_IMAGE_SIZE_ALIGNMENT</rc> + <description> + Procedure: proc_sbe_pibmem_loader + The size of the PIBMEM image to load is not a multiple of 8 bytes, which + is a hard requirement due to the PORE architecture. The image size passed + to the procedure can be found in SPRG0. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_PIBMEM_LOAD_ADDRESS_ALIGNMENT</rc> + <description> + Procedure: proc_sbe_pibmem_loader + The load address of the PIBMEM image is not a multiple of 8 bytes, which + is a hard requirement due to the PORE architecture. The load address + passed to the procedure can be found in SPRG0. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_PIBMEM_OVERFLOW</rc> + <description> + Procedure: proc_sbe_pibmem_loader + The load address and size of the PIBMEM image would overflow the physical + PIBMEM. The image size (in bytes) passed to the procedure is in SPRG0; + D1 contains the PIBMEM load address passed to the procedure. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> +</hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_scominit_errors.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_scominit_errors.xml new file mode 100644 index 000000000..c0eda9cef --- /dev/null +++ b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_scominit_errors.xml @@ -0,0 +1,154 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_scominit_errors.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2014 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- $Id: proc_sbe_scominit_errors.xml,v 1.6 2014/02/10 04:30:49 stillgs Exp $ --> +<!-- Halt codes for proc_sbe_scomint.S --> +<hwpErrors> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_WINKLE_STATE_OR_ERROR</rc> + <description> + Procedure: proc_sbe_scominit + Check of winkle state across all IPLed chiplets using READ-OR failed. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_FIR_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_PMC_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_PBA_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_SLW_PCBS_REGISTERS</id> + <basedOnPresentChildren> + <target>CHIP_IN_ERROR</target> + <childType>TARGET_TYPE_EX_CHIPLET</childType> + <childPosOffsetMultiplier>0x01000000</childPosOffsetMultiplier> + </basedOnPresentChildren> + </collectRegisterFfdc> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_WINKLE_STATE_AND_ERROR</rc> + <description> + Procedure: proc_sbe_scominit + Check of winkle state across all IPLed chiplets using READ-AND failed. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_FIR_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_PMC_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_PBA_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_SLW_PCBS_REGISTERS</id> + <basedOnPresentChildren> + <target>CHIP_IN_ERROR</target> + <childType>TARGET_TYPE_EX_CHIPLET</childType> + <childPosOffsetMultiplier>0x01000000</childPosOffsetMultiplier> + </basedOnPresentChildren> + </collectRegisterFfdc> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <callout> + <procedure>CODE</procedure> + <priority>LOW</priority> + </callout> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_WINKLE_FSM_TIMEOUT_ERROR</rc> + <description> + Procedure: proc_sbe_scominit + Polling of Idle FSM timed out. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_FIR_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_PMC_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_PBA_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_SLW_PCBS_REGISTERS</id> + <basedOnPresentChildren> + <target>CHIP_IN_ERROR</target> + <childType>TARGET_TYPE_EX_CHIPLET</childType> + <childPosOffsetMultiplier>0x01000000</childPosOffsetMultiplier> + </basedOnPresentChildren> + </collectRegisterFfdc> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_WINKLE_PFET_TIMEOUT_ERROR</rc> + <description> + Procedure: proc_sbe_scominit + Polling of PFET controller for idle timed out. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_FIR_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_PMC_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_PBA_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_SLW_PCBS_REGISTERS</id> + <basedOnPresentChildren> + <target>CHIP_IN_ERROR</target> + <childType>TARGET_TYPE_EX_CHIPLET</childType> + <childPosOffsetMultiplier>0x01000000</childPosOffsetMultiplier> + </basedOnPresentChildren> + </collectRegisterFfdc> + <callout> + <target>CHIP</target> + <priority>HIGH</priority> + </callout> + <sbeError/> + </hwpError> +</hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_select_ex_errors.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_select_ex_errors.xml index 4ef3610e5..097acaeea 100644 --- a/src/usr/hwpf/hwp/proc_sbe_select_ex_errors.xml +++ b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_select_ex_errors.xml @@ -1,11 +1,11 @@ <!-- IBM_PROLOG_BEGIN_TAG --> <!-- This is an automatically generated prolog. --> <!-- --> -<!-- $Source: src/usr/hwpf/hwp/proc_sbe_select_ex_errors.xml $ --> +<!-- $Source: src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_select_ex_errors.xml $ --> <!-- --> <!-- IBM CONFIDENTIAL --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2013 --> +<!-- COPYRIGHT International Business Machines Corp. 2014 --> <!-- --> <!-- p1 --> <!-- --> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_setup_evid_errors.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_setup_evid_errors.xml new file mode 100644 index 000000000..647d8dc99 --- /dev/null +++ b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_setup_evid_errors.xml @@ -0,0 +1,100 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_setup_evid_errors.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2014 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- $Id: proc_sbe_setup_evid_errors.xml,v 1.3 2014/03/03 22:00:57 stillgs Exp $ --> +<!-- Halt codes for proc_sbe_setup_evid --> +<hwpErrors> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_SET_VID_ERROR</rc> + <description> + Procedure: proc_sbe_setup_evid + Setting the VID with SPIVID returned bad status + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_SET_VID_TIMEOUT</rc> + <description> + Procedure: proc_sbe_setup_evid + Setting EVID during boot timed out on the SPIVID bus + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_O2S_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_SET_VID_ZERO_BOOT_VOLTAGE</rc> + <description> + Procedure: proc_sbe_setup_evid + Boot voltage IDs are invalid (0s) + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_SPIVID_STATUS_ERROR</rc> + <description> + Procedure: proc_sbe_setup_evid + Errors detected in O2S Status Reg setting Boot Voltage + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_O2S_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_SPIVID_WRITE_RETURN_STATUS_ERROR</rc> + <description> + Procedure: proc_sbe_setup_evid + SPIVID Device did not return good status the Boot Voltage Write operation + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_O2S_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> +</hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_tp_switch_gears_errors.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_tp_switch_gears_errors.xml new file mode 100644 index 000000000..f30d07be8 --- /dev/null +++ b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_tp_switch_gears_errors.xml @@ -0,0 +1,56 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_tp_switch_gears_errors.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2014 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- $Id: proc_sbe_tp_switch_gears_errors.xml,v 1.2 2013/06/21 14:45:05 jeshua Exp $ --> +<!-- Halt codes for proc_sbe_tp_switch_gears --> +<hwpErrors> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_TP_SWITCH_GEARS_XBUS_NOLOCK</rc> + <description> + Procedure: proc_sbe_tp_switch_gears + X-Bus PLL failed to lock (Murano DD1.x workaround). + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <ffdc>X_PLLLOCKREG_0x040F0019</ffdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_TP_SWITCH_GEARS_XBUS_HEADER_CHECK_FAIL</rc> + <description> + Procedure: proc_sbe_tp_switch_gears + X-Bus Murano DD1.x workaround header check fail (ie. scan failed) + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_XBUS_CLOCK_CONTROLLER</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> +</hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_trigger_winkle_errors.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_trigger_winkle_errors.xml new file mode 100644 index 000000000..86c47ca04 --- /dev/null +++ b/src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_trigger_winkle_errors.xml @@ -0,0 +1,132 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/proc_sbe_errors/proc_sbe_trigger_winkle_errors.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2014 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- $Id: proc_sbe_trigger_winkle_errors.xml,v 1.4 2014/01/26 20:06:34 stillgs Exp $ --> +<!-- Error definitions for proc_sbe_trigger_winkle procedure --> +<hwpErrors> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_SBE_TRIGGER_WINKLE_EX_DID_NOT_ENTER_WINKLE</rc> + <description> + Procedure: proc_sbe_trigger_winkle + The master EX chiplet did not enter winkle before the deadman timer expired. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_PIBMEM_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_FIR_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_PMC_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_PBA_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_SLW_PCBS_REGISTERS</id> + <basedOnPresentChildren> + <target>CHIP_IN_ERROR</target> + <childType>TARGET_TYPE_EX_CHIPLET</childType> + <childPosOffsetMultiplier>0x01000000</childPosOffsetMultiplier> + </basedOnPresentChildren> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_SBE_TRIGGER_WINKLE_EX_WAKEUP_DID_NOT_HIT_GOTO</rc> + <description> + Procedure: proc_sbe_trigger_winkle + The master EX chiplet wakeup did not hit GOTO before the deadman timer expired. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_PIBMEM_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_FIR_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_PMC_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_PBA_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_SLW_PCBS_REGISTERS</id> + <basedOnPresentChildren> + <target>CHIP_IN_ERROR</target> + <childType>TARGET_TYPE_EX_CHIPLET</childType> + <childPosOffsetMultiplier>0x01000000</childPosOffsetMultiplier> + </basedOnPresentChildren> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_SBE_TRIGGER_WINKLE_EX_WAKEUP_DID_NOT_FINISH</rc> + <description> + Procedure: proc_sbe_trigger_winkle + The master EX chiplet wakeup didn't finish before the deadman timer expired. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_PIBMEM_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_FIR_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_PMC_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_PBA_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_SLW_PCBS_REGISTERS</id> + <basedOnPresentChildren> + <target>CHIP_IN_ERROR</target> + <childType>TARGET_TYPE_EX_CHIPLET</childType> + <childPosOffsetMultiplier>0x01000000</childPosOffsetMultiplier> + </basedOnPresentChildren> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_SBE_TRIGGER_WINKLE_HOSTBOOT_DID_NOT_RESPOND</rc> + <description> + Procedure: proc_sbe_trigger_winkle + The master EX chiplet woke up but hostboot didn't indicate that it was running before the deadman timer expired. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_PIBMEM_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_FIR_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_PMC_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_PBA_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_SLW_PCBS_REGISTERS</id> + <basedOnPresentChildren> + <target>CHIP_IN_ERROR</target> + <childType>TARGET_TYPE_EX_CHIPLET</childType> + <childPosOffsetMultiplier>0x01000000</childPosOffsetMultiplier> + </basedOnPresentChildren> + </collectRegisterFfdc> + <sbeError/> + </hwpError> +</hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/proc_slw_base_halt_codes.xml b/src/usr/hwpf/hwp/proc_sbe_errors/proc_slw_base_halt_codes.xml new file mode 100644 index 000000000..0fedeffe8 --- /dev/null +++ b/src/usr/hwpf/hwp/proc_sbe_errors/proc_slw_base_halt_codes.xml @@ -0,0 +1,459 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/proc_sbe_errors/proc_slw_base_halt_codes.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2014 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- $Id: proc_slw_base_halt_codes.xml,v 1.9 2013/11/23 00:33:44 cmolsen Exp $ --> +<!-- Halt codes for proc_slw_*.S --> +<hwpErrors> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SLW_UNDEFINED_SV</rc> + <description> + This error is signalled by proc_slw_base and indicates that an + invalid start vector was detected in the EXE_TRIGGER (ETR) register when + kicking off an idle transition. The start vector is in ETR(8:11). + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SLW_PFET_VDD_TIMEOUT_ERROR</rc> + <description> + This error is signalled by proc_slw_poweronoff and indicates that a timeout + occured waiting for the VDD PFET sequencer(s) to complete. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SLW_PFET_VCS_TIMEOUT_ERROR</rc> + <description> + This error is signalled by proc_slw_poweronoff and indicates that a timeout + occured waiting for the VCS PFET sequencer(s) to complete. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SLW_PFET_DECODE_ERROR</rc> + <description> + This error is signalled by proc_slw_poweronoff and indicates that an invalid + PFET decode was detected. This is an SLW firmware issue. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SLW_IVRM_BS_SLEEP_ENTRY_TIMEOUT</rc> + <description> + This error is signalled by proc_slw_base and indicates that a timeout + occured waiting for the internal VRM babystepper to synchronize the idle + transition command during sleep entry. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SLW_IVRM_BS_WINKLE_ENTRY_TIMEOUT</rc> + <description> + This error is signalled by proc_slw_base and indicates that a timeout + occured waiting for the internal VRM babystepper to synchronize the idle + transition command during winkle entry. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SLW_IVRM_BS_EXIT_TIMEOUT</rc> + <description> + This error is signalled by proc_slw_base and indicates that a timeout + occured waiting for the internal VRM babystepper to synchronize the idle + transition command during a fast exit. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SLW_IVRM_CAL_TIMEOUT</rc> + <description> + This error is signalled by proc_slw_base and indicates that a timeout + occured while polling for the iVRM calibration to complete. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SLW_IVRM_CAL_BS_EXIT_TIMEOUT</rc> + <description> + This error is signalled by proc_slw_base and indicates that a timeout + occured waiting for the internal VRM babystepper to synchronize the idle + transition command during a deep exit after iVRM calibration. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SLW_IVRM_FORCESM_TIMEOUT</rc> + <description> + This error is signalled by proc_slw_base and indicates that a timeout + occured waiting for the internal VRM force safe mode to take effect. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SLW_RAM_THREAD_CHECK_ERROR</rc> + <description> + This error is signalled by proc_slw_ram and indicates that a timeout + occured waiting the RAM hardware to accept the instruction given to it.. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SLW_RAM_THREAD_QUIESCE_ERROR</rc> + <description> + This error is signalled by proc_slw_ram and indicates that a timeout + occured waiting the RAM hardware to quiesce. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SLW_RAM_CONTROL_EXCEPTION_ERROR</rc> + <description> + This error is signalled by proc_slw_ram and indicates that RAM controller + indicates recovery is inprogress or an exception has occured.. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SLW_RAM_STATUS_TIMEOUT_ERROR</rc> + <description> + This error is signalled by proc_slw_ram and indicates that a timeout occured + looking for good status from the RAM Controller. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SLW_GOTO_TIMEOUT_ERROR</rc> + <description> + This error is signalled by proc_slw_base and indicates that a timeout occured + looking for the proper PCBS-PM state before issuing a PCBS-PM "GOTO" command. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SLW_ERRINJ_NEVER_REACH_HALT</rc> + <description> + This error is signalled by proc_slw_pro_epi_log and indicates that the image + updated the PMC status reg but never reached the subsequent halt op. PMC SLW + Timeouts will be indicated without further FIR bits. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SLW_ERRINJ_SIMPLE_HALT</rc> + <description> + This error is signalled by proc_slw_pro_epi_log and indicates that the image + executed the simple halt error injection. PMC SLW Timeouts will be indicated + without further FIR bits. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SLW_ERRINJ_INVALID_INSTR</rc> + <description> + This error is signalled by proc_slw_pro_epi_log and indicates that the image + enabled invalid instruction error injection occured. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SLW_ERRINJ_INVALID_OCI_ADDRESS</rc> + <description> + This error is signalled by proc_slw_pro_epi_log and indicates that the image + enabled invalid OCI address error injection occured. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SLW_ERRINJ_INVALID_PIB_ADDRESS</rc> + <description> + This error is signalled by proc_slw_pro_epi_log and indicates that the image + enabled invalid PIB address error injection occured. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SLW_ERRINJ_PC_UNDERFLOW</rc> + <description> + This error is signalled by proc_slw_pro_epi_log and indicates that the image + enabled PC underflow error injection occured. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SLW_ERRINJ_PC_OVERRFLOW</rc> + <description> + This error is signalled by proc_slw_pro_epi_log and indicates that the image + enabled PC overflow error injection occured. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SLW_ERRINJ_TIMEOUT_ERROR</rc> + <description> + This error is signalled by proc_slw_pro_epi_log and indicates that the image + enabled timeout error injection occured. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SLW_EH_PIB_ERROR</rc> + <description> + This error is signalled by proc_slw_error_handler upon a detected error 0 + event (non-masked PIB error code). + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SLW_EH_OCI_ERROR</rc> + <description> + This error is signalled by proc_slw_error_handler upon a detected error 1 + event (non-masked OCI error code). + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SLW_EH_INSTRUCTION_ERROR</rc> + <description> + This error is signalled by proc_slw_error_handler upon a detected error 2 + event (instruction fetch or decode). + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SLW_EH_INTERNAL_DATA_ERROR</rc> + <description> + This error is signalled by proc_slw_error_handler upon a detected error 3 + event (internal data error). + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SLW_EH_ERROR_ON_ERROR</rc> + <description> + This error is signalled by proc_slw_error_handler upon a detected error 4 + event (an error was detected upon an error). + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SLW_PMGP1_ENABLE_CONFIG_ERROR</rc> + <description> + This error is signalled by proc_slw_base code when the multicast read AND + and the multicast read OR of the PMGP1 register for the chiplets + represented in the EXE Trigger register do not match. This could be caused + by a configuration error with the Deep Sleep power up and/or down bits or + Deep Winkle power up bit. If these bits match, then a hardware fault is + the next most probable. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>SLW_RC_ILLEGAL_WINKLE_ENTRY_POWER_DOWN</rc> + <description> + This error is signalled by proc_slw_base code (poweronoff portion) and indicates + that the PMGP1 bit for WINKLE_POWER_DOWN when WINKLE_POWER_OFF_SEL is set to 1 + (eg a Deep Winkle) has been detected. This is an illegal configuration as it + causes the loss of the High Availability Log Write pointer in the L3 before it + could be saved for restoration upon Deep Winkle Exit. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>SLW_RC_OHA_SPWUP_TIMEOUT</rc> + <description> + This error is signalled by proc_slw_base code when the polling for OHA AISS + achieving the special wake-up state after hitting the PCBS GOTO operation to + complete deep sleep exit. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SLW_CPM_SPWKUP_NOT_SET</rc> + <description> + This error is signalled by proc_slw_occ_cpm code when it is detected that + special wake-up override isnt enabled which it must be prior to calling + any of the CPM install or enable routines. + </description> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> +</hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/sbe_common_halt_codes.xml b/src/usr/hwpf/hwp/proc_sbe_errors/sbe_common_halt_codes.xml new file mode 100644 index 000000000..f601304d8 --- /dev/null +++ b/src/usr/hwpf/hwp/proc_sbe_errors/sbe_common_halt_codes.xml @@ -0,0 +1,304 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/proc_sbe_errors/sbe_common_halt_codes.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2014 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- $Id: sbe_common_halt_codes.xml,v 1.5 2013/06/21 22:57:28 jeshua Exp $ --> +<!-- Halt codes for proc_sbe_* procedures common to P8 and Centaur --> +<hwpErrors> + <!-- ******************************************************************** --> + <!-- ** Generic halt codes --> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_SUCCESS</rc> + <description> + This halt code does not represent an error; This is the code associated + with the normal successful completion of an IPL by an SBE istep + procedure. + </description> + <!-- JDS TODO - this FFDC should probably only log the target engine --> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_SUCCESS_SLAVE_CHIP</rc> + <description> + This halt code does not represent an error; This is the code associated + with the normal successful completion of an IPL by an SBE istep + procedure on a slave chip. + </description> + <!-- JDS TODO - this FFDC should probably only log the target engine --> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_PAUSE_WITH_SUCCESS</rc> + <description> + This halt code does not represent an error; This is the code associated + with a procedure initiated halt of the SBE code, with the expectation + that it will be resumed at a later point in time. + </description> + <!-- JDS TODO - this FFDC should probably only log the target engine --> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <!-- ** Halt codes from sbe_common.H --> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_PROC_ENTRY_HALT</rc> + <description> + This halt code does not represent an error; This is the code associated + with a HALT requested by the user prior to the execution of a procedure + by setting the PROC_CONTROL_ENTRY_HALT bit in the control word for the + procedure. + </description> + <!-- JDS TODO - this FFDC should probably only log the target engine --> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_PROC_EXIT_HALT</rc> + <description> + This halt code does not represent an error; This is the code associated + with a HALT requested by the user after the execution of a procedure + by setting the PROC_CONTROL_EXIT_HALT bit in the control word for the + procedure. + </description> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_PROC_CHECKSTOP</rc> + <description> + This halt code indicates that a checkstop was detected after executing a + procedure. Use the fields of the SBEVITAL register to identify the + procedure that failed. + </description> + <!-- JDS TODO - this FFDC should probably only log the target engine + and to log the FIR regs? --> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_PROC_RECOVERABLE</rc> + <description> + This halt code indicates that a recoverable error was detected after + executing a procedure. Use the fields of the SBEVITAL register to + identify the procedure that failed. + </description> + <!-- JDS TODO - this FFDC should probably only log the target engine + and to log the FIR regs? --> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_PROC_SPATTN</rc> + <description> + This halt code indicates that a Special Attention was detected after + executing a procedure. Use the fields of the SBEVITAL register to + identify the procedure that failed. + </description> + <!-- JDS TODO - this FFDC should probably only log the target engine + and to log the FIR regs? --> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <!-- ** Halt codes from proc_sbe_pore_errors.S --> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_PORE_ERROR0</rc> + <description> + This halt code indicates that an execution-phase PIB/PCB access + returned a non-0 response. The PORE PIBMS_DBG registers 0 and 1 + (plus the remainder of the PORE state) contain the information required + for an initial debug of the problem. + </description> + <!-- JDS TODO - this FFDC should probably only log the target engine --> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_PORE_ERROR1</rc> + <description> + This halt code indicates that an execution-phase OCI accesss had an + error. The PORE PIBMS_DBG registers 0 and 1 (plus the remainder of the + PORE state) contain the information required for an initial debug of the + problem. + + This error should never occur during an SBE IPL since the SBE does not + include an OCI interface. + </description> + <!-- JDS TODO - this FFDC should probably only log the target engine --> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_PORE_ERROR2</rc> + <description> + This halt code indicates an instruction fetch or decode error. The PORE + specification lists several causes of this error code. The most likely + causes in a production system are: + o An I2C hang when fetching code from SEEPROM; + o A bad branch that starts executing garbage or data; + o Memory corruption + </description> + <!-- JDS TODO - this FFDC should probably only log the target engine --> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_PORE_ERROR3</rc> + <description> + This halt code indicates an internal data error during consistency + checking, e.g., a bad scan-data CRC. + + This error should never occur during an SBE IPL since the SBE IPL does + not use the PORE SCAND instruction. + </description> + <!-- JDS TODO - this FFDC should probably only log the target engine --> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_PORE_ERROR4</rc> + <description> + This halt code indicates that a second error occurred during processing + of an initial error. + + It is extremely unlikely that this error would ever occur during an SBE + IPL since the PORE error handlers are nothing more than a single HALT + statement. + </description> + <!-- JDS TODO - this FFDC should probably only log the target engine --> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <!-- ** Halt codes from scan0 subroutine --> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_SCAN0_DONE_POLL_THRESHOLD</rc> + <description> + This error is signalled by the scan0 subroutine, indicating that the + scan0 DONE polling reached the specified threshold value. The scan0 + subroutine could have been called by various procedures. + </description> + <!-- JDS TODO - this FFDC should probably only log the target engine + and should log something about the target chiplet --> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- ******************************************************************** --> + <!-- ** Halt codes from arrayinit subroutine --> + <!-- ******************************************************************** --> + <hwpError> + <rc>RC_SBE_ARRAYINIT_POLL_THRESHOLD</rc> + <description> + This error is signalled by the arrayinit subroutine, indicating that the + arrayinit DONE polling reached the specified threshold value. The arrayinit + subroutine could have been called by various procedures. + </description> + <!-- JDS TODO - this FFDC should probably only log the target engine + and should log something about the target chiplet --> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> +</hwpErrors> diff --git a/src/usr/hwpf/hwp/proc_sbe_errors/sbe_load_ring_vec_ex_errors.xml b/src/usr/hwpf/hwp/proc_sbe_errors/sbe_load_ring_vec_ex_errors.xml new file mode 100644 index 000000000..6e27c0524 --- /dev/null +++ b/src/usr/hwpf/hwp/proc_sbe_errors/sbe_load_ring_vec_ex_errors.xml @@ -0,0 +1,93 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: src/usr/hwpf/hwp/proc_sbe_errors/sbe_load_ring_vec_ex_errors.xml $ --> +<!-- --> +<!-- IBM CONFIDENTIAL --> +<!-- --> +<!-- COPYRIGHT International Business Machines Corp. 2014 --> +<!-- --> +<!-- p1 --> +<!-- --> +<!-- Object Code Only (OCO) source materials --> +<!-- Licensed Internal Code Source Materials --> +<!-- IBM HostBoot Licensed Internal Code --> +<!-- --> +<!-- The source code for this program is not published or otherwise --> +<!-- divested of its trade secrets, irrespective of what has been --> +<!-- deposited with the U.S. Copyright Office. --> +<!-- --> +<!-- Origin: 30 --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- $Id: sbe_load_ring_vec_ex_errors.xml,v 1.3 2013/06/21 22:50:58 jeshua Exp $ --> +<!-- Error definitions for sbe_load_ring_vec_ex procedure --> +<hwpErrors> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_SBE_LOAD_RING_VEC_EX_ex_time_core_ERROR</rc> + <description> + Procedure: proc_sbe_ex_core_gptr_time_initf + Failed to find a chiplet to scan for ex_time_core + </description> + <!-- JDS TODO - this FFDC should probably only log the target engine + and should log something about the target EX --> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_SBE_LOAD_RING_VEC_EX_ex_time_eco_ERROR</rc> + <description> + Procedure: proc_sbe_ex_gptr_time_initf + Failed to find a chiplet to scan for ex_time_eco + </description> + <!-- JDS TODO - this FFDC should probably only log the target engine + and should log something about the target EX --> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_SBE_LOAD_RING_VEC_EX_ex_repr_core_ERROR</rc> + <description> + Procedure: proc_sbe_ex_core_repair_initf + Failed to find a chiplet to scan for ex_repr_core</description> + <!-- JDS TODO - this FFDC should probably only log the target engine + and should log something about the target EX --> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_SBE_LOAD_RING_VEC_EX_ex_repr_eco_ERROR</rc> + <description> + Procedure: proc_sbe_ex_repair_initf + Failed to find a chiplet to scan for ex_repr_eco + </description> + <!-- JDS TODO - this FFDC should probably only log the target engine + and should log something about the target EX --> + <collectRegisterFfdc> + <id>REG_FFDC_PROC_STATUS_AND_SBE_VITAL_REGISTERS</id> + <id>REG_FFDC_PROC_SBE_REGISTERS</id> + <id>REG_FFDC_PROC_SLW_REGISTERS</id> + <target>CHIP_IN_ERROR</target> + </collectRegisterFfdc> + <sbeError/> + </hwpError> +</hwpErrors> diff --git a/src/usr/hwpf/hwp/runtime_errors/p8_pstate_registers.xml b/src/usr/hwpf/hwp/runtime_errors/p8_pstate_registers.xml index b7a3a82f6..76b89fe3f 100644 --- a/src/usr/hwpf/hwp/runtime_errors/p8_pstate_registers.xml +++ b/src/usr/hwpf/hwp/runtime_errors/p8_pstate_registers.xml @@ -20,24 +20,80 @@ <!-- Origin: 30 --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- $Id: p8_pstate_registers.xml,v 1.1 2014/01/24 23:40:22 jdavidso Exp $ --> +<!-- $Id: p8_pstate_registers.xml,v 1.3 2014/03/05 21:03:14 stillgs Exp $ --> <!-- Definition of PMC registers to collect on some errors --> <hwpErrors> <registerFfdc> <id>REG_FFDC_PSTATE_REGISTERS</id> <scomRegister>PMC_STATUS_REG_0x00062009</scomRegister> - <scomRegister>PMC_LFIR_0x01010840</scomRegister> - <scomRegister>PMC_LFIR_MASK_0x01010843</scomRegister> - <scomRegister>PMC_MODE_REG_0x00062000</scomRegister> - <scomRegister>PMC_PSTATE_MONITOR_AND_CTRL_REG_0x00062002</scomRegister> - <scomRegister>PMC_RAIL_BOUNDS_0x00062003</scomRegister> - <scomRegister>PMC_PARAMETER_REG0_0x00062005</scomRegister> - <scomRegister>PMC_PARAMETER_REG1_0x00062006</scomRegister> - <scomRegister>PMC_EFF_GLOBAL_ACTUAL_VOLTAGE_REG_0x00062007</scomRegister> - <scomRegister>PMC_INTCHP_CTRL_REG1_0x00062010</scomRegister> - <scomRegister>PMC_INTCHP_CTRL_REG4_0x00062012</scomRegister> - <scomRegister>PMC_INTCHP_STATUS_REG_0x00062013</scomRegister> - <scomRegister>PMC_INTCHP_PSTATE_REG_0x00062017</scomRegister> - <scomRegister>PMC_INTCHP_COMMAND_REG_0x00062014</scomRegister> + <scomRegister>PMC_LFIR_0x01010840</scomRegister> + <scomRegister>PMC_LFIR_MASK_0x01010843</scomRegister> + <scomRegister>PMC_MODE_REG_0x00062000</scomRegister> + <scomRegister>PMC_PSTATE_MONITOR_AND_CTRL_REG_0x00062002</scomRegister> + <scomRegister>PMC_RAIL_BOUNDS_0x00062003</scomRegister> + <scomRegister>PMC_PARAMETER_REG0_0x00062005</scomRegister> + <scomRegister>PMC_PARAMETER_REG1_0x00062006</scomRegister> + <scomRegister>PMC_EFF_GLOBAL_ACTUAL_VOLTAGE_REG_0x00062007</scomRegister> + <scomRegister>PMC_INTCHP_CTRL_REG1_0x00062010</scomRegister> + <scomRegister>PMC_INTCHP_CTRL_REG4_0x00062012</scomRegister> + <scomRegister>PMC_INTCHP_STATUS_REG_0x00062013</scomRegister> + <scomRegister>PMC_INTCHP_PSTATE_REG_0x00062017</scomRegister> + <scomRegister>PMC_INTCHP_COMMAND_REG_0x00062014</scomRegister> + </registerFfdc> + <registerFfdc> + <id>REG_FFDC_O2S_REGISTERS</id> + <scomRegister>PMC_O2S_CTRL_REG0A_0x00062050</scomRegister> + <scomRegister>PMC_O2S_CTRL_REG0B_0x00062051</scomRegister> + <scomRegister>PMC_O2S_CTRL_REG1_0x00062052</scomRegister> + <scomRegister>PMC_O2S_CTRL_REG2_0x00062053</scomRegister> + <scomRegister>PMC_O2S_CTRL_REG4_0x00062055</scomRegister> + <scomRegister>PMC_O2S_STATUS_REG_0x00062056</scomRegister> + <scomRegister>PMC_O2S_COMMAND_REG_0x00062057</scomRegister> + <scomRegister>PMC_O2S_WDATA_REG_0x00062058</scomRegister> + <scomRegister>PMC_O2S_RDATA_REG_0x00062059</scomRegister> + </registerFfdc> + <registerFfdc> + <id>REG_FFDC_SPIVID_REGISTERS</id> + <scomRegister>PMC_SPIV_CTRL_REG0A_0x00062040</scomRegister> + <scomRegister>PMC_SPIV_CTRL_REG0B_0x00062041</scomRegister> + <scomRegister>PMC_SPIV_CTRL_REG1_0x00062042</scomRegister> + <scomRegister>PMC_SPIV_CTRL_REG2_0x00062043</scomRegister> + <scomRegister>PMC_SPIV_CTRL_REG3_0x00062044</scomRegister> + <scomRegister>PMC_SPIV_CTRL_REG4_0x00062045</scomRegister> + <scomRegister>PMC_SPIV_STATUS_REG_0x00062046</scomRegister> + <scomRegister>PMC_SPIV_COMMAND_REG_0x00062047</scomRegister> + </registerFfdc> + <registerFfdc> + <id>REG_FFDC_PCBS_PSSTATE_REGISTERS</id> + <scomRegister>EX_DPLL_CPM_PARM_REG_0x100F0152</scomRegister> + <scomRegister>EX_PCBS_POWER_MANAGEMENT_STATUS_REG_0x100F0153</scomRegister> + <scomRegister>EX_PCBS_iVRM_Control_Status_Reg_0x100F0154</scomRegister> + <scomRegister>EX_PCBS_iVRM_Value_Setting_Reg_0x100F0155</scomRegister> + <scomRegister>EX_PCBSPM_MODE_REG_0x100F0156</scomRegister> + <scomRegister>EX_PCBS_iVRM_PFETSTR_Sense_Reg_0x100F0157</scomRegister> + <scomRegister>EX_PCBS_Power_Management_Idle_Control_Reg_0x100F0158</scomRegister> + <scomRegister>EX_PCBS_Power_Management_Control_Reg_0x100F0159</scomRegister> + <scomRegister>EX_PCBS_PMC_VF_CTRL_REG_0x100F015A</scomRegister> + <scomRegister>EX_PCBS_UNDERVOLTING_REG_0x100F015B</scomRegister> + <scomRegister>EX_PCBS_Pstate_Index_Bound_Reg_0x100F015C</scomRegister> + <scomRegister>EX_PCBS_Power_Management_Bounds_Reg_0x100F015D</scomRegister> + <scomRegister>EX_PCBS_PSTATE_TABLE_CTRL_REG_0x100F015E</scomRegister> + <scomRegister>EX_PCBS_PSTATE_TABLE_REG_0x100F015F</scomRegister> + <scomRegister>EX_PCBS_Pstate_Step_Target_Register_0x100F0160</scomRegister> + <scomRegister>EX_PCBS_iVRM_VID_Control_Reg0_0x100F0162</scomRegister> + <scomRegister>EX_PCBS_DPLL_STATUS_REG_100F0161</scomRegister> + <scomRegister>EX_PCBS_iVRM_VID_Control_Reg1_0x100F0163</scomRegister> + <scomRegister>EX_PCBS_Resonant_Clock_Control_Reg0_0x100F0165</scomRegister> + <scomRegister>EX_PCBS_Resonant_Clock_Control_Reg1_0x100F0166</scomRegister> + <scomRegister>EX_PCBS_Resonant_Clock_Status_Reg_0x100F0167</scomRegister> + <scomRegister>EX_PCBS_FSM_MONITOR1_REG_0x100F0170</scomRegister> + <scomRegister>EX_PCBS_FSM_MONITOR2_REG_0x100F0171</scomRegister> + </registerFfdc> + <registerFfdc> + <id>REG_FFDC_PCBS_PSSTATE_MONITOR_REGISTERS</id> + <scomRegister>EX_DPLL_CPM_PARM_REG_0x100F0152</scomRegister> + <scomRegister>EX_PCBS_PMC_VF_CTRL_REG_0x100F015A</scomRegister> + <scomRegister>EX_PCBS_FSM_MONITOR1_REG_0x100F0170</scomRegister> + <scomRegister>EX_PCBS_FSM_MONITOR2_REG_0x100F0171</scomRegister> </registerFfdc> </hwpErrors> diff --git a/src/usr/hwpf/makefile b/src/usr/hwpf/makefile index 9acf90e55..32e5ac23f 100644 --- a/src/usr/hwpf/makefile +++ b/src/usr/hwpf/makefile @@ -93,7 +93,6 @@ HWP_ERROR_XML_FILES = hwp/fapiHwpErrorInfo.xml \ hwp/pstates/pstates/proc_get_voltage_errors.xml \ hwp/proc_cfam_registers.xml \ hwp/p8_slw_registers.xml \ - hwp/proc_sbe_select_ex_errors.xml \ hwp/utility_procedures/memory_mss_maint_cmds.xml \ hwp/mc_config/mss_volt/memory_mss_volt.xml \ hwp/mc_config/mss_freq/memory_mss_freq.xml \ @@ -146,7 +145,28 @@ HWP_ERROR_XML_FILES = hwp/fapiHwpErrorInfo.xml \ hwp/bus_training/io_read_erepair_errors.xml \ hwp/bus_training/io_fir_isolation_errors.xml \ hwp/bus_training/io_restore_erepair_errors.xml \ - hwp/bus_training/io_cleanup_errors.xml + hwp/bus_training/io_cleanup_errors.xml \ + hwp/proc_pibmem_registers.xml \ + hwp/proc_clock_control_registers.xml \ + hwp/proc_sbe_errors/proc_sbe_check_master_errors.xml \ + hwp/proc_sbe_errors/proc_sbe_chiplet_init_errors.xml \ + hwp/proc_sbe_errors/proc_sbe_decompress_scan_halt_codes.xml \ + hwp/proc_sbe_errors/proc_sbe_ex_dpll_setup_halt_codes.xml \ + hwp/proc_sbe_errors/proc_sbe_ex_startclocks_errors.xml \ + hwp/proc_sbe_errors/proc_sbe_fabricinit_errors.xml \ + hwp/proc_sbe_errors/proc_sbe_instruct_start_errors.xml \ + hwp/proc_sbe_errors/proc_sbe_lco_loader_errors.xml \ + hwp/proc_sbe_errors/proc_sbe_npll_setup_errors.xml \ + hwp/proc_sbe_errors/proc_sbe_pb_startclocks.xml \ + hwp/proc_sbe_errors/proc_sbe_pibmem_loader_halt_codes.xml \ + hwp/proc_sbe_errors/proc_sbe_scominit_errors.xml \ + hwp/proc_sbe_errors/proc_sbe_select_ex_errors.xml \ + hwp/proc_sbe_errors/proc_sbe_setup_evid_errors.xml \ + hwp/proc_sbe_errors/proc_sbe_tp_switch_gears_errors.xml \ + hwp/proc_sbe_errors/proc_sbe_trigger_winkle_errors.xml \ + hwp/proc_sbe_errors/proc_slw_base_halt_codes.xml \ + hwp/proc_sbe_errors/sbe_common_halt_codes.xml \ + hwp/proc_sbe_errors/sbe_load_ring_vec_ex_errors.xml ## these get generated into obj/genfiles/AttributeIds.H HWP_ATTR_XML_FILES = hwp/memory_attributes.xml \ |
