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| author | Zane Shelley <zshelle@us.ibm.com> | 2018-07-23 10:37:03 -0500 |
|---|---|---|
| committer | Zane C. Shelley <zshelle@us.ibm.com> | 2018-07-27 21:31:41 -0500 |
| commit | da9d0e7c5ed5ad0d86edb19edd0ebfc94a1de078 (patch) | |
| tree | 69182aed93ae1d3f9bce95f3cff84b1b20cb9332 /src/usr | |
| parent | df829c02d7d5ef1c76ac73c4ef3b18d3e7f58820 (diff) | |
| download | talos-hostboot-da9d0e7c5ed5ad0d86edb19edd0ebfc94a1de078.tar.gz talos-hostboot-da9d0e7c5ed5ad0d86edb19edd0ebfc94a1de078.zip | |
PRD: Add core scratch register 3 to FFDC
Change-Id: Ia30fb1b688bc60ea44b8998cd9930f8525b9eaca
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63146
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Brian J. Stegmiller <bjs@us.ibm.com>
Reviewed-by: Benjamin J. Weisenbeck <bweisenb@us.ibm.com>
Reviewed-by: Caleb N. Palmer <cnpalmer@us.ibm.com>
Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63397
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Diffstat (limited to 'src/usr')
| -rw-r--r-- | src/usr/diag/prdf/common/plat/p9/p9_proc_common_regs.rule | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/usr/diag/prdf/common/plat/p9/p9_proc_common_regs.rule b/src/usr/diag/prdf/common/plat/p9/p9_proc_common_regs.rule index c27983cf6..5da5bf198 100644 --- a/src/usr/diag/prdf/common/plat/p9/p9_proc_common_regs.rule +++ b/src/usr/diag/prdf/common/plat/p9/p9_proc_common_regs.rule @@ -27,6 +27,16 @@ # Additional registers for nimbus chip, not defined in XML ################################################################################ + # This register helps us determine where in the IPL the attention occurred. + # Possible values for this register (in ASCII): hostboot, bootload, shutdown + + register CORE_SCRATCH_REG_3 + { + name "Core scratch register 3"; + scomaddr 0x41010A89; + capture group default; + }; + ############################################################################ # N3 Chiplet PBEXTFIR ############################################################################ |
