diff options
| author | Zane Shelley <zshelle@us.ibm.com> | 2015-04-03 17:16:35 -0500 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2015-08-26 21:44:08 -0500 |
| commit | d774efe81a106739311388eb78ec4be20fb1901a (patch) | |
| tree | 105f13ad1bb8bc06fc2f9216059f15bf06af7eb0 /src/usr | |
| parent | 0012c29e1b559a726b8cb2df3787d3a759974a11 (diff) | |
| download | talos-hostboot-d774efe81a106739311388eb78ec4be20fb1901a.tar.gz talos-hostboot-d774efe81a106739311388eb78ec4be20fb1901a.zip | |
PRD: Chip support for the Naples processor
Change-Id: I7bda81f516a0df7519bf6d651187d18fe5c2971b
RTC: 119021
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/18016
Reviewed-by: Caleb N. Palmer <cnpalmer@us.ibm.com>
Tested-by: Jenkins Server
Reviewed-by: Brian J. Stegmiller <bjs@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Reviewed-by: Zane Shelley <zshelle@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/20082
Tested-by: Jenkins OP Build CI
Tested-by: Jenkins OP HW
Diffstat (limited to 'src/usr')
27 files changed, 2213 insertions, 745 deletions
diff --git a/src/usr/diag/prdf/common/framework/rule/prdfPluginDef.H b/src/usr/diag/prdf/common/framework/rule/prdfPluginDef.H index 54d4a91ba..a3c1f7164 100755 --- a/src/usr/diag/prdf/common/framework/rule/prdfPluginDef.H +++ b/src/usr/diag/prdf/common/framework/rule/prdfPluginDef.H @@ -5,7 +5,9 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* COPYRIGHT International Business Machines Corp. 2004,2014 */ +/* Contributors Listed Below - COPYRIGHT 2012,2015 */ +/* [+] International Business Machines Corp. */ +/* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ /* you may not use this file except in compliance with the License. */ @@ -342,6 +344,9 @@ inline Plugin_4arg<_A, _B, _C, _D, _ExtensibleObject> * #define __PRDF_PLUGIN_MAKENAME(X,Y,Z) __PRDF_PLUGIN_XYZ(X,Y,Z) #define PRDF_PLUGIN_DEFINE(CHIP,PLUGIN_NAME) \ + PRDF_PLUGIN_DEFINE_NS(CHIP,CHIP,PLUGIN_NAME) + +#define PRDF_PLUGIN_DEFINE_NS(CHIP,NAMESPACE,PLUGIN_NAME) \ class __PRDF_PLUGIN_MAKENAME(Plugin_Registration_,CHIP,PLUGIN_NAME) \ { \ private: \ @@ -350,7 +355,7 @@ inline Plugin_4arg<_A, _B, _C, _D, _ExtensibleObject> * char cv_plugin_space[sizeof(Plugin<ExtensibleChip>)]; \ public: \ __PRDF_PLUGIN_MAKENAME(Plugin_Registration_,CHIP,PLUGIN_NAME)() : \ - cv_plugin( bind_plugin_ptr(&CHIP::PLUGIN_NAME, \ + cv_plugin( bind_plugin_ptr(&NAMESPACE::PLUGIN_NAME, \ &cv_plugin_space) ), \ cv_registerClass(#CHIP,#PLUGIN_NAME,cv_plugin) \ {} \ diff --git a/src/usr/diag/prdf/common/framework/rule/prdfRuleFiles.C b/src/usr/diag/prdf/common/framework/rule/prdfRuleFiles.C index 000fe1581..dfe079d0b 100755 --- a/src/usr/diag/prdf/common/framework/rule/prdfRuleFiles.C +++ b/src/usr/diag/prdf/common/framework/rule/prdfRuleFiles.C @@ -5,7 +5,9 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* COPYRIGHT International Business Machines Corp. 2008,2014 */ +/* Contributors Listed Below - COPYRIGHT 2012,2015 */ +/* [+] International Business Machines Corp. */ +/* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ /* you may not use this file except in compliance with the License. */ @@ -32,7 +34,8 @@ namespace PRDF { // Pegasus P8 Chip - const char * Proc = "Proc"; + const char * MuranoVeniceProc = "MuranoVeniceProc"; + const char * NaplesProc = "NaplesProc"; const char * Ex = "Ex"; const char * Mcs = "Mcs"; diff --git a/src/usr/diag/prdf/common/framework/rule/prdfRuleFiles.H b/src/usr/diag/prdf/common/framework/rule/prdfRuleFiles.H index 60184abe9..a30aad875 100755 --- a/src/usr/diag/prdf/common/framework/rule/prdfRuleFiles.H +++ b/src/usr/diag/prdf/common/framework/rule/prdfRuleFiles.H @@ -5,7 +5,9 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* COPYRIGHT International Business Machines Corp. 2004,2014 */ +/* Contributors Listed Below - COPYRIGHT 2012,2015 */ +/* [+] International Business Machines Corp. */ +/* */ /* */ /* Licensed under the Apache License, Version 2.0 (the "License"); */ /* you may not use this file except in compliance with the License. */ @@ -33,7 +35,8 @@ namespace PRDF { // Pegasus P8 Chip - extern const char * Proc; + extern const char * MuranoVeniceProc; + extern const char * NaplesProc; extern const char * Ex; extern const char * Mcs; diff --git a/src/usr/diag/prdf/common/framework/rule/prdf_rule.mk b/src/usr/diag/prdf/common/framework/rule/prdf_rule.mk index d6da96f09..72e92ce53 100644 --- a/src/usr/diag/prdf/common/framework/rule/prdf_rule.mk +++ b/src/usr/diag/prdf/common/framework/rule/prdf_rule.mk @@ -24,7 +24,8 @@ # IBM_PROLOG_END_TAG # Add Rule tables here: -PRDR_RULE_TABLES += Proc.prf +PRDR_RULE_TABLES += MuranoVeniceProc.prf +PRDR_RULE_TABLES += NaplesProc.prf PRDR_RULE_TABLES += Ex.prf PRDR_RULE_TABLES += Mcs.prf PRDR_RULE_TABLES += Membuf.prf diff --git a/src/usr/diag/prdf/common/iipconst.h b/src/usr/diag/prdf/common/iipconst.h index 9156795b2..62410a432 100755 --- a/src/usr/diag/prdf/common/iipconst.h +++ b/src/usr/diag/prdf/common/iipconst.h @@ -77,6 +77,7 @@ enum DOMAIN_ID MBA_DOMAIN = 0x75, XBUS_DOMAIN = 0x76, ABUS_DOMAIN = 0x77, + NV_DOMAIN = 0x78, CLOCK_DOMAIN_FAB = 0x90, CLOCK_DOMAIN_MCS = 0x91, diff --git a/src/usr/diag/prdf/common/plat/pegasus/MuranoVeniceProc.rule b/src/usr/diag/prdf/common/plat/pegasus/MuranoVeniceProc.rule new file mode 100644 index 000000000..5c0a74155 --- /dev/null +++ b/src/usr/diag/prdf/common/plat/pegasus/MuranoVeniceProc.rule @@ -0,0 +1,170 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/common/plat/pegasus/MuranoVeniceProc.rule $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2015 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +chip Proc +{ + name "Power8 Murano or Venice Chip"; + targettype TYPE_PROC; + sigoff 0x8000; + dump DUMP_CONTENT_HW; + scomlen 64; + +#Import signatures +.include "prdfP8ProcExtraSig.H"; +.include "prdfP8ProcMbCommonExtraSig.H"; + +#Import Common Proc Registers +.include "Proc_regs_common.rule" + +# Import all of the chiplet registers +.include "Proc_regs_TP.rule" +.include "Proc_regs_PB.rule" +.include "Proc_regs_XBUS.rule" +.include "Proc_regs_ABUS.rule" +.include "Proc_regs_PCIE.rule" + +}; + +################################################################################ +# Global Broadcast Registers +################################################################################ + +rule GlobalFir +{ + CHECK_STOP: GLOBAL_CS_FIR; + RECOVERABLE: GLOBAL_RE_FIR; +}; + +group gGlobalFir attntype CHECK_STOP, RECOVERABLE filter singlebit +{ + /** GLOBAL_FIR[1] + * Attention from TP chiplet + */ + (GlobalFir, bit(1)) ? analyze(gTpChipletFir); + + /** GLOBAL_FIR[2] + * Attention from PB chiplet + */ + (GlobalFir, bit(2)) ? analyze(gPbChipletFir); + + /** GLOBAL_FIR[4] + * Attention from XBUS chiplet + */ + (GlobalFir, bit(4)) ? analyze(gXbusChipletFir); + + /** GLOBAL_FIR[8] + * Attention from ABUS + */ + (GlobalFir, bit(8)) ? analyze(gAbusChipletFir); + + /** GLOBAL_FIR[9] + * Attention from PCIE + */ + (GlobalFir, bit(9)) ? analyze(gPcieChipletFir); + + /** GLOBAL_FIR[17] + * Attention from EX1 (Venice only) + */ + (GlobalFir, bit(17)) ? analyzeEx1; + + /** GLOBAL_FIR[18] + * Attention from EX2 (Venice only) + */ + (GlobalFir, bit(18)) ? analyzeEx2; + + /** GLOBAL_FIR[19] + * Attention from EX3 (Venice only) + */ + (GlobalFir, bit(19)) ? analyzeEx3; + + /** GLOBAL_FIR[20] + * Attention from EX4 + */ + (GlobalFir, bit(20)) ? analyzeEx4; + + /** GLOBAL_FIR[21] + * Attention from EX5 + */ + (GlobalFir, bit(21)) ? analyzeEx5; + + /** GLOBAL_FIR[22] + * Attention from EX6 + */ + (GlobalFir, bit(22)) ? analyzeEx6; + + /** GLOBAL_FIR[25] + * Attention from EX9 (Venice only) + */ + (GlobalFir, bit(25)) ? analyzeEx9; + + /** GLOBAL_FIR[26] + * Attention from EX10 (Venice only) + */ + (GlobalFir, bit(26)) ? analyzeEx10; + + /** GLOBAL_FIR[27] + * Attention from EX11 (Venice only) + */ + (GlobalFir, bit(27)) ? analyzeEx11; + + /** GLOBAL_FIR[28] + * Attention from EX12 + */ + (GlobalFir, bit(28)) ? analyzeEx12; + + /** GLOBAL_FIR[29] + * Attention from EX13 + */ + (GlobalFir, bit(29)) ? analyzeEx13; + + /** GLOBAL_FIR[30] + * Attention from EX14 + */ + (GlobalFir, bit(30)) ? analyzeEx14; +}; + +# Import all of the chiplet rules and actions +# NOTE: Some of PB local FIRs are handled through the TP chiplet FIRs +.include "Proc_acts_TP.rule" +.include "Proc_acts_PB.rule" +.include "Proc_acts_XBUS.rule" +.include "Proc_acts_ABUS.rule" +.include "Proc_acts_PCIE.rule" + + ############################################################################## + # # + # # ### # + # # # ## ##### ### ### # # # # # # ### ### ### ### # + # # # # # # # # # ## # # # # # # # # # # + # ####### # # # # # # # # # # ##### ### ### ## ### # + # # # # # # # # # # ## # # # # # # # # # # + # # # ## # ### ### # # ### ### # # ### ### ### ### # + # # + ############################################################################## + +# Include the common action set. +.include "CommonActions.rule" + +#import common Proc actions +.include "Proc_acts_common.rule" diff --git a/src/usr/diag/prdf/common/plat/pegasus/NaplesProc.rule b/src/usr/diag/prdf/common/plat/pegasus/NaplesProc.rule new file mode 100644 index 000000000..d0b1da33d --- /dev/null +++ b/src/usr/diag/prdf/common/plat/pegasus/NaplesProc.rule @@ -0,0 +1,170 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/common/plat/pegasus/NaplesProc.rule $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2015 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +chip Proc +{ + name "Power8 Naples Chip"; + targettype TYPE_PROC; + sigoff 0x4000; + dump DUMP_CONTENT_HW; + scomlen 64; + +#Import signatures +.include "prdfP8ProcExtraSig.H"; +.include "prdfP8ProcMbCommonExtraSig.H"; + +#Import Common Proc rule file +.include "Proc_regs_common.rule" + +# Import all of the chiplet registers +.include "Proc_regs_TP.rule" +.include "Proc_regs_PB.rule" +.include "Proc_regs_XBUS.rule" +.include "Proc_regs_NV.rule" +.include "Proc_regs_PCIE.rule" + +}; + +################################################################################ +# Global Broadcast Registers +################################################################################ + +rule GlobalFir +{ + CHECK_STOP: GLOBAL_CS_FIR; + RECOVERABLE: GLOBAL_RE_FIR; +}; + +group gGlobalFir attntype CHECK_STOP, RECOVERABLE filter singlebit +{ + /** GLOBAL_FIR[1] + * Attention from TP chiplet + */ + (GlobalFir, bit(1)) ? analyze(gTpChipletFir); + + /** GLOBAL_FIR[2] + * Attention from PB chiplet + */ + (GlobalFir, bit(2)) ? analyze(gPbChipletFir); + + /** GLOBAL_FIR[4] + * Attention from XBUS chiplet + */ + (GlobalFir, bit(4)) ? analyze(gXbusChipletFir); + + /** GLOBAL_FIR[8] + * Attention from NV + */ + (GlobalFir, bit(8)) ? analyze(gNvChipletFir); + + /** GLOBAL_FIR[9] + * Attention from PCIE + */ + (GlobalFir, bit(9)) ? analyze(gPcieChipletFir); + + /** GLOBAL_FIR[17] + * Attention from EX1 (Venice only) + */ + (GlobalFir, bit(17)) ? analyzeEx1; + + /** GLOBAL_FIR[18] + * Attention from EX2 (Venice only) + */ + (GlobalFir, bit(18)) ? analyzeEx2; + + /** GLOBAL_FIR[19] + * Attention from EX3 (Venice only) + */ + (GlobalFir, bit(19)) ? analyzeEx3; + + /** GLOBAL_FIR[20] + * Attention from EX4 + */ + (GlobalFir, bit(20)) ? analyzeEx4; + + /** GLOBAL_FIR[21] + * Attention from EX5 + */ + (GlobalFir, bit(21)) ? analyzeEx5; + + /** GLOBAL_FIR[22] + * Attention from EX6 + */ + (GlobalFir, bit(22)) ? analyzeEx6; + + /** GLOBAL_FIR[25] + * Attention from EX9 (Venice only) + */ + (GlobalFir, bit(25)) ? analyzeEx9; + + /** GLOBAL_FIR[26] + * Attention from EX10 (Venice only) + */ + (GlobalFir, bit(26)) ? analyzeEx10; + + /** GLOBAL_FIR[27] + * Attention from EX11 (Venice only) + */ + (GlobalFir, bit(27)) ? analyzeEx11; + + /** GLOBAL_FIR[28] + * Attention from EX12 + */ + (GlobalFir, bit(28)) ? analyzeEx12; + + /** GLOBAL_FIR[29] + * Attention from EX13 + */ + (GlobalFir, bit(29)) ? analyzeEx13; + + /** GLOBAL_FIR[30] + * Attention from EX14 + */ + (GlobalFir, bit(30)) ? analyzeEx14; +}; + +# Import all of the chiplet rules and actions +# NOTE: Some of PB local FIRs are handled through the TP chiplet FIRs +.include "Proc_acts_TP.rule" +.include "Proc_acts_PB.rule" +.include "Proc_acts_XBUS.rule" +.include "Proc_acts_NV.rule" +.include "Proc_acts_PCIE.rule" + + ############################################################################## + # # + # # ### # + # # # ## ##### ### ### # # # # # # ### ### ### ### # + # # # # # # # # # ## # # # # # # # # # # + # ####### # # # # # # # # # # ##### ### ### ## ### # + # # # # # # # # # # ## # # # # # # # # # # + # # # ## # ### ### # # ### ### # # ### ### ### ### # + # # + ############################################################################## + +# Include the common action set. +.include "CommonActions.rule" + +#import common Proc actions +.include "Proc_acts_common.rule" diff --git a/src/usr/diag/prdf/common/plat/pegasus/Proc.rule b/src/usr/diag/prdf/common/plat/pegasus/Proc.rule deleted file mode 100755 index fdc2c0d86..000000000 --- a/src/usr/diag/prdf/common/plat/pegasus/Proc.rule +++ /dev/null @@ -1,480 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: src/usr/diag/prdf/common/plat/pegasus/Proc.rule $ -# -# OpenPOWER HostBoot Project -# -# Contributors Listed Below - COPYRIGHT 2012,2015 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG - -################################################################################ -# -# Scope: -# Registers and actions for the following chiplets: -# -# Chiplet Register Adddresses Description -# ======= ======================= ============================================ -# TP 0x01000000 - 0x01FFFFFF TP pervasive logic -# PB 0x02000000 - 0x02FFFFFF PB pervasive logic, note that this does -# include the SCOM addresses characterized by -# the MCS target. See Mcs.rule for those -# address ranges. -# XBUS 0x04000000 - 0x0400FFFF XBUS pervasive logic -# ABUS 0x08000000 - 0x0800FFFF ABUS pervasive logic -# PCIE 0x09000000 - 0x09FFFFFF PCIE pervasive logic -# -################################################################################ - -chip Proc -{ - name "Power8 Chip"; - targettype TYPE_PROC; - sigoff 0x8000; - dump DUMP_CONTENT_HW; - scomlen 64; - - -# Include Extra signatures -.include "prdfP8ProcExtraSig.H"; -.include "prdfP8ProcMbCommonExtraSig.H"; - - ############################################################################# - # # - # ###### # - # # # ###### #### ### #### ##### ###### ##### #### # - # # # # # # # # # # # # # # - # ###### ##### # # #### # ##### # # #### # - # # # # # ### # # # # ##### # # - # # # # # # # # # # # # # # # # - # # # ###### #### ### #### # ###### # # #### # - # # - ############################################################################# - - ############################################################################ - # Global Broadcast Registers - ############################################################################ - - register GLOBAL_CS_FIR - { - name "Global Checkstop Attention FIR"; - scomaddr 0x570F001C; - capture group default; - }; - - register GLOBAL_RE_FIR - { - name "Global Recoverable Attention FIR"; - scomaddr 0x570F001B; - capture group default; - }; - - register GLOBAL_SPA - { - name "Global Special Attention FIR"; - scomaddr 0x570F001A; - capture group default; - }; - - register GLOBALUNITXSTPFIR - { - name "Virtual Global Unit Checkstop FIR"; - scomaddr 0x51040001; - capture group default; - capture req funccall("CoreConfiguredAndNotHostboot"); - }; - -# Import all of the chiplet registers -.include "Proc_regs_TP.rule" -.include "Proc_regs_PB.rule" -.include "Proc_regs_XBUS.rule" -.include "Proc_regs_ABUS.rule" -.include "Proc_regs_PCIE.rule" - - ######################################################################## - # Non-existent Registers for Capture - ######################################################################## - register VPD_FAILED_LANES_0TO63 - { - name "Bit map 0-63 of failed lanes read from VPD"; - scomaddr 0xFFFF0001; - access no_access; - capture group never; - }; - - register VPD_FAILED_LANES_64TO127 - { - name "Bit map 64-127 of failed lanes read from VPD"; - scomaddr 0xFFFF0002; - access no_access; - capture group never; - }; - - register ALL_FAILED_LANES_0TO63 - { - name "Bit map 0-63 of failed lanes from io_read_erepair"; - scomaddr 0xFFFF0003; - access no_access; - capture group never; - }; - - register ALL_FAILED_LANES_64TO127 - { - name "Bit map 64-127 of failed lanes from io_read_erepair"; - scomaddr 0xFFFF0004; - access no_access; - capture group never; - }; - - ############################################################################ - # Non-FIR Registers - ############################################################################ - - register TODWOF - { - name "Time of Day / WOF Counter"; - scomaddr 0x00040020; - capture group default; - }; - - ############################################################################ - # PLL Registers - ############################################################################ - - register CFAM_FSI_STATUS - { - name "TPC.FSI.FSI2PIB.STATUS"; - scomaddr 0x00001007; - capture group never; - }; - - register CFAM_FSI_GP7 - { - name "TPC.FSI.FSI_MAILBOX.FSXCOMP.FSXLOG.FSIGP7"; - scomaddr 0x00002816; - capture group never; - }; - - register PCIE_OSC_SWITCH - { - name "TPC.FSI.FSI_MAILBOX.FSXCOMP.FSXLOG.SNS1LTH"; - scomaddr 0x00050019; - capture group PllFIRs; - }; - - register OSCERR - { - name "EH.TPCHIP.TPC.ITR.OSCERR.OSCERR_HOLD"; - scomaddr 0x01020019; - capture group PllFIRs; - }; - - register OSCERR_MASK - { - name "EH.TPCHIP.TPC.ITR.OSCERR.OSCERR_MASK"; - scomaddr 0x0102001A; - capture group PllFIRs; - }; -}; - - ############################################################################## - # # - # #### # # - # # # # # # ##### ### # # # ## ##### ### ### # # ### # - # # # # # # # # # # # # # # # # # ## # # # - # #### # # # #### ### # ####### # # # # # # # # ### # - # # # # # # # # # # # # # # # # # # ## # # - # # # ### #### ##### ### # # # ## # ### ### # # ### # - # # - ############################################################################## - -################################################################################ -# Global Broadcast Registers -################################################################################ - -rule GlobalFir -{ - CHECK_STOP: GLOBAL_CS_FIR; - RECOVERABLE: GLOBAL_RE_FIR; -}; - -group gGlobalFir attntype CHECK_STOP, RECOVERABLE filter singlebit -{ - /** GLOBAL_FIR[1] - * Attention from TP chiplet - */ - (GlobalFir, bit(1)) ? analyze(gTpChipletFir); - - /** GLOBAL_FIR[2] - * Attention from PB chiplet - */ - (GlobalFir, bit(2)) ? analyze(gPbChipletFir); - - /** GLOBAL_FIR[4] - * Attention from XBUS chiplet - */ - (GlobalFir, bit(4)) ? analyze(gXbusChipletFir); - - /** GLOBAL_FIR[8] - * Attention from ABUS chiplet - */ - (GlobalFir, bit(8)) ? analyze(gAbusChipletFir); - - /** GLOBAL_FIR[9] - * Attention from PCIE - */ - (GlobalFir, bit(9)) ? analyze(gPcieChipletFir); - - /** GLOBAL_FIR[17] - * Attention from EX1 (Venice only) - */ - (GlobalFir, bit(17)) ? analyzeEx1; - - /** GLOBAL_FIR[18] - * Attention from EX2 (Venice only) - */ - (GlobalFir, bit(18)) ? analyzeEx2; - - /** GLOBAL_FIR[19] - * Attention from EX3 (Venice only) - */ - (GlobalFir, bit(19)) ? analyzeEx3; - - /** GLOBAL_FIR[20] - * Attention from EX4 - */ - (GlobalFir, bit(20)) ? analyzeEx4; - - /** GLOBAL_FIR[21] - * Attention from EX5 - */ - (GlobalFir, bit(21)) ? analyzeEx5; - - /** GLOBAL_FIR[22] - * Attention from EX6 - */ - (GlobalFir, bit(22)) ? analyzeEx6; - - /** GLOBAL_FIR[25] - * Attention from EX9 (Venice only) - */ - (GlobalFir, bit(25)) ? analyzeEx9; - - /** GLOBAL_FIR[26] - * Attention from EX10 (Venice only) - */ - (GlobalFir, bit(26)) ? analyzeEx10; - - /** GLOBAL_FIR[27] - * Attention from EX11 (Venice only) - */ - (GlobalFir, bit(27)) ? analyzeEx11; - - /** GLOBAL_FIR[28] - * Attention from EX12 - */ - (GlobalFir, bit(28)) ? analyzeEx12; - - /** GLOBAL_FIR[29] - * Attention from EX13 - */ - (GlobalFir, bit(29)) ? analyzeEx13; - - /** GLOBAL_FIR[30] - * Attention from EX14 - */ - (GlobalFir, bit(30)) ? analyzeEx14; -}; - -rule GlobalSpa -{ - SPECIAL: GLOBAL_SPA; -}; - -group gGlobalSpa attntype SPECIAL filter singlebit -{ - /** GLOBAL_SPA[1] - * Attention from TP chiplet - */ - (GlobalSpa, bit(1)) ? analyze(gTpChipletSpa); - - /** GLOBAL_SPA[2] - * Attention from PB chiplet - */ - (GlobalSpa, bit(2)) ? analyze(gPbChipletSpa); - - /** GLOBAL_SPA[9] - * Attention from PCIE - */ - (GlobalSpa, bit(9)) ? analyze(gPcieChipletSpa); - - /** GLOBAL_SPA[11] - * Attention from EX1 (Venice only) - */ - (GlobalSpa, bit(11)) ? analyzeEx1; - - /** GLOBAL_SPA[12] - * Attention from EX2 (Venice only) - */ - (GlobalSpa, bit(12)) ? analyzeEx2; - - /** GLOBAL_SPA[13] - * Attention from EX3 (Venice only) - */ - (GlobalSpa, bit(13)) ? analyzeEx3; - - /** GLOBAL_SPA[14] - * Attention from EX4 - */ - (GlobalSpa, bit(14)) ? analyzeEx4; - - /** GLOBAL_SPA[15] - * Attention from EX5 - */ - (GlobalSpa, bit(15)) ? analyzeEx5; - - /** GLOBAL_SPA[16] - * Attention from EX6 - */ - (GlobalSpa, bit(16)) ? analyzeEx6; - - /** GLOBAL_SPA[19] - * Attention from EX9 (Venice only) - */ - (GlobalSpa, bit(19)) ? analyzeEx9; - - /** GLOBAL_SPA[20] - * Attention from EX10 (Venice only) - */ - (GlobalSpa, bit(20)) ? analyzeEx10; - - /** GLOBAL_SPA[21] - * Attention from EX11 (Venice only) - */ - (GlobalSpa, bit(21)) ? analyzeEx11; - - /** GLOBAL_SPA[22] - * Attention from EX12 - */ - (GlobalSpa, bit(22)) ? analyzeEx12; - - /** GLOBAL_SPA[23] - * Attention from EX13 - */ - (GlobalSpa, bit(23)) ? analyzeEx13; - - /** GLOBAL_SPA[24] - * Attention from EX14 - */ - (GlobalSpa, bit(24)) ? analyzeEx14; -}; - -# Import all of the chiplet rules and actions -# NOTE: Some of PB local FIRs are handled through the TP chiplet FIRs -.include "Proc_acts_TP.rule" -.include "Proc_acts_PB.rule" -.include "Proc_acts_XBUS.rule" -.include "Proc_acts_ABUS.rule" -.include "Proc_acts_PCIE.rule" - - ############################################################################## - # # - # # ### # - # # # ## ##### ### ### # # # # # # ### ### ### ### # - # # # # # # # # # ## # # # # # # # # # # - # ####### # # # # # # # # # # ##### ### ### ## ### # - # # # # # # # # # # ## # # # # # # # # # # - # # # ## # ### ### # # ### ### # # ### ### ### ### # - # # - ############################################################################## - -# Include the common action set. -.include "CommonActions.rule" - -################################################################################ -# Analyze Connected Parts # -################################################################################ - -/** Analyze connected EX1 */ -actionclass analyzeEx1 { analyze(connected(TYPE_EX, 1)); }; - -/** Analyze connected EX2 */ -actionclass analyzeEx2 { analyze(connected(TYPE_EX, 2)); }; - -/** Analyze connected EX3 */ -actionclass analyzeEx3 { analyze(connected(TYPE_EX, 3)); }; - -/** Analyze connected EX4 */ -actionclass analyzeEx4 { analyze(connected(TYPE_EX, 4)); }; - -/** Analyze connected EX5 */ -actionclass analyzeEx5 { analyze(connected(TYPE_EX, 5)); }; - -/** Analyze connected EX6 */ -actionclass analyzeEx6 { analyze(connected(TYPE_EX, 6)); }; - -/** Analyze connected EX9 */ -actionclass analyzeEx9 { analyze(connected(TYPE_EX, 9)); }; - -/** Analyze connected EX10 */ -actionclass analyzeEx10 { analyze(connected(TYPE_EX, 10)); }; - -/** Analyze connected EX11 */ -actionclass analyzeEx11 { analyze(connected(TYPE_EX, 11)); }; - -/** Analyze connected EX12 */ -actionclass analyzeEx12 { analyze(connected(TYPE_EX, 12)); }; - -/** Analyze connected EX13 */ -actionclass analyzeEx13 { analyze(connected(TYPE_EX, 13)); }; - -/** Analyze connected EX14 */ -actionclass analyzeEx14 { analyze(connected(TYPE_EX, 14)); }; - -actionclass calloutProcLevel2MedThr1 -{ - calloutSelfLow; - callout2ndLvlMed; - threshold1; -}; - -/** callout Proc with low priority ,Sec level Med priority, Thr1 - * and dump type SH, garding not done */ -actionclass calloutProcLevel2MedThr1dumpShNoGard -{ - calloutSelfLowNoGard; - callout2ndLvlMedThr1; - dumpSH; -}; - -/** callout Proc with low priority ,Sec level Med priority, Thr 32per day - * and dump type SH , garding not done */ -actionclass calloutProcLevel2MedThr32dumpShNoGard -{ - calloutSelfLow; - callout2ndLvlMed; - threshold32pday; - dumpSH; -}; - -actionclass calloutProcHighThr1SUE -{ - calloutSelfHigh; - SUEGenerationPoint; - threshold1; -}; diff --git a/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_NV.rule b/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_NV.rule new file mode 100755 index 000000000..3da506ba2 --- /dev/null +++ b/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_NV.rule @@ -0,0 +1,197 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/common/plat/pegasus/Proc_acts_NV.rule $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2015 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +################################################################################ +# NV Chiplet Registers +################################################################################ + +rule NvChipletFir +{ + CHECK_STOP: + (NV_CHIPLET_CS_FIR & `1700000000000000`) & ~NV_CHIPLET_FIR_MASK; + RECOVERABLE: + ((NV_CHIPLET_RE_FIR >> 2) & `1700000000000000`) & ~NV_CHIPLET_FIR_MASK; +}; + +group gNvChipletFir filter singlebit +{ + /** NV_CHIPLET_FIR[3] + * Attention from LFIR + */ + (NvChipletFir, bit(3)) ? analyze(gNVLFir); + + /** NV_CHIPLET_FIR[5] + * Attention from IONVFIR_0 + */ + (NvChipletFir, bit(5)) ? analyze(gIoNvFir_0); + + /** NV_CHIPLET_FIR[6] + * Attention from NPU + */ + (NvChipletFir, bit(6)) ? analyze(gNpuFir); + + /** NV_CHIPLET_FIR[7] + * Attention from IONVFIR_1 + */ + (NvChipletFir, bit(7)) ? analyze(gIoNvFir_1); +}; + +################################################################################ +# NV Chiplet LFIR +################################################################################ + +rule NVLFir +{ + CHECK_STOP: NV_LFIR & ~NV_LFIR_MASK & ~NV_LFIR_ACT0 & ~NV_LFIR_ACT1; + RECOVERABLE: NV_LFIR & ~NV_LFIR_MASK & ~NV_LFIR_ACT0 & NV_LFIR_ACT1; +}; + +group gNVLFir filter singlebit +{ + /** NV_LFIR[0] + * CFIR internal parity error + */ + (NVLFir, bit(0)) ? SelfHighThr32PerDay; + + /** NV_LFIR[1] + * Local errors from GPIO (PCB error) + */ + (NVLFir, bit(1)) ? defaultMaskedError; + + /** NV_LFIR[2] + * Local errors from CC (PCB error) + */ + (NVLFir, bit(2)) ? SelfHighThr32PerDay; + + /** NV_LFIR[3] + * Local errors from CC (OPCG, parity, scan collision, ...) + */ + (NVLFir, bit(3)) ? callout2ndLvlMedThr32; + + /** NV_LFIR[4] + * Local errors from PSC (PCB error) + */ + (NVLFir, bit(4)) ? defaultMaskedError; + + /** NV_LFIR[5] + * Local errors from PSC (parity error) + */ + (NVLFir, bit(5)) ? defaultMaskedError; + + /** NV_LFIR[6] + * Local errors from Thermal (parity error) + */ + (NVLFir, bit(6)) ? defaultMaskedError; + + /** NV_LFIR[7] + * Local errors from Thermal (PCB error) + */ + (NVLFir, bit(7)) ? defaultMaskedError; + + /** NV_LFIR[8|9] + * Local errors from Thermal (Trip error) + */ + (NVLFir, bit(8|9)) ? defaultMaskedError; + + /** NV_LFIR[10|11] + * Local errors from Trace Array ( error) + */ + (NVLFir, bit(10|11)) ? defaultMaskedError; + + /** NV_LFIR[12:20] + * FIR_IN12: unused local errors + */ + (NVLFir, bit(12|13|14|15|16|17|18|19|20)) ? defaultMaskedError; + + /** NV_LFIR[21:30] + * FIR_IN12: unused local errors + */ + (NVLFir, bit(21|22|23|24|25|26|27|28|29|30)) ? defaultMaskedError; + + /** NV_LFIR[31:39] + * FIR_IN12: unused local errors + */ + (NVLFir, bit(31|32|33|34|35|36|37|38|39)) ? defaultMaskedError; + + /** NV_LFIR[40] + * Malfunction alert + */ + (NVLFir, bit(40)) ? defaultMaskedError; +}; + +################################################################################ +# NV Chiplet IONVFIR_0s +################################################################################ + +rule IoNvFir_0 +{ + CHECK_STOP: + IONVFIR_0 & ~IONVFIR_0_MASK & ~IONVFIR_0_ACT0 & ~IONVFIR_0_ACT1; + RECOVERABLE: + IONVFIR_0 & ~IONVFIR_0_MASK & ~IONVFIR_0_ACT0 & IONVFIR_0_ACT1; +}; + +group gIoNvFir_0 filter singlebit +{ + /** IONVFIR_0[0:63] + * IONVFIR_0 errors + */ + (IoNvFir_0, bit(0|1|2|3|4|5|6|7|8|9|10|11|12|13|14|15|16|17|18|19|20|21|22|23|24|25|26|27|28|29|30|31|32|33|34|35|36|37|38|39|40|41|42|43|44|45|46|47|48|49|50|51|52|53|54|55|56|57|58|59|60|61|62|63)) ? defaultMaskedError; +}; + +rule IoNvFir_1 +{ + CHECK_STOP: + IONVFIR_1 & ~IONVFIR_1_MASK & ~IONVFIR_1_ACT0 & ~IONVFIR_1_ACT1; + RECOVERABLE: + IONVFIR_1 & ~IONVFIR_1_MASK & ~IONVFIR_1_ACT0 & IONVFIR_1_ACT1; +}; + +group gIoNvFir_1 filter singlebit +{ + /** IONVFIR_1[0:63] + * IONVFIR_1 errors + */ + (IoNvFir_1, bit(0|1|2|3|4|5|6|7|8|9|10|11|12|13|14|15|16|17|18|19|20|21|22|23|24|25|26|27|28|29|30|31|32|33|34|35|36|37|38|39|40|41|42|43|44|45|46|47|48|49|50|51|52|53|54|55|56|57|58|59|60|61|62|63)) ? defaultMaskedError; +}; + +rule NpuFir +{ + CHECK_STOP: NPUFIR & ~NPUFIR_MASK & ~NPUFIR_ACT0 & ~NPUFIR_ACT1; + RECOVERABLE: NPUFIR & ~NPUFIR_MASK & ~NPUFIR_ACT0 & NPUFIR_ACT1; +}; + +group gNpuFir filter singlebit +{ + /** NPUFIR[0:63] + * NPUFIR errors + */ + (NpuFir, bit(0|1|2|3|4|5|6|7|8|9|10|11|12|13|14|15|16|17|18|19|20|21|22|23|24|25|26|27|28|29|30|31|32|33|34|35|36|37|38|39|40|41|42|43|44|45|46|47|48|49|50|51|52|53|54|55|56|57|58|59|60|61|62|63)) ? defaultMaskedError; +}; + +################################################################################ +# Actions specific to NV chiplet +################################################################################ + diff --git a/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_PB.rule b/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_PB.rule index 96d92fee1..82ea81731 100755 --- a/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_PB.rule +++ b/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_PB.rule @@ -30,9 +30,9 @@ rule PbChipletFir { CHECK_STOP: - (PB_CHIPLET_CS_FIR & `1FDFF80000000000`) & ~PB_CHIPLET_FIR_MASK; + (PB_CHIPLET_CS_FIR & `1FDFFE0000000000`) & ~PB_CHIPLET_FIR_MASK; RECOVERABLE: - ((PB_CHIPLET_RE_FIR >> 2 ) & `1FDFF80000000000`) & ~PB_CHIPLET_FIR_MASK; + ((PB_CHIPLET_RE_FIR >> 2 ) & `1FDFFE0000000000`) & ~PB_CHIPLET_FIR_MASK; }; group gPbChipletFir filter singlebit @@ -103,9 +103,22 @@ group gPbChipletFir filter singlebit (PbChipletFir, bit(17|18|19)) ? analyze(gPciNestFir); /** PB_CHIPLET_FIR[20] - * Attention from NXCXAFIR + * Attention from NXCXAFIR_0 */ - (PbChipletFir, bit(20)) ? analyze(gNxCxaFir); + (PbChipletFir, bit(20)) ? analyze(gNxCxaFir_0); + + # It would be nice to include this in the above PCINESTFIRs, however since + # this bit only exists on naples, an attention from bits 17-19 would cause + # us to also try to read PciNestFir3 which would fail on non-naples chips. + /** PB_CHIPLET_FIR[21] + * Attention from PCINESTFIR3 + */ + (PbChipletFir, bit(21)) ? analyze(gPciNestFir3); + + /** PB_CHIPLET_FIR[22] + * Attention from NXCXAFIR_1 + */ + (PbChipletFir, bit(22)) ? analyze(gNxCxaFir_1); }; rule PbChipletSpa @@ -551,250 +564,492 @@ group gNxCqFir filter singlebit }; ################################################################################ -# PB Chiplet NXCXAFIR +# PB Chiplet NXCXAFIR_0 ################################################################################ # p8dd1_mss_FFDC_73_final.xls -rule NxCxaFir +rule NxCxaFir_0 { - CHECK_STOP: NXCXAFIR & ~NXCXAFIR_MASK & ~NXCXAFIR_ACT0 & ~NXCXAFIR_ACT1; - RECOVERABLE: NXCXAFIR & ~NXCXAFIR_MASK & ~NXCXAFIR_ACT0 & NXCXAFIR_ACT1; + CHECK_STOP: + NXCXAFIR_0 & ~NXCXAFIR_0_MASK & ~NXCXAFIR_0_ACT0 & ~NXCXAFIR_0_ACT1; + RECOVERABLE: + NXCXAFIR_0 & ~NXCXAFIR_0_MASK & ~NXCXAFIR_0_ACT0 & NXCXAFIR_0_ACT1; }; -group gNxCxaFir filter singlebit +group gNxCxaFir_0 filter singlebit { - /** NXCXAFIR[0] + /** NXCXAFIR_0[0] * BAR_PE */ - (NxCxaFir, bit(0)) ? defaultMaskedError; + (NxCxaFir_0, bit(0)) ? defaultMaskedError; - /** NXCXAFIR[1] + /** NXCXAFIR_0[1] * REGISTER_PE */ - (NxCxaFir, bit(1)) ? SelfMedThr1; + (NxCxaFir_0, bit(1)) ? SelfMedThr1; - /** NXCXAFIR[2] + /** NXCXAFIR_0[2] * MASTER_ARRAY_CE */ - (NxCxaFir, bit(2)) ? SelfMedThr32PerDay; + (NxCxaFir_0, bit(2)) ? SelfMedThr32PerDay; - /** NXCXAFIR[3] + /** NXCXAFIR_0[3] * MASTER_ARRAY_UE */ - (NxCxaFir, bit(3)) ? SelfMedThr1; + (NxCxaFir_0, bit(3)) ? SelfMedThr1; - /** NXCXAFIR[4] + /** NXCXAFIR_0[4] * TIMER_EXPIRED_RECOV_ERROR */ - (NxCxaFir, bit(4)) ? defaultMaskedError; + (NxCxaFir_0, bit(4)) ? defaultMaskedError; - /** NXCXAFIR[5] + /** NXCXAFIR_0[5] * TIMER_EXPIRED_XSTOP_ERROR */ - (NxCxaFir, bit(5)) ? SelfMedThr1; + (NxCxaFir_0, bit(5)) ? SelfMedThr1; - /** NXCXAFIR[6] + /** NXCXAFIR_0[6] * PSL_CMD_UE */ - (NxCxaFir, bit(6)) ? defaultMaskedError; + (NxCxaFir_0, bit(6)) ? defaultMaskedError; - /** NXCXAFIR[7] + /** NXCXAFIR_0[7] * PSL_CMD_SUE */ - (NxCxaFir, bit(7)) ? defaultMaskedError; + (NxCxaFir_0, bit(7)) ? defaultMaskedError; - /** NXCXAFIR[8] + /** NXCXAFIR_0[8] * SNOOP_ARRAY_CE */ - (NxCxaFir, bit(8)) ? callout2ndLvlMedThr32; + (NxCxaFir_0, bit(8)) ? callout2ndLvlMedThr32; - /** NXCXAFIR[9] + /** NXCXAFIR_0[9] * SNOOP_ARRAY_UE */ - (NxCxaFir, bit(9)) ? SelfMedThr1; + (NxCxaFir_0, bit(9)) ? SelfMedThr1; - /** NXCXAFIR[10] + /** NXCXAFIR_0[10] * RECOVERY_FAILED */ - (NxCxaFir, bit(10)) ? SelfMedThr1; + (NxCxaFir_0, bit(10)) ? SelfMedThr1; - /** NXCXAFIR[11] + /** NXCXAFIR_0[11] * ILLEGAL_LPC_BAR_ACCESS */ - (NxCxaFir, bit(11)) ? defaultMaskedError; + (NxCxaFir_0, bit(11)) ? defaultMaskedError; - /** NXCXAFIR[12] + /** NXCXAFIR_0[12] * XPT_RECOVERABLE_ERROR_MASK */ - (NxCxaFir, bit(12)) ? defaultMaskedError; + (NxCxaFir_0, bit(12)) ? defaultMaskedError; - /** NXCXAFIR[13] + /** NXCXAFIR_0[13] * MASTER_RECOVERABLE_ERROR */ - (NxCxaFir, bit(13)) ? defaultMaskedError; + (NxCxaFir_0, bit(13)) ? defaultMaskedError; - /** NXCXAFIR[14] + /** NXCXAFIR_0[14] * SNOOPER_RECOVERABLE_ERROR */ - (NxCxaFir, bit(14)) ? defaultMaskedError; + (NxCxaFir_0, bit(14)) ? defaultMaskedError; - /** NXCXAFIR[15] + /** NXCXAFIR_0[15] * XPT_RECOVERABLE_ERROR */ - (NxCxaFir, bit(15)) ? defaultMaskedError; + (NxCxaFir_0, bit(15)) ? defaultMaskedError; - /** NXCXAFIR[16] + /** NXCXAFIR_0[16] * MASTER_SYS_XSTOP_ERROR */ - (NxCxaFir, bit(16)) ? SelfMedThr1; + (NxCxaFir_0, bit(16)) ? SelfMedThr1; - /** NXCXAFIR[17] + /** NXCXAFIR_0[17] * SNOOPER_SYS_XSTOP_ERROR */ - (NxCxaFir, bit(17)) ? SelfMedThr1; + (NxCxaFir_0, bit(17)) ? SelfMedThr1; - /** NXCXAFIR[18] + /** NXCXAFIR_0[18] * XPT_SYS_XSTOP_ERROR */ - (NxCxaFir, bit(18)) ? SelfMedThr1; + (NxCxaFir_0, bit(18)) ? SelfMedThr1; - /** NXCXAFIR[19] + /** NXCXAFIR_0[19] * MUOP_ERROR_1 */ - (NxCxaFir, bit(19)) ? defaultMaskedError; + (NxCxaFir_0, bit(19)) ? defaultMaskedError; - /** NXCXAFIR[20] + /** NXCXAFIR_0[20] * MUOP_ERROR_2 */ - (NxCxaFir, bit(20)) ? defaultMaskedError; + (NxCxaFir_0, bit(20)) ? defaultMaskedError; - /** NXCXAFIR[21] + /** NXCXAFIR_0[21] * MUOP_ERROR_3 */ - (NxCxaFir, bit(21)) ? defaultMaskedError; + (NxCxaFir_0, bit(21)) ? defaultMaskedError; - /** NXCXAFIR[22] + /** NXCXAFIR_0[22] * SUOP_ERROR_1 */ - (NxCxaFir, bit(22)) ? defaultMaskedError; + (NxCxaFir_0, bit(22)) ? defaultMaskedError; - /** NXCXAFIR[23] + /** NXCXAFIR_0[23] * SUOP_ERROR_2 */ - (NxCxaFir, bit(23)) ? defaultMaskedError; + (NxCxaFir_0, bit(23)) ? defaultMaskedError; - /** NXCXAFIR[24] + /** NXCXAFIR_0[24] * SUOP_ERROR_3 */ - (NxCxaFir, bit(24)) ? defaultMaskedError; + (NxCxaFir_0, bit(24)) ? defaultMaskedError; - /** NXCXAFIR[25] + /** NXCXAFIR_0[25] * POWERBUS_MISC_ERROR */ - (NxCxaFir, bit(25)) ? SelfHighThr1; + (NxCxaFir_0, bit(25)) ? SelfHighThr1; - /** NXCXAFIR[26] + /** NXCXAFIR_0[26] * POWERBUS_INTERFACE_PE */ - (NxCxaFir, bit(26)) ? SelfHighThr1; + (NxCxaFir_0, bit(26)) ? SelfHighThr1; - /** NXCXAFIR[27] + /** NXCXAFIR_0[27] *POWERBUS_DATA_HANG_ERROR */ - (NxCxaFir, bit(27)) ? defaultMaskedError; + (NxCxaFir_0, bit(27)) ? defaultMaskedError; - /** NXCXAFIR[28] + /** NXCXAFIR_0[28] * POWERBUS_HANG_ERROR */ - (NxCxaFir, bit(28)) ? defaultMaskedError; + (NxCxaFir_0, bit(28)) ? defaultMaskedError; - /** NXCXAFIR[29] + /** NXCXAFIR_0[29] * LD_CLASS_CMD_ADDR_ERR */ - (NxCxaFir, bit(29)) ? callout2ndLvlMedThr1; + (NxCxaFir_0, bit(29)) ? callout2ndLvlMedThr1; - /** NXCXAFIR[30] + /** NXCXAFIR_0[30] * ST_CLASS_CMD_ADDR_ERR */ - (NxCxaFir, bit(30)) ? callout2ndLvlMedThr1; + (NxCxaFir_0, bit(30)) ? callout2ndLvlMedThr1; - /** NXCXAFIR[31] + /** NXCXAFIR_0[31] * PHB_LINK_DOWN */ - (NxCxaFir, bit(31)) ? defaultMaskedError; + (NxCxaFir_0, bit(31)) ? defaultMaskedError; - /** NXCXAFIR[32] + /** NXCXAFIR_0[32] * LD_CLASS_CMD_FOREIGN_LINK_FAIL */ - (NxCxaFir, bit(32)) ? defaultMaskedError; + (NxCxaFir_0, bit(32)) ? defaultMaskedError; - /** NXCXAFIR[33] + /** NXCXAFIR_0[33] * FOREIGN_LINK_HANG_ERROR */ - (NxCxaFir, bit(33)) ? defaultMaskedError; + (NxCxaFir_0, bit(33)) ? defaultMaskedError; - /** NXCXAFIR[34] + /** NXCXAFIR_0[34] * XPT_POWERBUS_CE */ - (NxCxaFir, bit(34)) ? callout2ndLvlMedThr32; + (NxCxaFir_0, bit(34)) ? callout2ndLvlMedThr32; - /** NXCXAFIR[35] + /** NXCXAFIR_0[35] * XPT_POWERBUS_UE */ - (NxCxaFir, bit(35)) ? defaultMaskedError; + (NxCxaFir_0, bit(35)) ? defaultMaskedError; - /** NXCXAFIR[36] + /** NXCXAFIR_0[36] * XPT_POWERBUS_SUE */ - (NxCxaFir, bit(36)) ? defaultMaskedError; + (NxCxaFir_0, bit(36)) ? defaultMaskedError; - /** NXCXAFIR[37] + /** NXCXAFIR_0[37] * TLBI_TIMEOUT */ - (NxCxaFir, bit(37)) ? defaultMaskedError; + (NxCxaFir_0, bit(37)) ? defaultMaskedError; - /** NXCXAFIR[38] + /** NXCXAFIR_0[38] * TLBI_SEQ_ERR */ - (NxCxaFir, bit(38)) ? SelfHighThr1; + (NxCxaFir_0, bit(38)) ? SelfHighThr1; - /** NXCXAFIR[39] + /** NXCXAFIR_0[39] * TLBI_BAD_OP_ERR */ - (NxCxaFir, bit(39)) ? SelfHighThr1; + (NxCxaFir_0, bit(39)) ? SelfHighThr1; - /** NXCXAFIR[40] + /** NXCXAFIR_0[40] * TLBI_SEQ_NUM_PARITY_ERR */ - (NxCxaFir, bit(40)) ? SelfHighThr1; + (NxCxaFir_0, bit(40)) ? SelfHighThr1; - /** NXCXAFIR[41] + /** NXCXAFIR_0[41] * ST_CLASS_CMD_FOREIGN_LINK_FAIL */ - (NxCxaFir, bit(41)) ? defaultMaskedError; + (NxCxaFir_0, bit(41)) ? defaultMaskedError; - /** NXCXAFIR[42] + /** NXCXAFIR_0[42] * TIMEBASE_ERR */ - (NxCxaFir, bit(42)) ? defaultMaskedError; + (NxCxaFir_0, bit(42)) ? defaultMaskedError; - /** NXCXAFIR[43] + /** NXCXAFIR_0[43] * XPT_INFORMATIONAL_ERR */ - (NxCxaFir, bit(43)) ? defaultMaskedError; + (NxCxaFir_0, bit(43)) ? defaultMaskedError; - /** NXCXAFIR[44|45|46] + /** NXCXAFIR_0[44|45|46] * SPARE_BIT */ - (NxCxaFir, bit(44|45|46)) ? defaultMaskedError; + (NxCxaFir_0, bit(44|45|46)) ? defaultMaskedError; - /** NXCXAFIR[47|48] + /** NXCXAFIR_0[47|48] * SCOM_ERR */ - (NxCxaFir, bit(47|48)) ? defaultMaskedError; + (NxCxaFir_0, bit(47|48)) ? defaultMaskedError; }; +rule NxCxaFir_1 +{ + CHECK_STOP: + NXCXAFIR_1 & ~NXCXAFIR_1_MASK & ~NXCXAFIR_1_ACT0 & ~NXCXAFIR_1_ACT1; + RECOVERABLE: + NXCXAFIR_1 & ~NXCXAFIR_1_MASK & ~NXCXAFIR_1_ACT0 & NXCXAFIR_1_ACT1; +}; + +group gNxCxaFir_1 filter singlebit +{ + /** NXCXAFIR_1[0] + * BAR_PE + */ + (NxCxaFir_1, bit(0)) ? defaultMaskedError; + + /** NXCXAFIR_1[1] + * REGISTER_PE + */ + (NxCxaFir_1, bit(1)) ? SelfMedThr1; + + /** NXCXAFIR_1[2] + * MASTER_ARRAY_CE + */ + (NxCxaFir_1, bit(2)) ? SelfMedThr32PerDay; + + /** NXCXAFIR_1[3] + * MASTER_ARRAY_UE + */ + (NxCxaFir_1, bit(3)) ? SelfMedThr1; + + /** NXCXAFIR_1[4] + * TIMER_EXPIRED_RECOV_ERROR + */ + (NxCxaFir_1, bit(4)) ? defaultMaskedError; + + /** NXCXAFIR_1[5] + * TIMER_EXPIRED_XSTOP_ERROR + */ + (NxCxaFir_1, bit(5)) ? SelfMedThr1; + + /** NXCXAFIR_1[6] + * PSL_CMD_UE + */ + (NxCxaFir_1, bit(6)) ? defaultMaskedError; + + /** NXCXAFIR_1[7] + * PSL_CMD_SUE + */ + (NxCxaFir_1, bit(7)) ? defaultMaskedError; + + /** NXCXAFIR_1[8] + * SNOOP_ARRAY_CE + */ + (NxCxaFir_1, bit(8)) ? callout2ndLvlMedThr32; + + /** NXCXAFIR_1[9] + * SNOOP_ARRAY_UE + */ + (NxCxaFir_1, bit(9)) ? SelfMedThr1; + + /** NXCXAFIR_1[10] + * RECOVERY_FAILED + */ + (NxCxaFir_1, bit(10)) ? SelfMedThr1; + + /** NXCXAFIR_1[11] + * ILLEGAL_LPC_BAR_ACCESS + */ + (NxCxaFir_1, bit(11)) ? defaultMaskedError; + + /** NXCXAFIR_1[12] + * XPT_RECOVERABLE_ERROR_MASK + */ + (NxCxaFir_1, bit(12)) ? defaultMaskedError; + + /** NXCXAFIR_1[13] + * MASTER_RECOVERABLE_ERROR + */ + (NxCxaFir_1, bit(13)) ? defaultMaskedError; + + /** NXCXAFIR_1[14] + * SNOOPER_RECOVERABLE_ERROR + */ + (NxCxaFir_1, bit(14)) ? defaultMaskedError; + + /** NXCXAFIR_1[15] + * XPT_RECOVERABLE_ERROR + */ + (NxCxaFir_1, bit(15)) ? defaultMaskedError; + + /** NXCXAFIR_1[16] + * MASTER_SYS_XSTOP_ERROR + */ + (NxCxaFir_1, bit(16)) ? SelfMedThr1; + + /** NXCXAFIR_1[17] + * SNOOPER_SYS_XSTOP_ERROR + */ + (NxCxaFir_1, bit(17)) ? SelfMedThr1; + + /** NXCXAFIR_1[18] + * XPT_SYS_XSTOP_ERROR + */ + (NxCxaFir_1, bit(18)) ? SelfMedThr1; + + /** NXCXAFIR_1[19] + * MUOP_ERROR_1 + */ + (NxCxaFir_1, bit(19)) ? defaultMaskedError; + + /** NXCXAFIR_1[20] + * MUOP_ERROR_2 + */ + (NxCxaFir_1, bit(20)) ? defaultMaskedError; + + /** NXCXAFIR_1[21] + * MUOP_ERROR_3 + */ + (NxCxaFir_1, bit(21)) ? defaultMaskedError; + + /** NXCXAFIR_1[22] + * SUOP_ERROR_1 + */ + (NxCxaFir_1, bit(22)) ? defaultMaskedError; + + /** NXCXAFIR_1[23] + * SUOP_ERROR_2 + */ + (NxCxaFir_1, bit(23)) ? defaultMaskedError; + + /** NXCXAFIR_1[24] + * SUOP_ERROR_3 + */ + (NxCxaFir_1, bit(24)) ? defaultMaskedError; + + /** NXCXAFIR_1[25] + * POWERBUS_MISC_ERROR + */ + (NxCxaFir_1, bit(25)) ? SelfHighThr1; + + /** NXCXAFIR_1[26] + * POWERBUS_INTERFACE_PE + */ + (NxCxaFir_1, bit(26)) ? SelfHighThr1; + + /** NXCXAFIR_1[27] + *POWERBUS_DATA_HANG_ERROR + */ + (NxCxaFir_1, bit(27)) ? defaultMaskedError; + + /** NXCXAFIR_1[28] + * POWERBUS_HANG_ERROR + */ + (NxCxaFir_1, bit(28)) ? defaultMaskedError; + + /** NXCXAFIR_1[29] + * LD_CLASS_CMD_ADDR_ERR + */ + (NxCxaFir_1, bit(29)) ? callout2ndLvlMedThr1; + + /** NXCXAFIR_1[30] + * ST_CLASS_CMD_ADDR_ERR + */ + (NxCxaFir_1, bit(30)) ? callout2ndLvlMedThr1; + + /** NXCXAFIR_1[31] + * PHB_LINK_DOWN + */ + (NxCxaFir_1, bit(31)) ? defaultMaskedError; + + /** NXCXAFIR_1[32] + * LD_CLASS_CMD_FOREIGN_LINK_FAIL + */ + (NxCxaFir_1, bit(32)) ? defaultMaskedError; + + /** NXCXAFIR_1[33] + * FOREIGN_LINK_HANG_ERROR + */ + (NxCxaFir_1, bit(33)) ? defaultMaskedError; + + /** NXCXAFIR_1[34] + * XPT_POWERBUS_CE + */ + (NxCxaFir_1, bit(34)) ? callout2ndLvlMedThr32; + + /** NXCXAFIR_1[35] + * XPT_POWERBUS_UE + */ + (NxCxaFir_1, bit(35)) ? defaultMaskedError; + + /** NXCXAFIR_1[36] + * XPT_POWERBUS_SUE + */ + (NxCxaFir_1, bit(36)) ? defaultMaskedError; + + /** NXCXAFIR_1[37] + * TLBI_TIMEOUT + */ + (NxCxaFir_1, bit(37)) ? defaultMaskedError; + + /** NXCXAFIR_1[38] + * TLBI_SEQ_ERR + */ + (NxCxaFir_1, bit(38)) ? SelfHighThr1; + + /** NXCXAFIR_1[39] + * TLBI_BAD_OP_ERR + */ + (NxCxaFir_1, bit(39)) ? SelfHighThr1; + + /** NXCXAFIR_1[40] + * TLBI_SEQ_NUM_PARITY_ERR + */ + (NxCxaFir_1, bit(40)) ? SelfHighThr1; + + /** NXCXAFIR_1[41] + * ST_CLASS_CMD_FOREIGN_LINK_FAIL + */ + (NxCxaFir_1, bit(41)) ? defaultMaskedError; + + /** NXCXAFIR_1[42] + * TIMEBASE_ERR + */ + (NxCxaFir_1, bit(42)) ? defaultMaskedError; + + /** NXCXAFIR_1[43] + * XPT_INFORMATIONAL_ERR + */ + (NxCxaFir_1, bit(43)) ? defaultMaskedError; + + /** NXCXAFIR_1[44|45|46] + * SPARE_BIT + */ + (NxCxaFir_1, bit(44|45|46)) ? defaultMaskedError; + + /** NXCXAFIR_1[47|48] + * SCOM_ERR + */ + (NxCxaFir_1, bit(47|48)) ? defaultMaskedError; +}; ################################################################################ # PB Chiplet MCDFIR ################################################################################ @@ -2590,6 +2845,175 @@ group gPciNestFir filter singlebit }; +rule PciNestFir_3 +{ + CHECK_STOP: + PCINESTFIR_3 & ~PCINESTFIR_3_MASK & ~PCINESTFIR_3_ACT0 & ~PCINESTFIR_3_ACT1; + RECOVERABLE: + PCINESTFIR_3 & ~PCINESTFIR_3_MASK & ~PCINESTFIR_3_ACT0 & PCINESTFIR_3_ACT1; +}; + +group gPciNestFir3 filter singlebit +{ + /** PCINESTFIR_3[0] + * BAR_PE + */ + (PciNestFir_3, bit(0)) ? calloutConnPci3Th1NoGard; + + /** PCINESTFIR_3[1] + * NONBAR_PE + */ + (PciNestFir_3, bit(1)) ? defaultMaskedError; + + /** PCINESTFIR_3[2] + * PB_TO_PEC_CE + */ + (PciNestFir_3, bit(2)) ? calloutConnPci3Th32NoGard; + + /** PCINESTFIR_3[3] + * PB_TO_PEC_UE + */ + (PciNestFir_3, bit(3)) ? defaultMaskedError; + + /** PCINESTFIR_3[4] + * PB_TO_PEC_SUE + */ + (PciNestFir_3, bit(4)) ? defaultMaskedError; + + /** PCINESTFIR_3[5] + * ARY_ECC_CE + */ + (PciNestFir_3, bit(5)) ? calloutConnPci3Th32NoGard; + + /** PCINESTFIR_3[6] + * ARY_ECC_UE + */ + (PciNestFir_3, bit(6)) ? defaultMaskedError; + + /** PCINESTFIR_3[7] + * ARY_ECC_SUE + */ + (PciNestFir_3, bit(7)) ? defaultMaskedError; + + /** PCINESTFIR_3[8] + * REGISTER_ARRAY_PE + */ + (PciNestFir_3, bit(8)) ? calloutConnPci3Th1NoGard; + + /** PCINESTFIR_3[9] + * PB_INTERFACE_PE + */ + (PciNestFir_3, bit(9)) ? calloutConnPci3Th1NoGard; + + /** PCINESTFIR_3[10] + * PB_DATA_HANG_ERRORS + */ + (PciNestFir_3, bit(10)) ? defaultMaskedError; + + /** PCINESTFIR_3[11] + * PB_HANG_ERRORS + */ + (PciNestFir_3, bit(11)) ? defaultMaskedError; + + /** PCINESTFIR_3[12] + * RD_ARE_ERRORS + */ + (PciNestFir_3, bit(12)) ? defaultMaskedError; + + /** PCINESTFIR_3[13] + * NONRD_ARE_ERRORS + */ + (PciNestFir_3, bit(13)) ? defaultMaskedError; + + /** PCINESTFIR_3[14] + * PCI_HANG_ERROR + */ + (PciNestFir_3, bit(14)) ? defaultMaskedError; + + /** PCINESTFIR_3[15] + * PCI_CLOCK_ERROR + * + * These should never trigger directly themselves. + * Should be handled by global PRD PLL code. + */ + (PciNestFir_3, bit(15)) ? threshold32pday; + + /** PCINESTFIR_3[16] + * AIB_FENCE + */ + (PciNestFir_3, bit(16)) ? defaultMaskedError; + + /** PCINESTFIR_3[17] + * HW_ERRORS + */ + (PciNestFir_3, bit(17)) ? calloutConnPci3Th1NoGard; + + /** PCINESTFIR_3[18] + * UNSOLICITIEDPBDATA + */ + (PciNestFir_3, bit(18)) ? callout2ndLvlMedThr1; + + /** PCINESTFIR_3[19] + * UNEXPECTEDCRESP + */ + (PciNestFir_3, bit(19)) ? callout2ndLvlMedThr1; + + /** PCINESTFIR_0[20] + * INVALIDCRESP + */ + (PciNestFir_3, bit(20)) ? calloutProcLevel2MedThr1; + + /** PCINESTFIR_0[21] + * PBUNSUPPORTEDSIZE + */ + (PciNestFir_3, bit(21)) ? calloutProcLevel2MedThr1; + + /** PCINESTFIR_0[22] + * PBUNSUPPORTEDCMD + */ + (PciNestFir_3, bit(22)) ? calloutProcLevel2MedThr1; + + /** PCINESTFIR_0[23] + * AIB_PE + */ + (PciNestFir_3, bit(23)) ? defaultMaskedError; + + /** PCINESTFIR_3[24] + * ASB_ERROR + */ + (PciNestFir_3, bit(24)) ? defaultMaskedError; + + /** PCINESTFIR_3[25] + * FOREIGN_LINK_FAIL + */ + (PciNestFir_3, bit(25)) ? defaultMaskedError; + + /** PCINESTFIR_3[26] + * FOREIGN_PB_HANG + */ + (PciNestFir_3, bit(26)) ? defaultMaskedError; + + /** PCINESTFIR_3[27] + * CAPP_ERROR + */ + (PciNestFir_3, bit(27)) ? defaultMaskedError; + + /** PCINESTFIR_3[28] + * SYNC_SCOM_ERR + */ + (PciNestFir_3, bit(28)) ? defaultMaskedError; + + /** PCINESTFIR_3[29] + * SCOM Engine ERROR 0 + */ + (PciNestFir_3, bit(29)) ? defaultMaskedError; + + /** PCINESTFIR_3[30] + * SCOM Engine ERROR 0 + */ + (PciNestFir_3, bit(30)) ? defaultMaskedError; +}; + ################################################################################ # PB Chiplet IOMCFIR_0 ################################################################################ @@ -2958,6 +3382,12 @@ actionclass calloutConnPci2NoGard callout(connected(TYPE_PCI,2), MRU_MED, NO_GARD); }; +/** Callout the connected PCI 3 controller. */ +actionclass calloutConnPci3NoGard +{ + callout(connected(TYPE_PCI,3), MRU_MED, NO_GARD); +}; + /** Callout the connected PCI 0 controller, threshold 1 , no garding */ actionclass calloutConnPci0Th1NoGard { @@ -2979,6 +3409,13 @@ actionclass calloutConnPci2Th1NoGard threshold1; }; +/** Callout the connected PCI 3 controller, threshold 1, no garding */ +actionclass calloutConnPci3Th1NoGard +{ + calloutConnPci3NoGard; + threshold1; +}; + /** Callout the connected PCI 0 controller, threshold 32 per day, no garding */ actionclass calloutConnPci0Th32NoGard { @@ -3000,6 +3437,13 @@ actionclass calloutConnPci2Th32NoGard threshold32pday; }; +/** Callout the connected PCI 3 controller, threshold 32 per day , no garding */ +actionclass calloutConnPci3Th32NoGard +{ + calloutConnPci3NoGard; + threshold32pday; +}; + /** Callout the DMI bus 0 */ actionclass calloutDmiBus0 { diff --git a/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_TP.rule b/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_TP.rule index 181344fba..a6df7f402 100755 --- a/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_TP.rule +++ b/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_TP.rule @@ -48,22 +48,22 @@ group gTpChipletFir filter singlebit (TpChipletFir, bit(4)) ? analyze(gOccFir); /** TP_CHIPLET_FIR[5] - * Attention from MCIFIR (MCS 00 Venice only) + * Attention from MCIFIR (MCS 00 not used in Murano) */ (TpChipletFir, bit(5)) ? analyzeMcs00; /** TP_CHIPLET_FIR[6] - * Attention from MCIFIR (MCS 01 Venice only) + * Attention from MCIFIR (MCS 01 not used in Murano) */ (TpChipletFir, bit(6)) ? analyzeMcs01; /** TP_CHIPLET_FIR[7] - * Attention from MCIFIR (MCS 10 Venice only) + * Attention from MCIFIR (MCS 10 not used in Murano) */ (TpChipletFir, bit(7)) ? analyzeMcs10; /** TP_CHIPLET_FIR[8] - * Attention from MCIFIR (MCS 11 Venice only) + * Attention from MCIFIR (MCS 11 not used in Murano) */ (TpChipletFir, bit(8)) ? analyzeMcs11; @@ -88,7 +88,7 @@ group gTpChipletFir filter singlebit (TpChipletFir, bit(12)) ? analyzeMcs31; /** TP_CHIPLET_FIR[13] - * Attention from IOMCFIR_0 (Venice only) + * Attention from IOMCFIR_0 (not used in Murano) */ (TpChipletFir, bit(13)) ? analyze(gIomcFir_0); @@ -126,22 +126,22 @@ group gTpChipletSpa filter singlebit (TpChipletSpa, bit(0)) ? analyze(gOccFir); /** TP_CHIPLET_SPA[1] - * Attention from MCIFIR_00 (Venice only) + * Attention from MCIFIR_00 (not used in Murano) */ (TpChipletSpa, bit(1)) ? analyzeMcs00; /** TP_CHIPLET_SPA[2] - * Attention from MCIFIR_01 (Venice only) + * Attention from MCIFIR_01 (not used in Murano) */ (TpChipletSpa, bit(2)) ? analyzeMcs01; /** TP_CHIPLET_SPA[3] - * Attention from MCIFIR_10 (Venice only) + * Attention from MCIFIR_10 (not used in Murano) */ (TpChipletSpa, bit(3)) ? analyzeMcs10; /** TP_CHIPLET_SPA[4] - * Attention from MCIFIR_11 (Venice only) + * Attention from MCIFIR_11 (not used in Murano) */ (TpChipletSpa, bit(4)) ? analyzeMcs11; diff --git a/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_common.rule b/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_common.rule new file mode 100755 index 000000000..c9add00df --- /dev/null +++ b/src/usr/diag/prdf/common/plat/pegasus/Proc_acts_common.rule @@ -0,0 +1,208 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/common/plat/pegasus/Proc_acts_common.rule $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2015 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + ############################################################################## + # # + # #### # # + # # # # # # ##### ### # # # ## ##### ### ### # # ### # + # # # # # # # # # # # # # # # # # ## # # # + # #### # # # #### ### # ####### # # # # # # # # ### # + # # # # # # # # # # # # # # # # # # ## # # + # # # ### #### ##### ### # # # ## # ### ### # # ### # + # # + ############################################################################## + +################################################################################ +# Global Broadcast Registers +################################################################################ + +#CS and RE in MuranoVenice and Naples specific rule files + +rule GlobalSpa +{ + SPECIAL: GLOBAL_SPA; +}; + +group gGlobalSpa attntype SPECIAL filter singlebit +{ + /** GLOBAL_SPA[1] + * Attention from TP chiplet + */ + (GlobalSpa, bit(1)) ? analyze(gTpChipletSpa); + + /** GLOBAL_SPA[2] + * Attention from PB chiplet + */ + (GlobalSpa, bit(2)) ? analyze(gPbChipletSpa); + + /** GLOBAL_SPA[9] + * Attention from PCIE + */ + (GlobalSpa, bit(9)) ? analyze(gPcieChipletSpa); + + /** GLOBAL_SPA[11] + * Attention from EX1 (Venice only) + */ + (GlobalSpa, bit(11)) ? analyzeEx1; + + /** GLOBAL_SPA[12] + * Attention from EX2 (Venice only) + */ + (GlobalSpa, bit(12)) ? analyzeEx2; + + /** GLOBAL_SPA[13] + * Attention from EX3 (Venice only) + */ + (GlobalSpa, bit(13)) ? analyzeEx3; + + /** GLOBAL_SPA[14] + * Attention from EX4 + */ + (GlobalSpa, bit(14)) ? analyzeEx4; + + /** GLOBAL_SPA[15] + * Attention from EX5 + */ + (GlobalSpa, bit(15)) ? analyzeEx5; + + /** GLOBAL_SPA[16] + * Attention from EX6 + */ + (GlobalSpa, bit(16)) ? analyzeEx6; + + /** GLOBAL_SPA[19] + * Attention from EX9 (Venice only) + */ + (GlobalSpa, bit(19)) ? analyzeEx9; + + /** GLOBAL_SPA[20] + * Attention from EX10 (Venice only) + */ + (GlobalSpa, bit(20)) ? analyzeEx10; + + /** GLOBAL_SPA[21] + * Attention from EX11 (Venice only) + */ + (GlobalSpa, bit(21)) ? analyzeEx11; + + /** GLOBAL_SPA[22] + * Attention from EX12 + */ + (GlobalSpa, bit(22)) ? analyzeEx12; + + /** GLOBAL_SPA[23] + * Attention from EX13 + */ + (GlobalSpa, bit(23)) ? analyzeEx13; + + /** GLOBAL_SPA[24] + * Attention from EX14 + */ + (GlobalSpa, bit(24)) ? analyzeEx14; +}; + + ############################################################################## + # # + # # ### # + # # # ## ##### ### ### # # # # # # ### ### ### ### # + # # # # # # # # # ## # # # # # # # # # # + # ####### # # # # # # # # # # ##### ### ### ## ### # + # # # # # # # # # # ## # # # # # # # # # # + # # # ## # ### ### # # ### ### # # ### ### ### ### # + # # + ############################################################################## + + +################################################################################ +# Analyze Connected Parts # +################################################################################ + +/** Analyze connected EX1 */ +actionclass analyzeEx1 { analyze(connected(TYPE_EX, 1)); }; + +/** Analyze connected EX2 */ +actionclass analyzeEx2 { analyze(connected(TYPE_EX, 2)); }; + +/** Analyze connected EX3 */ +actionclass analyzeEx3 { analyze(connected(TYPE_EX, 3)); }; + +/** Analyze connected EX4 */ +actionclass analyzeEx4 { analyze(connected(TYPE_EX, 4)); }; + +/** Analyze connected EX5 */ +actionclass analyzeEx5 { analyze(connected(TYPE_EX, 5)); }; + +/** Analyze connected EX6 */ +actionclass analyzeEx6 { analyze(connected(TYPE_EX, 6)); }; + +/** Analyze connected EX9 */ +actionclass analyzeEx9 { analyze(connected(TYPE_EX, 9)); }; + +/** Analyze connected EX10 */ +actionclass analyzeEx10 { analyze(connected(TYPE_EX, 10)); }; + +/** Analyze connected EX11 */ +actionclass analyzeEx11 { analyze(connected(TYPE_EX, 11)); }; + +/** Analyze connected EX12 */ +actionclass analyzeEx12 { analyze(connected(TYPE_EX, 12)); }; + +/** Analyze connected EX13 */ +actionclass analyzeEx13 { analyze(connected(TYPE_EX, 13)); }; + +/** Analyze connected EX14 */ +actionclass analyzeEx14 { analyze(connected(TYPE_EX, 14)); }; + +actionclass calloutProcLevel2MedThr1 +{ + calloutSelfLow; + callout2ndLvlMed; + threshold1; +}; + +/** callout Proc with low priority ,Sec level Med priority, Thr1 + * and dump type SH, garding not done */ +actionclass calloutProcLevel2MedThr1dumpShNoGard +{ + calloutSelfLowNoGard; + callout2ndLvlMedThr1; + dumpSH; +}; + +/** callout Proc with low priority ,Sec level Med priority, Thr 32per day + * and dump type SH , garding not done */ +actionclass calloutProcLevel2MedThr32dumpShNoGard +{ + calloutSelfLow; + callout2ndLvlMed; + threshold32pday; + dumpSH; +}; + +actionclass calloutProcHighThr1SUE +{ + calloutSelfHigh; + SUEGenerationPoint; + threshold1; +}; diff --git a/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_ABUS.rule b/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_ABUS.rule index 457087494..dd604358c 100755 --- a/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_ABUS.rule +++ b/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_ABUS.rule @@ -5,7 +5,9 @@ # # OpenPOWER HostBoot Project # -# COPYRIGHT International Business Machines Corp. 2012,2014 +# Contributors Listed Below - COPYRIGHT 2012,2015 +# [+] International Business Machines Corp. +# # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. @@ -21,6 +23,14 @@ # # IBM_PROLOG_END_TAG +################################################################################ +# +# Chiplet Register Adddresses Description +# ======= ======================= ============================================ +# ABUS 0x08000000 - 0x0800FFFF ABUS pervasive logic (Murano/Venice only) +# +################################################################################ + ############################################################################ # ABUS Chiplet Registers ############################################################################ diff --git a/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_NV.rule b/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_NV.rule new file mode 100755 index 000000000..9bfcab86e --- /dev/null +++ b/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_NV.rule @@ -0,0 +1,210 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/common/plat/pegasus/Proc_regs_NV.rule $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2015 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +################################################################################ +# +# Chiplet Register Adddresses Description +# ======= ======================= ============================================ +# NV 0x08000000 - 0x0800FFFF NV pervasive logic (Naples only) +# +################################################################################ + + ############################################################################ + # NV Chiplet Registers + ############################################################################ + + register NV_CHIPLET_CS_FIR + { + name "NV_WRAP_TOP.TPC.XFIR"; + scomaddr 0x08040000; + capture group default; + }; + + register NV_CHIPLET_RE_FIR + { + name "NV_WRAP_TOP.TPC.RFIR"; + scomaddr 0x08040001; + capture group default; + }; + + register NV_CHIPLET_FIR_MASK + { + name "NV_WRAP_TOP.TPC.FIR_MASK"; + scomaddr 0x08040002; + capture group default; + }; + + ############################################################################ + # NV Chiplet LFIR + ############################################################################ + + register NV_LFIR + { + name "NV_WRAP_TOP.TPC.LOCAL_FIR"; + scomaddr 0x0804000a; + reset (&, 0x0804000b); + mask (|, 0x0804000f); + capture group default; + }; + + register NV_LFIR_MASK + { + name "NV_WRAP_TOP.TPC.EPS.FIR.LOCAL_FIR_MASK"; + scomaddr 0x0804000d; + capture group default; + }; + + register NV_LFIR_ACT0 + { + name "NV_WRAP_TOP.TPC.EPS.FIR.LOCAL_FIR_ACTION0"; + scomaddr 0x08040010; + capture type secondary; + capture group default; + capture req nonzero("NV_LFIR"); + }; + + register NV_LFIR_ACT1 + { + name "NV_WRAP_TOP.TPC.EPS.FIR.LOCAL_FIR_ACTION1"; + scomaddr 0x08040011; + capture type secondary; + capture group default; + capture req nonzero("NV_LFIR"); + }; + + ############################################################################ + # NV Chiplet IONVFIR_0 + ############################################################################ + + register IONVFIR_0 + { + name "NVBUS0.BUSCTL.SCOM.FIR_REG"; + scomaddr 0x08010c00; + reset (&, 0x08010c01); + mask (|, 0x08010c05); + capture group default; + }; + + register IONVFIR_0_MASK + { + name "NVBUS0.BUSCTL.SCOM.FIR_MASK_REG"; + scomaddr 0x08010c03; + capture group default; + }; + + register IONVFIR_0_ACT0 + { + name "NVBUS0.BUSCTL.SCOM.FIR_ACTION0_REG"; + scomaddr 0x08010c06; + capture type secondary; + capture group default; + capture req nonzero("IONVFIR_0"); + }; + + register IONVFIR_0_ACT1 + { + name "NVBUS0.BUSCTL.SCOM.FIR_ACTION1_REG"; + scomaddr 0x08010c07; + capture type secondary; + capture group default; + capture req nonzero("IONVFIR_0"); + }; + + ############################################################################ + # NV Chiplet IONVFIR_1 + ############################################################################ + + register IONVFIR_1 + { + name "NVBUS1.BUSCTL.SCOM.FIR_REG"; + scomaddr 0x08010c40; + reset (&, 0x08010c41); + mask (|, 0x08010c45); + capture group default; + }; + + register IONVFIR_1_MASK + { + name "NVBUS1.BUSCTL.SCOM.FIR_MASK_REG"; + scomaddr 0x08010c43; + capture group default; + }; + + register IONVFIR_1_ACT0 + { + name "NVBUS1.BUSCTL.SCOM.FIR_ACTION0_REG"; + scomaddr 0x08010c46; + capture type secondary; + capture group default; + capture req nonzero("IONVFIR_1"); + }; + + register IONVFIR_1_ACT1 + { + name "NVBUS1.BUSCTL.SCOM.FIR_ACTION1_REG"; + scomaddr 0x08010c47; + capture type secondary; + capture group default; + capture req nonzero("IONVFIR_1"); + }; + + ############################################################################ + # NV Chiplet NPUFIR + ############################################################################ + + register NPUFIR + { + name "ES.NPU.NP_AT.REG.FIR_REG"; + scomaddr 0x08013d80; + reset (&, 0x08013d81); + mask (|, 0x08013d85); + capture group default; + }; + + register NPUFIR_MASK + { + name "ES.NPU.NP_AT.REG.FIR_MASK_REG"; + scomaddr 0x08013d83; + capture group default; + }; + + register NPUFIR_ACT0 + { + name "ES.NPU.NP_AT.REG.FIR_ACTION0_REG"; + scomaddr 0x08013d86; + capture type secondary; + capture group default; + capture req nonzero("NPUFIR"); + }; + + register NPUFIR_ACT1 + { + name "ES.NPU.NP_AT.REG.FIR_ACTION1_REG"; + scomaddr 0x08013d87; + capture type secondary; + capture group default; + capture req nonzero("NPUFIR"); + }; + diff --git a/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_PB.rule b/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_PB.rule index 1016fd345..ec465dfb2 100755 --- a/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_PB.rule +++ b/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_PB.rule @@ -23,6 +23,17 @@ # # IBM_PROLOG_END_TAG +################################################################################ +# +# Chiplet Register Adddresses Description +# ======= ======================= ============================================ +# PB 0x02000000 - 0x02FFFFFF PB pervasive logic, note that this does +# include the SCOM addresses characterized by +# the MCS target. See Mcs.rule for those +# address ranges. +# +################################################################################ + ############################################################################ # PB Chiplet Registers ############################################################################ @@ -236,10 +247,6 @@ capture group default; }; - ############################################################################ - # NXASFIR Error Report Registers - ############################################################################ - register NXASFIR_IN_ERROR_HOLD_REPORT { name "EN.NX.AS.AS_IN_ERROR_HOLD"; @@ -274,76 +281,157 @@ }; ############################################################################ - # PB Chiplet NXCXAFIR + # PB Chiplet NXCXAFIR_0 ############################################################################ - register NXCXAFIR + register NXCXAFIR_0 { - name "EN.NX.CXA.CXA_XPT.XPT_SCOMFIR.FIR_REG"; + name "EN.NX.CXA0.CXA_XPT.XPT_SCOMFIR.FIR_REG"; scomaddr 0x02013000; reset (&, 0x02013001); mask (|, 0x02013005); capture group default; }; - register NXCXAFIR_MASK + register NXCXAFIR_0_MASK { - name "EN.NX.CXA.CXA_XPT.XPT_SCOMFIR.FIR_MASK_REG"; + name "EN.NX.CXA0.CXA_XPT.XPT_SCOMFIR.FIR_MASK_REG"; scomaddr 0x02013003; capture group default; }; - register NXCXAFIR_ACT0 + register NXCXAFIR_0_ACT0 { - name "EN.NX.CXA.CXA_XPT.XPT_SCOMFIR.FIR_ACTION0_REG"; + name "EN.NX.CXA0.CXA_XPT.XPT_SCOMFIR.FIR_ACTION0_REG"; scomaddr 0x02013006; capture type secondary; capture group default; - capture req nonzero("NXCXAFIR"); + capture req nonzero("NXCXAFIR_0"); }; - register NXCXAFIR_ACT1 + register NXCXAFIR_0_ACT1 { - name "EN.NX.CXA.CXA_XPT.XPT_SCOMFIR.FIR_ACTION1_REG"; + name "EN.NX.CXA0.CXA_XPT.XPT_SCOMFIR.FIR_ACTION1_REG"; scomaddr 0x02013007; capture type secondary; capture group default; - capture req nonzero("NXCXAFIR"); + capture req nonzero("NXCXAFIR_0"); }; - register NXCXAFIR_SNP_ERROR_REPORT + register NXCXAFIR_0_SNP_ERROR_REPORT { - name "EN.NX.CXA.CXA_SNPFE.SNP_REGS.CXA_SNP_ERROR_REPORT_REG"; + name "EN.NX.CXA0.CXA_SNPFE.SNP_REGS.CXA_SNP_ERROR_REPORT_REG"; scomaddr 0x0201300A; capture group default; capture group CerrRegs; }; - register NXCXAFIR_APC1_ERROR_REPORT + register NXCXAFIR_0_APC1_ERROR_REPORT { - name "EN.NX.CXA.CXA_APC1.ERRRPT"; + name "EN.NX.CXA0.CXA_APC1.ERRRPT"; scomaddr 0x0201300B; capture group default; capture group CerrRegs; }; - register NXCXAFIR_XPT_ERROR_REPORT + register NXCXAFIR_0_XPT_ERROR_REPORT { - name "EN.NX.CXA.XPT_ERROR_REPORT"; + name "EN.NX.CXA0.XPT_ERROR_REPORT"; scomaddr 0x0201300C; capture group default; capture group CerrRegs; }; - register NXCXAFIR_TLBI_ERROR_REPORT + register NXCXAFIR_0_TLBI_ERROR_REPORT { - name "EN.NX.CXA.CXA_XPT.XPT_SCOMFIR.TLBI_ERROR_REPORT"; + name "EN.NX.CXA0.CXA_XPT.XPT_SCOMFIR.TLBI_ERROR_REPORT"; scomaddr 0x0201300D; capture group default; capture group CerrRegs; }; ############################################################################ + # PB Chiplet NXCXAFIR_1 + ############################################################################ + + # This FIR only exists on Naples. So we will have a conditional capture + # below, which is common on all P8/P8+ chips. + + register NXCXAFIR_1 + { + name "EN.NX.CXA1.CXA_XPT.XPT_SCOMFIR.FIR_REG"; + scomaddr 0x02013180; + reset (&, 0x02013181); + mask (|, 0x02013185); + capture req funccall("isNaplesProc"); + capture group default; + }; + + register NXCXAFIR_1_MASK + { + name "EN.NX.CXA1.CXA_XPT.XPT_SCOMFIR.FIR_MASK_REG"; + scomaddr 0x02013183; + capture req funccall("isNaplesProc"); + capture group default; + }; + + register NXCXAFIR_1_ACT0 + { + name "EN.NX.CXA1.CXA_XPT.XPT_SCOMFIR.FIR_ACTION0_REG"; + scomaddr 0x02013186; + capture type secondary; + capture req funccall("isNaplesProc"); + capture group default; + capture req nonzero("NXCXAFIR_1"); + }; + + register NXCXAFIR_1_ACT1 + { + name "EN.NX.CXA1.CXA_XPT.XPT_SCOMFIR.FIR_ACTION1_REG"; + scomaddr 0x02013187; + capture type secondary; + capture req funccall("isNaplesProc"); + capture group default; + capture req nonzero("NXCXAFIR_1"); + }; + + register NXCXAFIR_1_SNP_ERROR_REPORT + { + name "EN.NX.CXA1.CXA_SNPFE.SNP_REGS.CXA_SNP_ERROR_REPORT_REG"; + scomaddr 0x0201318A; + capture req funccall("isNaplesProc"); + capture group default; + capture group CerrRegs; + }; + + register NXCXAFIR_1_APC1_ERROR_REPORT + { + name "EN.NX.CXA1.CXA_APC1.ERRRPT"; + scomaddr 0x0201318B; + capture req funccall("isNaplesProc"); + capture group default; + capture group CerrRegs; + }; + + register NXCXAFIR_1_XPT_ERROR_REPORT + { + name "EN.NX.CXA1.XPT_ERROR_REPORT"; + scomaddr 0x0201318C; + capture req funccall("isNaplesProc"); + capture group default; + capture group CerrRegs; + }; + + register NXCXAFIR_1_TLBI_ERROR_REPORT + { + name "EN.NX.CXA1.CXA_XPT.XPT_SCOMFIR.TLBI_ERROR_REPORT"; + scomaddr 0x0201318D; + capture req funccall("isNaplesProc"); + capture group default; + capture group CerrRegs; + }; + + ############################################################################ # PB Chiplet MCDFIR ############################################################################ @@ -938,9 +1026,86 @@ }; ############################################################################ + # PB Chiplet PCINESTFIR_3 + ############################################################################ + + # This FIR only exists on Naples. So we will have a conditional capture + # below, which is common on all P8/P8+ chips. + + register PCINESTFIR_3 + { + name "ES.PE_WRAP_TOP.PE3.PEPBCQ.PBCQ.FIR_REG"; + scomaddr 0x02012c00; + reset (&, 0x02012c01); + mask (|, 0x02012c05); + capture req funccall("isNaplesProc"); + capture group default; + }; + + register PCINESTFIR_3_MASK + { + name "ES.PE_WRAP_TOP.PE3.PEPBCQ.PBCQ.FIR_MASK_REG"; + scomaddr 0x02012c03; + capture req funccall("isNaplesProc"); + capture group default; + }; + + register PCINESTFIR_3_ACT0 + { + name "ES.PE_WRAP_TOP.PE3.PEPBCQ.PBCQ.FIR_ACTION0_REG"; + scomaddr 0x02012c06; + capture type secondary; + capture req funccall("isNaplesProc"); + capture group default; + capture req nonzero("PCINESTFIR_3"); + }; + + register PCINESTFIR_3_ACT1 + { + name "ES.PE_WRAP_TOP.PE3.PEPBCQ.PBCQ.FIR_ACTION1_REG"; + scomaddr 0x02012c07; + capture type secondary; + capture req funccall("isNaplesProc"); + capture group default; + capture req nonzero("PCINESTFIR_3"); + }; + + register PCINESTFIR3_ERROR_REPORT_0 + { + name "ES.PE_WRAP_TOP.PE3.PEPBCQ.PBCQ.CERR_RPT0_REG"; + scomaddr 0x02012c1C; + capture req funccall("isNaplesProc"); + capture group default; + capture group CerrRegs; + }; + + register PCINESTFIR3_ERROR_REPORT_1 + { + name "ES.PE_WRAP_TOP.PE3.PEPBCQ.PBCQ.CERR_RPT1_REG"; + scomaddr 0x02012c1D; + capture req funccall("isNaplesProc"); + capture group default; + capture group CerrRegs; + }; + + register PCINESTFIR3_ERROR_REPORT_2 + { + name "ES.PE_WRAP_TOP.PE3.PEPBCQ.PBCQ.CERR_RPT2_REG"; + scomaddr 0x02012c1E; + capture req funccall("isNaplesProc"); + capture group default; + capture group CerrRegs; + }; + + ############################################################################ # PB Chiplet IOMCFIR_0 ############################################################################ + # This FIR does not exist on Murano, however, it is possible that the + # entire MCS block (0-3) may be disabled on Venice and Naples based on + # hardware availability. So we will have a conditional capture below, which + # is common on all P8/P8+ chips. + register IOMCFIR_0 { name "IOMC0.BUSCTL.SCOM.FIR_REG"; @@ -991,6 +1156,11 @@ # PB Chiplet IOMCFIR_1 ############################################################################ + # This FIR exists on all P8/P8+ processors, however, it is possible that the + # entire MCS block (4-7) may be disabled based on hardware availability. So + # we will have a conditional capture below, which is common on all P8/P8+ + # chips. + register IOMCFIR_1 { name "IOMC1.BUSCTL.SCOM.FIR_REG"; @@ -1058,8 +1228,10 @@ ############################################################################ # PB non-existent registers for capture ############################################################################ + register NXTRACE_ARRAY { name "Capture Data for NX Trace Array"; capture group never; }; + diff --git a/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_PCIE.rule b/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_PCIE.rule index dbda9a3ff..00541e63d 100755 --- a/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_PCIE.rule +++ b/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_PCIE.rule @@ -23,6 +23,14 @@ # # IBM_PROLOG_END_TAG +################################################################################ +# +# Chiplet Register Adddresses Description +# ======= ======================= ============================================ +# PCIE 0x09000000 - 0x09FFFFFF PCIE pervasive logic +# +################################################################################ + ############################################################################ # PCIE Chiplet Registers ############################################################################ @@ -107,7 +115,7 @@ register PCICLOCKFIR_0 { - name "ES.PE_WRAP_TOP.PE0.PH3_TOP.ETU.RSB.PR_REGS.LEM.FIR_REG"; + name "PE0.ETU.RSB.PR_REGS.LEM.FIR_REG"; scomaddr 0x09012000; capture group default; capture req funccall("phbConfigured_0"); @@ -115,7 +123,7 @@ register PCICLOCKFIR_1 { - name "ES.PE_WRAP_TOP.PE1.PH3_TOP.ETU.RSB.PR_REGS.LEM.FIR_REG"; + name "PE1.ETU.RSB.PR_REGS.LEM.FIR_REG"; scomaddr 0x09012400; capture group default; capture req funccall("phbConfigured_1"); @@ -123,42 +131,63 @@ register PCICLOCKFIR_2 { - name "ES.PE_WRAP_TOP.PE2.PH3_TOP.ETU.RSB.PR_REGS.LEM.FIR_REG"; + name "PE2.ETU.RSB.PR_REGS.LEM.FIR_REG"; scomaddr 0x09012800; capture group default; capture req funccall("phbConfigured_2"); }; + # This FIR only exist on Naples. So we will have a conditional capture + # below, which is common on all P8/P8+ chips. + + register PCICLOCKFIR_3 + { + name "PE3.ETU.RSB.PR_REGS.LEM.FIR_REG"; + scomaddr 0x09012C00; + capture group default; + capture req funccall("phbConfigured_3"); + }; + register PCI_ETU_RESET_0 { - name "ES.PE_WRAP_TOP.PE0.PEPBCQ.PBAIB.PEAIBREGS.PE_ETU_RESET_REG"; + name "ES.PE_WRAP_TOP.PE0.PBAIB.PEAIBREGS.PE_ETU_RESET_REG"; scomaddr 0x0901200A; capture group never; }; register PCI_ETU_RESET_1 { - name "ES.PE_WRAP_TOP.PE1.PEPBCQ.PBAIB.PEAIBREGS.PE_ETU_RESET_REG"; + name "ES.PE_WRAP_TOP.PE1.PBAIB.PEAIBREGS.PE_ETU_RESET_REG"; scomaddr 0x0901240A; capture group never; }; register PCI_ETU_RESET_2 { - name "ES.PE_WRAP_TOP.PE2.PEPBCQ.PBAIB.PEAIBREGS.PE_ETU_RESET_REG"; + name "ES.PE_WRAP_TOP.PE2.PBAIB.PEAIBREGS.PE_ETU_RESET_REG"; scomaddr 0x0901280A; capture group never; }; + register PCI_ETU_RESET_3 + { + name "ES.PE_WRAP_TOP.PE3.PBAIB.PEAIBREGS.PE_ETU_RESET_REG"; + scomaddr 0x09012C0A; + capture group never; + }; ############################################################################ # PCIE Chiplet PBFFIR ############################################################################ + # Used for FFDC only. This FIR does not exist on Naples. So we will have a + # conditional capture below, which is common on all P8/P8+ chips. + register PBFFIR { name "ES.PBES_WRAP_TOP.PBES_TOP.MISC_IOF.SCOM.PB_IOF_FIR_REG"; scomaddr 0x09010800; + capture req funccall("isNotNaplesProc"); capture group default; }; @@ -166,6 +195,7 @@ { name "ES.PBES_WRAP_TOP.PBES_TOP.IOF0.IOF.PCI_WRAP.PCI_BB.PB_IOF_ERR_STATUS"; scomaddr 0x0901083A; + capture req funccall("isNotNaplesProc"); capture group default; capture group CerrRegs; }; @@ -174,6 +204,7 @@ { name "ES.PBES_WRAP_TOP.PBES_TOP.IOF1.IOF.PCI_WRAP.PCI_BB.PB_IOF_ERR_STATUS"; scomaddr 0x0901083B; + capture req funccall("isNotNaplesProc"); capture group default; capture group CerrRegs; }; diff --git a/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_TP.rule b/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_TP.rule index 11a07b399..44dcdbf47 100755 --- a/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_TP.rule +++ b/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_TP.rule @@ -23,6 +23,14 @@ # # IBM_PROLOG_END_TAG +################################################################################ +# +# Chiplet Register Adddresses Description +# ======= ======================= ============================================ +# TP 0x01000000 - 0x01FFFFFF TP pervasive logic +# +################################################################################ + ############################################################################ # TP Chiplet Registers ############################################################################ @@ -240,9 +248,9 @@ capture req nonzero("PMCFIR"); }; -################################################################################ -# TOD Register -################################################################################ + ############################################################################ + # TOD Registers + ############################################################################ register TOD_MPCR { @@ -391,9 +399,10 @@ scomaddr 0x00040033; capture group TODReg; }; -###################################################################### -# Registers for FFDC only -###################################################################### + + ############################################################################ + # Registers for FFDC only + ############################################################################ register PMC_SPIV_STATUS_REG { diff --git a/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_XBUS.rule b/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_XBUS.rule index d59baa661..7ff77992c 100755 --- a/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_XBUS.rule +++ b/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_XBUS.rule @@ -5,7 +5,7 @@ # # OpenPOWER HostBoot Project # -# Contributors Listed Below - COPYRIGHT 2012,2014 +# Contributors Listed Below - COPYRIGHT 2012,2015 # [+] International Business Machines Corp. # # @@ -23,6 +23,14 @@ # # IBM_PROLOG_END_TAG +################################################################################ +# +# Chiplet Register Adddresses Description +# ======= ======================= ============================================ +# XBUS 0x04000000 - 0x0400FFFF XBUS pervasive logic +# +################################################################################ + ############################################################################ # XBUS Chiplet Registers ############################################################################ @@ -128,13 +136,16 @@ # XBUS Chiplet IOXFIR_0 (Venice only) ############################################################################ - register IOXFIR_0 - { + # This FIR does not exist on Murano. So we will have a conditional capture + # below, which is common on all P8/P8+ chips. + + register IOXFIR_0 + { name "XBUS01.X0.BUSCTL.SCOM.FIR_REG"; scomaddr 0x04011000; reset (&, 0x04011001); mask (|, 0x04011005); - capture req funccall("isVeniceProc"); + capture req funccall("isNotMuranoProc"); capture group default; }; @@ -142,7 +153,7 @@ { name "XBUS01.X0.BUSCTL.SCOM.FIR_MASK_REG"; scomaddr 0x04011003; - capture req funccall("isVeniceProc"); + capture req funccall("isNotMuranoProc"); capture group default; }; @@ -151,7 +162,7 @@ name "XBUS01.X0.BUSCTL.SCOM.FIR_ACTION0_REG"; scomaddr 0x04011006; capture type secondary; - capture req funccall("isVeniceProc"); + capture req funccall("isNotMuranoProc"); capture req nonzero("IOXFIR_0"); capture group default; }; @@ -161,7 +172,7 @@ name "XBUS01.X0.BUSCTL.SCOM.FIR_ACTION1_REG"; scomaddr 0x04011007; capture type secondary; - capture req funccall("isVeniceProc"); + capture req funccall("isNotMuranoProc"); capture req nonzero("IOXFIR_0"); capture group default; }; @@ -208,13 +219,16 @@ # XBUS Chiplet IOXFIR_2 (Venice only) ############################################################################ + # This FIR does not exist on Murano. So we will have a conditional capture + # below, which is common on all P8/P8+ chips. + register IOXFIR_2 { name "XBUS23.X1.BUSCTL.SCOM.FIR_REG"; scomaddr 0x04011C00; reset (&, 0x04011C01); mask (|, 0x04011C05); - capture req funccall("isVeniceProc"); + capture req funccall("isNotMuranoProc"); capture group default; }; @@ -222,7 +236,7 @@ { name "XBUS23.X1.BUSCTL.SCOM.FIR_MASK_REG"; scomaddr 0x04011C03; - capture req funccall("isVeniceProc"); + capture req funccall("isNotMuranoProc"); capture group default; }; @@ -231,7 +245,7 @@ name "XBUS23.X1.BUSCTL.SCOM.FIR_ACTION0_REG"; scomaddr 0x04011C06; capture type secondary; - capture req funccall("isVeniceProc"); + capture req funccall("isNotMuranoProc"); capture req nonzero("IOXFIR_2"); capture group default; }; @@ -241,7 +255,7 @@ name "XBUS23.X1.BUSCTL.SCOM.FIR_ACTION1_REG"; scomaddr 0x04011C07; capture type secondary; - capture req funccall("isVeniceProc"); + capture req funccall("isNotMuranoProc"); capture req nonzero("IOXFIR_2"); capture group default; }; @@ -250,13 +264,16 @@ # XBUS Chiplet IOXFIR_3 (Venice only) ############################################################################ + # This FIR does not exist on Murano. So we will have a conditional capture + # below, which is common on all P8/P8+ chips. + register IOXFIR_3 { name "XBUS23.X0.BUSCTL.SCOM.FIR_REG"; scomaddr 0x04011800; reset (&, 0x04011801); mask (|, 0x04011805); - capture req funccall("isVeniceProc"); + capture req funccall("isNotMuranoProc"); capture group default; }; @@ -264,7 +281,7 @@ { name "XBUS23.X0.XBUS1.BUSCTL.SCOM.FIR_MASK_REG"; scomaddr 0x04011803; - capture req funccall("isVeniceProc"); + capture req funccall("isNotMuranoProc"); capture group default; }; @@ -273,7 +290,7 @@ name "XBUS23.X0.XBUS1.BUSCTL.SCOM.FIR_ACTION0_REG"; scomaddr 0x04011806; capture type secondary; - capture req funccall("isVeniceProc"); + capture req funccall("isNotMuranoProc"); capture req nonzero("IOXFIR_3"); capture group default; }; @@ -283,7 +300,7 @@ name "XBUS23.X0.XBUS1.BUSCTL.SCOM.FIR_ACTION1_REG"; scomaddr 0x04011807; capture type secondary; - capture req funccall("isVeniceProc"); + capture req funccall("isNotMuranoProc"); capture req nonzero("IOXFIR_3"); capture group default; }; diff --git a/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_common.rule b/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_common.rule new file mode 100755 index 000000000..8b6c5a275 --- /dev/null +++ b/src/usr/diag/prdf/common/plat/pegasus/Proc_regs_common.rule @@ -0,0 +1,173 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/common/plat/pegasus/Proc_regs_common.rule $ +# +# OpenPOWER HostBoot Project +# +# Contributors Listed Below - COPYRIGHT 2015 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +################################################################################ +# +# Scope: +# Registers for the following chiplets: +# +# Chiplet Register Adddresses Description +# ======= ======================= ============================================ +# TP 0x01000000 - 0x01FFFFFF TP pervasive logic +# PB 0x02000000 - 0x02FFFFFF PB pervasive logic, note that this does +# include the SCOM addresses characterized by +# the MCS target. See Mcs.rule for those +# address ranges. +# XBUS 0x04000000 - 0x0400FFFF XBUS pervasive logic +# PCIE 0x09000000 - 0x09FFFFFF PCIE pervasive logic +# +################################################################################ + + ############################################################################# + # # + # ###### # + # # # ###### #### ### #### ##### ###### ##### #### # + # # # # # # # # # # # # # # + # ###### ##### # # #### # ##### # # #### # + # # # # # ### # # # # ##### # # + # # # # # # # # # # # # # # # # + # # # ###### #### ### #### # ###### # # #### # + # # + ############################################################################# + + ############################################################################ + # Global Broadcast Registers + ############################################################################ + + register GLOBAL_CS_FIR + { + name "Global Checkstop Attention FIR"; + scomaddr 0x570F001C; + capture group default; + }; + + register GLOBAL_RE_FIR + { + name "Global Recoverable Attention FIR"; + scomaddr 0x570F001B; + capture group default; + }; + + register GLOBAL_SPA + { + name "Global Special Attention FIR"; + scomaddr 0x570F001A; + capture group default; + }; + + register GLOBALUNITXSTPFIR + { + name "Virtual Global Unit Checkstop FIR"; + scomaddr 0x51040001; + capture group default; + capture req funccall("CoreConfiguredAndNotHostboot"); + }; + + ######################################################################## + # Non-existent Registers for Capture + ######################################################################## + register VPD_FAILED_LANES_0TO63 + { + name "Bit map 0-63 of failed lanes read from VPD"; + scomaddr 0xFFFF0001; + access no_access; + capture group never; + }; + + register VPD_FAILED_LANES_64TO127 + { + name "Bit map 64-127 of failed lanes read from VPD"; + scomaddr 0xFFFF0002; + access no_access; + capture group never; + }; + + register ALL_FAILED_LANES_0TO63 + { + name "Bit map 0-63 of failed lanes from io_read_erepair"; + scomaddr 0xFFFF0003; + access no_access; + capture group never; + }; + + register ALL_FAILED_LANES_64TO127 + { + name "Bit map 64-127 of failed lanes from io_read_erepair"; + scomaddr 0xFFFF0004; + access no_access; + capture group never; + }; + + ############################################################################ + # Non-FIR Registers + ############################################################################ + + register TODWOF + { + name "Time of Day / WOF Counter"; + scomaddr 0x00040020; + capture group default; + }; + + ############################################################################ + # PLL Registers + ############################################################################ + + register CFAM_FSI_STATUS + { + name "TPC.FSI.FSI2PIB.STATUS"; + scomaddr 0x00001007; + capture group never; + }; + + register CFAM_FSI_GP7 + { + name "TPC.FSI.FSI_MAILBOX.FSXCOMP.FSXLOG.FSIGP7"; + scomaddr 0x00002816; + capture group never; + }; + + register PCIE_OSC_SWITCH + { + name "TPC.FSI.FSI_MAILBOX.FSXCOMP.FSXLOG.SNS1LTH"; + scomaddr 0x00050019; + capture group PllFIRs; + }; + + register OSCERR + { + name "EH.TPCHIP.TPC.ITR.OSCERR.OSCERR_HOLD"; + scomaddr 0x01020019; + capture group PllFIRs; + }; + + register OSCERR_MASK + { + name "EH.TPCHIP.TPC.ITR.OSCERR.OSCERR_MASK"; + scomaddr 0x0102001A; + capture group PllFIRs; + }; + + diff --git a/src/usr/diag/prdf/common/plat/pegasus/prdfP8Pll.C b/src/usr/diag/prdf/common/plat/pegasus/prdfP8Pll.C index e572dd123..799ce108d 100755 --- a/src/usr/diag/prdf/common/plat/pegasus/prdfP8Pll.C +++ b/src/usr/diag/prdf/common/plat/pegasus/prdfP8Pll.C @@ -195,7 +195,8 @@ int32_t QueryProcPll( ExtensibleChip * i_chip, #undef PRDF_FUNC } -PRDF_PLUGIN_DEFINE( Proc, QueryProcPll ); +PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, QueryProcPll ); +PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, QueryProcPll ); /** * @brief Query the PLL chip for a PLL error on P8 @@ -257,7 +258,8 @@ int32_t QueryPll( ExtensibleChip * i_chip, #undef PRDF_FUNC } -PRDF_PLUGIN_DEFINE( Proc, QueryPll ); +PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, QueryPll ); +PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, QueryPll ); /** @@ -333,7 +335,8 @@ int32_t ClearPll( ExtensibleChip * i_chip, #undef PRDF_FUNC } -PRDF_PLUGIN_DEFINE( Proc, ClearPll ); +PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, ClearPll ); +PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, ClearPll ); /** * @brief Mask the PLL error for P8 Plugin @@ -404,7 +407,8 @@ int32_t MaskPll( ExtensibleChip * i_chip, #undef PRDF_FUNC } -PRDF_PLUGIN_DEFINE( Proc, MaskPll ); +PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, MaskPll ); +PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, MaskPll ); /** * @brief Optional plugin function called after analysis is complete but @@ -431,7 +435,8 @@ int32_t PllPostAnalysis( ExtensibleChip * i_chip, #undef PRDF_FUNC } -PRDF_PLUGIN_DEFINE( Proc, PllPostAnalysis ); +PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, PllPostAnalysis ); +PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, PllPostAnalysis ); /** * @brief capture additional PLL FFDC @@ -466,7 +471,8 @@ int32_t capturePllFfdc( ExtensibleChip * i_chip, #undef PRDF_FUNC } -PRDF_PLUGIN_DEFINE( Proc, capturePllFfdc ); +PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, capturePllFfdc ); +PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, capturePllFfdc ); /** * @brief Check PCB Slave internal parity errors @@ -784,7 +790,8 @@ int32_t AnalyzeParityErr( ExtensibleChip * i_chip, #undef PRDF_FUNC } -PRDF_PLUGIN_DEFINE( Proc, AnalyzeParityErr ); +PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, AnalyzeParityErr ); +PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, AnalyzeParityErr ); } // end namespace Proc diff --git a/src/usr/diag/prdf/common/plat/pegasus/prdfP8PllPcie.C b/src/usr/diag/prdf/common/plat/pegasus/prdfP8PllPcie.C index f638fb55a..a11d8f5af 100755 --- a/src/usr/diag/prdf/common/plat/pegasus/prdfP8PllPcie.C +++ b/src/usr/diag/prdf/common/plat/pegasus/prdfP8PllPcie.C @@ -146,7 +146,8 @@ int32_t QueryPciPll( ExtensibleChip * i_chip, #undef PRDF_FUNC } -PRDF_PLUGIN_DEFINE( Proc, QueryPciPll ); +PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, QueryPciPll ); +PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, QueryPciPll ); /** * @brief Query the PLL chip for a PLL error on P8 @@ -208,7 +209,8 @@ int32_t QueryPllIo( ExtensibleChip * i_chip, #undef PRDF_FUNC } -PRDF_PLUGIN_DEFINE( Proc, QueryPllIo ); +PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, QueryPllIo ); +PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, QueryPllIo ); /** @@ -298,7 +300,8 @@ int32_t ClearPllIo( ExtensibleChip * i_chip, #undef PRDF_FUNC } -PRDF_PLUGIN_DEFINE( Proc, ClearPllIo ); +PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, ClearPllIo ); +PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, ClearPllIo ); /** * @brief Mask the PLL error for P8 Plugin @@ -375,7 +378,8 @@ int32_t MaskPllIo( ExtensibleChip * i_chip, #undef PRDF_FUNC } -PRDF_PLUGIN_DEFINE( Proc, MaskPllIo ); +PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, MaskPllIo ); +PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, MaskPllIo ); /** * @brief capture additional PLL FFDC @@ -391,7 +395,8 @@ int32_t capturePllFfdcIo( ExtensibleChip * i_chip, return SUCCESS; } -PRDF_PLUGIN_DEFINE( Proc, capturePllFfdcIo ); +PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, capturePllFfdcIo ); +PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, capturePllFfdcIo ); /** * @brief calling out active pcie osc connected to this proc @@ -463,7 +468,8 @@ int32_t CalloutPllIo( ExtensibleChip * i_chip, #undef PRDF_FUNC } -PRDF_PLUGIN_DEFINE( Proc, CalloutPllIo ); +PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, CalloutPllIo ); +PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, CalloutPllIo ); } // end namespace Proc diff --git a/src/usr/diag/prdf/common/plat/pegasus/prdfP8Proc.C b/src/usr/diag/prdf/common/plat/pegasus/prdfP8Proc.C index 107bb8e2d..6d03253bf 100755 --- a/src/usr/diag/prdf/common/plat/pegasus/prdfP8Proc.C +++ b/src/usr/diag/prdf/common/plat/pegasus/prdfP8Proc.C @@ -65,7 +65,8 @@ int32_t Initialize( ExtensibleChip * i_chip ) i_chip->getDataBundle() = new P8DataBundle( i_chip ); return SUCCESS; } -PRDF_PLUGIN_DEFINE( Proc, Initialize ); +PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, Initialize ); +PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, Initialize ); /** * @brief Checks the Global Broadcast register. @@ -189,7 +190,9 @@ int32_t CheckForRecovered(ExtensibleChip * i_chip, } return SUCCESS; -} PRDF_PLUGIN_DEFINE( Proc, CheckForRecovered ); +} +PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, CheckForRecovered ); +PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, CheckForRecovered ); //------------------------------------------------------------------------------ /** @@ -264,7 +267,9 @@ int32_t CheckForRecoveredSev(ExtensibleChip * i_chip, return SUCCESS; -} PRDF_PLUGIN_DEFINE( Proc, CheckForRecoveredSev ); +} +PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, CheckForRecoveredSev ); +PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, CheckForRecoveredSev ); /** @func GetCheckstopInfo * To be called from the fabric domain to gather Checkstop information. This @@ -357,7 +362,9 @@ int32_t GetCheckstopInfo( ExtensibleChip * i_chip, return SUCCESS; -} PRDF_PLUGIN_DEFINE( Proc, GetCheckstopInfo ); +} +PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, GetCheckstopInfo ); +PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, GetCheckstopInfo ); int32_t CoreConfiguredAndNotHostboot(ExtensibleChip * i_chip, bool & o_isCoreConfigured) @@ -377,7 +384,9 @@ int32_t CoreConfiguredAndNotHostboot(ExtensibleChip * i_chip, } return SUCCESS; -} PRDF_PLUGIN_DEFINE(Proc, CoreConfiguredAndNotHostboot); +} +PRDF_PLUGIN_DEFINE_NS(NaplesProc, Proc, CoreConfiguredAndNotHostboot); +PRDF_PLUGIN_DEFINE_NS(MuranoVeniceProc, Proc, CoreConfiguredAndNotHostboot); //------------------------------------------------------------------------------ // Lane Repair plugins @@ -484,17 +493,20 @@ int32_t maxSparesExceeded_MCS( ExtensibleChip * i_procChip, int32_t spareDeployed_##BUS##POS( ExtensibleChip * i_chip, \ STEP_CODE_DATA_STRUCT & i_sc ) \ { return handleLaneRepairEvent(i_chip, TYPE, POS, i_sc, true); } \ -PRDF_PLUGIN_DEFINE( Proc, spareDeployed_##BUS##POS ); \ +PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, spareDeployed_##BUS##POS ); \ +PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, spareDeployed_##BUS##POS ); \ \ int32_t maxSparesExceeded_##BUS##POS( ExtensibleChip * i_chip, \ STEP_CODE_DATA_STRUCT & i_sc ) \ { return handleLaneRepairEvent(i_chip, TYPE, POS, i_sc, false); } \ -PRDF_PLUGIN_DEFINE( Proc, maxSparesExceeded_##BUS##POS ); \ +PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, maxSparesExceeded_##BUS##POS ); \ +PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, maxSparesExceeded_##BUS##POS ); \ \ int32_t tooManyBusErrors_##BUS##POS( ExtensibleChip * i_chip, \ STEP_CODE_DATA_STRUCT & i_sc ) \ { return handleLaneRepairEvent(i_chip, TYPE, POS, i_sc, false); } \ -PRDF_PLUGIN_DEFINE( Proc, tooManyBusErrors_##BUS##POS ); +PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, tooManyBusErrors_##BUS##POS ); \ +PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, tooManyBusErrors_##BUS##POS ); PLUGIN_LANE_REPAIR( xbus, TYPE_XBUS, 0 ) PLUGIN_LANE_REPAIR( xbus, TYPE_XBUS, 1 ) @@ -511,12 +523,14 @@ PLUGIN_LANE_REPAIR( abus, TYPE_ABUS, 2 ) int32_t spareDeployed_dmiBus##POS( ExtensibleChip * i_chip, \ STEP_CODE_DATA_STRUCT & i_sc ) \ { return handleLaneRepairEvent(i_chip, TYPE_MCS, POS, i_sc, true); } \ -PRDF_PLUGIN_DEFINE( Proc, spareDeployed_dmiBus##POS ); \ +PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, spareDeployed_dmiBus##POS ); \ +PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, spareDeployed_dmiBus##POS ); \ \ int32_t maxSparesExceeded_dmiBus##POS( ExtensibleChip * i_chip, \ STEP_CODE_DATA_STRUCT & i_sc ) \ { return maxSparesExceeded_MCS(i_chip, i_sc, POS); } \ -PRDF_PLUGIN_DEFINE( Proc, maxSparesExceeded_dmiBus##POS ); +PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, maxSparesExceeded_dmiBus##POS ); \ +PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, maxSparesExceeded_dmiBus##POS ); // Too Many Bus Error attentions not handled on DMI bus. @@ -570,7 +584,8 @@ int32_t mcsBlockConfigured( ExtensibleChip * i_chip, int32_t mcsBlockConfigured_##POS( ExtensibleChip * i_chip, \ bool & o_isMcsBlkConfigured ) \ { return mcsBlockConfigured( i_chip, POS, o_isMcsBlkConfigured ); } \ -PRDF_PLUGIN_DEFINE( Proc, mcsBlockConfigured_##POS ); +PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, mcsBlockConfigured_##POS ); \ +PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, mcsBlockConfigured_##POS ); PLUGIN_MCS_BLOCK_CONFIGURED( 0 ) PLUGIN_MCS_BLOCK_CONFIGURED( 1 ) @@ -588,48 +603,45 @@ PLUGIN_MCS_BLOCK_CONFIGURED( 1 ) * @param o_isPhbConfigured set to true if the PHB configured * @returns Success */ -int32_t phbConfigured(ExtensibleChip * i_chip, - uint32_t i_phbPos, - bool & o_isPhbConfigured) +int32_t phbConfigured( ExtensibleChip * i_chip, uint32_t i_phbPos, + bool & o_isPhbConfigured ) { #define PRDF_FUNC "[Proc::phbConfigured] " - static const uint32_t MAX_PCI_NUM = 3; - static const char * pciEtuResetReg[MAX_PCI_NUM] = - { "PCI_ETU_RESET_0", - "PCI_ETU_RESET_1", - "PCI_ETU_RESET_2" }; - int32_t o_rc = SUCCESS; o_isPhbConfigured = false; + uint32_t maxPhbs = 3; // Murano/Venice + if ( MODEL_NAPLES == getProcModel(i_chip->GetChipHandle()) ) + maxPhbs = 4; + do { - if( i_phbPos >= MAX_PCI_NUM ) + if ( maxPhbs <= i_phbPos ) { PRDF_ERR( PRDF_FUNC "invalid PCI number: %d", i_phbPos ); break; } - SCAN_COMM_REGISTER_CLASS * etuResetReg = - i_chip->getRegister( pciEtuResetReg[i_phbPos] ); + char reg_str[64]; + snprintf( reg_str, 64, "PCI_ETU_RESET_%d", i_phbPos ); - if(NULL == etuResetReg) + SCAN_COMM_REGISTER_CLASS * reg = i_chip->getRegister( reg_str ); + if ( NULL == reg ) { - PRDF_ERR( PRDF_FUNC "getRegister() Failed for register:%s", - pciEtuResetReg[i_phbPos] ); + PRDF_ERR( PRDF_FUNC"getRegister() failed for %s", reg_str ); break; } - o_rc = etuResetReg->Read(); - if ( SUCCESS != o_rc ) + int32_t l_rc = reg->Read(); + if ( SUCCESS != l_rc ) { - PRDF_ERR( PRDF_FUNC "%s Read() failed. Target=0x%08x", - pciEtuResetReg[i_phbPos], i_chip->GetId() ); + PRDF_ERR( PRDF_FUNC"Read() failed for %s: target=0x%08x", + reg_str, i_chip->GetId() ); break; } // If bit 0 is cleared then the PHB is configured - if ( ! etuResetReg->IsBitSet(0) ) + if ( !reg->IsBitSet(0) ) { o_isPhbConfigured = true; } @@ -645,11 +657,13 @@ int32_t phbConfigured(ExtensibleChip * i_chip, int32_t phbConfigured_##POS( ExtensibleChip * i_chip, \ bool & o_isPhbConfigured ) \ { return phbConfigured( i_chip, POS, o_isPhbConfigured ); } \ -PRDF_PLUGIN_DEFINE( Proc, phbConfigured_##POS ); +PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, phbConfigured_##POS ); \ +PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, phbConfigured_##POS ); PLUGIN_PHB_CONFIGURED( 0 ) PLUGIN_PHB_CONFIGURED( 1 ) PLUGIN_PHB_CONFIGURED( 2 ) +PLUGIN_PHB_CONFIGURED( 3 ) #undef PLUGIN_PHB_CONFIGURED @@ -684,7 +698,8 @@ int32_t deadManTimerCalloutAndFFDC( ExtensibleChip * i_chip, #undef PRDF_FUNC } -PRDF_PLUGIN_DEFINE( Proc, deadManTimerCalloutAndFFDC ); +PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, deadManTimerCalloutAndFFDC ); +PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, deadManTimerCalloutAndFFDC ); //------------------------------------------------------------------------------ @@ -762,7 +777,8 @@ int32_t combinedResponseCallout( ExtensibleChip * i_chip, #undef PRDF_FUNC } -PRDF_PLUGIN_DEFINE( Proc, combinedResponseCallout ); +PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, combinedResponseCallout ); +PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, combinedResponseCallout ); //------------------------------------------------------------------------------ @@ -773,7 +789,8 @@ int32_t calloutInterface_##BUS##POS( ExtensibleChip * i_chip, \ CalloutUtil::calloutBusInterface(i_chip, MRU_LOW, TYPE, POS); \ return SUCCESS; \ } \ -PRDF_PLUGIN_DEFINE( Proc, calloutInterface_##BUS##POS ); +PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, calloutInterface_##BUS##POS ); \ +PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, calloutInterface_##BUS##POS ); PLUGIN_BUS_INTERFACE_CALLOUT( abus, TYPE_ABUS, 0 ) PLUGIN_BUS_INTERFACE_CALLOUT( abus, TYPE_ABUS, 1 ) @@ -814,7 +831,8 @@ int32_t ClearServiceCallFlag( ExtensibleChip * i_chip, return SUCCESS; } -PRDF_PLUGIN_DEFINE( Proc, ClearServiceCallFlag ); +PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, ClearServiceCallFlag ); +PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, ClearServiceCallFlag ); /** * @brief Clear the service call flag (field and MNFG) so that thresholding @@ -833,7 +851,8 @@ int32_t ClearServiceCallFlag_mnfgInfo( ExtensibleChip * i_chip, return SUCCESS; } -PRDF_PLUGIN_DEFINE( Proc, ClearServiceCallFlag_mnfgInfo ); +PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, ClearServiceCallFlag_mnfgInfo ); +PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, ClearServiceCallFlag_mnfgInfo ); //------------------------------------------------------------------------------ // PHB Plugins for IOPCIFIR_x @@ -906,7 +925,8 @@ int32_t calloutPhbClk##CLK##_##IOPCI( ExtensibleChip * i_chip, \ { \ return calloutPhb( i_chip, i_sc, IOPCI, ERRA, ERRB ); \ }\ -PRDF_PLUGIN_DEFINE( Proc, calloutPhbClk##CLK##_##IOPCI ); +PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, calloutPhbClk##CLK##_##IOPCI ); \ +PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, calloutPhbClk##CLK##_##IOPCI ); PLUGIN_CALLOUT_PHB( A, 0, true, false ) PLUGIN_CALLOUT_PHB( B, 0, false, true ) @@ -921,7 +941,8 @@ int32_t calloutPhbBothClks_##IOPCI( ExtensibleChip * i_chip, \ { \ return calloutPhb( i_chip, i_sc, IOPCI, true, true ); \ }\ -PRDF_PLUGIN_DEFINE( Proc, calloutPhbBothClks_##IOPCI ); +PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, calloutPhbBothClks_##IOPCI ); \ +PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, calloutPhbBothClks_##IOPCI ); PLUGIN_CALLOUT_PHB( 0 ) PLUGIN_CALLOUT_PHB( 1 ) @@ -933,20 +954,89 @@ PLUGIN_CALLOUT_PHB( 1 ) //------------------------------------------------------------------------------ /** - * @brief checks if proc is Venice chip. - * @param i_chip P8 chip. - * @param isVenice TRUE if chip is venice false otherwise. - * @return SUCCESS - */ -int32_t isVeniceProc( ExtensibleChip * i_chip, bool & o_isVenice ) + * @brief Checks if this PROC is NOT a Murano chip. + * @param i_chip P8/P8+ chip. + * @param o_isNotMurano TRUE if this PROC is NOT a Murano chip, FALSE + * otherwise. + * @return SUCCESS + */ +int32_t isNotMuranoProc( ExtensibleChip * i_chip, bool & o_isNotMurano ) +{ + o_isNotMurano = false; + if ( MODEL_MURANO != getProcModel( i_chip->GetChipHandle() ) ) + o_isNotMurano = true; + + return SUCCESS; +} +PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, isNotMuranoProc ); +PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, isNotMuranoProc ); + +/** + * @brief Checks if this PROC is a Naples chip. + * @param i_chip P8/P8+ chip. + * @param o_isNaples TRUE if this PROC is a Naples chip, FALSE otherwise. + * @return SUCCESS + */ +int32_t isNaplesProc( ExtensibleChip * i_chip, bool & o_isNaples ) +{ + o_isNaples = false; + if ( MODEL_NAPLES == getProcModel( i_chip->GetChipHandle() ) ) + o_isNaples = true; + + return SUCCESS; +} +PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, isNaplesProc ); +PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, isNaplesProc ); + +/** + * * @brief Checks if this PROC is a Naples chip. + * @param i_chip P8/P8+ chip. + * @return FAIL if not naples, SUCCESS if naples +*/ +int32_t failIfNaples( ExtensibleChip * i_chip ) { - o_isVenice = false; - if( MODEL_VENICE == getProcModel( i_chip->GetChipHandle() ) ) - o_isVenice = true; + if ( MODEL_NAPLES == getProcModel( i_chip->GetChipHandle() ) ) + return FAIL; return SUCCESS; } -PRDF_PLUGIN_DEFINE( Proc, isVeniceProc ); +PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, failIfNaples ); +PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, failIfNaples ); + + +/** + * @brief Checks if this PROC is NOT a Naples chip. + * @param i_chip P8/P8+ chip. + * @param o_isNotNaples TRUE if this PROC is NOT a Naples chip, FALSE + * otherwise. + * @return SUCCESS + */ +int32_t isNotNaplesProc( ExtensibleChip * i_chip, bool & o_isNotNaples ) +{ + o_isNotNaples = false; + if ( MODEL_NAPLES != getProcModel( i_chip->GetChipHandle() ) ) + o_isNotNaples = true; + + return SUCCESS; +} +PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, isNotNaplesProc ); +PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, isNotNaplesProc ); + +/** + * @brief Checks if this PROC is a Naples chip. + * @param i_chip P8/P8+ chip. + * @return SUCCESS if not naples, FAIL if naples +*/ +int32_t failIfNotNaples( ExtensibleChip * i_chip ) +{ + if ( MODEL_NAPLES != getProcModel( i_chip->GetChipHandle() ) ) + return FAIL; + + return SUCCESS; +} +PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, failIfNotNaples ); +PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, failIfNotNaples ); + /** * @brief checks if proc is Murano chip and is at DD1.x level. @@ -963,7 +1053,8 @@ int32_t isMuranoDD1( ExtensibleChip * i_chip, bool & o_isMuranoDD1 ) return SUCCESS; } -PRDF_PLUGIN_DEFINE( Proc, isMuranoDD1 ); +PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, isMuranoDD1 ); +PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, isMuranoDD1 ); } // end namespace Proc diff --git a/src/usr/diag/prdf/common/plat/pegasus/prdfPegasusConfigurator.C b/src/usr/diag/prdf/common/plat/pegasus/prdfPegasusConfigurator.C index eb75c0752..b7ef7ff68 100644 --- a/src/usr/diag/prdf/common/plat/pegasus/prdfPegasusConfigurator.C +++ b/src/usr/diag/prdf/common/plat/pegasus/prdfPegasusConfigurator.C @@ -227,38 +227,42 @@ errlHndl_t PegasusConfigurator::addDomainChips( TARGETING::TYPE i_type, PllDomainList * io_pllDomains2) { using namespace TARGETING; - int32_t l_rc = SUCCESS; errlHndl_t l_errl = NULL ; // Get references to factory objects. ScanFacility & scanFac = ScanFacility::Access(); ResolutionFactory & resFac = ResolutionFactory::Access(); - // Get rule filename based on type. - const char * fileName = ""; - switch ( i_type ) + // Get all targets of specified type and add to given domain. + TargetHandleList list = PlatServices::getFunctionalTargetList( i_type ); + + if ( 0 == list.size() ) { - case TYPE_PROC: fileName = Proc; break; - case TYPE_EX: fileName = Ex; break; - case TYPE_MCS: fileName = Mcs; break; - case TYPE_MEMBUF: fileName = Membuf; break; - case TYPE_MBA: fileName = Mba; break; - - default: - // Print a trace statement, but do not fail the build. - PRDF_ERR( "[addDomainChips] Unsupported target type: %d", i_type ); - l_rc = FAIL; + PRDF_ERR( "[addDomainChips] getFunctionalTargetList " + "returned empty list for i_type=%d", i_type ); } - - if ( SUCCESS == l_rc ) + else { - // Get all targets of specified type and add to given domain. - TargetHandleList list = PlatServices::getFunctionalTargetList( i_type ); - - if ( 0 == list.size() ) + // Get rule filename based on type. + const char * fileName = ""; + switch ( i_type ) { - PRDF_ERR( "[addDomainChips] getFunctionalTargetList " - "returned empty list for i_type=%d", i_type ); + case TYPE_PROC: + // Check which Proc chip type + if (MODEL_NAPLES == getProcModel(list[0])) + fileName = NaplesProc; + else + fileName = MuranoVeniceProc; + break; + case TYPE_EX: fileName = Ex; break; + case TYPE_MCS: fileName = Mcs; break; + case TYPE_MEMBUF: fileName = Membuf; break; + case TYPE_MBA: fileName = Mba; break; + + default: + // Print a trace statement, but do not fail the build. + PRDF_ERR( "[addDomainChips] Unsupported target type: %d", + i_type ); } for ( TargetHandleList::const_iterator itr = list.begin(); diff --git a/src/usr/diag/prdf/common/plugins/prdfParserEnums.H b/src/usr/diag/prdf/common/plugins/prdfParserEnums.H index 743bb4718..34db50b81 100644 --- a/src/usr/diag/prdf/common/plugins/prdfParserEnums.H +++ b/src/usr/diag/prdf/common/plugins/prdfParserEnums.H @@ -57,7 +57,8 @@ enum PositionBounds MAX_XBUS_PER_PROC = 4, MAX_ABUS_PER_PROC = 3, - MAX_PHB_PER_PROC = 3, + MAX_PHB_PER_PROC = 4, + MAX_NV_PER_PROC = 1, MAX_MCS_PER_PROC = 8, MAX_MEMBUF_PER_PROC = MAX_MCS_PER_PROC, diff --git a/src/usr/diag/prdf/plat/pegasus/prdfP8TodPlugins.C b/src/usr/diag/prdf/plat/pegasus/prdfP8TodPlugins.C index f1886e07f..337332c8c 100755 --- a/src/usr/diag/prdf/plat/pegasus/prdfP8TodPlugins.C +++ b/src/usr/diag/prdf/plat/pegasus/prdfP8TodPlugins.C @@ -51,7 +51,8 @@ int32_t FUNC( ExtensibleChip * i_procChip, STEP_CODE_DATA_STRUCT & i_sc ) \ CalloutUtil::defaultError( i_sc ); \ return SUCCESS; \ } \ -PRDF_PLUGIN_DEFINE( Proc, FUNC ); +PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, FUNC ); \ +PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, FUNC ); PLUGIN_TOD_UNEXPECTED_ATTN( clearServiceCallFlag ) PLUGIN_TOD_UNEXPECTED_ATTN( todNewTopologyIfBackupMDMT ) @@ -85,7 +86,8 @@ int32_t isTodDisabled( ExtensibleChip * i_chip, return SUCCESS; } -PRDF_PLUGIN_DEFINE( Proc, isTodDisabled ); +PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, isTodDisabled ); +PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, isTodDisabled ); } //namespace Proc ends diff --git a/src/usr/diag/prdf/plat/pegasus/prdfPlatP8Proc.C b/src/usr/diag/prdf/plat/pegasus/prdfPlatP8Proc.C index 56f0aa247..9ab033b8a 100644 --- a/src/usr/diag/prdf/plat/pegasus/prdfPlatP8Proc.C +++ b/src/usr/diag/prdf/plat/pegasus/prdfPlatP8Proc.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2013,2014 */ +/* Contributors Listed Below - COPYRIGHT 2013,2015 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -61,7 +61,8 @@ int32_t analyzeMpIPL( ExtensibleChip * i_chip, return SUCCESS; } -PRDF_PLUGIN_DEFINE( Proc, analyzeMpIPL ); +PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, analyzeMpIPL ); +PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, analyzeMpIPL ); /** * @brief Handle SLW Malfunction alert @@ -78,7 +79,8 @@ int32_t slwRecovery( ExtensibleChip * i_chip, CalloutUtil::defaultError( i_sc ); return SUCCESS; } -PRDF_PLUGIN_DEFINE( Proc, slwRecovery ); +PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, slwRecovery ); +PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, slwRecovery ); /** * @brief Callout Peer PSI connected to given Proc target @@ -96,7 +98,8 @@ int32_t calloutPeerPsiBusTgt( ExtensibleChip * i_chip, CalloutUtil::defaultError( i_sc ); return SUCCESS; } -PRDF_PLUGIN_DEFINE( Proc, calloutPeerPsiBusTgt ); +PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, calloutPeerPsiBusTgt ); +PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, calloutPeerPsiBusTgt ); /** * @brief Check if we're running in hostboot @@ -108,7 +111,9 @@ int32_t inHostboot( ExtensibleChip * i_chip, STEP_CODE_DATA_STRUCT & i_sc ) { return SUCCESS; -} PRDF_PLUGIN_DEFINE( Proc, inHostboot ); +} +PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, inHostboot ); +PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, inHostboot ); /** * @brief Collect NX debug traces @@ -124,7 +129,9 @@ int32_t collectNxTraceArray( ExtensibleChip * i_chip, return SUCCESS; -} PRDF_PLUGIN_DEFINE( Proc, collectNxTraceArray ); +} +PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, collectNxTraceArray ); +PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, collectNxTraceArray ); }//namespace Proc ends diff --git a/src/usr/diag/prdf/plat/pegasus/prdfPllUtils.C b/src/usr/diag/prdf/plat/pegasus/prdfPllUtils.C index e72642b64..da83a7391 100644 --- a/src/usr/diag/prdf/plat/pegasus/prdfPllUtils.C +++ b/src/usr/diag/prdf/plat/pegasus/prdfPllUtils.C @@ -60,7 +60,9 @@ int32_t queryPciOscErr( ExtensibleChip * i_procChip, return o_rc; #undef PRDF_FUNC -}PRDF_PLUGIN_DEFINE( Proc, queryPciOscErr ); +} +PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, queryPciOscErr ); +PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, queryPciOscErr ); //------------------------------------------------------------------------------ @@ -81,7 +83,9 @@ int32_t analyzePciClkFailover( ExtensibleChip * i_procChip, return o_rc; #undef PRDF_FUNC -}PRDF_PLUGIN_DEFINE( Proc, analyzePciClkFailover ); +} +PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, analyzePciClkFailover ); +PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, analyzePciClkFailover ); //------------------------------------------------------------------------------ @@ -102,7 +106,9 @@ int32_t clearPciOscFailOver( ExtensibleChip * i_procChip, return o_rc; #undef PRDF_FUNC -}PRDF_PLUGIN_DEFINE( Proc, clearPciOscFailOver ); +} +PRDF_PLUGIN_DEFINE_NS( NaplesProc, Proc, clearPciOscFailOver ); +PRDF_PLUGIN_DEFINE_NS( MuranoVeniceProc, Proc, clearPciOscFailOver ); } // end namespace Proc |
