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authorChristian Geddes <crgeddes@us.ibm.com>2019-11-01 16:27:46 -0500
committerDaniel M Crowell <dcrowell@us.ibm.com>2019-11-06 11:33:17 -0600
commitd1260d0c7d61181763e71028fd170a67979fa0e4 (patch)
treef4b08580e1aca17b9ef6c4cc1e9f02b072380d95 /src/usr
parent22b39d874ddd07de74470b20d6b4a66ebb52c6ee (diff)
downloadtalos-hostboot-d1260d0c7d61181763e71028fd170a67979fa0e4.tar.gz
talos-hostboot-d1260d0c7d61181763e71028fd170a67979fa0e4.zip
Fix ipmifruinv calls for dimms in swift systems
We had a bug in the VPD map for the the DDR4_DDIMMs where we were missing fields that were expected in the data collection for the fruinventory. This commit adds the field we were missing and also adds the PART_NUMBER field which the BMC is currently just leaving blank. Change-Id: I65dbfb0b79bef9d3a9a3bf2d6aa135c5df5ece56 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/86420 Reviewed-by: William G Hoffa <wghoffa@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Matt Derksen <mderkse1@us.ibm.com> Reviewed-by: Daniel M Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/usr')
-rwxr-xr-xsrc/usr/vpd/spdDDR4_DDIMM.H2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/usr/vpd/spdDDR4_DDIMM.H b/src/usr/vpd/spdDDR4_DDIMM.H
index f6f05260d..9e10a049a 100755
--- a/src/usr/vpd/spdDDR4_DDIMM.H
+++ b/src/usr/vpd/spdDDR4_DDIMM.H
@@ -104,8 +104,10 @@ const KeywordData ddr4DDIMMData[] =
{ TRPMIN_FINE_OFFSET, 0x79, 0x01, 0x00, 0x00, false, false, ALL },
{ TRCMIN_FINE_OFFSET, 0x78, 0x01, 0x00, 0x00, false, false, ALL },
// Note - All data below 128 is common across all DDR4 DIMMs, except DDIMM
+ { MODULE_MANUFACTURER_ID, 0x200, 0x02, 0x00, 0x00, true, false, ALL },
{ MODULE_SERIAL_NUMBER, 0x205, 0x04, 0x00, 0x00, false, false, ALL },
{ MODULE_PART_NUMBER, 0x209, 0x1E, 0x00, 0x00, false, false, ALL },
+ { MODULE_REVISION_CODE, 0x277, 0x01, 0x00, 0x00, false, false, ALL },
// Normal fields supported on DDR4 only
{ BANK_GROUP_BITS, 0x04, 0x01, 0xC0, 0x06, false, false, ALL },
{ BANK_ADDRESS_BITS_DDR4, 0x04, 0x01, 0x30, 0x04, false, false, ALL },
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