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| author | Thi Tran <thi@us.ibm.com> | 2013-12-11 16:03:02 -0600 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2013-12-13 09:50:10 -0600 |
| commit | bbbd9786a0a3f535cf8f923eda561f1f0b3ec2b7 (patch) | |
| tree | 7fd4093c413ddc8a91c0bdd47e6ef5babe1f8f67 /src/usr | |
| parent | b080f2201c10e8c9ea7ed9813453ae4936fc3987 (diff) | |
| download | talos-hostboot-bbbd9786a0a3f535cf8f923eda561f1f0b3ec2b7.tar.gz talos-hostboot-bbbd9786a0a3f535cf8f923eda561f1f0b3ec2b7.zip | |
INITPROC: Hostboot - SW237985 - Initfiles update 12/10
Change-Id: I53ae766c39fa9c037443f137052cf6c266481910
CQ:SW237985
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/7685
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr')
7 files changed, 87 insertions, 50 deletions
diff --git a/src/usr/hwpf/hwp/initfiles/cen.dmi.custom.scom.initfile b/src/usr/hwpf/hwp/initfiles/cen.dmi.custom.scom.initfile index 1a4396b12..bb48c8f0d 100644 --- a/src/usr/hwpf/hwp/initfiles/cen.dmi.custom.scom.initfile +++ b/src/usr/hwpf/hwp/initfiles/cen.dmi.custom.scom.initfile @@ -1,8 +1,11 @@ -#-- $Id: cen.dmi.custom.scom.initfile,v 1.16 2013/10/28 21:59:47 jgrell Exp $ +#-- $Id: cen.dmi.custom.scom.initfile,v 1.18 2013/12/04 17:43:34 jgrell Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- +#-- 1.18|jgrell |11/21/13|Added rx_trc_grp setting at the request of Yuen Tschang +#-- |Set rx_eo_ddc_timeout_sel to 110 for DD2 +#-- 1.17|jgrell |10/29/13|Changed rx_ds_timeout_sel setting to 111 #-- 1.16|jgrell |10/28/13|Re-enabled recal bits for DD2+ hw #-- 1.15|jgrell |09/24/13|Changed "1" expression to "any" #-- 1.13|jgrell |09/17/13|Added DD2 specific inits @@ -361,7 +364,7 @@ rx_amp_gain, 0b1001, ATTR_DMI_DFE_OVERRIDE==1; #--*********************************************************************************** #------------------------------------------------------------------------------------- -#-- DD2 Murano +#-- DD2 Centaur #------------------------------------------------------------------------------------- #--*********************************************************************************** @@ -371,9 +374,20 @@ scom 0x800.0b(rx_timeout_sel_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr) { rx_ds_bl_timeout_sel_dd2, 0b101, ATTR_CENTAUR_EC_MCBIST_RANDOM_ADDRESS==1; rx_cl_timeout_sel_dd2, 0b010, ATTR_CENTAUR_EC_MCBIST_RANDOM_ADDRESS==1; rx_wt_timeout_sel_dd2, 0b111, ATTR_CENTAUR_EC_MCBIST_RANDOM_ADDRESS==1; - rx_ds_timeout_sel_dd2, 0b110, ATTR_CENTAUR_EC_MCBIST_RANDOM_ADDRESS==1; + rx_ds_timeout_sel_dd2, 0b111, ATTR_CENTAUR_EC_MCBIST_RANDOM_ADDRESS==1; } +scom 0x800.0b(rx_trace_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr) { + bits, scom_data, expr; + rx_trc_grp, 0b000000, ATTR_CENTAUR_EC_MCBIST_RANDOM_ADDRESS==1; +} + +scom 0x800.0b(rx_timeout_sel1_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr) { + bits, scom_data, expr; + rx_eo_ddc_timeout_sel, 0b110, ATTR_CENTAUR_EC_MCBIST_RANDOM_ADDRESS==1; +} + + #--************************************************************************************************************** #---------------------------------------------------------------------------------------------------------------- # Power Down Unused Lanes diff --git a/src/usr/hwpf/hwp/initfiles/cen.dmi.scom.initfile b/src/usr/hwpf/hwp/initfiles/cen.dmi.scom.initfile index ed7e376cf..ea1556a2b 100644 --- a/src/usr/hwpf/hwp/initfiles/cen.dmi.scom.initfile +++ b/src/usr/hwpf/hwp/initfiles/cen.dmi.scom.initfile @@ -1,4 +1,4 @@ -#-- $Id: cen.dmi.scom.initfile,v 1.18 2013/10/28 21:59:47 jgrell Exp $ +#-- $Id: cen.dmi.scom.initfile,v 1.20 2013/12/04 17:43:33 jgrell Exp $ #################################################################### @@ -7,13 +7,14 @@ ## Based on SETUP_ID_MODE DMI_BUS_TR_HW ## from ../../logic/mesa_sim/fusion/run/IODNC_MB_TOP.IODNC_MB_TOP.figdb ## -## Created on Mon Oct 28 11:08:13 CDT 2013, by jgrell +## Created on Tue Nov 26 11:34:19 CST 2013, by jgrell #################################################################### ## -- CHANGE HISTORY: ## -------------------------------------------------------------------------------- ## -- VersionID: |Author: | Date: | Comment: ## -- -----------|---------|--------|------------------------------------------------- + ## -- jgr13112600| jgr |11-26-13| CYC rx_ds_timeout_sel setting changed to 111 ## -- jgr13102800| jgr |10-28-13| zcal address fix and rx_ds_timeout_sel change (110 -> 111) ## -- jgr13082100| jgr |08-21-13| Added tx_zcal inits so they can be removed from scan ## -- jfg13072400| jfg |07-24-13| HW253558: change pgooddly to MAX from lab feedback @@ -319,8 +320,7 @@ scom 0x800898000201043F { bits, scom_data, expr; rx_ds_bl_timeout_sel, 0b101 , def_IS_HW; rx_ds_bl_timeout_sel, 0b001 , def_IS_VBU; - rx_ds_timeout_sel, 0b111 , def_IS_HW; - rx_ds_timeout_sel, 0b010 , def_IS_VBU; + rx_ds_timeout_sel, 0b111, any; rx_sls_timeout_sel, 0b110, any; rx_wt_timeout_sel, 0b111 , def_IS_HW; rx_wt_timeout_sel, 0b011 , def_IS_VBU; diff --git a/src/usr/hwpf/hwp/initfiles/p8.abus.custom.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.abus.custom.scom.initfile index 09415992d..45a3886d2 100644 --- a/src/usr/hwpf/hwp/initfiles/p8.abus.custom.scom.initfile +++ b/src/usr/hwpf/hwp/initfiles/p8.abus.custom.scom.initfile @@ -1,15 +1,17 @@ -#-- $Id: p8.abus.custom.scom.initfile,v 1.9 2013/10/28 21:59:13 jgrell Exp $ +#-- $Id: p8.abus.custom.scom.initfile,v 1.12 2013/12/04 17:25:28 jgrell Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- -#-- 1.9 |jgrell |10/28/13|Re-enabled recal bits for DD2+ hw -#-- 1.8 |jgrell |09/24/13|Changed "1" expression to "any" -#-- 1.6 |jgrell |09/17/13|Added DD2 specific inits -#-- 1.4 |jgrell |06/18/13|Added Venice specific PRBS tap IDs due to common initfile -#-- 1.3 |thomsen |04/30/13|Added TGT1. to ATTR_CHIP_EC* attribute instances to reference a chip target rather than a chiplet target -#-- 1.2 |jgrell |04/18/13|Added EC controled Recal enables -#-- 1.1 |thomsen |01/29/13|Created initial version +#-- 1.12|jgrell |12/03/13| Set rx_eo_ddc_timeout_sel to 110 for DD2 +#-- 1.11|jgrell |10/29/13| Changed rx_ds_timeout_sel setting to 111 +#-- 1.9 |jgrell |10/28/13| Re-enabled recal bits for DD2+ hw +#-- 1.8 |jgrell |09/24/13| Changed "1" expression to "any" +#-- 1.6 |jgrell |09/17/13| Added DD2 specific inits +#-- 1.4 |jgrell |06/18/13| Added Venice specific PRBS tap IDs due to common initfile +#-- 1.3 |thomsen |04/30/13| Added TGT1. to ATTR_CHIP_EC* attribute instances to reference a chip target rather than a chiplet target +#-- 1.2 |jgrell |04/18/13| Added EC controled Recal enables +#-- 1.1 |thomsen |01/29/13| Created initial version #-- --------|--------|--------|-------------------------------------------------- #-------------------------------------------------------------------------------- # End of revision history @@ -471,7 +473,7 @@ scom 0x8004340B08010C3F { #--*********************************************************************************** #------------------------------------------------------------------------------------- -#-- DD2 Murano +#-- DD2+ Murano & Venice #------------------------------------------------------------------------------------- #--*********************************************************************************** @@ -481,9 +483,15 @@ scom 0x800.0b(rx_timeout_sel_pg)(rx_grp0)(lane_na).0x(abus_gcr_addr) { rx_ds_bl_timeout_sel_dd2, 0b101, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; rx_cl_timeout_sel_dd2, 0b010, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; rx_wt_timeout_sel_dd2, 0b111, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; - rx_ds_timeout_sel_dd2, 0b110, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; + rx_ds_timeout_sel_dd2, 0b111, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; } +scom 0x800.0b(rx_timeout_sel1_pg)(rx_grp0)(lane_na).0x(abus_gcr_addr) { + bits, scom_data, expr; + rx_eo_ddc_timeout_sel, 0b110, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; +} + + ############################################################################################ # END OF FILE ############################################################################################ diff --git a/src/usr/hwpf/hwp/initfiles/p8.abus.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.abus.scom.initfile index ba63ee232..e4d142853 100644 --- a/src/usr/hwpf/hwp/initfiles/p8.abus.scom.initfile +++ b/src/usr/hwpf/hwp/initfiles/p8.abus.scom.initfile @@ -1,4 +1,4 @@ -#-- $Id: p8.abus.scom.initfile,v 1.17 2013/10/28 21:59:13 jgrell Exp $ +#-- $Id: p8.abus.scom.initfile,v 1.18 2013/12/04 17:25:20 jgrell Exp $ #################################################################### @@ -7,13 +7,14 @@ ## Based on SETUP_ID_MODE A_BUS_TR_HW ## from ../../logic/mesa_sim/fusion/run/IODUV_ABUS_WRAP.IODUV_ABUS_WRAP.figdb ## -## Created on Mon Oct 28 11:08:02 CDT 2013, by jgrell +## Created on Tue Nov 26 11:34:06 CST 2013, by jgrell #################################################################### ## -- CHANGE HISTORY: ## -------------------------------------------------------------------------------- ## -- VersionID: |Author: | Date: | Comment: ## -- -----------|---------|--------|------------------------------------------------- + ## -- jgr13112600| jgr |11-26-13| CYC rx_ds_timeout_sel setting changed to 111 ## -- jgr13102800| jgr |10-28-13| rx_ds_timeout_sel change (110 -> 111) ## -- jgr13092400| jgr |09-24-13| Fixed tx_zcal inits scom address ## -- jgr13082100| jgr |08-21-13| Added tx_zcal inits so they can be removed from scan @@ -736,16 +737,9 @@ scom 0x8008980008010C3F { rx_ds_bl_timeout_sel, 0b001, def_IS_VBU && def_bus_id1; rx_ds_bl_timeout_sel, 0b101, def_IS_HW && def_bus_id2; rx_ds_bl_timeout_sel, 0b001, def_IS_VBU && def_bus_id2; - rx_ds_timeout_sel, 0b111, def_IS_HW && def_bus_id0; - rx_ds_timeout_sel, 0b111, def_IS_HW && def_bus_id1; - rx_ds_timeout_sel, 0b010, def_IS_VBU && def_bus_id1; - rx_ds_timeout_sel, 0b111, def_IS_HW && def_bus_id2; - rx_ds_timeout_sel, 0b010, def_IS_VBU && def_bus_id2; - rx_ds_timeout_sel, 0b010, def_IS_VBU && def_bus_id0; - rx_ds_timeout_sel, 0b111, def_IS_HW && def_bus_id1; - rx_ds_timeout_sel, 0b010, def_IS_VBU && def_bus_id1; - rx_ds_timeout_sel, 0b111, def_IS_HW && def_bus_id2; - rx_ds_timeout_sel, 0b010, def_IS_VBU && def_bus_id2; + rx_ds_timeout_sel, 0b111, def_bus_id0; + rx_ds_timeout_sel, 0b111, def_bus_id1; + rx_ds_timeout_sel, 0b111, def_bus_id2; rx_sls_timeout_sel, 0b110, def_bus_id0; rx_sls_timeout_sel, 0b110, def_bus_id1; rx_sls_timeout_sel, 0b110, def_bus_id2; diff --git a/src/usr/hwpf/hwp/initfiles/p8.dmi.custom.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.dmi.custom.scom.initfile index 78f620bdb..a45893c13 100644 --- a/src/usr/hwpf/hwp/initfiles/p8.dmi.custom.scom.initfile +++ b/src/usr/hwpf/hwp/initfiles/p8.dmi.custom.scom.initfile @@ -1,8 +1,10 @@ -#-- $Id: p8.dmi.custom.scom.initfile,v 1.18 2013/10/28 21:59:13 jgrell Exp $ +#-- $Id: p8.dmi.custom.scom.initfile,v 1.20 2013/12/04 17:25:28 jgrell Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- +#-- 1.20|jgrell |12/03/13|Set rx_eo_ddc_timeout_sel to 110 for DD2 +#-- 1.19|jgrell |10/29/13|Changed rx_ds_timeout_sel setting to 111 #-- 1.18|jgrell |10/28/13|Re-enabled recal bits for DD2+ hw #-- 1.17|jgrell |09/24/13|Changed "1" expression to "any" #-- 1.15|jgrell |09/17/13|Added DD2 specific inits @@ -304,7 +306,7 @@ rx_amp_gain, 0b1001, ATTR_DMI_DFE_OVERRIDE==1; #--*********************************************************************************** #------------------------------------------------------------------------------------- -#-- DD2 Murano +#-- DD2+ Murano & Venice #------------------------------------------------------------------------------------- #--*********************************************************************************** @@ -314,7 +316,12 @@ scom 0x800.0b(rx_timeout_sel_pg)(rx_grp3)(lane_na).0x(dmi0_gcr_addr) { rx_ds_bl_timeout_sel_dd2, 0b101, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; rx_cl_timeout_sel_dd2, 0b010, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; rx_wt_timeout_sel_dd2, 0b111, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; - rx_ds_timeout_sel_dd2, 0b110, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; + rx_ds_timeout_sel_dd2, 0b111, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; +} + +scom 0x800.0b(rx_timeout_sel1_pg)(rx_grp3)(lane_na).0x(dmi0_gcr_addr) { + bits, scom_data, expr; + rx_eo_ddc_timeout_sel, 0b110, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; } ############################################################################################ diff --git a/src/usr/hwpf/hwp/initfiles/p8.dmi.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.dmi.scom.initfile index 70d7f9bd7..238fc719b 100644 --- a/src/usr/hwpf/hwp/initfiles/p8.dmi.scom.initfile +++ b/src/usr/hwpf/hwp/initfiles/p8.dmi.scom.initfile @@ -1,4 +1,4 @@ -#-- $Id: p8.dmi.scom.initfile,v 1.24 2013/10/28 21:59:13 jgrell Exp $ +#-- $Id: p8.dmi.scom.initfile,v 1.25 2013/12/04 17:25:28 jgrell Exp $ #################################################################### @@ -7,13 +7,14 @@ ## Based on SETUP_ID_MODE DMI_BUS_TR_HW ## from ../../logic/mesa_sim/fusion/run/IODPV_MC_WRAP.IODPV_MC_WRAP.figdb ## -## Created on Mon Oct 28 11:07:50 CDT 2013, by jgrell +## Created on Tue Nov 26 11:33:54 CST 2013, by jgrell #################################################################### ## -- CHANGE HISTORY: ## -------------------------------------------------------------------------------- ## -- VersionID: |Author: | Date: | Comment: ## -- -----------|---------|--------|------------------------------------------------- + ## -- jgr13112600| jgr |11-26-13| CYC rx_ds_timeout_sel setting changed to 111 ## -- jgr13102800| jgr |10-28-13| rx_ds_timeout_sel change (110 -> 111) ## -- jgr13082100| jgr |08-21-13| Added tx_zcal inits so they can be removed from scan ## -- jfg13072400| jfg |07-24-13| HW253558: change pgooddly to MAX from lab feedback @@ -70,6 +71,11 @@ include edi.io.define +#define def_bus_id3 = ((ATTR_CHIP_UNIT_POS == 3) || (ATTR_CHIP_UNIT_POS == 7)); +#define def_bus_id2 = ((ATTR_CHIP_UNIT_POS == 2) || (ATTR_CHIP_UNIT_POS == 6)); +#define def_bus_id1 = ((ATTR_CHIP_UNIT_POS == 1) || (ATTR_CHIP_UNIT_POS == 5)); +#define def_bus_id0 = ((ATTR_CHIP_UNIT_POS == 0) || (ATTR_CHIP_UNIT_POS == 4)); + define def_bus_id3 = ((ATTR_CHIP_UNIT_POS == 0) || (ATTR_CHIP_UNIT_POS == 4)); define def_bus_id2 = ((ATTR_CHIP_UNIT_POS == 1) || (ATTR_CHIP_UNIT_POS == 5)); define def_bus_id1 = ((ATTR_CHIP_UNIT_POS == 3) || (ATTR_CHIP_UNIT_POS == 7)); @@ -939,20 +945,10 @@ scom 0x8008986002011A3F { rx_ds_bl_timeout_sel, 0b001, def_IS_VBU && def_bus_id1; rx_ds_bl_timeout_sel, 0b101, def_IS_HW && def_bus_id2; rx_ds_bl_timeout_sel, 0b001, def_IS_VBU && def_bus_id2; - rx_ds_timeout_sel, 0b111, def_IS_HW && def_bus_id3; - rx_ds_timeout_sel, 0b111, def_IS_HW && def_bus_id0; - rx_ds_timeout_sel, 0b010, def_IS_VBU && def_bus_id0; - rx_ds_timeout_sel, 0b111, def_IS_HW && def_bus_id1; - rx_ds_timeout_sel, 0b010, def_IS_VBU && def_bus_id1; - rx_ds_timeout_sel, 0b111, def_IS_HW && def_bus_id2; - rx_ds_timeout_sel, 0b010, def_IS_VBU && def_bus_id2; - rx_ds_timeout_sel, 0b010, def_IS_VBU && def_bus_id3; - rx_ds_timeout_sel, 0b111, def_IS_HW && def_bus_id0; - rx_ds_timeout_sel, 0b010, def_IS_VBU && def_bus_id0; - rx_ds_timeout_sel, 0b111, def_IS_HW && def_bus_id1; - rx_ds_timeout_sel, 0b010, def_IS_VBU && def_bus_id1; - rx_ds_timeout_sel, 0b111, def_IS_HW && def_bus_id2; - rx_ds_timeout_sel, 0b010, def_IS_VBU && def_bus_id2; + rx_ds_timeout_sel, 0b111, def_bus_id3; + rx_ds_timeout_sel, 0b111, def_bus_id0; + rx_ds_timeout_sel, 0b111, def_bus_id1; + rx_ds_timeout_sel, 0b111, def_bus_id2; rx_sls_timeout_sel, 0b110, def_bus_id3; rx_sls_timeout_sel, 0b110, def_bus_id0; rx_sls_timeout_sel, 0b110, def_bus_id1; diff --git a/src/usr/hwpf/hwp/initfiles/p8.xbus.custom.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.xbus.custom.scom.initfile index 2bf3dda72..a8efed802 100644 --- a/src/usr/hwpf/hwp/initfiles/p8.xbus.custom.scom.initfile +++ b/src/usr/hwpf/hwp/initfiles/p8.xbus.custom.scom.initfile @@ -1,8 +1,9 @@ -#-- $Id: p8.xbus.custom.scom.initfile,v 1.6 2013/09/17 22:28:51 jgrell Exp $ +#-- $Id: p8.xbus.custom.scom.initfile,v 1.7 2013/12/04 17:25:29 jgrell Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- +#-- 1.7 |jgrell |12/03/13|Set rx_sls_extend_sel to 001 for DD2 #-- 1.5 |jgrell |09/17/13|Added DD2 specific inits #-- 1.3 |jgrell |03/14/13|Added temporary masking of the GCR Buffer Parity Checkers in the GCR Master until the source of the error can be found. This ungates the lab. #-- 1.2 |thomsen |02/13/13|Cleaned up and Added Commented-out Lane Power Ups @@ -80,7 +81,7 @@ define def_all_lanes=11111; #--*********************************************************************************** #------------------------------------------------------------------------------------- -#-- DD2 Murano +#-- DD2+ Murano & Venice #------------------------------------------------------------------------------------- #--*********************************************************************************** @@ -117,6 +118,23 @@ scom 0x800.0b(rx_timeout_sel_pg)(rx_grp3)(lane_na).0x(xbus0_gcr_addr) { rx_ds_timeout_sel_dd2, 0b110, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; } +scom 0x800.0b(rx_spare_mode_pg)(rx_grp0)(lane_na).0x(xbus0_gcr_addr) { + bits, scom_data, expr; + rx_sls_extend_sel, 0b001, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; +} +scom 0x800.0b(rx_spare_mode_pg)(rx_grp1)(lane_na).0x(xbus0_gcr_addr) { + bits, scom_data, expr; + rx_sls_extend_sel, 0b001, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; +} +scom 0x800.0b(rx_spare_mode_pg)(rx_grp2)(lane_na).0x(xbus0_gcr_addr) { + bits, scom_data, expr; + rx_sls_extend_sel, 0b001, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; +} +scom 0x800.0b(rx_spare_mode_pg)(rx_grp3)(lane_na).0x(xbus0_gcr_addr) { + bits, scom_data, expr; + rx_sls_extend_sel, 0b001, ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG==0; +} + ############################################################################################ # END OF FILE ############################################################################################ |
