SW302259: INITPROC: FSP&Hostboot - hardware procedure changes from the

Change-Id: Idc00a24ad24505b820084690fdbca73d271544b1
CQ:SW302259
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/16935
Reviewed-by: PRACHI GUPTA <pragupta@us.ibm.com>
Tested-by: PRACHI GUPTA <pragupta@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/16951
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

10 files changed, 206 insertions, 13 deletions

diff --git a/src/usr/hwpf/hwp/mc_config/mc_config.C b/src/usr/hwpf/hwp/mc_config/mc_config.C
index a509047bb..e230b88b7 100644
--- a/src/usr/hwpf/hwp/mc_config/mc_config.C
+++ b/src/usr/hwpf/hwp/mc_config/mc_config.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER HostBoot Project                                             */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
+/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
 /* [+] Google Inc.                                                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.C
index 044d00488..525ef5d9a 100644
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.C
+++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.C
@@ -22,7 +22,7 @@
 /* permissions and limitations under the License.                         */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_eff_config.C,v 1.50 2014/12/03 19:55:07 jdsloat Exp $
+// $Id: mss_eff_config.C,v 1.51 2015/03/13 19:13:44 asaetow Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/
 //          centaur/working/procedures/ipl/fapi/mss_eff_config.C,v $
 //------------------------------------------------------------------------------
@@ -45,7 +45,8 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
-//   1.50  | asaetow  |03-DEC-14| Removed string data types that are not supported.
+//   1.51  | asaetow  |13-MAR-15| Changed DRAM_AL to be CL-2 in 2N/2T mode and CL-1 in 1N/1T mode.
+//   1.50  | jdsloat  |03-DEC-14| Removed string data types that are not supported.
 //   1.49  | asaetow  |01-DEC-14| Added RDIMM SPD/VPD support for ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15 to take in SPD bits69:76 thru new VPD attribute ATTR_VPD_DIMM_RCD_CNTL_WORD_0_15.
 //         |          |         | Added ATTR_VPD_DIMM_RCD_IBT and ATTR_VPD_DIMM_RCD_OUTPUT_TIMING merge, per meeting with Ken and Dan P.
 //         |          |         | NOTE: DO NOT pickup w/o getMBvpdTermData.C v1.18 or newer from Dan.C and Corey.
@@ -371,7 +372,7 @@ struct mss_eff_config_atts
     uint8_t eff_dimm_size[PORT_SIZE][DIMM_SIZE];
     uint8_t eff_dimm_type;
     uint8_t eff_custom_dimm;
-    uint8_t eff_dram_al; // Always use AL = CL - 1.
+    uint8_t eff_dram_al; // Based on 2N/2T or 1N/1T enable
     uint8_t eff_dram_asr;
     uint8_t eff_dram_bl;
     uint8_t eff_dram_banks;
@@ -1225,8 +1226,15 @@ fapi::ReturnCode mss_eff_config_setup_eff_atts(
     fapi::ReturnCode rc;
     const fapi::Target& TARGET_MBA = i_target_mba;
 
+    uint8_t mss_dram_2n_mode_enable;
+    rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_2N_MODE_ENABLED, &i_target_mba, mss_dram_2n_mode_enable);
+    if(rc) return rc;
     // set select atts members to non-zero
-    p_o_atts->eff_dram_al = fapi::ENUM_ATTR_EFF_DRAM_AL_CL_MINUS_1; // Always use AL = CL - 1.
+    if ( mss_dram_2n_mode_enable == fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_TRUE ) {
+       p_o_atts->eff_dram_al = fapi::ENUM_ATTR_EFF_DRAM_AL_CL_MINUS_2; // Always use AL = CL - 2 for 2N/2T mode
+    } else {
+       p_o_atts->eff_dram_al = fapi::ENUM_ATTR_EFF_DRAM_AL_CL_MINUS_1; // Always use AL = CL - 1 for 1N/1T mode
+    }
 
     // Transfer powerdown request from system attr to DRAM attr
     uint8_t mss_power_control_requested;
diff --git a/src/usr/hwpf/hwp/memory_attributes.xml b/src/usr/hwpf/hwp/memory_attributes.xml
index 270b155af..a78cfdf34 100644
--- a/src/usr/hwpf/hwp/memory_attributes.xml
+++ b/src/usr/hwpf/hwp/memory_attributes.xml
@@ -23,7 +23,7 @@
 <!--                                                                        -->
 <!-- IBM_PROLOG_END_TAG                                                     -->
 <attributes>
-<!-- $Id: memory_attributes.xml,v 1.139 2014/11/18 17:35:29 jdsloat Exp $ -->
+<!-- $Id: memory_attributes.xml,v 1.145 2015/04/06 21:03:33 jdsloat Exp $ -->
 <!-- DO NOT EDIT THIS FILE DIRECTLY PLEASE UPDATE THE ODS FILE AND FOLLOW THE INSTRUCTION TAB -->
 <!-- PLEASE SEE MARK BELLOWS (BELLOWS.IBM.COM) OR OTHERS ON MEMORY TEAM FOR HELP -->
 <!-- *********************************************************************** -->
@@ -2262,7 +2262,7 @@ Firmware shares some code with the processor, so the attribute is named so they
     <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
     <description>DQS Swizzle type is set by the platform to describe what kind of DQS connection is being used for register acceses. Type 0 is normal, type 1 is for systems with wiring like glacier 1, type 2 is for Pallmeto.  Additional types maybe defined if new boards have even different DQS swizzle features</description>
     <valueType>uint8</valueType>
-    <enum>NORMAL_TYPE_0 = 0, GLACIER_TYPE_1 = 1, PALMETTO_TYPE_2 = 2</enum>
+    <enum>NORMAL_TYPE_0 = 0, GLACIER_TYPE_1 = 1, ISDIMM_TYPE_2 = 2</enum>
     <platInit/>
     <odmVisable/>
     <odmChangeable/>
@@ -2771,6 +2771,16 @@ Will be set at an MBA level with one policy to be used</description>
 </attribute>
 
 <attribute>
+    <id>ATTR_MSS_VOLT_COMPLIANT_DIMMS</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>List of Voltages that are compliant with the system. DIMMs that do not have voltages listed in their SPD as supported are errored out. Procedure defined is currently 1.2V and 1.35V only.</description>
+    <valueType>uint8</valueType>
+    <enum> PROCEDURE_DEFINED = 0x00, ALL_VOLTAGES = 0x01</enum>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
     <id>ATTR_MRW_POWER_CONTROL_REQUESTED</id>
     <targetType>TARGET_TYPE_SYSTEM</targetType>
     <description>Capable power control settings. In MRW.</description>
@@ -2888,13 +2898,51 @@ Will be set at an MBA level with one policy to be used</description>
 
 <attribute>
     <id>ATTR_MRW_MEM_SENSOR_CACHE_ADDR_MAP</id>
-    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
     <description>Machine Readable Workbook value detailing the wiring of the 8 dimm temperature sensors for non custom dimms, in DIMM A0,A1,B0,B1,C0,C1,D0,D1 order. One nibble per sensor where bit0 (MSB) is the i2c bus the sensor is attached to (0 for master, 1 for spare) and bits 1:3 are for A2,A1,A0 of the sensor i2c address (where A2 is MSB)</description>
     <valueType>uint32</valueType>
     <platInit/>
     <odmVisable/>
 </attribute>
 
+<attribute>
+    <id>ATTR_MSS_VMEM_REGULATOR_MAX_DIMM_COUNT</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Maximum number of installed DIMMs per VMEM regulator for all VMEM regulators in the system.</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_MRW_VMEM_REGULATOR_POWER_LIMIT_PER_DIMM_ADJ_ENABLE</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Machine Readable Workbook enablement of the HWP code to adjust the VMEM regulator power limit based on number of installed DIMMs.</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <enum>FALSE = 0, TRUE = 1</enum>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_MRW_MAX_NUMBER_DIMMS_POSSIBLE_PER_VMEM_REGULATOR</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Machine Readable Workbook value for the maximum possible number of dimms that can be installed under any of the VMEM regulators.</description>
+    <valueType>uint8</valueType>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Machine Readable Workbook VMEM regulator power limit per CDIMM assuming a full configuration. Units in cW.</description>
+    <valueType>uint32</valueType>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
 <!-- DO NOT EDIT THIS FILE DIRECTLY PLEASE UPDATE THE ODS FILE AND FOLLOW THE INSTRUCTION TAB -->
 <!-- PLEASE SEE MARK BELLOWS (BELLOWS.IBM.COM) OR OTHERS ON MEMORY TEAM FOR HELP -->
 </attributes>
diff --git a/src/usr/targeting/common/genHwsvMrwXml.pl b/src/usr/targeting/common/genHwsvMrwXml.pl
index 9373de6d4..e07d21d4d 100755
--- a/src/usr/targeting/common/genHwsvMrwXml.pl
+++ b/src/usr/targeting/common/genHwsvMrwXml.pl
@@ -224,9 +224,13 @@ push @systemAttr,
         $reqPol->{'cdimm_master_i2c_temp_sensor_enable'},
     "MRW_CDIMM_SPARE_I2C_TEMP_SENSOR_ENABLE",
         $reqPol->{'cdimm_spare_i2c_temp_sensor_enable'},
-    "MRW_MEM_SENSOR_CACHE_ADDR_MAP",
-        $reqPol->{'mem_sensor_cache_addr_map'},
-     "PM_SYSTEM_IVRMS_ENABLED", $reqPol->{'pm_system_ivrms_enabled'},
+    "MRW_VMEM_REGULATOR_POWER_LIMIT_PER_DIMM_ADJ_ENABLE",
+        $reqPol->{'vmem_regulator_memory_power_limit_per_dimm_adjustment_enable'},
+    "MRW_MAX_NUMBER_DIMMS_POSSIBLE_PER_VMEM_REGULATOR",
+        $reqPol->{'max_number_dimms_possible_per_vmem_regulator'},
+    "MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM",
+        $reqPol->{'vmem_regulator_memory_power_limit_per_dimm'},
+    "PM_SYSTEM_IVRMS_ENABLED", $reqPol->{'pm_system_ivrms_enabled'},
     "PM_SYSTEM_IVRM_VPD_MIN_LEVEL", $reqPol->{'pm_system_ivrm_vpd_min_level'},
     "MRW_ENHANCED_GROUPING_NO_MIRRORING", $reqPol->{'mcs_enhanced_grouping_no_mirroring'},
     "MRW_STRICT_MBA_PLUG_RULE_CHECKING", $reqPol->{'strict_mba_plug_rule_checking'},
diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml
index dab406c1f..d1cce5b86 100644
--- a/src/usr/targeting/common/xmltohb/attribute_types.xml
+++ b/src/usr/targeting/common/xmltohb/attribute_types.xml
@@ -14412,6 +14412,26 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript
 </attribute>
 
 <attribute>
+    <id>MSS_VOLT_COMPLIANT_DIMMS</id>
+    <description>
+        Compliant Voltages. Created to call out non-compliant dimms
+        if they exist in the system.
+    </description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_VOLT_COMPLIANT_DIMMS</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
     <id>MSS_VDDR_OVERIDE_SPD</id>
     <description>
         DIMM SPD voltage override for VDDR voltage calculations.
@@ -15467,4 +15487,77 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript
 
 <!-- === Manufacturing threshold Attributes of PRD === -->
 
+<attribute>
+    <id>MSS_VMEM_REGULATOR_MAX_DIMM_COUNT</id>
+    <description>Maximum number of installed DIMMs per VMEM regulator for all
+    VMEM regulators in the system.
+    </description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_VMEM_REGULATOR_MAX_DIMM_COUNT</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MRW_VMEM_REGULATOR_POWER_LIMIT_PER_DIMM_ADJ_ENABLE</id>
+    <description>Machine Readable Workbook enablement of the HWP code to adjust 
+    the VMEM regulator power limit based on number of installed DIMMs.
+    </description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MRW_VMEM_REGULATOR_POWER_LIMIT_PER_DIMM_ADJ_ENABLE</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MRW_MAX_NUMBER_DIMMS_POSSIBLE_PER_VMEM_REGULATOR</id>
+    <description>Machine Readable Workbook value for the maximum possible number
+    of dimms that can be installed under any of the VMEM regulators.
+    </description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MRW_MAX_NUMBER_DIMMS_POSSIBLE_PER_VMEM_REGULATOR</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM</id>
+    <description>Machine Readable Workbook VMEM regulator power limit per CDIMM 
+    assuming a full configuration. Units in cW.
+    </description>
+    <simpleType>
+        <uint32_t>
+            <default>0</default>
+        </uint32_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
 </attributes>
diff --git a/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml b/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml
index f7551fc7d..07967cce0 100644
--- a/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml
+++ b/src/usr/targeting/common/xmltohb/simics_MURANO.system.xml
@@ -249,6 +249,18 @@
         <id>REDUNDANT_CLOCKS</id>
         <default>0x00</default>
     </attribute>
+    <attribute>
+        <id>MRW_VMEM_REGULATOR_POWER_LIMIT_PER_DIMM_ADJ_ENABLE</id>
+        <default>1</default>
+    </attribute>
+    <attribute>
+        <id>MRW_MAX_NUMBER_DIMMS_POSSIBLE_PER_VMEM_REGULATOR</id>
+        <default>3</default>
+    </attribute>
+    <attribute>
+        <id>MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM</id>
+        <default>2532</default>
+    </attribute>
     <!-- End System Attributes from MRW -->
     <attribute>
         <id>ISTEP_MODE</id>
diff --git a/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml b/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml
index c25236472..73714c0ac 100644
--- a/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml
+++ b/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml
@@ -253,6 +253,14 @@
         <id>REDUNDANT_CLOCKS</id>
         <default>0x01</default>
     </attribute>
+    <attribute>
+        <id>MRW_MAX_NUMBER_DIMMS_POSSIBLE_PER_VMEM_REGULATOR</id>
+        <default>8</default>
+    </attribute>
+    <attribute>
+        <id>MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM</id>
+        <default>5500</default>
+    </attribute>
     <!-- End System Attributes from MRW -->
     <attribute>
         <id>ISTEP_MODE</id>
diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml
index aabb107f3..5503e3ce1 100644
--- a/src/usr/targeting/common/xmltohb/target_types.xml
+++ b/src/usr/targeting/common/xmltohb/target_types.xml
@@ -129,8 +129,10 @@
     <attribute><id>MRW_POWER_CONTROL_REQUESTED</id></attribute>
     <attribute><id>MRW_DDR3_VDDR_MAX_LIMIT</id></attribute>
     <attribute><id>MRW_DDR4_VDDR_MAX_LIMIT</id></attribute>
-    <attribute><id>MRW_MEM_SENSOR_CACHE_ADDR_MAP</id></attribute>
-
+    <attribute><id>MSS_VMEM_REGULATOR_MAX_DIMM_COUNT</id></attribute>
+    <attribute><id>MRW_VMEM_REGULATOR_POWER_LIMIT_PER_DIMM_ADJ_ENABLE</id></attribute>
+    <attribute><id>MRW_MAX_NUMBER_DIMMS_POSSIBLE_PER_VMEM_REGULATOR</id></attribute>
+    <attribute><id>MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM</id></attribute>
     <!-- Start pm_plat_attributes.xml -->
     <attribute><id>PM_EXTERNAL_VRM_STEPSIZE</id></attribute>
     <attribute><id>PM_EXTERNAL_VRM_STEPDELAY</id></attribute>
@@ -274,6 +276,7 @@
     <attribute><id>MSS_VOLT_DDR4_VDDR_SLOPE</id></attribute>
     <attribute><id>MSS_VOLT_DDR4_VDDR_INTERCEPT</id></attribute>
     <attribute><id>MSS_VDDR_OVERIDE_SPD</id></attribute>
+    <attribute><id>MSS_VOLT_COMPLIANT_DIMMS</id></attribute>
     <attribute><id>PM_PFET_WORKAROUND_RUN_FLAG</id></attribute>
     <attribute><id>PM_SLEEP_ENABLE</id></attribute>
     <attribute><id>MSS_DRAMINIT_RESET_DISABLE</id></attribute>
@@ -1433,6 +1436,7 @@
     <attribute><id>MSS_FREQ</id></attribute>
     <attribute><id>MSS_LAB_OVERRIDE_FOR_MEM_PLL</id></attribute>
     <attribute><id>ECID</id></attribute>
+    <attribute><id>MRW_MEM_SENSOR_CACHE_ADDR_MAP</id></attribute>
     <attribute>
         <!-- Centaur memory buffer chips do not have SCOM accessible FSI GP regs -->
         <id>FSI_GP_REG_SCOM_ACCESS</id>
diff --git a/src/usr/targeting/common/xmltohb/vbu_MURANO.system.xml b/src/usr/targeting/common/xmltohb/vbu_MURANO.system.xml
index 6fe6c9532..d1f16bfb7 100644
--- a/src/usr/targeting/common/xmltohb/vbu_MURANO.system.xml
+++ b/src/usr/targeting/common/xmltohb/vbu_MURANO.system.xml
@@ -212,6 +212,14 @@
         <id>REDUNDANT_CLOCKS</id>
         <default>0x00</default>
     </attribute>
+    <attribute>
+        <id>MRW_MAX_NUMBER_DIMMS_POSSIBLE_PER_VMEM_REGULATOR</id>
+        <default>3</default>
+    </attribute>
+    <attribute>
+        <id>MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM</id>
+        <default>2532</default>
+    </attribute>
     <!-- End System Attributes from MRW -->
     <attribute>
         <id>ISTEP_MODE</id>
diff --git a/src/usr/targeting/common/xmltohb/vbu_VENICE.system.xml b/src/usr/targeting/common/xmltohb/vbu_VENICE.system.xml
index 0f507e5b6..9da901e28 100644
--- a/src/usr/targeting/common/xmltohb/vbu_VENICE.system.xml
+++ b/src/usr/targeting/common/xmltohb/vbu_VENICE.system.xml
@@ -211,6 +211,14 @@
         <id>REDUNDANT_CLOCKS</id>
         <default>0x01</default>
     </attribute>
+    <attribute>
+        <id>MRW_MAX_NUMBER_DIMMS_POSSIBLE_PER_VMEM_REGULATOR</id>
+        <default>8</default>
+    </attribute>
+    <attribute>
+        <id>MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM</id>
+        <default>5500</default>
+    </attribute>
     <!-- End System Attributes from MRW -->
     <attribute>
         <id>BOOT_FREQ_MHZ</id>