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authorRick Mata Jr <ricmata@us.ibm.com>2017-01-06 15:27:26 -0600
committerChristian R. Geddes <crgeddes@us.ibm.com>2017-01-14 15:28:49 -0500
commitb4380fca211feeefe4733b8e70418327dc32c30c (patch)
tree40f07ef0dad6035ddb62e427e79e88bf27211452 /src/usr
parent0e390962ea4e502d4fe828436e2913a5329cd29a (diff)
downloadtalos-hostboot-b4380fca211feeefe4733b8e70418327dc32c30c.tar.gz
talos-hostboot-b4380fca211feeefe4733b8e70418327dc32c30c.zip
p9_pcie_scominit procedure update to addresss PHY issues
Change-Id: I4304e754056a741b250ea2861cd9afef529a50b0 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34521 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> CMVC-Coreq: 1014186 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34523 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Diffstat (limited to 'src/usr')
-rw-r--r--src/usr/targeting/common/xmltohb/attribute_types.xml149
-rwxr-xr-xsrc/usr/targeting/common/xmltohb/target_types.xml6
2 files changed, 155 insertions, 0 deletions
diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml
index 492c0292b..bd1fbfe03 100644
--- a/src/usr/targeting/common/xmltohb/attribute_types.xml
+++ b/src/usr/targeting/common/xmltohb/attribute_types.xml
@@ -21752,6 +21752,155 @@ Measured in GB</description>
</attribute>
<attribute>
+ <id>PROC_PCIE_PCS_RX_PK_INIT</id>
+ <!-- TARGET_TYPE_PEC -->
+ <description>
+ PCS rx vga peak init value
+ creator: platform
+ consumer: p9_pcie_scominit
+ firmware notes:
+ The value of rx vga peak init for PCS.
+ Array index: Configuration number
+ index 0~3 for CONFIG0~3
+ lane 0~15 for each PCIE Lane
+ </description>
+ <simpleType>
+ <uint8_t>
+ <default>0</default>
+ </uint8_t>
+ <array>4,16</array>
+ </simpleType>
+ <persistency>non-volatile</persistency>
+ <readable/>
+ <hwpfToHbAttrMap>
+ <id>ATTR_PROC_PCIE_PCS_RX_PK_INIT</id>
+ <macro>DIRECT</macro>
+ </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+ <id>PROC_PCIE_PCS_RX_INIT_GAIN</id>
+ <!-- TARGET_TYPE_PEC -->
+ <description>
+ PCS rx vga gain init value
+ creator: platform
+ consumer: p9_pcie_scominit
+ firmware notes:
+ The value of rx vga gain init for PCS.
+ Array index: Configuration number
+ index 0~3 for CONFIG0~3
+ lane 0~15 for each PCIE Lane
+ </description>
+ <simpleType>
+ <uint8_t>
+ <default>0</default>
+ </uint8_t>
+ <array>4,16</array>
+ </simpleType>
+ <persistency>non-volatile</persistency>
+ <readable/>
+ <hwpfToHbAttrMap>
+ <id>ATTR_PROC_PCIE_PCS_RX_INIT_GAIN</id>
+ <macro>DIRECT</macro>
+ </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+ <id>PROC_PCIE_PCS_RX_SIGDET_LVL</id>
+ <!-- TARGET_TYPE_PEC -->
+ <description>
+ PCS rx sigdet lvl value
+ creator: platform
+ consumer: p9_pcie_scominit
+ firmware notes:
+ The value of rx sigdet lvl for PCS.
+ Array index: Configuration number
+ index 0~3 for CONFIG0~3
+ </description>
+ <simpleType>
+ <uint8_t>
+ <default>0x0B</default>
+ </uint8_t>
+ <array>4</array>
+ </simpleType>
+ <persistency>non-volatile</persistency>
+ <readable/>
+ <hwpfToHbAttrMap>
+ <id>ATTR_PROC_PCIE_PCS_RX_SIGDET_LVL</id>
+ <macro>DIRECT</macro>
+ </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+ <id>PROC_PCIE_PCS_RX_ROT_EXTEL</id>
+ <!-- TARGET_TYPE_PEC -->
+ <description>
+ Value of PCS RX ROT extel latch
+ creator: platform
+ consumer: p9_pcie_scominit
+ firmware notes:
+ 0 for internal (default)
+ 1 for external (freezes phase rotators)
+ </description>
+ <simpleType>
+ <uint8_t>
+ <default>0</default>
+ </uint8_t>
+ </simpleType>
+ <persistency>non-volatile</persistency>
+ <readable/>
+ <hwpfToHbAttrMap>
+ <id>ATTR_PROC_PCIE_PCS_RX_ROT_EXTEL</id>
+ <macro>DIRECT</macro>
+ </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+ <id>PROC_PCIE_PCS_RX_ROT_RST_FW</id>
+ <!-- TARGET_TYPE_PEC -->
+ <description>
+ Value of PCS RX ROT rstfw latch
+ creator: platform
+ consumer: p9_pcie_scominit
+ firmware notes:
+ 0 normal, flywheel is enabled (default)
+ 1 assert reset to the phase rotator flywheel (disable the flywheel)
+ </description>
+ <simpleType>
+ <uint8_t>
+ <default>0</default>
+ </uint8_t>
+ </simpleType>
+ <persistency>non-volatile</persistency>
+ <readable/>
+ <hwpfToHbAttrMap>
+ <id>ATTR_PROC_PCIE_PCS_RX_ROT_RST_FW</id>
+ <macro>DIRECT</macro>
+ </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+ <id>PROC_PCIE_PCS_RX_DFE_FDDC</id>
+ <!-- TARGET_TYPE_PEC -->
+ <description>
+ Value of PCS rx dfe func fddc control latch
+ creator: platform
+ consumer: p9_pcie_scominit
+ </description>
+ <simpleType>
+ <uint8_t>
+ <default>0</default>
+ </uint8_t>
+ </simpleType>
+ <persistency>non-volatile</persistency>
+ <readable/>
+ <hwpfToHbAttrMap>
+ <id>ATTR_PROC_PCIE_PCS_RX_DFE_FDDC</id>
+ <macro>DIRECT</macro>
+ </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
<id>PROC_PCIE_PCS_RX_LOFF_CONTROL</id>
<!-- TARGET_TYPE_PEC -->
<description>
diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml
index c21631a02..fabeb397d 100755
--- a/src/usr/targeting/common/xmltohb/target_types.xml
+++ b/src/usr/targeting/common/xmltohb/target_types.xml
@@ -1988,6 +1988,12 @@
<attribute><id>PROC_PCIE_IOVALID_ENABLE</id></attribute>
<attribute><id>PROC_PCIE_PCS_RX_CDR_GAIN</id></attribute>
+ <attribute><id>PROC_PCIE_PCS_RX_PK_INIT</id></attribute>
+ <attribute><id>PROC_PCIE_PCS_RX_INIT_GAIN</id></attribute>
+ <attribute><id>PROC_PCIE_PCS_RX_SIGDET_LVL</id></attribute>
+ <attribute><id>PROC_PCIE_PCS_RX_ROT_EXTEL</id></attribute>
+ <attribute><id>PROC_PCIE_PCS_RX_ROT_RST_FW</id></attribute>
+ <attribute><id>PROC_PCIE_PCS_RX_DFE_FDDC</id></attribute>
<attribute><id>PROC_PCIE_PCS_RX_LOFF_CONTROL</id></attribute>
<attribute><id>PROC_PCIE_PCS_RX_VGA_CONTRL_REGISTER3</id></attribute>
<attribute><id>PROC_PCIE_PCS_RX_ROT_CDR_LOOKAHEAD</id></attribute>
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