PON - HW procedures update 01/29/2013

Change-Id: Ifc0de7fa7d76ec2551b0dfb56cc348652677ee05
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/3047
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

43 files changed, 5176 insertions, 1493 deletions

diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.C b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.C
index f108940f5..545e378bb 100644
--- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.C
+++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_build_smp.C,v 1.6 2013/01/21 03:11:23 jmcgill Exp $
+// $Id: proc_build_smp.C,v 1.7 2013/01/28 14:45:45 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp.C,v $
 //------------------------------------------------------------------------------
 // *|
@@ -124,12 +124,12 @@ fapi::ReturnCode proc_build_smp_process_system(
 
         // get core floor frequency attribute
         FAPI_DBG("proc_build_smp_process_system: Querying core floor frequency attribute");
-        rc = FAPI_ATTR_GET(ATTR_FREQ_CORE_FLOOR,
+        rc = FAPI_ATTR_GET(ATTR_BOOT_FREQ_MHZ,
                            NULL,
                            io_smp.freq_core_floor);
         if (!rc.ok())
         {
-            FAPI_ERR("proc_build_smp_process_system: Error from FAPI_ATTR_GET (ATTR_FREQ_CORE_FLOOR");
+            FAPI_ERR("proc_build_smp_process_system: Error from FAPI_ATTR_GET (ATTR_BOOT_FREQ_MHZ");
             break;
         }
 
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/proc_pll_ring_attributes.xml b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/proc_pll_ring_attributes.xml
index 90694d04e..7b0a3f97a 100644
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/proc_pll_ring_attributes.xml
+++ b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/proc_pll_ring_attributes.xml
@@ -43,7 +43,7 @@
       firmware notes:
     </description>
     <valueType>uint8</valueType>
-    <array>192</array>
+    <array>231</array>
     <platInit/>
     <persistRuntime/>
   </attribute>
diff --git a/src/usr/hwpf/hwp/bus_training/io_dccal.C b/src/usr/hwpf/hwp/bus_training/io_dccal.C
index 1c9386710..5e93ce761 100644
--- a/src/usr/hwpf/hwp/bus_training/io_dccal.C
+++ b/src/usr/hwpf/hwp/bus_training/io_dccal.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012                   */
+/* COPYRIGHT International Business Machines Corp. 2012,2013              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: io_dccal.C,v 1.14 2012/12/07 13:43:57 varkeykv Exp $

+// $Id: io_dccal.C,v 1.18 2013/01/26 17:35:09 jaswamin Exp $

 // *!***************************************************************************

 // *! (C) Copyright International Business Machines Corp. 1997, 1998

 // *!           All Rights Reserved -- Property of IBM

@@ -39,8 +39,9 @@
 //------------------------------------------------------------------------------

 // Version:|Author: | Date:  | Comment:

 // --------|--------|--------|--------------------------------------------------

+//   1.18  |jaswamin|01/26/11| Commented out offset cal for X and A bus

 //   1.0   |varkeykv|09/27/11|Initial check in . Have to modify targets once bus target is defined and available.Not tested in any way other than in unit SIM IOTK

-//   1.1   |varkeykv |17/11/11|Code cleanup . Fixed header files. Changed fAPI API 

+//   1.1   |varkeykv |17/11/11|Code cleanup . Fixed header files. Changed fAPI API

 //------------------------------------------------------------------------------

 

 #include <fapi.H>

@@ -94,7 +95,6 @@ uint32_t  BinaryRound(uint32_t val, uint32_t numTruncBits, uint32_t center) {
   return newVal;

 }

 

-

 // Offset cal doesnt do anything in VBU/sim ...

 ReturnCode run_offset_cal(const Target &target,io_interface_t master_interface,uint32_t master_group){

 // Assuming I will receive a target and slave_target from the Invoker. 

@@ -105,12 +105,47 @@ ReturnCode run_offset_cal(const Target &target,io_interface_t master_interface,u
  

     ecmdDataBufferBase set_bits(16);

     ecmdDataBufferBase clear_bits(16);

-     io_interface_t chip_interface=master_interface;//first we run on master chip

+    

+    FAPI_DBG("In the Dccal procedure");

+    io_interface_t chip_interface=master_interface;//first we run on master chip

     uint32_t group=master_group;

     const Target *target_ptr=&target; // Assuming I am allowed to do this . 

- 

-    for(int i=0;i<2;++i){ // master and slave side looper

+

         FAPI_DBG("IO_DCCAL : Starting Offset Calibration on interface %d group %d",chip_interface,group);

+        // read and save rx_pdwn_lite_disable

+        int read_bit=rx_pdwn_lite_disable;

+        rc= GCR_read(*target_ptr,master_interface,rx_mode_pg ,group,0,data_buffer);if (rc) {return(rc);}

+        int rx_pdwn_lite_value=data_buffer.getHalfWord(0) & read_bit;

+        

+        // read and save rx_wt_timeout_sel

+        read_bit=rx_wt_timeout_sel_tap7; //find the 3 bit value of the field. need it to be all 1's to do an &

+        rc= GCR_read(*target_ptr,master_interface,rx_timeout_sel_pg ,group,0,data_buffer);if (rc) {return(rc);}

+        int rx_wt_timeout_value=data_buffer.getHalfWord(0) & read_bit;

+        

+        // set power down lite disable, rx_pdwn_lite_disable

+        bits=rx_pdwn_lite_disable;

+        rc_ecmd|=set_bits.insert(bits,0,16);

+        bits=rx_pdwn_lite_disable_clear;

+        rc_ecmd|=clear_bits.insert(bits,0,16);

+        if(rc_ecmd)

+        {

+            rc.setEcmdError(rc_ecmd);

+            return(rc);

+        }

+        rc=GCR_write(*target_ptr,chip_interface,rx_mode_pg,group,0,set_bits ,clear_bits);if (rc) {return(rc);}

+        

+        // write rx_wt_timeout_sel to '111'

+        bits=rx_wt_timeout_sel_tap7;

+        rc_ecmd|=set_bits.insert(bits,0,16);

+        bits=rx_wt_timeout_sel_clear;

+        rc_ecmd|=clear_bits.insert(bits,0,16);

+        if(rc_ecmd)

+        {

+            rc.setEcmdError(rc_ecmd);

+            return(rc);

+        }

+        rc=GCR_write(*target_ptr,chip_interface,rx_timeout_sel_pg,group,0,set_bits ,clear_bits);if (rc) {return(rc);}

+        

         bits=rx_start_offset_cal;

         rc_ecmd|=set_bits.insert(bits,0,16);

         bits=rx_start_offset_cal_clear;

@@ -130,7 +165,7 @@ ReturnCode run_offset_cal(const Target &target,io_interface_t master_interface,u
         bool fail= data_buffer.getHalfWord(0) & fail_bit;

         bool done = data_buffer.getHalfWord(0)& done_bit;

         int timeoutCnt = 0;

-        while ( ( !done ) && ( timeoutCnt < 150 ) && !fail )

+        while ( ( !done ) && ( timeoutCnt < 1000 ) && !fail )

         {

                 // wait for 80000 time units

                 // Time units may be something for simulation, and something else (or nothing) for hardware

@@ -150,7 +185,7 @@ ReturnCode run_offset_cal(const Target &target,io_interface_t master_interface,u
                 return rc;

         }

         // Check for errors

-        else if ( timeoutCnt >= 100 && !done && !fail )

+        else if ( timeoutCnt >= 1000 && !done && !fail )

         {

                 FAPI_ERR("Timed out waiting for Done bit to be set");

                 //Set HWP error

@@ -161,7 +196,49 @@ ReturnCode run_offset_cal(const Target &target,io_interface_t master_interface,u
         {

              FAPI_DBG("IO Offset cal Completed on interface %d",chip_interface);

         }

-    }

+        

+        // clear eye opt offset cal done bit, rx_eo_latch_offset_done

+        bits=0x0000;

+        rc_ecmd|=set_bits.insert(bits,0,16);

+        bits=rx_eo_latch_offset_done_clear;

+        rc_ecmd|=clear_bits.insert(bits,0,16);

+        if(rc_ecmd)

+        {

+            rc.setEcmdError(rc_ecmd);

+            return(rc);

+        }

+        rc=GCR_write(*target_ptr,chip_interface,rx_eo_step_stat_pg,group,0,set_bits ,clear_bits);if (rc) {return(rc);}

+        

+        //restore rx_pdwn_lite_disable to saved value

+        

+        bits=rx_pdwn_lite_value;

+        rc_ecmd|=set_bits.insert(bits,0,16);

+        bits=rx_pdwn_lite_disable_clear;

+        rc_ecmd|=clear_bits.insert(bits,0,16);

+        if(rc_ecmd)

+        {

+            rc.setEcmdError(rc_ecmd);

+            return(rc);

+        }

+        rc=GCR_write(*target_ptr,chip_interface,rx_mode_pg,group,0,set_bits ,clear_bits);if (rc) {return(rc);}

+        

+        // restore rx_wt_timeout_sel to saved value

+        

+        bits=rx_wt_timeout_value;

+        rc_ecmd|=set_bits.insert(bits,0,16);

+        bits=rx_wt_timeout_sel_clear;

+        rc_ecmd|=clear_bits.insert(bits,0,16);

+        if(rc_ecmd)

+        {

+            rc.setEcmdError(rc_ecmd);

+            return(rc);

+        }

+        rc=GCR_write(*target_ptr,chip_interface,rx_timeout_sel_pg,group,0,set_bits ,clear_bits);if (rc) {return(rc);}

+        

+    

+    

+    

+    

     return(rc);

 }

 

@@ -349,58 +426,51 @@ ReturnCode run_zcal(const Target& target,io_interface_t master_interface,uint32_
         FAPI_DBG("main_n value %d",main_n);

         FAPI_DBG("post_n value %d",post_n);

         FAPI_DBG("margin_n value %d",margin_n);

-

-        //p segments

-        rc_ecmd|=set_bits.insert(main_p,0,7,25);

-        bits=tx_ffe_main_p_enc_clear;

-        rc_ecmd|=clear_bits.insert(bits,0,16);

+        

+              

+        rc_ecmd|=set_bits.flushTo0();

+        rc_ecmd|=clear_bits.flushTo0(); // I dont want to clear anything by default

         if(rc_ecmd)

         {

             rc.setEcmdError(rc_ecmd);

             return(rc);

         }

-        rc=GCR_write(*target_ptr,chip_interface,tx_ffe_main_pg ,group,0,set_bits,clear_bits);if (rc) {return(rc);}

-        rc_ecmd|=set_bits.insert(post_p,0,5,27);

-        bits=tx_ffe_post_p_enc_clear;

-        rc_ecmd|=clear_bits.insert(bits,0,16);

+        //N segments

+        rc_ecmd|=set_bits.insert(main_p,1,7,25);

+        rc_ecmd|=set_bits.insert(main_n,9,7,25);

+

         if(rc_ecmd)

         {

             rc.setEcmdError(rc_ecmd);

             return(rc);

         }

-        rc=GCR_write(*target_ptr,chip_interface,tx_ffe_post_pg ,group,0,set_bits,clear_bits);if (rc) {return(rc);}

-        rc_ecmd|=set_bits.insert(margin_p,0,5,27);

-        bits=tx_ffe_margin_p_enc_clear;

-        rc_ecmd|=clear_bits.insert(bits,0,16);

+        rc=GCR_write(*target_ptr,chip_interface,tx_ffe_main_pg ,group,0,set_bits,clear_bits);if (rc) {return(rc);}

+        

+        rc_ecmd|=set_bits.flushTo0();

+        rc_ecmd|=clear_bits.flushTo0(); // I dont want to clear anything by default

         if(rc_ecmd)

         {

             rc.setEcmdError(rc_ecmd);

             return(rc);

         }

-        rc=GCR_write(*target_ptr,chip_interface,tx_ffe_margin_pg  ,group,0,set_bits,clear_bits);if (rc) {return(rc);}

-

-        //N segments

-        rc_ecmd|=set_bits.insert(main_n,0,7,25);

-        bits=tx_ffe_main_n_enc_clear;

-        rc_ecmd|=clear_bits.insert(bits,0,16);

+        rc_ecmd|=set_bits.insert(post_p,3,5,27);

+        rc_ecmd|=set_bits.insert(post_n,11,5,27);

         if(rc_ecmd)

         {

             rc.setEcmdError(rc_ecmd);

             return(rc);

         }

-        rc=GCR_write(*target_ptr,chip_interface,tx_ffe_main_pg ,group,0,set_bits,clear_bits);if (rc) {return(rc);}

-        rc_ecmd|=set_bits.insert(post_n,0,5,27);

-        bits=tx_ffe_post_n_enc_clear;

-        rc_ecmd|=clear_bits.insert(bits,0,16);

+        rc=GCR_write(*target_ptr,chip_interface,tx_ffe_post_pg ,group,0,set_bits,clear_bits);if (rc) {return(rc);}

+        

+        rc_ecmd|=set_bits.flushTo0();

+        rc_ecmd|=clear_bits.flushTo0(); // I dont want to clear anything by default

         if(rc_ecmd)

         {

             rc.setEcmdError(rc_ecmd);

             return(rc);

         }

-        rc=GCR_write(*target_ptr,chip_interface,tx_ffe_post_pg ,group,0,set_bits,clear_bits);if (rc) {return(rc);}

-        rc_ecmd|=set_bits.insert(margin_n,0,5,27);

-        bits=tx_ffe_margin_n_enc_clear;

-        rc_ecmd|=clear_bits.insert(bits,0,16);

+        rc_ecmd|=set_bits.insert(margin_p,3,5,27);

+        rc_ecmd|=set_bits.insert(margin_n,11,5,27);

         if(rc_ecmd)

         {

             rc.setEcmdError(rc_ecmd);

@@ -455,7 +525,7 @@ ReturnCode io_dccal(const Target& target){
       // Z cal doesnt require group since its a per bus feature , but to satisfy PLAT swapped translation requirements we pass group=3 on master

       rc=run_zcal(target,master_interface,master_group);if (rc) {return(rc);};

       // Offset cal requires group address

-      rc=run_offset_cal(target,master_interface,master_group);if (rc) {return(rc);};

+     // rc=run_offset_cal(target,master_interface,master_group);if (rc) {return(rc);};

     }

     else if( (target.getType() ==  fapi::TARGET_TYPE_MEMBUF_CHIP)){

       FAPI_DBG("This is a Centaur DMI bus using base DMI scom address");

@@ -465,7 +535,7 @@ ReturnCode io_dccal(const Target& target){
       // Z cal doesnt require group since its a per bus feature , but to satisfy PLAT swapped translation requirements we pass group=3 on master

       rc=run_zcal(target,master_interface,master_group);if (rc) {return(rc);};

       // Offset cal requires group address

-      rc=run_offset_cal(target,master_interface,master_group);if (rc) {return(rc);};

+      //rc=run_offset_cal(target,master_interface,master_group);if (rc) {return(rc);};

     }

     //This is an X Bus

     else if( (target.getType() == fapi::TARGET_TYPE_XBUS_ENDPOINT  )){

@@ -476,7 +546,7 @@ ReturnCode io_dccal(const Target& target){
           // No Z cal in EI4/X bus design

           for(int i=0;i<5;++i){

              master_group=i;

-              rc=run_offset_cal(target,master_interface,master_group);if (rc) {return(rc);};            

+              //rc=run_offset_cal(target,master_interface,master_group);if (rc) {return(rc);};            

           }

       }

     }

@@ -486,8 +556,8 @@ ReturnCode io_dccal(const Target& target){
       master_interface=CP_FABRIC_A0; // base scom for A bus , assume translation to A1 by PLAT 

       master_group=0; // Design requires us to do this as per scom map and layout

                 // EDI-A bus needs both impedance cal and offset cal 

-       rc=run_zcal(target,master_interface,master_group);if (rc) {return(rc);};

-       rc=run_offset_cal(target,master_interface,master_group);if (rc) {return(rc);};

+      rc=run_zcal(target,master_interface,master_group);if (rc) {return(rc);};

+       //rc=run_offset_cal(target,master_interface,master_group);if (rc) {return(rc);};

     }

     else{

       FAPI_ERR("Invalid io_dccal HWP invocation . Target doesnt belong to DMI/X/A instances");

diff --git a/src/usr/hwpf/hwp/bus_training/io_funcs.C b/src/usr/hwpf/hwp/bus_training/io_funcs.C
index 94263cb11..2e9c55806 100644
--- a/src/usr/hwpf/hwp/bus_training/io_funcs.C
+++ b/src/usr/hwpf/hwp/bus_training/io_funcs.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012                   */
+/* COPYRIGHT International Business Machines Corp. 2012,2013              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: io_funcs.C,v 1.13 2012/12/04 08:28:37 varkeykv Exp $
+// $Id: io_funcs.C,v 1.14 2013/01/28 20:19:06 jaswamin Exp $
 // *!***************************************************************************
 // *! (C) Copyright International Business Machines Corp. 1997, 1998
 // *!           All Rights Reserved -- Property of IBM
@@ -39,6 +39,7 @@
 //------------------------------------------------------------------------------
 // Version:|Author: | Date:  | Comment:
 // --------|--------|--------|--------------------------------------------------
+//  1.14   |jaswamin|01/28/12| Changed fatal errors to warning prints to allow training to continue
 //   1.0   |varkeykv|01/19/12| Initial check in to solve linker problems in host
 //			       boot..moved in from io_run_training
 //------------------------------------------------------------------------------
@@ -241,7 +242,7 @@ ReturnCode  edi_training::training_function_status(const Target&  master_chip_ta
                                     if (status_data.getHalfWord(0) & fail_bit)
                                     {
                                        FAPI_ERR("io_run_training: the wiretest training state reported a fail  \n");
-				       FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_WIRETEST_RC);
+				       //FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_WIRETEST_RC);
                                        wire_test_status =  FAILED ;
                                        rx_wderf_failed[WIRE_TEST]=true;
                                       // Run First FAILED Data Capture for Wire Test for FAILED bus
@@ -269,7 +270,7 @@ ReturnCode  edi_training::training_function_status(const Target&  master_chip_ta
                                     {
                                             rx_wderf_failed[DESKEW]=true;
                                             FAPI_ERR("io_run_training : deskew training state reported a fail  \n");
-                                            FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_DESKEW_RC);
+                                            //FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_DESKEW_RC);
                                             desckew_status =  FAILED ;
 					    break;
                                     }
@@ -292,7 +293,7 @@ ReturnCode  edi_training::training_function_status(const Target&  master_chip_ta
                                     if (status_data.getHalfWord(0) & fail_bit)
                                     {
                                              FAPI_ERR("io_run_training : eye_opt_ training state reported a fail\n");
-                                             FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_EYE_OPT_RC);
+                                             //FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_EYE_OPT_RC);
                                              rx_wderf_failed[EYE_OPT]=true;
                                              eye_opt_status =  FAILED ;
 					     break;
@@ -317,7 +318,7 @@ ReturnCode  edi_training::training_function_status(const Target&  master_chip_ta
                                     {
                                              FAPI_DBG("io_run_training: static repair encountered an error    \n");
                                              rx_wderf_failed[REPAIR]=true;
-                                             FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_REPAIR_RC);
+                                             //FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_REPAIR_RC);
                                              repair_status =  FAILED ;
 					     break;
                                     }
@@ -343,7 +344,7 @@ ReturnCode  edi_training::training_function_status(const Target&  master_chip_ta
                                     {
                                              FAPI_DBG("io_run_training:   rx_func_mode_failed    \n");
                                              rx_wderf_failed[FUNCTIONAL]=true;
-                                             FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_FUNC_MODE_RC);
+                                             //FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_FUNC_MODE_RC);
                                              functional_status =   FAILED ;
 					     break;
                                     }
@@ -384,27 +385,27 @@ ReturnCode  edi_training::training_function_status(const Target&  master_chip_ta
 			    if (wire_test_selected && wire_test_status== RUNNING)
 			    {
 			    FAPI_ERR("io_run_training: wiretest timeout");
-			    FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_WIRETEST_TIMEOUT_RC);
+			    //FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_WIRETEST_TIMEOUT_RC);
 			    }
 			    else if (desckew_selected && desckew_status == RUNNING)
 			    {
 			    FAPI_ERR("io_run_training: deskew timeout");
-			    FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_DESKEW_TIMEOUT_RC);
+			    //FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_DESKEW_TIMEOUT_RC);
 			    }
 			    else if (repair_selected && repair_status == RUNNING)
 			    {
 			    FAPI_ERR("io_run_training: repair timeout");
-			    FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_REPAIR_TIMEOUT_RC);
+			    //FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_REPAIR_TIMEOUT_RC);
 			    }
 			    else if (eye_opt_selected && eye_opt_status == RUNNING)
 			    {
 			    FAPI_ERR("io_run_training: eyeopt timeout");
-			    FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_EYE_OPT_TIMEOUT_RC);
+			    //FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_EYE_OPT_TIMEOUT_RC);
 			    }
 			    else
 			    {
 			    FAPI_ERR("io_run_training: func timeout");
-			    FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FUNC_MODE_TIMEOUT_RC);
+			    //FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FUNC_MODE_TIMEOUT_RC);
 			    }
 			    break;
                     }
diff --git a/src/usr/hwpf/hwp/bus_training/io_run_training.C b/src/usr/hwpf/hwp/bus_training/io_run_training.C
index 4f3a27b31..07ca1471d 100644
--- a/src/usr/hwpf/hwp/bus_training/io_run_training.C
+++ b/src/usr/hwpf/hwp/bus_training/io_run_training.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012                   */
+/* COPYRIGHT International Business Machines Corp. 2012,2013              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: io_run_training.C,v 1.25 2012/12/04 08:29:17 varkeykv Exp $
+// $Id: io_run_training.C,v 1.28 2013/01/28 20:19:06 jaswamin Exp $
 // *!***************************************************************************
 // *! (C) Copyright International Business Machines Corp. 1997, 1998
 // *!           All Rights Reserved -- Property of IBM
@@ -39,6 +39,7 @@
 //------------------------------------------------------------------------------
 // Version:|Author: | Date:  | Comment:
 // --------|--------|--------|--------------------------------------------------
+//  1.27   |jaswamin|01/28/13|Changed fatal errors to warning prints to allow training to continue
 //   1.0   |varkeykv|09/27/11|Initial check in . Have to modify targets once bus target is defined and available.Not tested in any way other than in unit SIM IOTK
 //   1.1   |varkeykv|11/16/11|Fixed header files & dependencies
 //------------------------------------------------------------------------------
@@ -70,6 +71,9 @@ ReturnCode io_run_training(const Target &master_target,const Target &slave_targe
           slave_group=0;
           // Workaround - HW 220654 -- Need to split WDERF into WDE + RF due to sync problem
           rc=init1.run_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group);
+          if(rc){
+               return rc;
+          }
           rc=init2.run_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group);
      }
      //This is an X Bus
@@ -84,18 +88,14 @@ ReturnCode io_run_training(const Target &master_target,const Target &slave_targe
                if(!is_master){
                      //Swap master and slave targets !!
                      FAPI_DBG("X Bus ..target swap performed");
-                     rc=init.run_training(slave_target,slave_interface,slave_group,master_target,master_interface,master_group);
-                     //If one clock group cannot be trained.. bus cannot be used..so return rc to plat
-                     if(!rc.ok()){
-                         return(rc);
-                     }
-			   }
+                    rc=init1.run_training(slave_target,slave_interface,slave_group,master_target,master_interface,master_group);
+                    if(rc) return rc;
+                    rc=init2.run_training(slave_target,slave_interface,slave_group,master_target,master_interface,master_group);
+	       }
                else{
-                     rc=init.run_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group);
-                     //If one clock group cannot be trained.. bus cannot be used..so return rc to plat
-                     if(!rc.ok()){
-                         return(rc);
-                     }
+                    rc=init1.run_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group);
+                    if(rc) return rc;
+                    rc=init2.run_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group);
                }
           }
      }
@@ -111,11 +111,15 @@ ReturnCode io_run_training(const Target &master_target,const Target &slave_targe
                if(!is_master)
                {
                     FAPI_DBG("A Bus ..target swap performed");
-                    rc=init.run_training(slave_target,slave_interface,slave_group,master_target,master_interface,master_group);
+                    rc=init1.run_training(slave_target,slave_interface,slave_group,master_target,master_interface,master_group);
+                    if(rc) return rc;
+                    rc=init2.run_training(slave_target,slave_interface,slave_group,master_target,master_interface,master_group);
                }
                else
                {
-                    rc=init.run_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group);
+                    rc=init1.run_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group);
+                    if(rc) return rc;
+                    rc=init2.run_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group);
                }
           }
      }
diff --git a/src/usr/hwpf/hwp/dimm_spd_attributes.xml b/src/usr/hwpf/hwp/dimm_spd_attributes.xml
index 47e3e9d92..de5a47bd0 100644
--- a/src/usr/hwpf/hwp/dimm_spd_attributes.xml
+++ b/src/usr/hwpf/hwp/dimm_spd_attributes.xml
@@ -5,7 +5,7 @@
 <!--                                                                        -->
 <!-- IBM CONFIDENTIAL                                                       -->
 <!--                                                                        -->
-<!-- COPYRIGHT International Business Machines Corp. 2012                   -->
+<!-- COPYRIGHT International Business Machines Corp. 2012,2013              -->
 <!--                                                                        -->
 <!-- p1                                                                     -->
 <!--                                                                        -->
@@ -41,6 +41,7 @@
     <description>
         Module Type.
         Located in DDR3 SPD byte 3, bits 3-0.
+	Note that CDIMM designation here is obsolete.  See ATTR_SPD_CUSTOM
     </description>
     <valueType>uint8</valueType>
     <enum>CDIMM = 0x00, RDIMM = 0x01, UDIMM = 0x02, LRDIMM = 0x0b</enum>
@@ -48,6 +49,19 @@
 </attribute>
 
 <attribute>
+    <id>ATTR_SPD_CUSTOM</id>
+    <targetType>TARGET_TYPE_DIMM</targetType>
+    <description>
+        Module Type is CUSTOM
+        Located in DDR3 SPD byte 3, bit 7. (Most significant bit)
+	If bit 7 (reserved) is a '1' then this attribute value should be set to YES
+    </description>
+    <valueType>uint8</valueType>
+    <enum>NO = 0x0, YES = 0x1</enum>
+    <platInit/>
+</attribute>
+
+<attribute>
     <id>ATTR_SPD_SDRAM_BANKS</id>
     <targetType>TARGET_TYPE_DIMM</targetType>
     <description>
diff --git a/src/usr/hwpf/hwp/dmi_training/cen_dmi_scominit/cen_dmi_scominit.C b/src/usr/hwpf/hwp/dmi_training/cen_dmi_scominit/cen_dmi_scominit.C
new file mode 100644
index 000000000..d2413c303
--- /dev/null
+++ b/src/usr/hwpf/hwp/dmi_training/cen_dmi_scominit/cen_dmi_scominit.C
@@ -0,0 +1,116 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/dmi_training/cen_dmi_scominit/cen_dmi_scominit.C $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2013                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: cen_dmi_scominit.C,v 1.2 2013/01/24 20:21:23 thomsen Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/cen_dmi_scominit.C,v $
+//------------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2012
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//------------------------------------------------------------------------------
+// *! TITLE       : cen_dmi_scominit.C
+// *! DESCRIPTION : Invoke DMI initfiles (FAPI)
+// *!
+// *! OWNER NAME  : Mike Jones        Email: mjjones@us.ibm.com
+// *! BACKUP NAME : Joe McGill        Email: jmcgill@us.ibm.com
+// *!
+// *! ADDITIONAL COMMENTS :
+// *!
+//------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
+//  Version		Date		Owner		Description
+//------------------------------------------------------------------------------
+//    1.3	   	01/23/13	thomsen		Added separate calls to base & customized scominit files. Removed separate calls to SIM vs. HW scominit files
+//    1.2	   	01/09/13	thomsen		Added separate calls to SIM vs. HW scominit files
+//    									Added commented-out call to OVERRIDE initfile for system/bus/lane specific inits
+//    1.1       8/11/12     jmcgill		Initial release
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+//  Includes
+//------------------------------------------------------------------------------
+#include <fapiHwpExecInitFile.H>
+#include <cen_dmi_scominit.H>
+
+extern "C" {
+
+//------------------------------------------------------------------------------
+// Function definitions
+//------------------------------------------------------------------------------
+
+// HWP entry point, comments in header
+fapi::ReturnCode cen_dmi_scominit(const fapi::Target & i_target)
+{
+    fapi::ReturnCode rc;
+    fapi::TargetType target_type;
+    std::vector<fapi::Target> targets;
+
+    // mark HWP entry
+    FAPI_INF("cen_dmi_scominit: Start");
+
+    do
+    {
+        // obtain target type to determine which initfile(s) to execute
+        target_type = i_target.getType();
+        targets.push_back(i_target);
+
+        // Centaur chip target
+        if (target_type == fapi::TARGET_TYPE_MEMBUF_CHIP)
+        {
+		    // Call BASE DMI SCOMINIT
+            FAPI_INF("cen_dmi_scominit: Executing %s on %s",
+                 CEN_DMI_BASE_IF, i_target.toEcmdString());
+		    FAPI_EXEC_HWP(rc, fapiHwpExecInitFile, targets, CEN_DMI_BASE_IF);
+            if (!rc.ok())
+            {
+                FAPI_ERR("cen_dmi_scominit: Error from fapiHwpExecInitfile executing %s on %s",
+                         CEN_DMI_BASE_IF, i_target.toEcmdString());
+                break;
+            }
+		    // Call CUSTOMIZED DMI SCOMINIT (system specific)
+            FAPI_INF("cen_dmi_scominit: Error from fapiHwpExecInitfile executing %s on %s & %s",
+                  CEN_DMI_CUSTOM_IF, i_target.toEcmdString(), i_target.toEcmdString());
+            FAPI_EXEC_HWP(rc, fapiHwpExecInitFile, targets, CEN_DMI_CUSTOM_IF);
+            if (!rc.ok())
+            {
+                FAPI_ERR("cen_dmi_scominit: Error from fapiHwpExecInitfile executing %s on %s",
+                         CEN_DMI_CUSTOM_IF, i_target.toEcmdString());
+                break;
+            }
+			
+        }
+        // unsupported target type
+        else
+        {
+            FAPI_ERR("cen_dmi_scominit: Unsupported target type");
+            FAPI_SET_HWP_ERROR(rc, RC_CEN_DMI_SCOMINIT_INVALID_TARGET);
+            break;
+        }
+    } while (0);
+
+    // mark HWP exit
+    FAPI_INF("cen_dmi_scominit: End");
+	return rc;
+}
+
+
+} // extern "C"
diff --git a/src/usr/hwpf/hwp/dmi_training/cen_dmi_scominit/cen_dmi_scominit.H b/src/usr/hwpf/hwp/dmi_training/cen_dmi_scominit/cen_dmi_scominit.H
new file mode 100644
index 000000000..d3301707f
--- /dev/null
+++ b/src/usr/hwpf/hwp/dmi_training/cen_dmi_scominit/cen_dmi_scominit.H
@@ -0,0 +1,94 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/dmi_training/cen_dmi_scominit/cen_dmi_scominit.H $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2013                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: cen_dmi_scominit.H,v 1.2 2013/01/24 20:21:23 thomsen Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/cen_dmi_scominit.H,v $
+//------------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2012
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//------------------------------------------------------------------------------
+// *! TITLE       : cen_dmi_scominit.H
+// *! DESCRIPTION : Invoke DMI initfiles (FAPI)
+// *!
+// *! OWNER NAME  : Mike Jones        Email: mjjones@us.ibm.com
+// *! BACKUP NAME : Joe McGill        Email: jmcgill@us.ibm.com
+// *!
+// *! ADDITIONAL COMMENTS :
+// *!
+//------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
+//  Version		Date		Owner		Description
+//------------------------------------------------------------------------------
+//    1.3	   	01/23/13	thomsen		Added separate calls to base & customized scominit files. Removed separate calls to SIM vs. HW scominit files
+//    1.2	   	01/09/13	thomsen		Added SIM and HW scominit filename strings
+//										Added *_OVERRIDE_IF to allow DMI initfile overrides for specific bus instances
+//    1.1       8/11/12     jmcgill		Initial release
+//------------------------------------------------------------------------------
+
+
+#ifndef CEN_DMI_SCOMINIT_H_
+#define CEN_DMI_SCOMINIT_H_
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+#include <fapi.H>
+
+//------------------------------------------------------------------------------
+// Constant definitions
+//------------------------------------------------------------------------------
+const char * const CEN_DMI_BASE_IF   = "cen.dmi.scom.if";
+const char * const CEN_DMI_CUSTOM_IF = "cen.dmi.custom.scom.if";
+
+//------------------------------------------------------------------------------
+// Structure definitions
+//------------------------------------------------------------------------------
+
+// function pointer typedef definition for HWP call support
+typedef fapi::ReturnCode
+(*cen_dmi_scominit_FP_t)(const fapi::Target & i_target);
+
+extern "C" {
+
+//------------------------------------------------------------------------------
+// Function prototypes
+//------------------------------------------------------------------------------
+
+/**
+ * @brief HWP that calls the DMI SCOM initfiles
+ *
+ * Should be called with all functional Centaur chips
+ *
+ *
+ * @param[in] i_target Reference to target
+ *                     If TARGET_TYPE_MEMBUF_CHIP, calls:
+ *                     - cen.dmi.scom.initfile
+ *
+ * @return ReturnCode
+ */
+fapi::ReturnCode cen_dmi_scominit(const fapi::Target & i_target);
+
+
+} // extern "C"
+
+#endif // CEN_DMI_SCOMINIT_H_
diff --git a/src/usr/hwpf/hwp/dmi_training/cen_dmi_scominit_errors.xml b/src/usr/hwpf/hwp/dmi_training/cen_dmi_scominit_errors.xml
new file mode 100644
index 000000000..df6234576
--- /dev/null
+++ b/src/usr/hwpf/hwp/dmi_training/cen_dmi_scominit_errors.xml
@@ -0,0 +1,30 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/usr/hwpf/hwp/dmi_training/cen_dmi_scominit_errors.xml $   -->
+<!--                                                                        -->
+<!-- IBM CONFIDENTIAL                                                       -->
+<!--                                                                        -->
+<!-- COPYRIGHT International Business Machines Corp. 2013                   -->
+<!--                                                                        -->
+<!-- p1                                                                     -->
+<!--                                                                        -->
+<!-- Object Code Only (OCO) source materials                                -->
+<!-- Licensed Internal Code Source Materials                                -->
+<!-- IBM HostBoot Licensed Internal Code                                    -->
+<!--                                                                        -->
+<!-- The source code for this program is not published or otherwise         -->
+<!-- divested of its trade secrets, irrespective of what has been           -->
+<!-- deposited with the U.S. Copyright Office.                              -->
+<!--                                                                        -->
+<!-- Origin: 30                                                             -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- Error definitions for cen_dmi_scominit procedure -->
+<hwpErrors>
+  <!-- *********************************************************************** -->
+  <hwpError>
+    <rc>RC_CEN_DMI_SCOMINIT_INVALID_TARGET</rc>
+    <description>Invalid target type presented to cen_dmi_scominit HWP (expects TARGET_TYPE_MEMBUF_CHIP).</description>
+  </hwpError>
+</hwpErrors>
diff --git a/src/usr/hwpf/hwp/dmi_training/dmi_scominit/dmi_scominit.C b/src/usr/hwpf/hwp/dmi_training/dmi_scominit/dmi_scominit.C
deleted file mode 100644
index 709b4aeb6..000000000
--- a/src/usr/hwpf/hwp/dmi_training/dmi_scominit/dmi_scominit.C
+++ /dev/null
@@ -1,108 +0,0 @@
-/*  IBM_PROLOG_BEGIN_TAG
- *  This is an automatically generated prolog.
- *
- *  $Source: src/usr/hwpf/hwp/dmi_training/dmi_scominit/dmi_scominit.C $
- *
- *  IBM CONFIDENTIAL
- *
- *  COPYRIGHT International Business Machines Corp. 2012
- *
- *  p1
- *
- *  Object Code Only (OCO) source materials
- *  Licensed Internal Code Source Materials
- *  IBM HostBoot Licensed Internal Code
- *
- *  The source code for this program is not published or other-
- *  wise divested of its trade secrets, irrespective of what has
- *  been deposited with the U.S. Copyright Office.
- *
- *  Origin: 30
- *
- *  IBM_PROLOG_END_TAG
- */
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//------------------------------------------------------------------------------
-// *! TITLE       : dmi_scominit.C
-// *! DESCRIPTION : Wrapper HWP that invokes the dmi_scominit initfiles
-// *! OWNER NAME  : Mike Jones        Email: mjjones@us.ibm.com
-// *! BACKUP NAME : Mark Bellows      Email: bellows@us.ibm.com
-// *! ADDITIONAL COMMENTS :
-//
-// The purpose of this procedure execute dmi initfiles
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//   1.1   | mjjones  |05-JUL-12| Initial version
-
-//----------------------------------------------------------------------
-//  My Includes
-//----------------------------------------------------------------------
-#include <dmi_scominit.H>
-
-//----------------------------------------------------------------------
-//  Includes
-//----------------------------------------------------------------------
-#include <fapiHwpExecInitFile.H>
-
-const char * const MCS_DMI_IF = "p8.dmi.scom.if";
-const char * const CEN_DMI_IF = "cen.dmi.scom.if";
-
-extern "C" {
-
-fapi::ReturnCode dmi_scominit(const fapi::Target & i_target)
-{
-    FAPI_INF("Performing HWP: dmi_scominit on %s",
-             i_target.toEcmdString());
-    
-    fapi::ReturnCode l_rc;
-    fapi::TargetType l_type = i_target.getType();
-    std::vector<fapi::Target> l_target;
-    l_target.push_back(i_target);
-    
-    do
-    {
-        if (l_type == fapi::TARGET_TYPE_MCS_CHIPLET)
-        {
-            FAPI_INF("Executing %s on %s", MCS_DMI_IF, i_target.toEcmdString());
-            FAPI_EXEC_HWP(l_rc, fapiHwpExecInitFile, l_target, MCS_DMI_IF);
-        
-            if (l_rc)
-            {
-                FAPI_ERR("Error executing %s on %s", MCS_DMI_IF,
-                         i_target.toEcmdString());
-                break;
-            }
-        }
-        else if (l_type == fapi::TARGET_TYPE_MEMBUF_CHIP)
-        {
-            FAPI_INF("Executing %s on %s", CEN_DMI_IF, i_target.toEcmdString());
-            FAPI_EXEC_HWP(l_rc, fapiHwpExecInitFile, l_target, CEN_DMI_IF);
-        
-            if (l_rc)
-            {
-                FAPI_ERR("Error executing %s on %s", CEN_DMI_IF,
-                         i_target.toEcmdString());
-                break;
-            }
-        }
-        else
-        {
-            FAPI_ERR("dmi_scominit has nothing to do for %s",
-                     i_target.toEcmdString());
-        }
-        
-    } while (0);
-
-	return l_rc;
-}
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/dmi_training/dmi_scominit/dmi_scominit.H b/src/usr/hwpf/hwp/dmi_training/dmi_scominit/dmi_scominit.H
deleted file mode 100644
index 793742423..000000000
--- a/src/usr/hwpf/hwp/dmi_training/dmi_scominit/dmi_scominit.H
+++ /dev/null
@@ -1,81 +0,0 @@
-/*  IBM_PROLOG_BEGIN_TAG
- *  This is an automatically generated prolog.
- *
- *  $Source: src/usr/hwpf/hwp/dmi_training/dmi_scominit/dmi_scominit.H $
- *
- *  IBM CONFIDENTIAL
- *
- *  COPYRIGHT International Business Machines Corp. 2012
- *
- *  p1
- *
- *  Object Code Only (OCO) source materials
- *  Licensed Internal Code Source Materials
- *  IBM HostBoot Licensed Internal Code
- *
- *  The source code for this program is not published or other-
- *  wise divested of its trade secrets, irrespective of what has
- *  been deposited with the U.S. Copyright Office.
- *
- *  Origin: 30
- *
- *  IBM_PROLOG_END_TAG
- */
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *! *** IBM Confidential ***
-//------------------------------------------------------------------------------
-// *! TITLE       : dmi_scominit.H
-// *! DESCRIPTION : Wrapper HWP that invokes the dmi_scominit initfiles
-// *! OWNER NAME  : Mike Jones        Email: mjjones@us.ibm.com
-// *! BACKUP NAME : Mark Bellows      Email: bellows@us.ibm.com
-// *! ADDITIONAL COMMENTS :
-//
-// Header file for dmi_scominit.
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//   1.1   | mjjones  |05-JUL-12| Initial version
-
-
-#ifndef DMI_SCOMINIT_H_
-#define DMI_SCOMINIT_H_
-
-//----------------------------------------------------------------------
-//  My Includes
-//----------------------------------------------------------------------
-
-//----------------------------------------------------------------------
-//  Includes
-//----------------------------------------------------------------------
-#include <fapi.H>
-
-typedef fapi::ReturnCode (*dmi_scominit_FP_t)(const fapi::Target & i_target);
-
-extern "C" {
-
-/**
- * @brief HWP that calls the dmi_scominit initfiles
- * 
- * Should be called with all functional MCS chiplets and all functional
- * membuf chips.
- * 
- * @param[in] i_target Reference to target
- *                     If MCS_CHIPLET, calls:
- *                     - p8.dmi.scom.initfile
- *                     If MEMBUF_CHIP, calls:
- *                     - cen.dmi.scom.initfile
- *
- * @return ReturnCode
- */
-fapi::ReturnCode dmi_scominit(const fapi::Target & i_target);
-
-} // extern "C"
-
-#endif // DMI_SCOMINIT_H_
diff --git a/src/usr/hwpf/hwp/dmi_training/dmi_training.C b/src/usr/hwpf/hwp/dmi_training/dmi_training.C
index 9d966470e..594b4277d 100644
--- a/src/usr/hwpf/hwp/dmi_training/dmi_training.C
+++ b/src/usr/hwpf/hwp/dmi_training/dmi_training.C
@@ -64,7 +64,8 @@
 #include    "dmi_training.H"
 #include    "proc_cen_framelock.H"
 #include    "dmi_io_run_training.H"
-#include    "dmi_scominit.H"
+#include    "proc_dmi_scominit.H"
+#include    "cen_dmi_scominit.H"
 #include    "proc_cen_set_inband_addr.H"
 #include    "mss_get_cen_ecid.H"
 #include    "io_restore_erepair.H"
@@ -96,6 +97,9 @@ void*    call_mss_getecid( void *io_pArgs )
     errlHndl_t l_err = NULL;
     IStepError l_StepError;
     uint8_t    l_ddr_port_status = 0;
+    uint8_t    l_cache_enable = 0;
+    uint8_t    l_centaur_sub_revision = 0;
+    
 
     mss_get_cen_ecid_ddr_status l_mbaBadMask[2] =
        { MSS_GET_CEN_ECID_DDR_STATUS_MBA0_BAD,
@@ -129,8 +133,8 @@ void*    call_mss_getecid( void *io_pArgs )
         //  updates the attribute ATTR_MSS_ECID and returns the DDR port status
         //  which is a portion of the ECID data.
         FAPI_INVOKE_HWP(l_err, mss_get_cen_ecid,
-                        l_fapi_centaur, l_ddr_port_status);
-
+                        l_fapi_centaur, l_ddr_port_status,
+                        l_cache_enable, l_centaur_sub_revision);
         if (l_err)
         {
             TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
@@ -240,26 +244,10 @@ void*    call_mss_getecid( void *io_pArgs )
 //
 void*    call_proc_dmi_scominit( void *io_pArgs )
 {
-    errlHndl_t l_err = NULL;
-    TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_proc_dmi_scominit entry" );
-
-    // call proc_dmi_scominit.C
-
-    TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_proc_dmi_scominit exit" );
-
-    return l_err;
-}
-
-
-//
-//  Wrapper function to call dmi_scominit
-//
-void*    call_dmi_scominit( void *io_pArgs )
-{
     errlHndl_t l_errl = NULL;
     IStepError l_StepError;
 
-    TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_dmi_scominit entry" );
+    TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_proc_dmi_scominit entry" );
 
     // Get all functional MCS chiplets
     TARGETING::TargetHandleList l_mcsTargetList;
@@ -276,14 +264,14 @@ void*    call_dmi_scominit( void *io_pArgs )
                 (const_cast<TARGETING::Target*>(l_pTarget)));
 
         TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                "Running dmi_scominit HWP on "
+                "Running proc_dmi_scominit HWP on "
                 "target HUID %.8X", TARGETING::get_huid(l_pTarget));
 
-        FAPI_INVOKE_HWP(l_errl, dmi_scominit, l_fapi_target);
+        FAPI_INVOKE_HWP(l_errl, proc_dmi_scominit, l_fapi_target);
         if (l_errl)
         {
             TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                        "ERROR 0x%.8X : dmi_scominit HWP returns error",
+                        "ERROR 0x%.8X : proc_dmi_scominit HWP returns error",
                         l_errl->reasonCode());
 
             // capture the target data in the elog
@@ -293,48 +281,83 @@ void*    call_dmi_scominit( void *io_pArgs )
         }
         else
         {
-            TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                    "SUCCESS :  dmi_scominit HWP");
+            TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "SUCCESS :  proc_dmi_scominit HWP");
         }
     }
 
-    if ( l_StepError.isNull() )
+    if( l_errl )
     {
-        // Get all functional membuf chips
-        TARGETING::TargetHandleList l_membufTargetList;
-        getAllChips(l_membufTargetList, TYPE_MEMBUF);
+        /*@
+         * @errortype
+         * @reasoncode  ISTEP_DMI_TRAINING_FAILED
+         * @severity    ERRORLOG::ERRL_SEV_UNRECOVERABLE
+         * @moduleid    ISTEP_PROC_DMI_SCOMINIT
+         * @userdata1   bytes 0-1: plid identifying first error
+         *              bytes 2-3: reason code of first error
+         * @userdata2   bytes 0-1: total number of elogs included
+         *              bytes 2-3: N/A
+         * @devdesc     call to proc_dmi_scominit has failed, target data
+         *              is included in the error logs listed in the
+         *              user data section of this error log.
+         *
+         */
+        l_StepError.addErrorDetails(ISTEP_DMI_TRAINING_FAILED,
+                                    ISTEP_PROC_DMI_SCOMINIT,
+                                    l_errl);
 
-        // Invoke dmi_scominit on each one
-        for (TargetHandleList::const_iterator
-                l_membuf_iter = l_membufTargetList.begin();
-                l_membuf_iter != l_membufTargetList.end();
-                ++l_membuf_iter)
-        {
-            const TARGETING::Target* l_pTarget = *l_membuf_iter;
-            const fapi::Target l_fapi_target( TARGET_TYPE_MEMBUF_CHIP,
-                    (const_cast<TARGETING::Target*>(l_pTarget)));
+        errlCommit( l_errl, HWPF_COMP_ID );
+    }
 
-            TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                "Running dmi_scominit HWP on "
-                "target HUID %.8X", TARGETING::get_huid(l_pTarget));
+    TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_proc_dmi_scominit exit" );
 
-            FAPI_INVOKE_HWP(l_errl, dmi_scominit, l_fapi_target);
-            if (l_errl)
-            {
-                TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                        "ERROR 0x%.8X : dmi_scominit HWP returns error",
-                        l_errl->reasonCode());
+    // end task, returning any errorlogs to IStepDisp
+    return l_StepError.getErrorHandle();
+}
 
-                // capture the target data in the elog
-                ErrlUserDetailsTarget(l_pTarget).addToLog( l_errl );
+//
+//  Wrapper function to call dmi_scominit
+//
+void*    call_dmi_scominit( void *io_pArgs )
+{
+    errlHndl_t l_errl = NULL;
+    IStepError l_StepError;
 
-                break;
-            }
-            else
-            {
-                TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                        "SUCCESS :  dmi_scominit HWP");
-            }
+    TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_dmi_scominit entry" );
+
+    // Get all functional membuf chips
+    TARGETING::TargetHandleList l_membufTargetList;
+    getAllChips(l_membufTargetList, TYPE_MEMBUF);
+
+    // Invoke dmi_scominit on each one
+    for (TargetHandleList::iterator l_membuf_iter = l_membufTargetList.begin();
+            l_membuf_iter != l_membufTargetList.end();
+            ++l_membuf_iter)
+    {
+        const TARGETING::Target* l_pTarget = *l_membuf_iter;
+        const fapi::Target l_fapi_target(
+            TARGET_TYPE_MEMBUF_CHIP,
+            reinterpret_cast<void *>
+                (const_cast<TARGETING::Target*>(l_pTarget)));
+
+        TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "Running cen_dmi_scominit HWP on...");
+        EntityPath l_path;
+        l_path = l_pTarget->getAttr<ATTR_PHYS_PATH>();
+        l_path.dump();
+
+        FAPI_INVOKE_HWP(l_errl, cen_dmi_scominit, l_fapi_target);
+        if (l_errl)
+        {
+            TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "ERROR 0x%.8X : cen_dmi_scominit HWP returns error",
+                      l_errl->reasonCode());
+
+            // capture the target data in the elog
+            ErrlUserDetailsTarget(l_pTarget).addToLog( l_errl );
+
+            break;
+        }
+        else
+        {
+            TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "SUCCESS :  dmi_scominit HWP");
         }
     }
 
@@ -349,7 +372,7 @@ void*    call_dmi_scominit( void *io_pArgs )
          *              bytes 2-3: reason code of first error
          * @userdata2   bytes 0-1: total number of elogs included
          *              bytes 2-3: N/A
-         * @devdesc     call to dmi_scominit has failed, target data
+         * @devdesc     call to cen_dmi_scominit has failed, target data
          *              is included in the error logs listed in the
          *              user data section of this error log.
          *
diff --git a/src/usr/hwpf/hwp/dmi_training/makefile b/src/usr/hwpf/hwp/dmi_training/makefile
index 8ad952631..62edbdeea 100644
--- a/src/usr/hwpf/hwp/dmi_training/makefile
+++ b/src/usr/hwpf/hwp/dmi_training/makefile
@@ -1,25 +1,25 @@
-#   IBM_PROLOG_BEGIN_TAG
-#  This is an automatically generated prolog.
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
 #
-#  $Source: src/usr/hwpf/hwp/dmi_training/makefile $
+# $Source: src/usr/hwpf/hwp/dmi_training/makefile $
 #
-#  IBM CONFIDENTIAL
+# IBM CONFIDENTIAL
 #
-#  COPYRIGHT International Business Machines Corp. 2012
+# COPYRIGHT International Business Machines Corp. 2012,2013
 #
-#  p1
+# p1
 #
-#  Object Code Only (OCO) source materials
-#  Licensed Internal Code Source Materials
-#  IBM HostBoot Licensed Internal Code
+# Object Code Only (OCO) source materials
+# Licensed Internal Code Source Materials
+# IBM HostBoot Licensed Internal Code
 #
-#  The source code for this program is not published or other-
-#  wise divested of its trade secrets, irrespective of what has
-#  been deposited with the U.S. Copyright Office.
+# The source code for this program is not published or otherwise
+# divested of its trade secrets, irrespective of what has been
+# deposited with the U.S. Copyright Office.
 #
-#  Origin: 30
+# Origin: 30
 #
-#  IBM_PROLOG_END_TAG
+# IBM_PROLOG_END_TAG
 
 ROOTPATH = ../../../../..
 
@@ -39,26 +39,29 @@ EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/bus_training
 ##  NOTE: add a new EXTRAINCDIR when you add a new HWP
 EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock
 EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/dmi_io_run_training
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/dmi_scominit
 EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/proc_cen_set_inband_addr
 EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/mss_getecid
 EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/io_restore_erepair
 EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/dmi_io_dccal
+EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/proc_dmi_scominit
+EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/cen_dmi_scominit
 
 OBJS =  dmi_training.o  \
         proc_cen_framelock.o    \
         dmi_io_run_training.o \
-        dmi_scominit.o \
         proc_cen_set_inband_addr.o \
         mss_get_cen_ecid.o \
-        dmi_io_dccal.o
+        dmi_io_dccal.o \
+        proc_dmi_scominit.o \
+        cen_dmi_scominit.o
 
 ##  NOTE: add a new directory onto the vpaths when you add a new HWP
 VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock
 VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/dmi_io_run_training
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/dmi_scominit
 VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/proc_cen_set_inband_addr
 VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/mss_getecid
 VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/dmi_io_dccal
+VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/proc_dmi_scominit
+VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/cen_dmi_scominit
 
 include ${ROOTPATH}/config.mk
diff --git a/src/usr/hwpf/hwp/dmi_training/mss_getecid/mss_get_cen_ecid.C b/src/usr/hwpf/hwp/dmi_training/mss_getecid/mss_get_cen_ecid.C
index da5b28fdf..8e56ec71c 100644
--- a/src/usr/hwpf/hwp/dmi_training/mss_getecid/mss_get_cen_ecid.C
+++ b/src/usr/hwpf/hwp/dmi_training/mss_getecid/mss_get_cen_ecid.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012                   */
+/* COPYRIGHT International Business Machines Corp. 2012,2013              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_get_cen_ecid.C,v 1.8 2012/12/10 17:49:53 lapietra Exp $
+// $Id: mss_get_cen_ecid.C,v 1.13 2013/01/24 18:29:59 bellows Exp $
 //------------------------------------------------------------------------------
 // *|
 // *! (C) Copyright International Business Machines Corp. 2012
@@ -39,10 +39,16 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//   1.13  | bellows  |24-JAN-13| Cache Disable Valid bit is ecid_128, made bit
+//         |          |         | number consistent
+//   1.12  | bellows  |23-JAN-13| PSRO attriubute is available in cronus dev
+//   1.11  | bellows  |21-JAN-13| fixed log comment
+//   1.10  | bellows  |21-JAN-13| chip sub id read, psro shell added
+//   1.9   | bellows  |15-JAN-13| moved Cache Enable Information to the caller
 //   1.8   | sglancy  |10-DEC-12| Corrected typo
-//   1.7   | sglancy  |6-DEC-12| Updated to coincide with firmware updates to ECID attribute
-//   1.6   | sglancy  |5-DEC-12| Updated to coincide with firmware change requests
-//   1.5-1 | sglancy  |5-DEC-12| Lost due to no update log
+//   1.7   | sglancy  | 6-DEC-12| Updated to coincide with firmware updates to ECID attribute
+//   1.6   | sglancy  | 5-DEC-12| Updated to coincide with firmware change requests
+//   1.5-1 | sglancy  | 5-DEC-12| Lost due to no update log
 
 //------------------------------------------------------------------------------
 // Includes
@@ -60,12 +66,15 @@ extern "C" {
 // HWP entry point
 fapi::ReturnCode mss_get_cen_ecid(
     const fapi::Target& i_target,
-    uint8_t & ddr_port_status
+    uint8_t & ddr_port_status,
+    uint8_t & cache_enable_o,
+    uint8_t & centaur_sub_revision_o
     )
 {
     // return code
     fapi::ReturnCode rc;
     uint64_t data[2];
+    uint32_t rc_ecmd;
     // mark HWP entry
 
     ecmdDataBufferBase scom(64);
@@ -93,28 +102,47 @@ fapi::ReturnCode mss_get_cen_ecid(
         FAPI_ERR("mss_get_cen_ecid: set ATTR_MSS_ECID" );
         return rc;
     }
-    
-    //gets bits 113 and 114 to determine the state of the cache
-    uint8_t bit113_114=0;
-    uint32_t rc_ecmd = scom.extract(&bit113_114,48,2);
-    bit113_114 = bit113_114 >> 6;
-    uint8_t t;
+
+    //get bit128
+    uint8_t bit128=0;
+    rc_ecmd = scom.extract(&bit128,63,1);
+    bit128 = bit128 >> 7;
     if(rc_ecmd) {
-       FAPI_ERR("mss_get_cen_ecid: could not extract cache data" );
-       rc.setEcmdError(rc_ecmd);
-       return rc;
+      FAPI_ERR("mss_get_cen_ecid: could not extract cache data_valid bit" );
+      rc.setEcmdError(rc_ecmd);
+      return rc;
     }
+
+    if(bit128 == 1) { // Cache enable bit is valid
+
+    //gets bits 113 and 114 to determine the state of the cache
+      uint8_t bit113_114=0;
+      rc_ecmd = scom.extract(&bit113_114,48,2);
+      bit113_114 = bit113_114 >> 6;
+      uint8_t t;
+      if(rc_ecmd) {
+        FAPI_ERR("mss_get_cen_ecid: could not extract cache data" );
+        rc.setEcmdError(rc_ecmd);
+        return rc;
+      }
     //determines the state of the cache
-    if(bit113_114 == 0) t = fapi::ENUM_ATTR_MSS_CACHE_ENABLE_ON;
-    else if(bit113_114 == 1) t = fapi::ENUM_ATTR_MSS_CACHE_ENABLE_HALF_A;
-    else if(bit113_114 == 2) t = fapi::ENUM_ATTR_MSS_CACHE_ENABLE_HALF_B;
-    else t = fapi::ENUM_ATTR_MSS_CACHE_ENABLE_OFF;
-    //sets the cache attribute and error checks
-    rc = FAPI_ATTR_SET(ATTR_MSS_CACHE_ENABLE, &i_target, t);
-    if (!rc.ok()) {
-       FAPI_ERR("mss_get_cen_ecid: could not set ATTR_MSS_CACHE_ENABLE" );
-       return rc;
+      if(bit113_114 == 0) t = fapi::ENUM_ATTR_MSS_CACHE_ENABLE_ON;
+      else if(bit113_114 == 1) t = fapi::ENUM_ATTR_MSS_CACHE_ENABLE_HALF_A;
+      else if(bit113_114 == 2) t = fapi::ENUM_ATTR_MSS_CACHE_ENABLE_HALF_B;
+      else t = fapi::ENUM_ATTR_MSS_CACHE_ENABLE_OFF;
+      cache_enable_o = t;
+    }
+    else {
+      FAPI_INF("Cache Dissbled because eDRAM data bits are assumed to be bad");
+      cache_enable_o = fapi::ENUM_ATTR_MSS_CACHE_ENABLE_OFF;
     }
+
+//    //sets the cache attribute and error checks
+//    rc = FAPI_ATTR_SET(ATTR_MSS_CACHE_ENABLE, &i_target, t);
+//    if (!rc.ok()) {
+//       FAPI_ERR("mss_get_cen_ecid: could not set ATTR_MSS_CACHE_ENABLE" );
+//       return rc;
+//    }
     
     //reads in the ECID info for whether a DDR port side is good or bad
     rc_ecmd = scom.extract(&ddr_port_status,50,2);
@@ -125,7 +153,33 @@ fapi::ReturnCode mss_get_cen_ecid(
        return rc;
     }
     
-    // mark HWP exit
+     //116..123         average PSRO from 85C wafer test
+    uint8_t bit117_124=0;
+    rc_ecmd = scom.extract(&bit117_124,52,8);
+    if(rc_ecmd) {
+       FAPI_ERR("mss_get_cen_ecid: could not extract PSRO" );
+       rc.setEcmdError(rc_ecmd);
+       return rc;
+    }
+    rc = FAPI_ATTR_SET(ATTR_MSS_PSRO, &i_target, bit117_124);
+    if (!rc.ok()) {
+       FAPI_ERR("mss_get_cen_ecid: could not set ATTR_MSS_PSRO" );
+       return rc;
+    }
+
+    // read the bit in the ecid to see if we are a DD1.01
+   // Bit 124 DD1.01  Indicator Bit. Set to '1' for DD1.01 devices
+    uint8_t bit125 =0;
+    rc_ecmd = scom.extract(&bit125,60,1);
+    bit125 = bit125 >> 7;
+    if(rc_ecmd) {
+       FAPI_ERR("mss_get_cen_ecid: could not extract dd1.01 indicator bit" );
+       rc.setEcmdError(rc_ecmd);
+       return rc;
+    }
+    centaur_sub_revision_o=bit125;
+
+   // mark HWP exit
     FAPI_IMP("Exiting mss_get_cen_ecid....");
     return rc;
 }
diff --git a/src/usr/hwpf/hwp/dmi_training/mss_getecid/mss_get_cen_ecid.H b/src/usr/hwpf/hwp/dmi_training/mss_getecid/mss_get_cen_ecid.H
index 7ac839584..d2b9ae780 100644
--- a/src/usr/hwpf/hwp/dmi_training/mss_getecid/mss_get_cen_ecid.H
+++ b/src/usr/hwpf/hwp/dmi_training/mss_getecid/mss_get_cen_ecid.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012                   */
+/* COPYRIGHT International Business Machines Corp. 2012,2013              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_get_cen_ecid.H,v 1.4 2012/12/07 19:12:05 lapietra Exp $
+// $Id: mss_get_cen_ecid.H,v 1.6 2013/01/21 17:11:37 bellows Exp $
 //------------------------------------------------------------------------------
 // *|
 // *! (C) Copyright International Business Machines Corp. 2012
@@ -37,6 +37,13 @@
 // *!
 // *!
 //------------------------------------------------------------------------------
+// CHANGE HISTORY:
+//------------------------------------------------------------------------------
+// Version:|  Author: |  Date:  | Comment:
+//---------|----------|---------|-----------------------------------------------
+//   1.6   | bellows  |21-JAN-13| added in sub revision reader
+//   1.5   | bellows  |15-JAN-13| moved Cache Enable Information to the caller
+// 1.1-1.4 | various  |07-DEC-12| Original Program
 
 #ifndef _MSS_GET_CEN_ECID_H_
 #define _MSS_GET_CEN_ECID_H_
@@ -63,7 +70,8 @@ enum mss_get_cen_ecid_ddr_status
 
 // function pointer typedef definition for HWP call support
 typedef fapi::ReturnCode
-(*mss_get_cen_ecid_FP_t)(const fapi::Target& i_target, uint8_t & ddr_port_status);
+(*mss_get_cen_ecid_FP_t)(const fapi::Target& i_target, uint8_t & ddr_port_status, uint8_t & cache_enable_o,      uint8_t & centaur_sub_revision_o
+);
 
 
 //------------------------------------------------------------------------------
@@ -76,13 +84,17 @@ extern "C"
 // function: FAPI mss_get_cen_ecid HWP entry point
 // parameters: i_target => cen chip target
 //             &ddr_port_status => indicates if the MBA's are bad, with MBA 1 being the rightmost bit and MBA 0 being the next to right most bit
+//             &cache_enable_o => what it would have set the cache enable attribute to if it sets attributes
 // returns: FAPI_RC_SUCCESS if FBC stop is deasserted at end of execution
 //          else FAPI getscom/putscom return code for failing operation
 // Updates attributes: ATTR_MSS_ECID[2] -> bits 1-64 and 65-128 of the ECID
 //                     ATTR_MSS_CACHE_ENABLE -> Stores which parts of the eDRAM are enabled
 fapi::ReturnCode mss_get_cen_ecid(
     const fapi::Target& i_target,
-    uint8_t & ddr_port_status
+    uint8_t & ddr_port_status,
+    uint8_t & cache_enable_o,
+    uint8_t & centaur_sub_revision_o
+
     );
 
 } // extern "C"
diff --git a/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.C b/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.C
index 85cdaf2d3..421c8e55a 100644
--- a/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.C
+++ b/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012                   */
+/* COPYRIGHT International Business Machines Corp. 2012,2013              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-/// $Id: proc_cen_framelock.C,v 1.9 2012/12/03 22:25:37 baysah Exp $
+/// $Id: proc_cen_framelock.C,v 1.11 2013/01/28 03:31:02 baysah Exp $
 
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_cen_framelock.C,v $
 //------------------------------------------------------------------------------
@@ -563,7 +563,7 @@ fapi::ReturnCode proc_cen_framelock_run_framelock(
     if (rc)
     {
         FAPI_ERR("proc_cen_framelock_run_framelock: Error clearing P8 MCI FIR regs");
-       // break;
+        return rc;
     }
 
 
@@ -572,7 +572,7 @@ fapi::ReturnCode proc_cen_framelock_run_framelock(
     if (rc)
     {
         FAPI_ERR("proc_cen_framelock_run_framelock: Error clearing P8 MCI Status regs");
-       // break;
+        return rc;
     }
 
 
@@ -595,14 +595,14 @@ fapi::ReturnCode proc_cen_framelock_run_framelock(
         FAPI_ERR("proc_cen_framelock_run_framelock: Error 0x%x setting up data buffers to set init timeout",
                  rc_ecmd);
         rc.setEcmdError(rc_ecmd);
-       // break;
+        return rc;
     }
 
     rc = proc_cen_framelock_set_pu_mci_cfg_reg(i_pu_target, data, mask);
     if (rc)
     {
         FAPI_ERR("proc_cen_framelock_run_framelock: Error writing P8 MCI Configuration register to set init timeout");
-      //  break;
+        return rc;
     }
 
     // start framelock
@@ -615,14 +615,14 @@ fapi::ReturnCode proc_cen_framelock_run_framelock(
         FAPI_ERR("proc_cen_framelock_run_framelock: Error 0x%x setting up data buffers to initiate framelock",
                  rc_ecmd);
         rc.setEcmdError(rc_ecmd);
-       // break;
+        return rc;
     }
 
     rc = proc_cen_framelock_set_pu_mci_cfg_reg(i_pu_target, data, mask);
     if (rc)
     {
         FAPI_ERR("proc_cen_framelock_run_framelock: Error writing P8 MCI Configuration register to initiate framelock");
-       // break;
+        return rc;
     }
 
     // poll until framelock operation is finished, a timeout is deemed to
@@ -637,7 +637,7 @@ fapi::ReturnCode proc_cen_framelock_run_framelock(
         if (rc)
         {
             FAPI_ERR("proc_cen_framelock_run_framelock: Error reading P8 MCI Status Register");
-            break;
+            return rc;
         }
 
         // Read P8 MCI FIR Register
@@ -646,7 +646,7 @@ fapi::ReturnCode proc_cen_framelock_run_framelock(
         if (rc)
         {
             FAPI_ERR("proc_cen_framelock_run_framelock: Error reading P8 MCI FIR Register");
-            break;
+            return rc;
         }
 
 
@@ -663,7 +663,7 @@ fapi::ReturnCode proc_cen_framelock_run_framelock(
         {
             fl_fail = 1;
             FAPI_ERR("proc_cen_framelock_run_framelock: Framelock fail. P8 MCI STAT OR FIR errors set");
-            //FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_FL_P8_FAIL_ERR);
+
             break;
         }
 
@@ -681,7 +681,10 @@ fapi::ReturnCode proc_cen_framelock_run_framelock(
         if (polls >= PROC_CEN_FRAMELOCK_MAX_FRAMELOCK_POLLS)
         {
             // Loop count has expired, timeout
-            break;
+            FAPI_ERR("!!!! NO FRAME LOCK STATUS DETECTED !!!!");
+            FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_FL_TIMEOUT_ERR);
+            return rc;
+
         }
         else
         {
@@ -690,7 +693,8 @@ fapi::ReturnCode proc_cen_framelock_run_framelock(
             FAPI_DBG("proc_cen_framelock_run_framelock: Loop %d of %d ...",
                      polls, PROC_CEN_FRAMELOCK_MAX_FRAMELOCK_POLLS);
         }
-    }
+
+    } // End While
 
     return rc;
 }
@@ -754,7 +758,7 @@ fapi::ReturnCode proc_cen_framelock_run_frtl(
          FAPI_ERR("proc_cen_framelock_run_frtl: Error 0x%x setting up data buffers to initiate FRTL",
                   rc_ecmd);
          rc.setEcmdError(rc_ecmd);
-        // break;
+         return rc;
      }
 
      rc = proc_cen_framelock_set_pu_mci_cfg_reg(i_pu_target, data, mask);
@@ -762,7 +766,7 @@ fapi::ReturnCode proc_cen_framelock_run_frtl(
      if (rc)
      {
          FAPI_ERR("proc_cen_framelock_run_frtl: Error writing P8 MCI Configuration register to initiate FRTL");
-        // break;
+         return rc;
      }
 
      // Poll until FRTL operation is finished, a timeout is deemed to
@@ -777,7 +781,7 @@ fapi::ReturnCode proc_cen_framelock_run_frtl(
          if (rc)
          {
              FAPI_ERR("proc_cen_framelock_run_frtl: Error reading P8 MCI Status Register");
-             break;
+             return rc;
          }
 
          // Read P8 MCI FIR Register
@@ -785,7 +789,7 @@ fapi::ReturnCode proc_cen_framelock_run_frtl(
          if (rc)
          {
              FAPI_ERR("proc_cen_framelock_run_frtl: Error reading P8 MCI FIR Register");
-             break;
+             return rc;
          }
 
 
@@ -802,7 +806,7 @@ fapi::ReturnCode proc_cen_framelock_run_frtl(
          {
              frtl_fail = 1;
              FAPI_ERR("proc_cen_framelock_run_frtl: FRTL fail. P8 MCI STAT OR FIR errors set");
-             // FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_FRTL_P8_FAIL_ERR);
+
              break;
          }
 
@@ -819,17 +823,11 @@ fapi::ReturnCode proc_cen_framelock_run_frtl(
          if (polls >= PROC_CEN_FRAMELOCK_MAX_FRTL_POLLS)
          {
              // Loop count has expired, timeout
-             if (mci_stat.isBitClear(MCI_STAT_FRTL_PASS_BIT))
-             {
-                 FAPI_ERR("proc_cen_framelock_run_frtl: FRTL timeout (auto) waiting on pass/fail indication in P8 MCI Status Register!");
-             }
-             if (mci_stat.isBitClear(MCI_STAT_CHANNEL_INTERLOCK_PASS_BIT))
-             {
-                 FAPI_ERR("proc_cen_framelock_run_frtl: InterLock timeout (auto) waiting on pass/fail indication in P8 MCI Status Register!");
-             }
-            // FAPI_SET_HWP_ERROR(rc,
-            //                    RC_PROC_CEN_FRAMELOCK_FRTL_TIMEOUT_ERR);
-             break;
+            FAPI_ERR("!!!! NO FRAME LOCK STATUS DETECTED !!!!");
+            FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_FRTL_TIMEOUT_ERR);
+            return rc;
+
+
          }
          else
          {
@@ -838,7 +836,9 @@ fapi::ReturnCode proc_cen_framelock_run_frtl(
              FAPI_DBG("proc_cen_framelock_run_frtl: Loop %d of %d ...\n",
                       polls, PROC_CEN_FRAMELOCK_MAX_FRTL_POLLS);
          }
-     }
+
+
+     } // End While
 
 
     return rc;
@@ -913,14 +913,14 @@ fapi::ReturnCode proc_cen_framelock_run_errstate_framelock(
         FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error 0x%x clearing MBI force channel fail bit",
                  rc_ecmd);
         rc.setEcmdError(rc_ecmd);
-      //  break;
+        return rc;
     }
 
     rc = proc_cen_framelock_set_cen_mbi_cfg_reg(i_mem_target, data,  mask);
     if (rc)
     {
         FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error writing Centaur MBI Configuration Register to clear the force channel fail bit");
-       // break;
+        return rc;
     }
 
 
@@ -934,13 +934,14 @@ fapi::ReturnCode proc_cen_framelock_run_errstate_framelock(
         FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error 0x%x clearing MCI force channel fail bit",
                  rc_ecmd);
         rc.setEcmdError(rc_ecmd);
-       // break;
+        return rc;
     }
+
     rc = proc_cen_framelock_set_pu_mci_cfg_reg(i_pu_target, data, mask);
     if (rc)
     {
         FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error writing P8 MCI Configuration register to clear the force channel fail bit");
-      //  break;
+        return rc;
     }
 
 
@@ -949,7 +950,7 @@ fapi::ReturnCode proc_cen_framelock_run_errstate_framelock(
     if (rc)
     {
         FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error clearing Centaur MBI FIR regs");
-       // break;
+        return rc;
     }
 
 
@@ -958,7 +959,7 @@ fapi::ReturnCode proc_cen_framelock_run_errstate_framelock(
     if (rc)
     {
         FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error clearing Centaur MBI Status regs");
-       // break;
+        return rc;
     }
 
 
@@ -967,7 +968,7 @@ fapi::ReturnCode proc_cen_framelock_run_errstate_framelock(
     if (rc)
     {
         FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error clearing P8 MCI FIR regs");
-       // break;
+        return rc;
     }
 
 
@@ -976,7 +977,7 @@ fapi::ReturnCode proc_cen_framelock_run_errstate_framelock(
     if (rc)
     {
         FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error clearing P8 MCI Status regs");
-       // break;
+        return rc;
     }
 
 
@@ -1000,14 +1001,14 @@ fapi::ReturnCode proc_cen_framelock_run_errstate_framelock(
         FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error 0x%x setting up data buffers to set init timeout",
                  rc_ecmd);
         rc.setEcmdError(rc_ecmd);
-       // break;
+        return rc;
     }
 
     rc = proc_cen_framelock_set_pu_mci_cfg_reg(i_pu_target, data, mask);
     if (rc)
     {
         FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error writing P8 MCI Configuration register to set init timeout");
-      //  break;
+        return rc;
     }
 
 
@@ -1021,14 +1022,14 @@ fapi::ReturnCode proc_cen_framelock_run_errstate_framelock(
         FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error 0x%x setting up data buffers to force framelock",
                  rc_ecmd);
         rc.setEcmdError(rc_ecmd);
-      //  break;
+        return rc;
     }
 
     rc = proc_cen_framelock_set_cen_mbi_cfg_reg(i_mem_target, data, mask);
     if (rc)
     {
         FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error writing Centaur MBI Configuration Register to force framelock");
-      //  break;
+        return rc;
     }
 
 
@@ -1042,14 +1043,14 @@ fapi::ReturnCode proc_cen_framelock_run_errstate_framelock(
         FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error 0x%x setting up data buffers to initiate framelock",
                  rc_ecmd);
         rc.setEcmdError(rc_ecmd);
-       // break;
+        return rc;
     }
 
     rc = proc_cen_framelock_set_pu_mci_cfg_reg(i_pu_target, data, mask);
     if (rc)
     {
         FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error writing P8 MCI Configuration register to initiate framelock");
-      //  break;
+        return rc;
     }
 
     // poll until framelock operation is finished, a timeout is deemed to
@@ -1064,7 +1065,7 @@ fapi::ReturnCode proc_cen_framelock_run_errstate_framelock(
         if (rc)
         {
             FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error reading Centaur MBI status Register");
-            break;
+            return rc;
         }
 
         // Read CEN MBI FIR Register
@@ -1072,7 +1073,7 @@ fapi::ReturnCode proc_cen_framelock_run_errstate_framelock(
         if (rc)
         {
             FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error reading Centaur MBI FIR Register");
-            break;
+            return rc;
         }
 
 
@@ -1083,7 +1084,7 @@ fapi::ReturnCode proc_cen_framelock_run_errstate_framelock(
         if (rc)
         {
             FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error reading P8 MCI Status Register");
-            break;
+            return rc;
         }
 
         // Read P8 MCI FIR Register
@@ -1091,7 +1092,7 @@ fapi::ReturnCode proc_cen_framelock_run_errstate_framelock(
         if (rc)
         {
             FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error reading P8 MCI FIR Register");
-            break;
+            return rc;
         }
 
 
@@ -1108,7 +1109,7 @@ fapi::ReturnCode proc_cen_framelock_run_errstate_framelock(
         {
             fl_fail = 1;
             FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Framelock fail. Centaur MBI STAT OR FIR errors set");
-            //FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_FL_CEN_FAIL_ERR);
+
             break;
         }
 
@@ -1126,7 +1127,7 @@ fapi::ReturnCode proc_cen_framelock_run_errstate_framelock(
         {
             fl_fail = 1;
             FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Framelock fail. P8 MCI STAT OR FIR errors set");
-            // FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_FL_P8_FAIL_ERR);
+
             break;
         }
 
@@ -1142,8 +1143,10 @@ fapi::ReturnCode proc_cen_framelock_run_errstate_framelock(
 
         if (polls >= PROC_CEN_FRAMELOCK_MAX_FRAMELOCK_POLLS)
         {
-            //FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_FL_TIMEOUT_ERR);
-            break;
+            FAPI_ERR("!!!! NO FRAME LOCK STATUS DETECTED !!!!");
+            FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_FL_TIMEOUT_ERR);
+            return rc;
+
         }
         else
         {
@@ -1152,7 +1155,9 @@ fapi::ReturnCode proc_cen_framelock_run_errstate_framelock(
             FAPI_DBG("proc_cen_framelock_run_errstate_framelock: Loop %d of %d ...",
                      polls, PROC_CEN_FRAMELOCK_MAX_FRAMELOCK_POLLS);
         }
-    }
+
+
+    } // End While
 
     return rc;
 }
@@ -1217,14 +1222,14 @@ fapi::ReturnCode proc_cen_framelock_run_errstate_frtl(
         FAPI_ERR("proc_cen_framelock_run_errstate_frtl: Error 0x%x setting up data buffers to force FRTL",
                  rc_ecmd);
         rc.setEcmdError(rc_ecmd);
-       // break;
+        return rc;
     }
 
     rc = proc_cen_framelock_set_cen_mbi_cfg_reg(i_mem_target, data, mask);
     if (rc)
     {
         FAPI_ERR("proc_cen_framelock_run_errstate_frtl: Error writing Centaur MBI Configuration Register to force FRTL");
-       // break;
+        return rc;
     }
 
 
@@ -1238,14 +1243,15 @@ fapi::ReturnCode proc_cen_framelock_run_errstate_frtl(
         FAPI_ERR("proc_cen_framelock_run_errstate_frtl: Error 0x%x setting up data buffers to initiate FRTL",
                  rc_ecmd);
         rc.setEcmdError(rc_ecmd);
-       // break;
+        return rc;
     }
 
     rc = proc_cen_framelock_set_pu_mci_cfg_reg(i_pu_target, data, mask);
     if (rc)
     {
         FAPI_ERR("proc_cen_framelock_run_errstate_frtl: Error writing P8 MCI Configuration register to initiate FRTL");
-       // break;
+        rc.setEcmdError(rc);
+        return rc;
     }
 
     // Poll until FRTL operation is finished, a timeout is deemed to
@@ -1259,7 +1265,7 @@ fapi::ReturnCode proc_cen_framelock_run_errstate_frtl(
         if (rc)
         {
             FAPI_ERR("proc_cen_framelock_run_errstate_frtl: Error reading Centaur MBI Status Register");
-            break;
+            return rc;
         }
 
         // Read Centaur MBI FIR Register
@@ -1267,7 +1273,7 @@ fapi::ReturnCode proc_cen_framelock_run_errstate_frtl(
         if (rc)
         {
             FAPI_ERR("proc_cen_framelock_run_errstate_frtl: Error reading Centaur MBI FIR Register");
-            break;
+            return rc;
         }
 
         // Read P8 MCI Status Register
@@ -1275,7 +1281,7 @@ fapi::ReturnCode proc_cen_framelock_run_errstate_frtl(
         if (rc)
         {
             FAPI_ERR("proc_cen_framelock_run_errstate_frtl: Error reading P8 MCI Status Register");
-            break;
+            return rc;
         }
 
         // Read P8 MCI FIR Register
@@ -1283,7 +1289,7 @@ fapi::ReturnCode proc_cen_framelock_run_errstate_frtl(
         if (rc)
         {
             FAPI_ERR("proc_cen_framelock_run_errstate_frtl: Error reading P8 MCI FIR Register");
-            break;
+            return rc;
         }
 
 
@@ -1300,7 +1306,7 @@ fapi::ReturnCode proc_cen_framelock_run_errstate_frtl(
         {
             frtl_fail = 1;
             FAPI_ERR("proc_cen_framelock_run_errstate_frtl: FRTL fail. Centaur MBI STAT OR FIR errors set");
-            // FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_FRTL_CEN_FAIL_ERR);
+
             break;
         }
 
@@ -1318,8 +1324,8 @@ fapi::ReturnCode proc_cen_framelock_run_errstate_frtl(
         {
             frtl_fail = 1;
             FAPI_ERR("proc_cen_framelock_run_errstate_frtl: FRTL fail. P8 MCI STAT OR FIR errors set");
-           // FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_FRTL_P8_FAIL_ERR);
-           break;
+
+            break;
         }
 
 
@@ -1341,8 +1347,10 @@ fapi::ReturnCode proc_cen_framelock_run_errstate_frtl(
         if (polls >= PROC_CEN_FRAMELOCK_MAX_FRTL_POLLS)
         {
             // Loop count has expired, timeout
-            //FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_FRTL_TIMEOUT_ERR);
-            break;
+            FAPI_ERR("!!!! NO FRAME LOCK STATUS DETECTED !!!!");
+            FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_FRTL_TIMEOUT_ERR);
+            return rc;
+
         }
         else
         {
@@ -1352,7 +1360,8 @@ fapi::ReturnCode proc_cen_framelock_run_errstate_frtl(
                      polls, PROC_CEN_FRAMELOCK_MAX_FRTL_POLLS);
         }
 
-    }   // End While
+
+    }  // End While
 
 
     return rc;
@@ -1431,14 +1440,14 @@ fapi::ReturnCode proc_cen_framelock_run_manual_frtl(
         FAPI_ERR("proc_cen_framelock_run_manual_frtl: Error 0x%x setting up data buffers to disable Centaur auto FRTL mode",
                  rc_ecmd);
         rc.setEcmdError(rc_ecmd);
-      //  break;
+        return rc;
     }
 
     rc = proc_cen_framelock_set_cen_mbi_cfg_reg(i_mem_target, data, mask);
     if (rc)
     {
         FAPI_ERR("proc_cen_framelock_run_manual_frtl: Error writing Centaur MBI Configuration register to disable auto FRTL mode");
-       // break;
+        return rc;
     }
 
     // write specified FRTL value into Centaur MBI Configuration
@@ -1450,7 +1459,7 @@ fapi::ReturnCode proc_cen_framelock_run_manual_frtl(
                  i_args.frtl_manual_mem);
         const proc_cen_framelock_args & ARGS = i_args;
         FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_INVALID_ARGS);
-       // break;
+        return rc;
     }
 
     rc_ecmd |= data.flushTo0();
@@ -1471,14 +1480,14 @@ fapi::ReturnCode proc_cen_framelock_run_manual_frtl(
         FAPI_ERR("proc_cen_framelock_run_manual_frtl: Error 0x%x setting up data buffers to set Centaur manual FRTL value",
                  rc_ecmd);
         rc.setEcmdError(rc_ecmd);
-       // break;
+        return rc;
     }
 
     rc = proc_cen_framelock_set_cen_mbi_cfg_reg(i_mem_target, data, mask);
     if (rc)
     {
         FAPI_ERR("proc_cen_framelock_run_manual_frtl: Error writing Centaur MBI Configuration register to set manual FRTL value");
-       // break;
+        return rc;
     }
 
 
@@ -1503,14 +1512,14 @@ fapi::ReturnCode proc_cen_framelock_run_manual_frtl(
         FAPI_ERR("proc_cen_framelock_run_manual_frtl: Error 0x%x setting up data buffers to disable P8 auto FRTL mode",
                  rc_ecmd);
         rc.setEcmdError(rc_ecmd);
-      //  break;
+        return rc;
     }
 
     rc = proc_cen_framelock_set_pu_mci_cfg_reg(i_pu_target, data, mask);
     if (rc)
     {
         FAPI_ERR("proc_cen_framelock_run_manual_frtl: Error writing P8 MCI Configuration register to disable auto FRTL mode");
-       // break;
+        return rc;
     }
 
     // write specified FRTL value into P8 MCI Configuration Register
@@ -1521,7 +1530,7 @@ fapi::ReturnCode proc_cen_framelock_run_manual_frtl(
                  i_args.frtl_manual_pu);
         const proc_cen_framelock_args & ARGS = i_args;
         FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_INVALID_ARGS);
-       // break;
+        return rc;
     }
     rc_ecmd |= data.flushTo0();
     rc_ecmd |= mask.flushTo0();
@@ -1541,14 +1550,15 @@ fapi::ReturnCode proc_cen_framelock_run_manual_frtl(
         FAPI_ERR("proc_cen_framelock_run_manual_frtl: Error 0x%x setting up data buffers to set P8 manual FRTL value",
                  rc_ecmd);
         rc.setEcmdError(rc_ecmd);
-       // break;
+        return rc;
     }
 
     rc = proc_cen_framelock_set_pu_mci_cfg_reg(i_pu_target, data, mask);
     if (rc)
     {
         FAPI_ERR("proc_cen_framelock_run_manual_frtl: Error writing P8 MCI Configuration register to set manual FRTL value");
-       // break;
+        rc.setEcmdError(rc_ecmd);
+        return rc;
     }
 
 
@@ -1563,14 +1573,14 @@ fapi::ReturnCode proc_cen_framelock_run_manual_frtl(
         FAPI_ERR( "proc_cen_framelock_run_manual_frtl: Error 0x%x setting up data buffers to set Centaur manual FRTL done",
                   rc_ecmd);
         rc.setEcmdError(rc_ecmd);
-       // break;
+        return rc;
     }
 
     rc = proc_cen_framelock_set_cen_mbi_cfg_reg(i_mem_target, data, mask);
     if (rc)
     {
         FAPI_ERR("proc_cen_framelock_run_manual_frtl: Error writing Centaur MBI Configuration register to set manual FRTL done");
-       // break;
+        return rc;
     }
 
     // write FRTL manual done bit into P8 MCI Configuration Register
@@ -1583,14 +1593,14 @@ fapi::ReturnCode proc_cen_framelock_run_manual_frtl(
         FAPI_ERR("proc_cen_framelock_run_manual_frtl: Error 0x%x setting up data buffers to write P8 manual FRTL done",
                  rc_ecmd);
         rc.setEcmdError(rc_ecmd);
-       // break;
+        return rc;
     }
 
     rc = proc_cen_framelock_set_pu_mci_cfg_reg(i_pu_target, data, mask);
     if (rc)
     {
         FAPI_ERR("proc_cen_framelock_run_manual_frtl: Error writing P8 MCI Configuration register to set manual FRTL done");
-       // break;
+        return rc;
     }
 
 
@@ -1607,7 +1617,7 @@ fapi::ReturnCode proc_cen_framelock_run_manual_frtl(
         if (rc)
         {
             FAPI_ERR("proc_cen_framelock_run_manual_frtl: Error reading Centaur MBI Status Register");
-            break;
+            return rc;
         }
 
         // Read Centaur MBI FIR Register
@@ -1615,7 +1625,7 @@ fapi::ReturnCode proc_cen_framelock_run_manual_frtl(
         if (rc)
         {
             FAPI_ERR("proc_cen_framelock_run_manual_frtl: Error reading Centaur MBI FIR Register");
-            break;
+            return rc;
         }
 
         // Read P8 MCI Status Register
@@ -1623,7 +1633,7 @@ fapi::ReturnCode proc_cen_framelock_run_manual_frtl(
         if (rc)
         {
             FAPI_ERR("proc_cen_framelock_run_manual_frtl: Error reading P8 MCI Status Register");
-            break;
+            return rc;
         }
 
         // Read P8 MCI FIR Register
@@ -1631,7 +1641,7 @@ fapi::ReturnCode proc_cen_framelock_run_manual_frtl(
         if (rc)
         {
             FAPI_ERR("proc_cen_framelock_run_manual_frtl: Error reading P8 MCI FIR Register");
-            break;
+            return rc;
         }
 
 
@@ -1685,9 +1695,11 @@ fapi::ReturnCode proc_cen_framelock_run_manual_frtl(
         if (polls >= PROC_CEN_FRAMELOCK_MAX_FRTL_POLLS)
         {
             // Loop count has expired, timeout
-            //FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_FRTL_TIMEOUT_ERR);
+            FAPI_ERR("!!!! NO FRAME LOCK STATUS DETECTED !!!!");
+            FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_FRTL_TIMEOUT_ERR);
+            return rc;
+
 
-            break;
         }
         else
         {
@@ -1696,7 +1708,10 @@ fapi::ReturnCode proc_cen_framelock_run_manual_frtl(
             FAPI_DBG("proc_cen_framelock_run_manual_frtl: Loop %d of %d ...\n",
                      polls, PROC_CEN_FRAMELOCK_MAX_FRTL_POLLS);
         }
-    }
+
+
+
+    } // End While
 
     return rc;
 }
@@ -1765,7 +1780,7 @@ fapi::ReturnCode proc_cen_framelock(const fapi::Target& i_pu_target,
                      i_args.frtl_manual_mem);
             const proc_cen_framelock_args & ARGS = i_args;
             FAPI_SET_HWP_ERROR(l_rc, RC_PROC_CEN_FRAMELOCK_INVALID_ARGS);
-            break;
+            return l_rc;
         }
 
         if (i_args.frtl_manual_pu > MCI_CFG_MANUAL_FRTL_FIELD_MASK)
@@ -1774,7 +1789,7 @@ fapi::ReturnCode proc_cen_framelock(const fapi::Target& i_pu_target,
                      i_args.frtl_manual_pu);
             const proc_cen_framelock_args & ARGS = i_args;
             FAPI_SET_HWP_ERROR(l_rc, RC_PROC_CEN_FRAMELOCK_INVALID_ARGS);
-            break;
+            return l_rc;
         }
 
 
@@ -1789,7 +1804,7 @@ fapi::ReturnCode proc_cen_framelock(const fapi::Target& i_pu_target,
                                                  i_args);
            if (l_rc)
            {
-               break;
+              return l_rc;
            }
 
         }
@@ -1809,7 +1824,8 @@ fapi::ReturnCode proc_cen_framelock(const fapi::Target& i_pu_target,
                                                  i_args);
                 if (l_rc)
                 {
-                    break;
+
+                    return l_rc;
                 }
 
             }
@@ -1822,7 +1838,8 @@ fapi::ReturnCode proc_cen_framelock(const fapi::Target& i_pu_target,
                                                          i_args);
                if (l_rc)
                {
-                   break;
+
+                   return l_rc;
                }
 
             } // end else
@@ -1851,14 +1868,14 @@ fapi::ReturnCode proc_cen_framelock(const fapi::Target& i_pu_target,
                 FAPI_ERR("proc_cen_framelock: Error 0x%x setting up data buffers to force MBI in channel fail state",
                          l_ecmdRc);
                 l_rc.setEcmdError(l_ecmdRc);
-                break;
+                return l_rc;
             }
 
             l_rc = proc_cen_framelock_set_cen_mbi_cfg_reg(i_mem_target, mbi_data,  mbi_mask);
             if (l_rc)
             {
                 FAPI_ERR("proc_cen_framelock: Error writing Centaur MBI Configuration Register to force framelock");
-                break;
+                return l_rc;
             }
 
 
@@ -1871,13 +1888,14 @@ fapi::ReturnCode proc_cen_framelock(const fapi::Target& i_pu_target,
                 FAPI_ERR("proc_cen_framelock: Error 0x%x setting up data buffers to force MCI in channel fail state",
                          l_ecmdRc);
                 l_rc.setEcmdError(l_ecmdRc);
-                break;
+                return l_rc;
             }
+
             l_rc = proc_cen_framelock_set_pu_mci_cfg_reg(i_pu_target, mci_data, mci_mask);
             if (l_rc)
             {
-                FAPI_ERR("proc_cen_framelock: Error writing P8 MCI Configuration register to force MCI in channel fail state");
-                break;
+                 FAPI_ERR("proc_cen_framelock: Error writing P8 MCI Configuration register to force MCI in channel fail state");
+                 return l_rc;
             }
 
 
@@ -1894,7 +1912,8 @@ fapi::ReturnCode proc_cen_framelock(const fapi::Target& i_pu_target,
                                                             i_args);
            if (l_rc)
            {
-               break;
+
+               return l_rc;
            }
 
 
@@ -1908,7 +1927,8 @@ fapi::ReturnCode proc_cen_framelock(const fapi::Target& i_pu_target,
                                                            i_args);
                if (l_rc)
                {
-                   break;
+
+                   return l_rc;
                }
 
            }
@@ -1921,7 +1941,8 @@ fapi::ReturnCode proc_cen_framelock(const fapi::Target& i_pu_target,
                                                         i_args);
               if (l_rc)
               {
-                  break;
+
+                  return l_rc;
               }
 
            } // end if .... else
@@ -1935,11 +1956,12 @@ fapi::ReturnCode proc_cen_framelock(const fapi::Target& i_pu_target,
         fapiDelay(1000000, 200);    //fapiDelay(nanoseconds, simcycles)
 
 
-        if ( (num_try > 3) && ((fl_fail == 1) || (frtl_fail == 1)) )
+       if ( (num_try > 3) && ((fl_fail == 1) || (frtl_fail == 1)) )   // assumes the DMI toggle before this procedure is started.
         {
 
-           FAPI_SET_HWP_ERROR(l_rc, RC_PROC_CEN_FRAMELOCK_FRTL_TIMEOUT_ERR);
-
+            FAPI_ERR("!!!! Maximum Retry Attempts Exceeded !!!!");
+            FAPI_SET_HWP_ERROR(l_rc, RC_PROC_CEN_FRAMELOCK_FRTL_TIMEOUT_ERR);
+            return l_rc;
 
         }
 
@@ -1950,7 +1972,6 @@ fapi::ReturnCode proc_cen_framelock(const fapi::Target& i_pu_target,
          //FAPI_DBG("FRTL Pass Value at End of Loop: %d", frtl_pass);
          //FAPI_DBG("FRTL Fail Value at End of Loop: %d", frtl_fail);
 
-
     }  // End While
 
 
@@ -1967,7 +1988,7 @@ fapi::ReturnCode proc_cen_framelock(const fapi::Target& i_pu_target,
         if (l_rc)
         {
             FAPI_ERR("proc_cen_framelock: Error clearing P8 MCI FIR regs");
-           // break;
+            return l_rc;
         }
 
         // Clear Centaur MBI FIR registers
@@ -1975,18 +1996,34 @@ fapi::ReturnCode proc_cen_framelock(const fapi::Target& i_pu_target,
         if (l_rc)
         {
             FAPI_ERR("proc_cen_framelock: Error clearing Centaur MBI FIR regs");
-           // break;
+            return l_rc;
         }
 
     }
 
 
+    // Return bad code from while loops here, before the get overwritten by the procedure EXIT scoms below
+    if (l_rc)
+    {
+        //FAPI_DBG(" HELLO...THIS IS A BAD RETURN CODE");
+        return l_rc;
+    }
 
 
     // EXIT Procedure
     // by setting the MCI and MBI fir mask and action registers according to PRD requirements.
 
 
+      // (Action0, Action1, Mask)
+      // ------------------------
+      // (0,0,0) = Checkstop
+      // (0,1,0) = Recoverable
+      // (1,0,x) = Report Unused
+      // (1,1,0) = Machine Check
+      // (x,x,1) = MASKED
+      // (1,0,0) = Use this setting for non-implemented bits
+
+
         // Set P8 MCI FIR Mask
         l_ecmdRc |= mci_data.flushTo0();
         l_ecmdRc |= mci_data.setBit(0);     //Replay Timeout
@@ -2002,6 +2039,7 @@ fapi::ReturnCode proc_cen_framelock(const fapi::Target& i_pu_target,
         l_ecmdRc |= mci_data.setBit(17);    //Centaur Maintenance Complete
         l_ecmdRc |= mci_data.setBit(20);    //SCOM Register Parity Error
         l_ecmdRc |= mci_data.setBit(22);    //MCICFGQ Parity Error
+        l_ecmdRc |= mci_data.setBit(23);    //Replay Buffer Overrun
         l_ecmdRc |= mci_data.setBit(40);    //MCS Channel Timeout Error
         l_ecmdRc |= mci_data.copy(mci_mask);
         l_ecmdRc |= mci_data.clearBit(0);     //Replay Timeout
@@ -2017,20 +2055,21 @@ fapi::ReturnCode proc_cen_framelock(const fapi::Target& i_pu_target,
         l_ecmdRc |= mci_data.clearBit(17);    //Centaur Maintenance Complete
         l_ecmdRc |= mci_data.clearBit(20);    //SCOM Register Parity Error
         l_ecmdRc |= mci_data.clearBit(22);    //MCICFGQ Parity Error
+        l_ecmdRc |= mci_data.clearBit(23);    //Replay Buffer Overrun
         l_ecmdRc |= mci_data.clearBit(40);    //MCS Channel Timeout Error
         if (l_ecmdRc)
         {
             FAPI_ERR("proc_cen_framelock: Error 0x%x setting up data buffers to mask MCI FIRs",
                      l_ecmdRc);
             l_rc.setEcmdError(l_ecmdRc);
-           // break;
+            // return l_rc;
         }
 
         l_rc = proc_cen_framelock_set_pu_mci_firmask_reg(i_pu_target, mci_data, mci_mask);
         if (l_rc)
         {
             FAPI_ERR("proc_cen_framelock: Error writing P8 MCI Fir Mask Register");
-           // break;
+            //return l_rc;
         }
 
 
@@ -2047,14 +2086,14 @@ fapi::ReturnCode proc_cen_framelock(const fapi::Target& i_pu_target,
             FAPI_ERR("proc_cen_framelock: Error 0x%x setting up data buffers to set MCI FIR actions",
                      l_ecmdRc);
             l_rc.setEcmdError(l_ecmdRc);
-           // break;
+            // return l_rc;
         }
 
         l_rc = proc_cen_framelock_set_pu_mci_firact0_reg(i_pu_target, mci_data, mci_mask);
         if (l_rc)
         {
             FAPI_ERR("proc_cen_framelock: Error writing P8 MCI Fir Action0 Register");
-           // break;
+            // return l_rc;
         }
 
 
@@ -2071,6 +2110,7 @@ fapi::ReturnCode proc_cen_framelock(const fapi::Target& i_pu_target,
         l_ecmdRc |= mci_data.setBit(10);    //CRC Performance Degradation
         l_ecmdRc |= mci_data.setBit(20);    //Scom Register parity error
         l_ecmdRc |= mci_data.setBit(22);    //mcicfgq parity error
+        l_ecmdRc |= mci_data.setBit(23);    //Replay Buffer Overrun
         l_ecmdRc |= mci_data.setBit(40);    //MCS Channel Timeout Error
         l_ecmdRc |= mci_data.copy(mci_mask);
         if (l_ecmdRc)
@@ -2078,14 +2118,14 @@ fapi::ReturnCode proc_cen_framelock(const fapi::Target& i_pu_target,
             FAPI_ERR("proc_cen_framelock: Error 0x%x setting up data buffers to set MCI FIR actions",
                      l_ecmdRc);
             l_rc.setEcmdError(l_ecmdRc);
-           // break;
+            //return l_rc;
         }
 
         l_rc = proc_cen_framelock_set_pu_mci_firact1_reg(i_pu_target, mci_data, mci_mask);
         if (l_rc)
         {
             FAPI_ERR("proc_cen_framelock: Error writing P8 MCI Fir Action1 Register");
-           // break;
+            //return l_rc;
         }
 
 
@@ -2105,14 +2145,14 @@ fapi::ReturnCode proc_cen_framelock(const fapi::Target& i_pu_target,
             FAPI_ERR("proc_cen_framelock: Error 0x%x setting up data buffers to set MCS Mode4 Register",
                      l_ecmdRc);
             l_rc.setEcmdError(l_ecmdRc);
-           // break;
+            //return l_rc;
         }
 
         l_rc = proc_cen_framelock_set_pu_mcs_mode4_reg(i_pu_target, mci_data, mci_mask);
         if (l_rc)
         {
             FAPI_ERR("proc_cen_framelock: Error writing P8 MCS Mode4 Register");
-           // break;
+            //return l_rc;
         }
 
 
@@ -2130,6 +2170,7 @@ fapi::ReturnCode proc_cen_framelock(const fapi::Target& i_pu_target,
         l_ecmdRc |= mbi_data.setBit(10);    //CRC Performance Degradation
         l_ecmdRc |= mbi_data.setBit(16);    //SCOM Register parity
         l_ecmdRc |= mbi_data.setBit(19);    //MBICFGQ Parity Error
+        l_ecmdRc |= mbi_data.setBit(20);    //Replay Buffer Overrun Error
         l_ecmdRc |= mbi_data.copy(mbi_mask);
         l_ecmdRc |= mbi_data.clearBit(0);     //Replay Timeout
         l_ecmdRc |= mbi_data.clearBit(4);     //Seqid ooo
@@ -2140,19 +2181,20 @@ fapi::ReturnCode proc_cen_framelock(const fapi::Target& i_pu_target,
         l_ecmdRc |= mbi_data.clearBit(10);    //CRC Performance Degradation
         l_ecmdRc |= mbi_data.clearBit(16);    //SCOM Register parity
         l_ecmdRc |= mbi_data.clearBit(19);    //MBICFGQ Parity Error
+        l_ecmdRc |= mbi_data.clearBit(20);    //Replay Buffer Overrun Error
         if (l_ecmdRc)
         {
             FAPI_ERR("proc_cen_framelock: Error 0x%x setting up data buffers to mask MBI FIRs",
                      l_ecmdRc);
             l_rc.setEcmdError(l_ecmdRc);
-           // break;
+            // return l_rc;
         }
 
         l_rc = proc_cen_framelock_set_cen_mbi_firmask_reg(i_mem_target, mbi_data, mbi_mask);
         if (l_rc)
         {
             FAPI_ERR("proc_cen_framelock: Error writing Centaur MBI Fir Mask Register");
-           // break;
+            //return l_rc;
         }
 
 
@@ -2170,24 +2212,24 @@ fapi::ReturnCode proc_cen_framelock(const fapi::Target& i_pu_target,
             FAPI_ERR("proc_cen_framelock: Error 0x%x setting up data buffers to set MBI FIR actions",
                      l_ecmdRc);
             l_rc.setEcmdError(l_ecmdRc);
-           // break;
+            //return l_rc;
         }
 
         l_rc = proc_cen_framelock_set_cen_mbi_firact1_reg(i_mem_target, mbi_data, mbi_mask);
         if (l_rc)
         {
             FAPI_ERR("proc_cen_framelock: Error writing Centaur MBI Fir Action1 Register");
-           // break;
+            //return l_rc;
         }
 
 
 
-
     // mark HWP exit
     FAPI_IMP("proc_cen_framelock: Exiting ...");
+
     return l_rc;
-}
 
+}   // End While
 
 
 
diff --git a/src/usr/hwpf/hwp/dmi_training/proc_dmi_scominit/proc_dmi_scominit.C b/src/usr/hwpf/hwp/dmi_training/proc_dmi_scominit/proc_dmi_scominit.C
new file mode 100644
index 000000000..a236f9207
--- /dev/null
+++ b/src/usr/hwpf/hwp/dmi_training/proc_dmi_scominit/proc_dmi_scominit.C
@@ -0,0 +1,124 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/dmi_training/proc_dmi_scominit/proc_dmi_scominit.C $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2013                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: proc_dmi_scominit.C,v 1.3 2013/01/24 20:20:34 thomsen Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_dmi_scominit.C,v $
+//------------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2012
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//------------------------------------------------------------------------------
+// *! TITLE       : proc_dmi_scominit.C
+// *! DESCRIPTION : Invoke DMI initfiles (FAPI)
+// *!
+// *! OWNER NAME  : Mike Jones        Email: mjjones@us.ibm.com
+// *! BACKUP NAME : Joe McGill        Email: jmcgill@us.ibm.com
+// *!
+// *! ADDITIONAL COMMENTS :
+// *!
+//------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
+//  Version		Date		Owner		Description
+//------------------------------------------------------------------------------
+//    1.3	   	01/23/13	thomsen		Added separate calls to base & customized scominit files. Removed separate calls to SIM vs. HW scominit files
+//    1.2	   	01/10/13	thomsen		Added separate calls to SIM vs. HW scominit files
+//   									Added commented-out call to OVERRIDE initfile for system/bus/lane specific inits
+//                                      Changed passed targets in order to match scominit file updates. 
+//                                      CO-REQs required: p8.dmi.vbu.scom.initfile v1.1 and p8.dmi.hw.scom.initfile v1.1
+//    1.1       8/11/12     jmcgill		Initial release
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+//  Includes
+//------------------------------------------------------------------------------
+#include <fapiHwpExecInitFile.H>
+#include <proc_dmi_scominit.H>
+
+extern "C" {
+
+//------------------------------------------------------------------------------
+// Function definitions
+//------------------------------------------------------------------------------
+
+// HWP entry point, comments in header
+fapi::ReturnCode proc_dmi_scominit(const fapi::Target & i_target)
+{
+    fapi::ReturnCode rc;
+    //fapi::TargetType target_type;
+    fapi::Target i_this_pu_target;
+    std::vector<fapi::Target> targets;
+
+    // mark HWP entry
+    FAPI_INF("proc_dmi_scominit: Start");
+
+    do
+    {
+  
+	    // Get parent chip target
+        rc = fapiGetParentChip(i_target, i_this_pu_target); if(rc) return rc;
+
+		// populate targets vector (i_this_pu_target=proc target, i_target=chiplet target)
+        targets.push_back(i_this_pu_target); 
+        targets.push_back(i_target);
+
+        // processor target, processor MCS chiplet target
+        // test target types to confirm correct before calling initfile(s) to execute
+        if ((i_this_pu_target.getType() == fapi::TARGET_TYPE_PROC_CHIP)   &&
+            (i_target.getType()         == fapi::TARGET_TYPE_MCS_CHIPLET))
+        {
+		    // Call BASE DMI SCOMINIT
+            FAPI_INF("proc_dmi_scominit: Error from fapiHwpExecInitfile executing %s on %s & %s",
+                  MCS_DMI_BASE_IF, i_this_pu_target.toEcmdString(), i_target.toEcmdString());
+            FAPI_EXEC_HWP(rc, fapiHwpExecInitFile, targets, MCS_DMI_BASE_IF);
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_dmi_scominit: Error from fapiHwpExecInitfile executing %s on %s",
+                         MCS_DMI_BASE_IF, i_target.toEcmdString());
+                break;
+            }
+		    // Call CUSTOMIZED DMI SCOMINIT (system specific)
+            FAPI_INF("proc_dmi_scominit: Error from fapiHwpExecInitfile executing %s on %s & %s",
+                  MCS_DMI_CUSTOM_IF, i_this_pu_target.toEcmdString(), i_target.toEcmdString());
+            FAPI_EXEC_HWP(rc, fapiHwpExecInitFile, targets, MCS_DMI_CUSTOM_IF);
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_dmi_scominit: Error from fapiHwpExecInitfile executing %s on %s",
+                         MCS_DMI_CUSTOM_IF, i_target.toEcmdString());
+                break;
+            }
+	    }
+        // unsupported target type
+        else
+        {
+            FAPI_ERR("proc_dmi_scominit: Unsupported target type");
+            FAPI_SET_HWP_ERROR(rc, RC_PROC_DMI_SCOMINIT_INVALID_TARGET);
+            break;
+        }
+    } while (0);
+
+    // mark HWP exit
+    FAPI_INF("proc_dmi_scominit: End");
+	return rc;
+}
+
+
+} // extern "C"
diff --git a/src/usr/hwpf/hwp/dmi_training/proc_dmi_scominit/proc_dmi_scominit.H b/src/usr/hwpf/hwp/dmi_training/proc_dmi_scominit/proc_dmi_scominit.H
new file mode 100644
index 000000000..ea9b30814
--- /dev/null
+++ b/src/usr/hwpf/hwp/dmi_training/proc_dmi_scominit/proc_dmi_scominit.H
@@ -0,0 +1,93 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/dmi_training/proc_dmi_scominit/proc_dmi_scominit.H $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2013                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: proc_dmi_scominit.H,v 1.3 2013/01/24 20:20:34 thomsen Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_dmi_scominit.H,v $
+//------------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2012
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//------------------------------------------------------------------------------
+// *! TITLE       : proc_dmi_scominit.H
+// *! DESCRIPTION : Invoke DMI initfile (FAPI)
+// *!
+// *! OWNER NAME  : Mike Jones        Email: mjjones@us.ibm.com
+// *! BACKUP NAME : Joe McGill        Email: jmcgill@us.ibm.com
+// *!
+// *! ADDITIONAL COMMENTS :
+// *!
+//------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
+//  Version		Date		Owner		Description
+//------------------------------------------------------------------------------
+//    1.3	   	01/23/13	thomsen		Added separate calls to base & customized scominit files. Removed separate calls to SIM vs. HW scominit files
+//    1.2	   	01/10/13	thomsen		Added SIM and HW scominit filename strings
+//										Added *_OVERRIDE_IF to allow initfile overrides for specific bus instances
+//                                      CO-REQs required: p8.dmi.vbu.scom.initfile v1.1 and p8.dmi.hw.scom.initfile v1.1
+//    1.1       8/11/12     jmcgill		Initial release
+//------------------------------------------------------------------------------
+
+#ifndef PROC_DMI_SCOMINIT_H_
+#define PROC_DMI_SCOMINIT_H_
+
+//------------------------------------------------------------------------------
+// Includes
+//------------------------------------------------------------------------------
+#include <fapi.H>
+
+//------------------------------------------------------------------------------
+// Constant definitions
+//------------------------------------------------------------------------------
+const char * const MCS_DMI_BASE_IF   = "p8.dmi.scom.if";
+const char * const MCS_DMI_CUSTOM_IF = "p8.dmi.custom.scom.if";
+
+//------------------------------------------------------------------------------
+// Structure definitions
+//------------------------------------------------------------------------------
+
+// function pointer typedef definition for HWP call support
+typedef fapi::ReturnCode
+(*proc_dmi_scominit_FP_t)(const fapi::Target & i_target);
+
+extern "C" {
+
+//------------------------------------------------------------------------------
+// Function prototypes
+//------------------------------------------------------------------------------
+
+/**
+ * @brief HWP that calls the DMI SCOM initfiles
+ *
+ * Should be called with all functional MCS chiplets
+ *
+ * @param[in] i_target Reference to target
+ *                     If TARGET_TYPE_MCS_CHIPLET, calls:
+ *                     - p8.dmi.scom.initfile
+ *
+ * @return ReturnCode
+ */
+fapi::ReturnCode proc_dmi_scominit(const fapi::Target & i_target);
+
+
+} // extern "C"
+
+#endif // PROC_DMI_SCOMINIT_H_
diff --git a/src/usr/hwpf/hwp/dmi_training/proc_dmi_scominit_errors.xml b/src/usr/hwpf/hwp/dmi_training/proc_dmi_scominit_errors.xml
new file mode 100644
index 000000000..af4657ba6
--- /dev/null
+++ b/src/usr/hwpf/hwp/dmi_training/proc_dmi_scominit_errors.xml
@@ -0,0 +1,30 @@
+<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
+<!-- This is an automatically generated prolog.                             -->
+<!--                                                                        -->
+<!-- $Source: src/usr/hwpf/hwp/dmi_training/proc_dmi_scominit_errors.xml $  -->
+<!--                                                                        -->
+<!-- IBM CONFIDENTIAL                                                       -->
+<!--                                                                        -->
+<!-- COPYRIGHT International Business Machines Corp. 2013                   -->
+<!--                                                                        -->
+<!-- p1                                                                     -->
+<!--                                                                        -->
+<!-- Object Code Only (OCO) source materials                                -->
+<!-- Licensed Internal Code Source Materials                                -->
+<!-- IBM HostBoot Licensed Internal Code                                    -->
+<!--                                                                        -->
+<!-- The source code for this program is not published or otherwise         -->
+<!-- divested of its trade secrets, irrespective of what has been           -->
+<!-- deposited with the U.S. Copyright Office.                              -->
+<!--                                                                        -->
+<!-- Origin: 30                                                             -->
+<!--                                                                        -->
+<!-- IBM_PROLOG_END_TAG                                                     -->
+<!-- Error definitions for proc_dmi_scominit procedure -->
+<hwpErrors>
+  <!-- *********************************************************************** -->
+  <hwpError>
+    <rc>RC_PROC_DMI_SCOMINIT_INVALID_TARGET</rc>
+    <description>Invalid target type presented to proc_dmi_scominit HWP (expects TARGET_TYPE_MCS_CHIPLET).</description>
+  </hwpError>
+</hwpErrors>
diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.C b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.C
index e3642c1cb..11961b81c 100644
--- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.C
+++ b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012                   */
+/* COPYRIGHT International Business Machines Corp. 2012,2013              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_setup_bars.C,v 1.7 2012/10/09 15:31:38 jmcgill Exp $
+// $Id: proc_setup_bars.C,v 1.8 2012/12/11 23:59:28 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_setup_bars.C,v $
 //------------------------------------------------------------------------------
 // *|
@@ -1138,6 +1138,8 @@ fapi::ReturnCode proc_setup_bars_process_chip(
 {
     // return code
     fapi::ReturnCode rc;
+    uint8_t pcie_enabled;
+    uint8_t nx_enabled;
 
     // mark function entry
     FAPI_DBG("proc_setup_bars_process_chip: Start");
@@ -1181,6 +1183,32 @@ fapi::ReturnCode proc_setup_bars_process_chip(
             break;
         }
 
+        // query NX partial good attribute
+        rc = FAPI_ATTR_GET(ATTR_PROC_NX_ENABLE,
+                           &(io_smp_chip.chip->this_chip),
+                           nx_enabled);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_setup_bars_process_chip: Error querying ATTR_PROC_NX_ENABLE");
+            break;
+        }
+
+        // query PCIE partial good attribute
+        rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_ENABLE,
+                           &(io_smp_chip.chip->this_chip),
+                           pcie_enabled);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_setup_bars_process_chip: Error querying ATTR_PROC_PCIE_ENABLE");
+            break;
+        }
+
+        io_smp_chip.nx_enabled =
+            (nx_enabled == fapi::ENUM_ATTR_PROC_NX_ENABLE_ENABLE);
+
+        io_smp_chip.pcie_enabled =
+            (pcie_enabled == fapi::ENUM_ATTR_PROC_PCIE_ENABLE_ENABLE);
+
         // get BAR attributes
         rc = proc_setup_bars_get_bar_attrs(io_smp_chip);
         if (!rc.ok())
@@ -2321,7 +2349,7 @@ proc_setup_bars_write_local_chip_region_bars(
         }
 
         // NX (MMIO)
-        if (i_smp_chip.nx_mmio_range.enabled)
+        if (i_smp_chip.nx_mmio_range.enabled && i_smp_chip.nx_enabled)
         {
             FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing NX MMIO BAR register");
             rc = proc_setup_bars_common_write_bar_reg(
@@ -2337,7 +2365,7 @@ proc_setup_bars_write_local_chip_region_bars(
         }
 
         // NX (non-mirrored)
-        if (i_smp_chip.non_mirrored_range.enabled)
+        if (i_smp_chip.non_mirrored_range.enabled && i_smp_chip.nx_enabled)
         {
             FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing NX APC Nodal Non-Mirrored BAR register");
             rc = proc_setup_bars_common_write_bar_reg(
@@ -2365,7 +2393,7 @@ proc_setup_bars_write_local_chip_region_bars(
         }
 
         // NX (mirrored)
-        if (i_smp_chip.mirrored_range.enabled)
+        if (i_smp_chip.mirrored_range.enabled && i_smp_chip.nx_enabled)
         {
             FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing NX APC Nodal Mirrored BAR register");
             rc = proc_setup_bars_common_write_bar_reg(
@@ -2457,24 +2485,30 @@ proc_setup_bars_write_local_chip_region_bars(
         }
 
         // PCIe (non-mirrored/mirrored)
-        rc = proc_setup_bars_pcie_write_local_chip_memory_bars(
-            i_smp_chip.chip->this_chip,
-            i_smp_chip.non_mirrored_range,
-            i_smp_chip.mirrored_range);
-        if (!rc.ok())
+        if (i_smp_chip.pcie_enabled)
         {
-            FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_pcie_write_local_chip_memory_bars");
-            break;
+            rc = proc_setup_bars_pcie_write_local_chip_memory_bars(
+                i_smp_chip.chip->this_chip,
+                i_smp_chip.non_mirrored_range,
+                i_smp_chip.mirrored_range);
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_pcie_write_local_chip_memory_bars");
+                break;
+            }
         }
 
         // PCIe (IO)
-        rc = proc_setup_bars_pcie_write_io_bar_regs(
-            i_smp_chip.chip->this_chip,
-            i_smp_chip.pcie_ranges);
-        if (!rc.ok())
+        if (i_smp_chip.pcie_enabled)
         {
-            FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_pcie_write_io_bar_regs");
-            break;
+            rc = proc_setup_bars_pcie_write_io_bar_regs(
+                i_smp_chip.chip->this_chip,
+                i_smp_chip.pcie_ranges);
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_pcie_write_io_bar_regs");
+                break;
+            }
         }
     } while(0);
 
@@ -2528,7 +2562,7 @@ proc_setup_bars_write_local_node_region_bars(
     do
     {
         // NX (non-mirrored)
-        if (i_smp_node.non_mirrored_range.enabled)
+        if (i_smp_node.non_mirrored_range.enabled && i_smp_chip.nx_enabled)
         {
             FAPI_DBG("proc_setup_bars_write_local_node_region_bars: Writing NX APC Group Non-Mirrored BAR register");
             rc = proc_setup_bars_common_write_bar_reg(
@@ -2556,7 +2590,7 @@ proc_setup_bars_write_local_node_region_bars(
         }
 
         // NX (mirrored)
-        if (i_smp_node.mirrored_range.enabled)
+        if (i_smp_node.mirrored_range.enabled && i_smp_chip.nx_enabled)
         {
             FAPI_DBG("proc_setup_bars_write_local_node_region_bars: Writing NX APC Group Mirrored BAR register");
             rc = proc_setup_bars_common_write_bar_reg(
@@ -2616,14 +2650,17 @@ proc_setup_bars_write_local_node_region_bars(
         }
 
         // PCIe (non-mirrored/mirrored)
-        rc = proc_setup_bars_pcie_write_local_node_memory_bars(
-            i_smp_chip.chip->this_chip,
-            i_smp_node.non_mirrored_range,
-            i_smp_node.mirrored_range);
-        if (!rc.ok())
+        if (i_smp_chip.pcie_enabled)
         {
-            FAPI_ERR("proc_setup_bars_write_local_node_region_bars: Error from proc_setup_bars_pcie_write_local_node_memory_bars");
-            break;
+            rc = proc_setup_bars_pcie_write_local_node_memory_bars(
+                i_smp_chip.chip->this_chip,
+                i_smp_node.non_mirrored_range,
+                i_smp_node.mirrored_range);
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_setup_bars_write_local_node_region_bars: Error from proc_setup_bars_pcie_write_local_node_memory_bars");
+                break;
+            }
         }
     } while(0);
 
@@ -2848,15 +2885,18 @@ proc_setup_bars_write_foreign_region_bars(
         };
 
         // PCIe (near/far)
-        rc = proc_setup_bars_pcie_write_foreign_memory_bars(
-            i_smp_chip.chip->this_chip,
-            process_links,
-            i_smp_chip.foreign_near_ranges,
-            i_smp_chip.foreign_far_ranges);
-        if (!rc.ok())
+        if (i_smp_chip.pcie_enabled)
         {
-            FAPI_ERR("proc_setup_bars_write_foreign_region_bars: Error from proc_setup_bars_pcie_write_foreign_memory_bars");
-            break;
+            rc = proc_setup_bars_pcie_write_foreign_memory_bars(
+                i_smp_chip.chip->this_chip,
+                process_links,
+                i_smp_chip.foreign_near_ranges,
+                i_smp_chip.foreign_far_ranges);
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_setup_bars_write_foreign_region_bars: Error from proc_setup_bars_pcie_write_foreign_memory_bars");
+                break;
+            }
         }
 
         // process ranges
@@ -2880,7 +2920,7 @@ proc_setup_bars_write_foreign_region_bars(
                     i_smp_chip.foreign_near_ranges[r]);
                 if (!rc.ok())
                 {
-                    FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg");
+                    FAPI_ERR("proc_setup_bars_write_foreign_region_bars: Error from proc_setup_bars_common_write_bar_reg");
                     break;
                 }
 
@@ -2896,7 +2936,7 @@ proc_setup_bars_write_foreign_region_bars(
                     i_smp_chip.foreign_near_ranges[r]);
                 if (!rc.ok())
                 {
-                    FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg");
+                    FAPI_ERR("proc_setup_bars_write_foreign_region_bars: Error from proc_setup_bars_common_write_bar_reg");
                     break;
                 }
 
@@ -2912,40 +2952,46 @@ proc_setup_bars_write_foreign_region_bars(
                     i_smp_chip.foreign_near_ranges[r]);
                 if (!rc.ok())
                 {
-                    FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg");
+                    FAPI_ERR("proc_setup_bars_write_foreign_region_bars: Error from proc_setup_bars_common_write_bar_reg");
                     break;
                 }
 
                 // NX APC (near)
-                FAPI_DBG("proc_setup_bars_write_foreign_region_bars: Writing NX APC F%d Near BAR register",
-                         r);
-                rc = proc_setup_bars_common_write_bar_reg(
-                    i_smp_chip.chip->this_chip,
-                    (r == 0)?
-                    NX_APC_NEAR_BAR_F0_0x02013031:
-                    NX_APC_NEAR_BAR_F1_0x02013033,
-                    common_f_scope_bar_reg_def,
-                    i_smp_chip.foreign_near_ranges[r]);
-                if (!rc.ok())
+                if (i_smp_chip.nx_enabled)
                 {
-                    FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                    break;
+                    FAPI_DBG("proc_setup_bars_write_foreign_region_bars: Writing NX APC F%d Near BAR register",
+                             r);
+                    rc = proc_setup_bars_common_write_bar_reg(
+                        i_smp_chip.chip->this_chip,
+                        (r == 0)?
+                        NX_APC_NEAR_BAR_F0_0x02013031:
+                        NX_APC_NEAR_BAR_F1_0x02013033,
+                        common_f_scope_bar_reg_def,
+                        i_smp_chip.foreign_near_ranges[r]);
+                    if (!rc.ok())
+                    {
+                        FAPI_ERR("proc_setup_bars_write_foreign_region_bars: Error from proc_setup_bars_common_write_bar_reg");
+                        break;
+                    }
                 }
 
                 // NX (near)
-                FAPI_DBG("proc_setup_bars_write_foreign_region_bars: Writing NX F%d Near BAR register",
-                         r);
-                rc = proc_setup_bars_common_write_bar_reg(
-                    i_smp_chip.chip->this_chip,
-                    (r == 0)?
-                    NX_NEAR_BAR_F0_0x02013099:
-                    NX_NEAR_BAR_F1_0x0201309B,
-                    common_f_scope_bar_reg_def,
-                    i_smp_chip.foreign_near_ranges[r]);
-                if (!rc.ok())
+                if (i_smp_chip.nx_enabled)
                 {
-                    FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                    break;
+                    FAPI_DBG("proc_setup_bars_write_foreign_region_bars: Writing NX F%d Near BAR register",
+                             r);
+                    rc = proc_setup_bars_common_write_bar_reg(
+                        i_smp_chip.chip->this_chip,
+                        (r == 0)?
+                        NX_NEAR_BAR_F0_0x02013099:
+                        NX_NEAR_BAR_F1_0x0201309B,
+                        common_f_scope_bar_reg_def,
+                        i_smp_chip.foreign_near_ranges[r]);
+                    if (!rc.ok())
+                    {
+                        FAPI_ERR("proc_setup_bars_write_foreign_region_bars: Error from proc_setup_bars_common_write_bar_reg");
+                        break;
+                    }
                 }
 
                 // MCD (near only)
@@ -2962,7 +3008,7 @@ proc_setup_bars_write_foreign_region_bars(
                     i_smp_chip.foreign_near_ranges[r]);
                 if (!rc.ok())
                 {
-                    FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg");
+                    FAPI_ERR("proc_setup_bars_write_foreign_region_bars: Error from proc_setup_bars_common_write_bar_reg");
                     break;
                 }
             }
@@ -2983,7 +3029,7 @@ proc_setup_bars_write_foreign_region_bars(
                     i_smp_chip.foreign_far_ranges[r]);
                 if (!rc.ok())
                 {
-                    FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg");
+                    FAPI_ERR("proc_setup_bars_write_foreign_region_bars: Error from proc_setup_bars_common_write_bar_reg");
                     break;
                 }
 
@@ -2999,7 +3045,7 @@ proc_setup_bars_write_foreign_region_bars(
                     i_smp_chip.foreign_far_ranges[r]);
                 if (!rc.ok())
                 {
-                    FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg");
+                    FAPI_ERR("proc_setup_bars_write_foreign_region_bars: Error from proc_setup_bars_common_write_bar_reg");
                     break;
                 }
 
@@ -3015,40 +3061,46 @@ proc_setup_bars_write_foreign_region_bars(
                     i_smp_chip.foreign_far_ranges[r]);
                 if (!rc.ok())
                 {
-                    FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg");
+                    FAPI_ERR("proc_setup_bars_write_foreign_region_bars: Error from proc_setup_bars_common_write_bar_reg");
                     break;
                 }
 
                 // NX APC (far)
-                FAPI_DBG("proc_setup_bars_write_foreign_region_bars: Writing NX APC F%d Far BAR register",
-                         r);
-                rc = proc_setup_bars_common_write_bar_reg(
-                    i_smp_chip.chip->this_chip,
-                    (r == 0)?
-                    NX_APC_FAR_BAR_F0_0x02013032:
-                    NX_APC_FAR_BAR_F1_0x02013034,
-                    common_f_scope_bar_reg_def,
-                    i_smp_chip.foreign_far_ranges[r]);
-                if (!rc.ok())
+                if (i_smp_chip.nx_enabled)
                 {
-                    FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                    break;
+                    FAPI_DBG("proc_setup_bars_write_foreign_region_bars: Writing NX APC F%d Far BAR register",
+                             r);
+                    rc = proc_setup_bars_common_write_bar_reg(
+                        i_smp_chip.chip->this_chip,
+                        (r == 0)?
+                        NX_APC_FAR_BAR_F0_0x02013032:
+                        NX_APC_FAR_BAR_F1_0x02013034,
+                        common_f_scope_bar_reg_def,
+                        i_smp_chip.foreign_far_ranges[r]);
+                    if (!rc.ok())
+                    {
+                        FAPI_ERR("proc_setup_bars_write_foreign_region_bars: Error from proc_setup_bars_common_write_bar_reg");
+                        break;
+                    }
                 }
 
                 // NX (far)
-                FAPI_DBG("proc_setup_bars_write_foreign_region_bars: Writing NX F%d Far BAR register",
-                         r);
-                rc = proc_setup_bars_common_write_bar_reg(
-                    i_smp_chip.chip->this_chip,
-                    (r == 0)?
-                    NX_FAR_BAR_F0_0x0201309A:
-                    NX_FAR_BAR_F1_0x0201309C,
-                    common_f_scope_bar_reg_def,
-                    i_smp_chip.foreign_far_ranges[r]);
-                if (!rc.ok())
+                if (i_smp_chip.nx_enabled)
                 {
-                    FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                    break;
+                    FAPI_DBG("proc_setup_bars_write_foreign_region_bars: Writing NX F%d Far BAR register",
+                             r);
+                    rc = proc_setup_bars_common_write_bar_reg(
+                        i_smp_chip.chip->this_chip,
+                        (r == 0)?
+                        NX_FAR_BAR_F0_0x0201309A:
+                        NX_FAR_BAR_F1_0x0201309C,
+                        common_f_scope_bar_reg_def,
+                        i_smp_chip.foreign_far_ranges[r]);
+                    if (!rc.ok())
+                    {
+                        FAPI_ERR("proc_setup_bars_write_foreign_region_bars: Error from proc_setup_bars_common_write_bar_reg");
+                        break;
+                    }
                 }
             }
         }
@@ -3090,7 +3142,7 @@ proc_setup_bars_find_node(
                                            node_id);
         if (!rc.ok())
         {
-            FAPI_ERR("proc_setup_bars_process_chip: Error from proc_fab_smp_get_node_id_attr");
+            FAPI_ERR("proc_setup_bars_find_node: Error from proc_fab_smp_get_node_id_attr");
             break;
         }
 
@@ -3102,7 +3154,7 @@ proc_setup_bars_find_node(
         // no match node found, exit
         if (n_iter == i_smp.nodes.end())
         {
-            FAPI_ERR("proc_setup_bars_process_chip: insert_chip: Error encountered finding node in SMP");
+            FAPI_ERR("proc_setup_bars_find_node: insert_chip: Error encountered finding node in SMP");
             FAPI_SET_HWP_ERROR(rc,
                 RC_PROC_SETUP_BARS_NODE_FIND_INTERNAL_ERR);
             break;
diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.H b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.H
index df3acb937..494210403 100644
--- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.H
+++ b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.H
@@ -1,27 +1,26 @@
-/*  IBM_PROLOG_BEGIN_TAG
- *  This is an automatically generated prolog.
- *
- *  $Source: src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.H $
- *
- *  IBM CONFIDENTIAL
- *
- *  COPYRIGHT International Business Machines Corp. 2012
- *
- *  p1
- *
- *  Object Code Only (OCO) source materials
- *  Licensed Internal Code Source Materials
- *  IBM HostBoot Licensed Internal Code
- *
- *  The source code for this program is not published or other-
- *  wise divested of its trade secrets, irrespective of what has
- *  been deposited with the U.S. Copyright Office.
- *
- *  Origin: 30
- *
- *  IBM_PROLOG_END_TAG
- */
-// $Id: proc_setup_bars.H,v 1.3 2012/07/23 17:47:41 jmcgill Exp $
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.H $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2012,2013              */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: proc_setup_bars.H,v 1.4 2012/12/11 23:59:31 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_setup_bars.H,v $
 //------------------------------------------------------------------------------
 // *|
@@ -318,6 +317,9 @@ struct proc_setup_bars_smp_chip
     // fabric chip/node ID
     proc_fab_smp_chip_id chip_id;
     proc_fab_smp_node_id node_id;
+    // partial good attributes
+    bool nx_enabled;
+    bool pcie_enabled;
     // select for PCIe/DSMP mux (one per link)
     bool pcie_not_f_link[PROC_FAB_SMP_NUM_F_LINKS];
     // real address ranges covered by resources on this chip
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C b/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C
index f01d83112..f5ab3267f 100755
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012                   */
+/* COPYRIGHT International Business Machines Corp. 2012,2013              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_draminit.C,v 1.43 2012/12/07 13:44:07 bellows Exp $
+// $Id: mss_draminit.C,v 1.44 2013/01/25 15:16:21 jdsloat Exp $
 //------------------------------------------------------------------------------
 // Don't forget to create CVS comments when you check in your changes!
 //------------------------------------------------------------------------------
@@ -28,6 +28,7 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//  1.44   | jdsloat  | 01/25/13| Address Mirror Mode added for dual drop CDIMMs
 //  1.43   | bellows  | 12/06/12| Fixed Review Comment
 //  1.42   | jdsloat  | 12/02/12| SHADOW REG PRINT OUT FIX
 //  1.41   | jdsloat  | 11/19/12| RCD Bit order fix.
@@ -152,6 +153,7 @@ ReturnCode mss_draminit_cloned(Target& i_target)
     uint8_t dram_gen; 
     uint8_t dimm_type;
     uint8_t rank_pair_group = 0;
+    uint8_t bit_position = 0;
     ecmdDataBufferBase data_buffer_64(64);
     ecmdDataBufferBase mrs0(16); 
     ecmdDataBufferBase mrs1(16);
@@ -161,7 +163,12 @@ ReturnCode mss_draminit_cloned(Target& i_target)
     uint16_t MRS1 = 0;
     uint16_t MRS2 = 0;
     uint16_t MRS3 = 0;
+    uint8_t num_drops_per_port;
     uint8_t primary_ranks_array[4][2]; //primary_ranks_array[group][port]
+    uint8_t secondary_ranks_array[4][2]; //secondary_ranks_array[group][port]
+    uint8_t tertiary_ranks_array[4][2]; //tertiary_ranks_array[group][port]
+    uint8_t quaternary_ranks_array[4][2]; //quaternary_ranks_array[group][port]
+    
  
     //populate primary_ranks_arrays_array
     rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP0, &i_target, primary_ranks_array[0]);
@@ -172,13 +179,194 @@ ReturnCode mss_draminit_cloned(Target& i_target)
     if(rc) return rc;
     rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP3, &i_target, primary_ranks_array[3]);
     if(rc) return rc;
+    rc = FAPI_ATTR_GET(ATTR_EFF_SECONDARY_RANK_GROUP0, &i_target, secondary_ranks_array[0]);
+    if(rc) return rc;
+    rc = FAPI_ATTR_GET(ATTR_EFF_SECONDARY_RANK_GROUP1, &i_target, secondary_ranks_array[1]);
+    if(rc) return rc;
+    rc = FAPI_ATTR_GET(ATTR_EFF_SECONDARY_RANK_GROUP2, &i_target, secondary_ranks_array[2]);
+    if(rc) return rc;
+    rc = FAPI_ATTR_GET(ATTR_EFF_SECONDARY_RANK_GROUP3, &i_target, secondary_ranks_array[3]);
+    if(rc) return rc;
+    rc = FAPI_ATTR_GET(ATTR_EFF_TERTIARY_RANK_GROUP0, &i_target, tertiary_ranks_array[0]);
+    if(rc) return rc;
+    rc = FAPI_ATTR_GET(ATTR_EFF_TERTIARY_RANK_GROUP1, &i_target, tertiary_ranks_array[1]);
+    if(rc) return rc;
+    rc = FAPI_ATTR_GET(ATTR_EFF_TERTIARY_RANK_GROUP2, &i_target, tertiary_ranks_array[2]);
+    if(rc) return rc;
+    rc = FAPI_ATTR_GET(ATTR_EFF_TERTIARY_RANK_GROUP3, &i_target, tertiary_ranks_array[3]);
+    if(rc) return rc;
+    rc = FAPI_ATTR_GET(ATTR_EFF_QUATERNARY_RANK_GROUP0, &i_target, quaternary_ranks_array[0]);
+    if(rc) return rc;
+    rc = FAPI_ATTR_GET(ATTR_EFF_QUATERNARY_RANK_GROUP1, &i_target, quaternary_ranks_array[1]);
+    if(rc) return rc;
+    rc = FAPI_ATTR_GET(ATTR_EFF_QUATERNARY_RANK_GROUP2, &i_target, quaternary_ranks_array[2]);
+    if(rc) return rc;
+    rc = FAPI_ATTR_GET(ATTR_EFF_QUATERNARY_RANK_GROUP3, &i_target, quaternary_ranks_array[3]);
+    if(rc) return rc;
 
 
+
+    rc = FAPI_ATTR_GET(ATTR_EFF_NUM_DROPS_PER_PORT, &i_target, num_drops_per_port);
+    if(rc) return rc;
     rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_GEN, &i_target, dram_gen);
     if(rc) return rc;
     rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target, dimm_type);
     if(rc) return rc;
 
+    // Check to see if it's Dual drop and needs address mirror mode.  Set the approriate flag. 
+    if (   (dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_CDIMM)
+	&& (num_drops_per_port == ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL)
+	&& (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3) )
+    {
+
+	FAPI_INF( "Setting Address Mirroring in the PHY");
+
+	//Set the Address and BA bits affected by mirroring
+	rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P0_0x8000C0110301143F, data_buffer_64);
+	if(rc) return rc;
+	rc_num = rc_num | data_buffer_64.setBit(58);
+	rc_num = rc_num | data_buffer_64.setBit(59);
+	rc_num = rc_num | data_buffer_64.setBit(60);
+	rc_num = rc_num | data_buffer_64.setBit(62);
+	rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P0_0x8000C0110301143F, data_buffer_64);
+	if(rc) return rc;
+
+	rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P1_0x8001C0110301143F, data_buffer_64);
+	if(rc) return rc;
+	rc_num = rc_num | data_buffer_64.setBit(58);
+	rc_num = rc_num | data_buffer_64.setBit(59);
+	rc_num = rc_num | data_buffer_64.setBit(60);
+	rc_num = rc_num | data_buffer_64.setBit(62);
+	rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P1_0x8001C0110301143F, data_buffer_64);
+	if(rc) return rc;
+
+	for ( port_number = 0; port_number < MAX_NUM_PORTS; port_number++)
+	{
+	    for ( rank_pair_group = 0; rank_pair_group < MAX_NUM_RANK_PAIR; rank_pair_group++)
+	    {
+		// Set the rank pairs that will be affected.
+		if ( port_number == 0 )
+		{
+		    if ( ( primary_ranks_array[rank_pair_group][port_number] == 0x04) ||
+			 ( primary_ranks_array[rank_pair_group][port_number] == 0x05) ||
+			 ( primary_ranks_array[rank_pair_group][port_number] == 0x06) ||
+			 ( primary_ranks_array[rank_pair_group][port_number] == 0x07) )
+		    {
+			FAPI_INF( "Address Mirroring on PORT%d RANKPAIR%d RANK%d", port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]);
+			bit_position = 2 * rank_pair_group + 48;
+			FAPI_INF( "Setting bit %d", bit_position);
+			rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P0_0x8000C0110301143F, data_buffer_64);
+			if(rc) return rc;
+			rc_num = rc_num | data_buffer_64.setBit(bit_position);
+			rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P0_0x8000C0110301143F, data_buffer_64);
+			if(rc) return rc;
+		    }
+		    if ( ( secondary_ranks_array[rank_pair_group][port_number] == 0x04) ||
+			 ( secondary_ranks_array[rank_pair_group][port_number] == 0x05) ||
+			 ( secondary_ranks_array[rank_pair_group][port_number] == 0x06) ||
+			 ( secondary_ranks_array[rank_pair_group][port_number] == 0x07) )
+		    {
+			FAPI_INF( "Address Mirroring on PORT%d RANKPAIR%d RANK%d", port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]);
+			bit_position = 2 * rank_pair_group + 49;
+			FAPI_INF( "Setting bit %d", bit_position);
+			rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P0_0x8000C0110301143F, data_buffer_64);
+			if(rc) return rc;
+			rc_num = rc_num | data_buffer_64.setBit(bit_position);
+			rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P0_0x8000C0110301143F, data_buffer_64);
+			if(rc) return rc;
+		    }
+		    if ( ( tertiary_ranks_array[rank_pair_group][port_number] == 0x04) ||
+			 ( tertiary_ranks_array[rank_pair_group][port_number] == 0x05) ||
+			 ( tertiary_ranks_array[rank_pair_group][port_number] == 0x06) ||
+			 ( tertiary_ranks_array[rank_pair_group][port_number] == 0x07) )
+		    {
+			FAPI_INF( "Address Mirroring on PORT%d RANKPAIR%d RANK%d", port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]);
+			bit_position = 2 * rank_pair_group + 48;
+			FAPI_INF( "Setting bit %d", bit_position);
+			rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P0_0x8000C0350301143F, data_buffer_64);
+			if(rc) return rc;
+			rc_num = rc_num | data_buffer_64.setBit(bit_position);
+			rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P0_0x8000C0350301143F, data_buffer_64);
+			if(rc) return rc;
+		    }
+		    if ( ( quaternary_ranks_array[rank_pair_group][port_number] == 0x04) ||
+			 ( quaternary_ranks_array[rank_pair_group][port_number] == 0x05) ||
+			 ( quaternary_ranks_array[rank_pair_group][port_number] == 0x06) ||
+			 ( quaternary_ranks_array[rank_pair_group][port_number] == 0x07) )
+		    {
+			FAPI_INF( "Address Mirroring on PORT%d RANKPAIR%d RANK%d", port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]);
+			bit_position = 2 * rank_pair_group + 49;
+			FAPI_INF( "Setting bit %d", bit_position);
+			rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P0_0x8000C0350301143F, data_buffer_64);
+			if(rc) return rc;
+			rc_num = rc_num | data_buffer_64.setBit(bit_position);
+			rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P0_0x8000C0350301143F, data_buffer_64);
+			if(rc) return rc;
+		    }
+		}
+		if ( port_number == 1 )
+		{
+		    if ( ( primary_ranks_array[rank_pair_group][port_number] == 0x04) ||
+			 ( primary_ranks_array[rank_pair_group][port_number] == 0x05) ||
+			 ( primary_ranks_array[rank_pair_group][port_number] == 0x06) ||
+			 ( primary_ranks_array[rank_pair_group][port_number] == 0x07) )
+		    {
+			FAPI_INF( "Address Mirroring on PORT%d RANKPAIR%d RANK%d", port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]);
+			bit_position = 2 * rank_pair_group + 48;
+			FAPI_INF( "Setting bit %d", bit_position);
+			rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P1_0x8001C0110301143F, data_buffer_64);
+			if(rc) return rc;
+			rc_num = rc_num | data_buffer_64.setBit(bit_position);
+			rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P1_0x8001C0110301143F, data_buffer_64);
+			if(rc) return rc;
+		    }
+		    if ( ( secondary_ranks_array[rank_pair_group][port_number] == 0x04) ||
+			 ( secondary_ranks_array[rank_pair_group][port_number] == 0x05) ||
+			 ( secondary_ranks_array[rank_pair_group][port_number] == 0x06) ||
+			 ( secondary_ranks_array[rank_pair_group][port_number] == 0x07) )
+		    {
+			FAPI_INF( "Address Mirroring on PORT%d RANKPAIR%d RANK%d", port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]);
+			bit_position = 2 * rank_pair_group + 49;
+			FAPI_INF( "Setting bit %d", bit_position);
+			rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P1_0x8001C0110301143F, data_buffer_64);
+			if(rc) return rc;
+			rc_num = rc_num | data_buffer_64.setBit(bit_position);
+			rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P1_0x8001C0110301143F, data_buffer_64);
+			if(rc) return rc;
+		    }
+		    if ( ( tertiary_ranks_array[rank_pair_group][port_number] == 0x04) ||
+			 ( tertiary_ranks_array[rank_pair_group][port_number] == 0x05) ||
+			 ( tertiary_ranks_array[rank_pair_group][port_number] == 0x06) ||
+			 ( tertiary_ranks_array[rank_pair_group][port_number] == 0x07) )
+		    {
+			FAPI_INF( "Address Mirroring on PORT%d RANKPAIR%d RANK%d", port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]);
+			bit_position = 2 * rank_pair_group + 48;
+			FAPI_INF( "Setting bit %d", bit_position);
+			rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P1_0x8001C0350301143F, data_buffer_64);
+			if(rc) return rc;
+			rc_num = rc_num | data_buffer_64.setBit(bit_position);
+			rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P1_0x8001C0350301143F, data_buffer_64);
+			if(rc) return rc;
+		    }
+		    if ( ( quaternary_ranks_array[rank_pair_group][port_number] == 0x04) ||
+			 ( quaternary_ranks_array[rank_pair_group][port_number] == 0x05) ||
+			 ( quaternary_ranks_array[rank_pair_group][port_number] == 0x06) ||
+			 ( quaternary_ranks_array[rank_pair_group][port_number] == 0x07) )
+		    {
+			FAPI_INF( "Address Mirroring on PORT%d RANKPAIR%d RANK%d", port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]);
+			bit_position = 2 * rank_pair_group + 49;
+			FAPI_INF( "Setting bit %d", bit_position);
+			rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P1_0x8001C0350301143F, data_buffer_64);
+			if(rc) return rc;
+			rc_num = rc_num | data_buffer_64.setBit(bit_position);
+			rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P1_0x8001C0350301143F, data_buffer_64);
+			if(rc) return rc;
+		    }
+		}
+
+	    }
+	}
+    }
 
     if ((!(dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM)) && (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3))
     {
@@ -777,7 +965,8 @@ ReturnCode mss_mrs_load(
     uint32_t rc_num = 0;
 
     ecmdDataBufferBase data_buffer_64(64);
-
+    ecmdDataBufferBase address_pre_AMM_16(16);
+    ecmdDataBufferBase bank_pre_AMM_3(3);
     ecmdDataBufferBase address_16(16);
     ecmdDataBufferBase bank_3(3);
     ecmdDataBufferBase activate_1(1);
@@ -812,6 +1001,10 @@ ReturnCode mss_mrs_load(
     uint16_t MRS2 = 0;
     uint16_t MRS3 = 0;
 
+    uint16_t mirror_mode_ba = 0;
+    uint16_t mirror_mode_ad  = 0;
+
+
     uint16_t num_ranks = 0;
 
     FAPI_INF( "+++++++++++++++++++++ LOADING MRS SETTINGS FOR PORT %d +++++++++++++++++++++", i_port_number);
@@ -820,6 +1013,11 @@ ReturnCode mss_mrs_load(
     rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target, num_ranks_array);
     if(rc) return rc;
 
+    uint8_t dimm_type;
+    rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target, dimm_type);
+    if(rc) return rc;
+
+
     //Lines commented out in the following section are waiting for xml attribute adds
     //MRS0
     uint8_t dram_bl;
@@ -1262,33 +1460,75 @@ ReturnCode mss_mrs_load(
                         // Setting the bank address
                         if (mrs_number == 0)
                         {
-                            rc_num = rc_num | address_16.insert(mrs2, 0, 16, 0);
-			    rc_num = rc_num | bank_3.insert((uint8_t) MRS2_BA, 0, 1, 7);
-                            rc_num = rc_num | bank_3.insert((uint8_t) MRS2_BA, 1, 1, 6);
-                            rc_num = rc_num | bank_3.insert((uint8_t) MRS2_BA, 2, 1, 5);
+                            rc_num = rc_num | address_pre_AMM_16.insert(mrs2, 0, 16, 0);
+			    rc_num = rc_num | bank_pre_AMM_3.insert((uint8_t) MRS2_BA, 0, 1, 7);
+                            rc_num = rc_num | bank_pre_AMM_3.insert((uint8_t) MRS2_BA, 1, 1, 6);
+                            rc_num = rc_num | bank_pre_AMM_3.insert((uint8_t) MRS2_BA, 2, 1, 5);
                         }
                         else if ( mrs_number == 1)
                         {
-                            rc_num = rc_num | address_16.insert(mrs3, 0, 16, 0);
-			    rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 0, 1, 7);
-                            rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 1, 1, 6);
-                            rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 2, 1, 5);
+                            rc_num = rc_num | address_pre_AMM_16.insert(mrs3, 0, 16, 0);
+			    rc_num = rc_num | bank_pre_AMM_3.insert((uint8_t) MRS3_BA, 0, 1, 7);
+                            rc_num = rc_num | bank_pre_AMM_3.insert((uint8_t) MRS3_BA, 1, 1, 6);
+                            rc_num = rc_num | bank_pre_AMM_3.insert((uint8_t) MRS3_BA, 2, 1, 5);
                         }
                         else if ( mrs_number == 2)
                         {
-                            rc_num = rc_num | address_16.insert(mrs1, 0, 16, 0);
-			    rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 0, 1, 7);
-                            rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 1, 1, 6);
-                            rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 2, 1, 5);
+                            rc_num = rc_num | address_pre_AMM_16.insert(mrs1, 0, 16, 0);
+			    rc_num = rc_num | bank_pre_AMM_3.insert((uint8_t) MRS1_BA, 0, 1, 7);
+                            rc_num = rc_num | bank_pre_AMM_3.insert((uint8_t) MRS1_BA, 1, 1, 6);
+                            rc_num = rc_num | bank_pre_AMM_3.insert((uint8_t) MRS1_BA, 2, 1, 5);
                         }
                         else if ( mrs_number == 3)
                         {
-                            rc_num = rc_num | address_16.insert(mrs0, 0, 16, 0);
-			    rc_num = rc_num | bank_3.insert((uint8_t) MRS0_BA, 0, 1, 7);
-                            rc_num = rc_num | bank_3.insert((uint8_t) MRS0_BA, 1, 1, 6);
-                            rc_num = rc_num | bank_3.insert((uint8_t) MRS0_BA, 2, 1, 5);
+                            rc_num = rc_num | address_pre_AMM_16.insert(mrs0, 0, 16, 0);
+			    rc_num = rc_num | bank_pre_AMM_3.insert((uint8_t) MRS0_BA, 0, 1, 7);
+                            rc_num = rc_num | bank_pre_AMM_3.insert((uint8_t) MRS0_BA, 1, 1, 6);
+                            rc_num = rc_num | bank_pre_AMM_3.insert((uint8_t) MRS0_BA, 2, 1, 5);
                         }
-                
+
+			if ( (dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_CDIMM) && (dimm_number == 1) )
+			{
+			    FAPI_INF( "ADDRESS MIRRORING ON PORT%d DIMM%d RANK%d", i_port_number, dimm_number, rank_number);
+
+			    rc_num = rc_num | address_pre_AMM_16.extractPreserve(&mirror_mode_ad, 0, 16, 0);
+			    FAPI_INF( "PRE - MIRROR MODE ADDRESS: 0x%04X", mirror_mode_ad);
+			    rc_num = rc_num | bank_pre_AMM_3.extractPreserve(&mirror_mode_ba, 0, 3, 0);
+			    FAPI_INF( "PRE - MIRROR MODE BANK ADDRESS: 0x%04X", mirror_mode_ba);
+
+			    //Initialize address and bank address as the same pre mirror mode swizzle
+			    rc_num = rc_num | address_16.insert(address_pre_AMM_16, 0, 16, 0);
+			    rc_num = rc_num | bank_3.insert(bank_pre_AMM_3, 0, 3, 0);
+
+			    //Swap A3 and A4
+			    rc_num = rc_num | address_16.insert(address_pre_AMM_16, 4, 1, 3);
+			    rc_num = rc_num | address_16.insert(address_pre_AMM_16, 3, 1, 4);
+
+			    //Swap A5 and A6
+			    rc_num = rc_num | address_16.insert(address_pre_AMM_16, 6, 1, 5);
+			    rc_num = rc_num | address_16.insert(address_pre_AMM_16, 5, 1, 6);
+
+			    //Swap A7 and A8
+			    rc_num = rc_num | address_16.insert(address_pre_AMM_16, 8, 1, 7);
+			    rc_num = rc_num | address_16.insert(address_pre_AMM_16, 7, 1, 8);
+
+			    //Swap BA0 and BA1
+			    rc_num = rc_num | bank_3.insert(bank_pre_AMM_3, 1, 1, 0);
+			    rc_num = rc_num | bank_3.insert(bank_pre_AMM_3, 0, 1, 1);
+
+			    rc_num = rc_num | address_16.extractPreserve(&mirror_mode_ad, 0, 16, 0);
+			    FAPI_INF( "POST - MIRROR MODE ADDRESS: 0x%04X", mirror_mode_ad);
+			    rc_num = rc_num | bank_3.extractPreserve(&mirror_mode_ba, 0, 3, 0);
+			    FAPI_INF( "POST - MIRROR MODE BANK ADDRESS: 0x%04X", mirror_mode_ba);
+
+			}
+			else
+			{
+			    // No need to worry about swizzle
+			    rc_num = rc_num | address_16.insert(address_pre_AMM_16, 0, 16, 0);
+			    rc_num = rc_num | bank_3.insert(bank_pre_AMM_3, 0, 3, 0);
+			}
+
                         if (rc_num)
                         {
                             FAPI_ERR( "mss_mrs_load: Error setting up buffers");
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C
index 2f216693c..954849674 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_draminit_mc.C,v 1.29 2013/01/14 19:29:25 jdsloat Exp $
+// $Id: mss_draminit_mc.C,v 1.31 2013/01/21 16:47:20 lapietra Exp $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
 // *! All Rights Reserved -- Property of IBM
@@ -44,6 +44,8 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//  1.31   | dcadiga  |21-JAN-13| Fixed variable name for memcal_interval (coded as memcal_iterval...)
+//  1.30   | dcadiga  |21-JAN-13| Hardcoded memcal interval to 0 (disabled) until attribute for EC is available
 //  1.29   | jdsloat  |14-JAN-13| Owner changed to Dave Cadigan.
 //  1.28   | bellows  |01-JAN-13| Added ECC Enable 64-byte data/checkbit inversion (from jdsloat)
 //  1.27   | gollub   |21-DEC-12| Calling mss_unmask_maint_errors and mss_unmask_inband_errors after mss_draminit_mc_cloned
@@ -247,6 +249,10 @@ ReturnCode mss_enable_periodic_cal (Target& i_target)
     uint32_t memcal_iterval; //  00 = Disable
     rc = FAPI_ATTR_GET(ATTR_EFF_MEMCAL_INTERVAL, &i_target, memcal_iterval);
     if(rc) return rc;
+    //dcadigan workaround for rd phase select issue.  Hardcoded until we have an attribute for chip EC
+    FAPI_INF("+++ RD Phase Select Workaround, DISABLING MEMCAL VIA HARDCODE +++");
+    memcal_iterval = 0;
+
 
     uint32_t zq_cal_iterval; //  00 = Disable
     rc = FAPI_ATTR_GET(ATTR_EFF_ZQCAL_INTERVAL, &i_target, zq_cal_iterval);
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.C
index a2bf7b4f8..c576bec61 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_generic_shmoo.C,v 1.23 2013/01/18 12:04:57 sasethur Exp $
+// $Id: mss_generic_shmoo.C,v 1.27 2013/01/22 17:31:26 sasethur Exp $
 // *!***************************************************************************
 // *! (C) Copyright International Business Machines Corp. 1997, 1998
 // *!           All Rights Reserved -- Property of IBM
@@ -39,8 +39,10 @@
 //------------------------------------------------------------------------------
 // Version:|Author: | Date:   | Comment:
 // --------|--------|---------|--------------------------------------------------
+//   1.26  |abhijit	|01/21/13 | fixed fw comments  
+//   1.25  |abhijit	|01/21/13 | fixed the constructor definition 
 //   1.21  |sasethur|01/17/13 | Updated for sanity mcbist function
-//   1.20  |abhijith|01/11/13 | Updated for change in setup_mcbist function
+//   1.20  |abhijit |01/11/13 | Updated for change in setup_mcbist function
 //   1.19  |aditya  |01/07/13 | Updated for change in setup_mcbist function
 //   1.18  |sasethur|14-DEC-12| Updated for change in access delay function 
 //   1.16  |sasethur|14-DEC-12| Updated for Warning 
@@ -72,9 +74,9 @@ using namespace fapi;
  *
  * Parameters: i_target: mba;		iv_port: 0, 1
  * ---------------------------------------------------------------------------*/
-generic_shmoo:: generic_shmoo(uint8_t prt,uint32_t shmoo_mask,shmoo_algorithm_t shmoo_algorithm)
+generic_shmoo:: generic_shmoo(uint8_t prt,shmoo_type_t shmoo_mask,shmoo_algorithm_t shmoo_algorithm)
 {
-    this->shmoo_mask=shmoo_mask; //! Sets what Shmoos the caller wants to run
+    //this->shmoo_mask=shmoo_mask; //! Sets what Shmoos the caller wants to run
     this->algorithm=shmoo_algorithm ;
     this->iv_port=prt ;
     
@@ -92,8 +94,18 @@ generic_shmoo:: generic_shmoo(uint8_t prt,uint32_t shmoo_mask,shmoo_algorithm_t
     }
     
     FAPI_DBG("mss_generic_shmoo : constructor running for shmoo type %d",shmoo_mask);
-    
-    
+    iv_shmoo_type = 0;
+	SHMOO[iv_shmoo_type].static_knob.min_val=0;
+    SHMOO[iv_shmoo_type].static_knob.max_val=512; 
+	
+	
+	if(shmoo_mask & TEST_NONE)
+    {
+        FAPI_DBG("mss_generic_shmoo : WR_EYE selected %d",shmoo_mask);
+        iv_shmoo_type = 0;
+        SHMOO[0].static_knob.min_val=0;
+        SHMOO[0].static_knob.max_val=512;   
+    }
     
     if(shmoo_mask & WR_EYE)
     {
@@ -175,7 +187,7 @@ fapi::ReturnCode generic_shmoo::run(const fapi::Target & i_target,uint32_t *o_ri
     iv_MAX_RANKS=num_ranks_per_dimm[iv_port][0]+num_ranks_per_dimm[iv_port][1];
     iv_pattern=i_pattern;
     iv_test_type=i_test_type;
-    //FAPI_INF("\n abhijit the test type %d \n",l_attr_schmoo_test_type_u8);
+    
     if ( l_attr_eff_dimm_type_u8 == 0 )
     {
 	iv_MAX_BYTES=8;
@@ -211,9 +223,11 @@ fapi::ReturnCode generic_shmoo::run(const fapi::Target & i_target,uint32_t *o_ri
      // Check if all bytes/bits are in a pass condition initially .Otherwise quit
     if(l_attr_schmoo_test_type_u8 == 0){
 	FAPI_INF("This procedure wont change any delay settings");
+	return rc;
 	}
-    if(l_attr_schmoo_test_type_u8 == 1){
+	if(l_attr_schmoo_test_type_u8 == 1){
 	rc=sanity_check(i_target); // Run MCBIST only when ATTR_EFF_SCHMOO_TEST_VALID is mcbist only 
+
     if(!rc.ok())
     {
     FAPI_ERR("generic_shmoo::run MSS Generic Shmoo failed initial Sanity Check. Memory not in an all pass Condition");
@@ -316,7 +330,7 @@ fapi::ReturnCode generic_shmoo::sanity_check(const fapi::Target & i_target){
 		    {
 			l_dqBitmap[l_byte] = 0x0f;
 		    }	
-		    rc = dimmSetBadDqBitmap(i_target,iv_port,l_socket, l_rank_valid, l_dqBitmap);if(rc) return rc;
+		    //rc = dimmSetBadDqBitmap(i_target,iv_port,l_socket, l_rank_valid, l_dqBitmap);if(rc) return rc;
 		}
 	    }    
         }
@@ -387,7 +401,7 @@ fapi::ReturnCode generic_shmoo::do_mcbist_test(const fapi::Target & i_target,uin
     
 	
     
-   rc = setup_mcbist(i_target, iv_port, MCBIST_2D_CUP_PAT5, CENSHMOO, UNMASK_ALL, 0,iv_pattern,iv_test_type,i_rank,0,l_start,l_end);if(rc) return rc;  //send shmoo mode to vary the address range
+   rc = setup_mcbist(i_target, iv_port, ABLE_FIVE, CENSHMOO, UNMASK_ALL, 0,iv_pattern,iv_test_type,i_rank,0,l_start,l_end);if(rc) return rc;  //send shmoo mode to vary the address range
    
    rc = start_mcb(i_target);
     if(rc)
@@ -708,14 +722,10 @@ fapi::ReturnCode generic_shmoo::knob_update(const fapi::Target & i_target,bound_
 			}
 		}	
 	    }
-	    if(!pass)
-	    {
-		SHMOO[scenario].MBA.P[iv_port].S[rank].K.lb_regval[l_dq][l_rp]=l_current_val+l_left_del;
-	    }
-	    else
-	    {
+	    
 		SHMOO[scenario].MBA.P[iv_port].S[rank].K.lb_regval[l_dq][l_rp]=l_current_val+l_left_del;
-	    }
+	    
+	    
 	    l_current_val=SHMOO[scenario].MBA.P[iv_port].S[rank].K.nom_val[l_dq][l_rp];
 		FAPI_INF("  the restoring nominal value for rank=%d dq=%d and rp=%d is %d",rank,l_dq,l_rp,l_current_val);
 	    rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,rank,l_input_type_e,l_dq,0,l_current_val);if(rc) return rc;
@@ -814,14 +824,9 @@ fapi::ReturnCode generic_shmoo::knob_update(const fapi::Target & i_target,bound_
 		    }
 		}
 	    }
-	    if(!pass)
-	    {
-		SHMOO[scenario].MBA.P[iv_port].S[rank].K.rb_regval[l_dq][l_rp]=l_current_val-l_right_del;
-	    }
-	    else
-	    {
+	    
 		SHMOO[scenario].MBA.P[iv_port].S[rank].K.rb_regval[l_dq][l_rp]=l_current_val-l_right_del;
-	    }
+	    
 	    FAPI_INF(" the right bound  for dq=%d is %d ",l_dq,SHMOO[scenario].MBA.P[iv_port].S[rank].K.rb_regval[l_dq][l_rp]);
 	    l_current_val=SHMOO[scenario].MBA.P[iv_port].S[rank].K.nom_val[l_dq][l_rp];
 		FAPI_INF("  the restoring nominal value for rank=%d dq=%d and rp=%d is %d",rank,l_dq,l_rp,l_current_val);
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.H b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.H
index d21302df8..609697507 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.H
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012                   */
+/* COPYRIGHT International Business Machines Corp. 2012,2013              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_generic_shmoo.H,v 1.10 2012/12/14 08:48:13 lapietra Exp $
+// $Id: mss_generic_shmoo.H,v 1.11 2013/01/21 12:36:52 sasethur Exp $
 // *!***************************************************************************
 // *! (C) Copyright International Business Machines Corp. 1997, 1998
 // *!           All Rights Reserved -- Property of IBM
@@ -39,6 +39,7 @@
 //------------------------------------------------------------------------------
 // Version:|Author: | Date:  | Comment:
 // --------|--------|--------|--------------------------------------------------
+//   1.11  |abhijit |1/21/13 |fixed constructor definition  
 //   1.9   |abhijit |06/12/12|fixed fw review comments 
 //   1.4   |abhijit |09/27/11|made changes according to new design
 //   1.5   |abhijit |10/29/12|made changes after target and returncode 
@@ -83,7 +84,7 @@ class generic_shmoo
         shmoo_algorithm_t algorithm;
         shmoo_mode mcbist_mode;
         uint8_t mcbist_error_map[MAX_PORT][MAX_RANK][MAX_BYTE][MAX_NIBBLES];
-		uint32_t shmoo_mask;
+		shmoo_type_t shmoo_mask;
 	uint8_t iv_port;
 	uint8_t iv_MAX_RANKS;
 	uint8_t iv_MAX_BYTES;
@@ -102,7 +103,7 @@ class generic_shmoo
 	
         enum bound_t { LEFT , RIGHT};    
      
-        generic_shmoo(uint8_t iv_port,uint32_t shmoo_mask,shmoo_algorithm_t shmoo_algorithm);// Constructor
+        generic_shmoo(uint8_t iv_port,shmoo_type_t shmoo_mask,shmoo_algorithm_t shmoo_algorithm);// Constructor
         generic_shmoo(){};
         ~generic_shmoo(){};  // Destructor
         void  init_multi_array(uint32_t (&array)[MAX_DQ][MAX_RPS],uint32_t init_val); //initialize multi dim arrays to known value
diff --git a/src/usr/hwpf/hwp/dram_training/mss_termination_control.C b/src/usr/hwpf/hwp/dram_training/mss_termination_control.C
index deca4a099..f94aac915 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_termination_control.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_termination_control.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_termination_control.C,v 1.15 2013/01/14 23:41:58 mwuu Exp $
+// $Id: mss_termination_control.C,v 1.16 2013/01/24 20:56:09 mwuu Exp $
 /* File is created by SARAVANAN SETHURAMAN on Thur 29 Sept 2011. */
 
 //------------------------------------------------------------------------------
@@ -43,6 +43,7 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//  1.16   | mwuu	  |24-Jan-13| Fixed cal_slew extraction of bits.
 //  1.15   | mwuu	  |14-Jan-13| Altered error message for unsupported slew rate
 //  1.14   | mwuu	  |14-Jan-13| Removed error messages from slew cal fail when
 //         |          |         | in SIM and using unsupported slew rates.
@@ -853,7 +854,7 @@ fapi::ReturnCode config_rd_cen_vref (const fapi::Target & i_target_mba, uint8_t
  * Parameters: target: mba;
  * ---------------------------------------------------------------------------*/
 
-fapi::ReturnCode mss_slew_cal(const fapi::Target &i_target)
+fapi::ReturnCode mss_slew_cal(const fapi::Target &i_target_mba)
 {
 	fapi::ReturnCode rc;
     uint32_t rc_ecmd = 0;
@@ -945,13 +946,14 @@ fapi::ReturnCode mss_slew_cal(const fapi::Target &i_target)
 	const uint8_t BB_LOCK_BIT = 56;
 	// general purpose 100 ns delay for HW mode  (2000 sim cycles if simclk = 20ghz)
 	const uint16_t	DELAY_100NS		= 100;
+	const uint16_t	DELAY_2000NCLKS	= 4000;		// roughly 2000 nclks if DDR freq >= 1066
 	// normally 2000, but since cal doesn't work in SIM, setting to 1
 	const uint16_t	DELAY_SIMCYCLES	= 1;	
 	const uint8_t	MAX_POLL_LOOPS	= 20;
 
 	// verify which ports are functional
 	rc = FAPI_ATTR_GET(ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR,
-			&i_target, ports_valid);
+			&i_target_mba, ports_valid);
 	if (rc)
 	{
 		FAPI_ERR("Failed to get attribute: "
@@ -967,7 +969,7 @@ fapi::ReturnCode mss_slew_cal(const fapi::Target &i_target)
 		return rc;
 	}
 	// Get DDR type (DDR3 or DDR4)
-	rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_GEN, &i_target, ddr_type);
+	rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_GEN, &i_target_mba, ddr_type);
 	if (rc)
 	{
 		FAPI_ERR("Failed to get attribute: ATTR_EFF_DRAM_GEN");
@@ -980,19 +982,19 @@ fapi::ReturnCode mss_slew_cal(const fapi::Target &i_target)
 		ddr_idx = 0;
 	} else {	// EMPTY ?? how to handle?
 		FAPI_ERR("Invalid ATTR_DRAM_DRAM_GEN = %d, %s!", ddr_type,
-				i_target.toEcmdString());
+				i_target_mba.toEcmdString());
 		FAPI_SET_HWP_ERROR(rc, RC_MSS_INVALID_DRAM_GEN);
 		return rc;
 	}
 
 	// get freq from parent
-	rc = fapiGetParentChip(i_target, l_target_centaur); if(rc) return rc;
+	rc = fapiGetParentChip(i_target_mba, l_target_centaur); if(rc) return rc;
 	rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_target_centaur, ddr_freq);
 	if(rc) return rc;
 
 	if (ddr_freq == 0) {
 		FAPI_ERR("Invalid ATTR_MSS_FREQ = %d on %s!", ddr_freq,
-				i_target.toEcmdString());
+				i_target_mba.toEcmdString());
 		FAPI_SET_HWP_ERROR(rc, RC_MSS_INVALID_FREQ);
 		return rc;
 	}
@@ -1007,9 +1009,6 @@ fapi::ReturnCode mss_slew_cal(const fapi::Target &i_target)
 		freq_idx = 0;		// for 1066-
 	}
 
-	FAPI_INF("Enabling slew calibration engine... dram=DDR%i(%u), freq=%u(%u)",
-			(ddr_type+2), ddr_idx, ddr_freq, freq_idx);
-
 	for (uint8_t l_port=0; l_port < MAX_NUM_PORTS; l_port++)
 	{
 		uint8_t port_val = (ports_valid & (0xF0 >> (4 * l_port)));
@@ -1022,7 +1021,7 @@ fapi::ReturnCode mss_slew_cal(const fapi::Target &i_target)
 		}
 	//	Step A: Configure ADR registers and MCLK detect (done in ddr_phy_reset)
 	// DPHY01_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0_0x800080390301143F + port
-		rc = fapiGetScom(i_target, slew_cal_cntl[l_port], ctl_reg);
+		rc = fapiGetScom(i_target_mba, slew_cal_cntl[l_port], ctl_reg);
 		if (rc)
 		{
 			FAPI_ERR("Error reading DDRPHY_ADR_SLEW_CAL_CNTL register.");
@@ -1039,18 +1038,28 @@ fapi::ReturnCode mss_slew_cal(const fapi::Target &i_target)
 			return rc;
 		}
 
+		FAPI_INF("%s: Enabling slew calibration engine on Port %i: DDR%i(%u) "
+			   "%u(%u)", i_target_mba.toEcmdString(), l_port, (ddr_type+2),
+			   ddr_idx, ddr_freq, freq_idx);
+
 		// DPHY01_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0_0x800080390301143F + port
-		rc = fapiPutScom(i_target, slew_cal_cntl[l_port], ctl_reg);
+		rc = fapiPutScom(i_target_mba, slew_cal_cntl[l_port], ctl_reg);
 		if (rc)
 		{
 			FAPI_ERR("Error enabling slew calibration engine in "
 					"DDRPHY_ADR_SLEW_CAL_CNTL register.");
 			return rc;
 		}
+		// Note: must be 2000 nclks+ after setting enable bit
+		rc = fapiDelay(DELAY_2000NCLKS, 1);
+		if (rc) {
+			FAPI_ERR("Error executing fapiDelay of 2000 nclks or 1 simcycle");
+			return rc;
+		}
 
 		//---------------------------------------------------------------------/
 		//	Step 1. Check for BB lock.
-		FAPI_INF("Wait for BB lock in status register, bit %u", BB_LOCK_BIT);
+		FAPI_DBG("Wait for BB lock in status register, bit %u", BB_LOCK_BIT);
 		for (poll_count=0; poll_count < MAX_POLL_LOOPS; poll_count++)
 		{
 			rc = fapiDelay(DELAY_100NS, DELAY_SIMCYCLES);
@@ -1059,7 +1068,7 @@ fapi::ReturnCode mss_slew_cal(const fapi::Target &i_target)
 				return rc;
 			}
 	// DPHY01_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0_0x800080340301143F + port
-			rc = fapiGetScom(i_target, slew_cal_stat[l_port], stat_reg);
+			rc = fapiGetScom(i_target_mba, slew_cal_stat[l_port], stat_reg);
 			if (rc)
 			{
 				FAPI_ERR("Error reading DDRPHY_ADR_SYSCLK_PR_VALUE_RO register "
@@ -1073,7 +1082,13 @@ fapi::ReturnCode mss_slew_cal(const fapi::Target &i_target)
 		}
 
 		if (poll_count == MAX_POLL_LOOPS) {
-			FAPI_INF("Timeout on polling BB_Lock, continuing...");
+			FAPI_INF("WARNING: Timeout on polling BB_Lock, continuing...");
+//			return rc;
+		}
+		else
+		{
+			FAPI_DBG("polling finished in %i loops (%u ns)",
+					poll_count, (100*poll_count));
 		}
 
 		//---------------------------------------------------------------------/
@@ -1095,7 +1110,6 @@ fapi::ReturnCode mss_slew_cal(const fapi::Target &i_target)
 					// slew_table[ddr3/4][dq/adr][freq][impedance][slew_rate]
 					rc_ecmd |= ctl_reg.insertFromRight(cal_slew, 59, 5);
 
-					// Note: must be 2000 nclks+ after setting enable bit
 					rc_ecmd |= ctl_reg.setBit(START_BIT);	// set start bit(48)
 					FAPI_DBG("%s Slew cntl_reg(48:63)=0x%04X, i_slew=%i,0x%02x "
 						"(59:63)", (data_adr ? "ADR" : "DATA"),
@@ -1111,7 +1125,7 @@ fapi::ReturnCode mss_slew_cal(const fapi::Target &i_target)
 					FAPI_INF("Starting slew calibration, ddr_idx=%i, "
 						"data_adr=%i, imp=%i, slewrate=%i", ddr_idx, data_adr,
 						imp, (slew+3));
-					rc = fapiPutScom(i_target, slew_cal_cntl[l_port], ctl_reg);
+					rc = fapiPutScom(i_target_mba, slew_cal_cntl[l_port], ctl_reg);
 					if (rc)
 					{
 						FAPI_ERR("Error starting slew calibration.");
@@ -1122,10 +1136,8 @@ fapi::ReturnCode mss_slew_cal(const fapi::Target &i_target)
 					for (poll_count=0; poll_count < MAX_POLL_LOOPS;
 							poll_count++)
 					{
-						FAPI_INF("polling for calibration status, count=%i",
-								poll_count);
 	// DPHY01_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0_0x800080340301143F + port
-						rc = fapiGetScom(i_target, slew_cal_stat[l_port],
+						rc = fapiGetScom(i_target_mba, slew_cal_stat[l_port],
 								stat_reg);
 						if (rc)
 						{
@@ -1152,28 +1164,25 @@ fapi::ReturnCode mss_slew_cal(const fapi::Target &i_target)
 						}
 					}
 
-					if (cal_status == 3)
+					if (cal_status > 1)
 					{
-						FAPI_INF("slew calibration completed successfully");
-
-						cal_slew = cal_slew & 0x80;	// clear bits 6:0
-						rc_ecmd = stat_reg.extractPreserve(&cal_slew, 60, 4);
-						if (rc_ecmd)
+						if (cal_status == 3)
 						{
-							FAPI_ERR("Error getting calibration output "
-									"slew value");
-							rc.setEcmdError(rc_ecmd);
-							return rc;
+							FAPI_DBG("slew calibration completed successfully,"
+								" loop=%i input=0x%02x",	poll_count, 
+								(cal_slew & 0x1F));
+						}
+						else if (cal_status == 2)
+						{
+							FAPI_INF("WARNING: occurred during slew "
+								"calibration, imp=%i, slew=%i, input=0x%x "
+								"continuing...", imp, slew, (cal_slew & 0x1F));
 						}
-						calibrated_slew[data_adr][l_port][imp][slew] = cal_slew;
-					}
-					else if (cal_status == 2)
-					{
-						FAPI_INF("WARNING: occurred during slew "
-								"calibration, continuing...");
-
 						cal_slew = cal_slew & 0x80;	// clear bits 6:0
-						rc_ecmd = stat_reg.extractPreserve(&cal_slew, 60, 4);
+						rc_ecmd = stat_reg.extractPreserve(&cal_slew, 60, 4, 4);
+						FAPI_DBG("MSS_SLEW_RATE_%s port[%i]imp[%i]slew[%i] = "
+								"0x%02x",	(data_adr ? "ADR" : "DATA"), l_port,
+								imp, slew, (cal_slew & 0xF));
 						if (rc_ecmd)
 						{
 							FAPI_ERR("Error getting calibration output "
@@ -1202,14 +1211,15 @@ fapi::ReturnCode mss_slew_cal(const fapi::Target &i_target)
 							}
 							else
 							{
-								FAPI_ERR("Slew calibration timed out");
+								FAPI_ERR("Slew calibration timed out, loop=%i",
+										poll_count);
 							}
 							FAPI_ERR("Slew calibration failed on %s slew: imp_idx="
 							"%d, slew_idx=%d, slew_table=0x%02X, "
 							"status=0x%04X on %s!",
 							(data_adr ? "ADR" : "DATA"), imp, slew,
 							cal_slew, stat_reg.getHalfWord(3),
-							i_target.toEcmdString());
+							i_target_mba.toEcmdString());
 
 							FAPI_SET_HWP_ERROR(rc, RC_MSS_SLEW_CAL_ERROR);
 							//return rc;
@@ -1223,7 +1233,7 @@ fapi::ReturnCode mss_slew_cal(const fapi::Target &i_target)
 
 		// disable calibration engine for port
 		ctl_reg.clearBit(ENABLE_BIT);
-		rc = fapiPutScom(i_target, slew_cal_cntl[l_port], ctl_reg);
+		rc = fapiPutScom(i_target_mba, slew_cal_cntl[l_port], ctl_reg);
 		if (rc)
 		{
 			FAPI_ERR("Error disabling slew calibration engine in "
@@ -1242,14 +1252,14 @@ fapi::ReturnCode mss_slew_cal(const fapi::Target &i_target)
 	}
 	FAPI_INF("Setting output slew tables ATTR_MSS_SLEW_RATE_DATA/ADR");
 	// ATTR_MSS_SLEW_RATE_DATA [2][4][4]	port, imped, slew_rate
-	rc = FAPI_ATTR_SET(ATTR_MSS_SLEW_RATE_DATA, &i_target, calibrated_slew[0]);
+	rc = FAPI_ATTR_SET(ATTR_MSS_SLEW_RATE_DATA, &i_target_mba, calibrated_slew[0]);
 	if (rc)
 	{
 		FAPI_ERR("Failed to set attribute: ATTR_MSS_SLEW_RATE_DATA");
 		return rc;
 	}
 	// ATTR_MSS_SLEW_RATE_ADR [2][4][4]		port, imped, slew_rate
-	rc = FAPI_ATTR_SET(ATTR_MSS_SLEW_RATE_ADR, &i_target, calibrated_slew[1]);
+	rc = FAPI_ATTR_SET(ATTR_MSS_SLEW_RATE_ADR, &i_target_mba, calibrated_slew[1]);
 	if (rc)
 	{
 		FAPI_ERR("Failed to set attribute: ATTR_MSS_SLEW_RATE_ADR");
@@ -1264,14 +1274,14 @@ fapi::ReturnCode mss_slew_cal(const fapi::Target &i_target)
 	};
 
 	// Get desired dq/dqs slew rate & impedance from attribute
-	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS, &i_target,
+	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS, &i_target_mba,
 			slew_imp_val[SLEW_TYPE_DATA][SLEW]);
 	if (rc)
 	{
 		FAPI_ERR("Failed to get attribute: ATTR_EFF_CEN_SLEW_RATE_DQ_DQS");
 		return rc;
 	}
-	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS, &i_target,
+	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS, &i_target_mba,
 			slew_imp_val[SLEW_TYPE_DATA][IMP]);
 	if (rc)
 	{
@@ -1310,19 +1320,24 @@ fapi::ReturnCode mss_slew_cal(const fapi::Target &i_target)
 			case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE120:
 				slew_imp_val[SLEW_TYPE_DATA][IMP][j]=40;
 				break;
+			default:
+				FAPI_INF("WARNING: EFF_CEN_DRV_IMP_DQ_DQS attribute "
+						"invalid, using value of 0");
+//				FAPI_SET_HWP_ERROR(rc, RC_MSS_IMP_INPUT_ERROR);
+//				return rc;
 		}
 		FAPI_DBG("switched imp to value of %u",
 				slew_imp_val[SLEW_TYPE_DATA][IMP][j]);
 	}
 	// Get desired ADR control slew rate & impedance from attribute
-	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_SLEW_RATE_CNTL, &i_target,
+	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_SLEW_RATE_CNTL, &i_target_mba,
 			slew_imp_val[SLEW_TYPE_ADR_CNTL][SLEW]);
 	if (rc)
 	{
 		FAPI_ERR("Failed to get attribute: ATTR_EFF_CEN_SLEW_RATE_CNTL");
 		return rc;
 	}
-	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_CNTL, &i_target,
+	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_CNTL, &i_target_mba,
 			slew_imp_val[SLEW_TYPE_ADR_CNTL][IMP]);
 	if (rc)
 	{
@@ -1330,14 +1345,14 @@ fapi::ReturnCode mss_slew_cal(const fapi::Target &i_target)
 		return rc;
 	}
 	// Get desired ADR command slew rate & impedance from attribute
-	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_SLEW_RATE_ADDR, &i_target,
+	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_SLEW_RATE_ADDR, &i_target_mba,
 			slew_imp_val[SLEW_TYPE_ADR_ADDR][SLEW]);
 	if (rc)
 	{
 		FAPI_ERR("Failed to get attribute: ATTR_EFF_CEN_SLEW_RATE_ADDR");
 		return rc;
 	}
-	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_ADDR, &i_target,
+	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_ADDR, &i_target_mba,
 			slew_imp_val[SLEW_TYPE_ADR_ADDR][IMP]);
 	if (rc)
 	{
@@ -1345,14 +1360,14 @@ fapi::ReturnCode mss_slew_cal(const fapi::Target &i_target)
 		return rc;
 	}
 	// Get desired ADR clock slew rate & impedance from attribute
-	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_SLEW_RATE_CLK, &i_target,
+	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_SLEW_RATE_CLK, &i_target_mba,
 			slew_imp_val[SLEW_TYPE_ADR_CLK][SLEW]);
 	if (rc)
 	{
 		FAPI_ERR("Failed to get attribute: ATTR_EFF_CEN_SLEW_RATE_CLK");
 		return rc;
 	}
-	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_CLK, &i_target,
+	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_CLK, &i_target_mba,
 			slew_imp_val[SLEW_TYPE_ADR_CLK][IMP]);
 	if (rc)
 	{
@@ -1360,14 +1375,14 @@ fapi::ReturnCode mss_slew_cal(const fapi::Target &i_target)
 		return rc;
 	}
 	// Get desired ADR Spare clock slew rate & impedance from attribute
-	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_SLEW_RATE_SPCKE, &i_target,
+	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_SLEW_RATE_SPCKE, &i_target_mba,
 			slew_imp_val[SLEW_TYPE_ADR_SPCKE][SLEW]);
 	if (rc)
 	{
 		FAPI_ERR("Failed to get attribute: ATTR_EFF_CEN_SLEW_RATE_SPCKE");
 		return rc;
 	}
-	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_SPCKE, &i_target,
+	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_SPCKE, &i_target_mba,
 			slew_imp_val[SLEW_TYPE_ADR_SPCKE][IMP]);
 	if (rc)
 	{
@@ -1394,7 +1409,7 @@ fapi::ReturnCode mss_slew_cal(const fapi::Target &i_target)
 				slew_imp_val[slew_type][IMP][l_port],
 				slew_imp_val[slew_type][SLEW][l_port]);
 
-			config_slew_rate(i_target, l_port, slew_type,
+			config_slew_rate(i_target_mba, l_port, slew_type,
 					slew_imp_val[slew_type][IMP][l_port],
 					slew_imp_val[slew_type][SLEW][l_port]);
 		}
diff --git a/src/usr/hwpf/hwp/include/cen_scom_addresses.H b/src/usr/hwpf/hwp/include/cen_scom_addresses.H
index df2731cec..44734b1c8 100755
--- a/src/usr/hwpf/hwp/include/cen_scom_addresses.H
+++ b/src/usr/hwpf/hwp/include/cen_scom_addresses.H
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: cen_scom_addresses.H,v 1.48 2013/01/09 20:32:14 jdsloat Exp $
+// $Id: cen_scom_addresses.H,v 1.49 2013/01/24 00:56:27 jdsloat Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/cen_scom_addresses.H,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -44,6 +44,7 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//  1.49   | jdsloat  |23-Jan-13| Added PC_RANK_GROUP and PC_RANK_GROUP_EXT
 //  1.48   | jdsloat  |09-Jan-13| Fixed typos.  Excuse me.
 //  1.47   | jdsloat  |09-Jan-13| Added DQS READ Phase select regs for RP 1-3
 //  1.46   | gollub   |19-Dec-12| Added:
@@ -67,7 +68,7 @@
 //  1.41   | gollub   |26-Oct-12| Added MBECCFIR AND/OR MASK registers
 //         |          |         | Added MBSPA AND/OR MASK registers
 //  1.38   | pardeik  |31-Oct-12| Added N/M Throttling Control Register
-//  1.37   | aditya   |26-Oct-12| Added MCBIST Random Data Seed Registers
+//  1.37   | aditya   |26-Oct-12| Added MCBIST Random Data Seed Registers 
 //  1.36   | menlowuu |25-Oct-12| Added PHY port 1 disable bit registers
 //  1.35   | menlowuu |25-Oct-12| Added PHY disable bit registers
 //  1.34   | aditya   |12-Oct-12| Added MCBIST and DPHY registers
@@ -442,6 +443,13 @@ CONST_UINT64_T( DPHY01_DDRPHY_PC_MR0_SEC_RP3_P1_0x8001C32C0301143F,
 CONST_UINT64_T( DPHY01_DDRPHY_PC_MR1_SEC_RP3_P1_0x8001C32D0301143F,                  ULL(0x8001C32D0301143F) );
 CONST_UINT64_T( DPHY01_DDRPHY_PC_MR2_SEC_RP3_P1_0x8001C32E0301143F,                  ULL(0x8001C32E0301143F) );
 CONST_UINT64_T( DPHY01_DDRPHY_PC_MR3_SEC_RP3_P1_0x8001C32F0301143F,                  ULL(0x8001C32F0301143F) );
+
+CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_GROUP_P0_0x8000C0110301143F,                  ULL(0x8000C0110301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_GROUP_P1_0x8001C0110301143F,                  ULL(0x8001C0110301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P0_0x8000C0350301143F,                  ULL(0x8000C0350301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P1_0x8001C0350301143F,                  ULL(0x8001C0350301143F) );
+
+
 //------------------------------------------------------------------------------
 //   DISABLE BIT SCOM ADDRESSES (DPHY REGISTERS)
 //------------------------------------------------------------------------------
@@ -787,7 +795,7 @@ CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF2_DATA_ECC0_0x02011632			, ULL(0x02011632)
 CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF2_DATA_ECC1_0x02011633			, ULL(0x02011633) );
 CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF2_DATA_ECC2_0x02011634			, ULL(0x02011634) );
 CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF2_DATA_ECC3_0x02011635			, ULL(0x02011635) );
-
+		
 // Maint Write Buffer 3
 CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF3_DATA0_0x0201163A				, ULL(0x0201163A) );
 CONST_UINT64_T( MAINT0_MBS_MAINT_BUFF3_DATA1_0x0201163B				, ULL(0x0201163B) );
@@ -844,7 +852,7 @@ CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF2_DATA_ECC0_0x02011732			, ULL(0x02011732)
 CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF2_DATA_ECC1_0x02011733			, ULL(0x02011733) );
 CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF2_DATA_ECC2_0x02011734			, ULL(0x02011734) );
 CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF2_DATA_ECC3_0x02011735			, ULL(0x02011735) );
-
+	
 // Maint Write Buffer 3
 CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF3_DATA0_0x0201173A				, ULL(0x0201173A) );
 CONST_UINT64_T( MAINT1_MBS_MAINT_BUFF3_DATA1_0x0201173B				, ULL(0x0201173B) );
@@ -1071,7 +1079,7 @@ CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P1_1_0x8001047A0301143F,
 CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P1_2_0x8001087A0301143F,	           ULL(0x8001087A0301143F) );
 CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P1_3_0x80010C7A0301143F,	           ULL(0x80010C7A0301143F) );
 CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P1_4_0x8001107A0301143F,	           ULL(0x8001107A0301143F) );
-
+                                                                                       
 CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P0_0_0x8000007B0301143F,	           ULL(0x8000007B0301143F) );
 CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P0_1_0x8000047B0301143F,	           ULL(0x8000047B0301143F) );
 CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P0_2_0x8000087B0301143F,	           ULL(0x8000087B0301143F) );
@@ -1353,7 +1361,7 @@ CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFD1Q_0x02011782  , ULL(0x02011782) );
 CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFD2Q_0x02011783  , ULL(0x02011783) );
 CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFD3Q_0x02011784  , ULL(0x02011784) );
 CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFD4Q_0x02011785  , ULL(0x02011785) );
-CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFD5Q_0x02011786  , ULL(0x02011786) );
+CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFD5Q_0x02011786  , ULL(0x02011786) ); 
 CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFD6Q_0x02011787  , ULL(0x02011787) );
 CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFD7Q_0x02011788  , ULL(0x02011788) );
 CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFDQ_0x02011789   , ULL(0x02011789) );
@@ -1363,7 +1371,7 @@ CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFDSPQ_0x0201178A , ULL(0x0201178A) );
 //------------------------------------------------------------------------------
 
 CONST_UINT64_T( MBA01_CCS_MODEQ_0x030106a7       		, ULL(0x030106a7) );
-CONST_UINT64_T( MBA01_MCBIST_MCB_CNTLSTATQ_0x030106dc	, ULL(0x030106dc) );
+CONST_UINT64_T( MBA01_MCBIST_MCB_CNTLSTATQ_0x030106dc	, ULL(0x030106dc) ); 
 //------------------------------------------------------------------------------
 //     MBA MCBIST Configuration Register
 //------------------------------------------------------------------------------
@@ -1373,39 +1381,39 @@ CONST_UINT64_T( MBA01_MCBIST_MCBCFGQ_0x030106e0  		, ULL(0x030106e0) );
 //     MBS Error Map Register
 
 //------------------------------------------------------------------------------
-CONST_UINT64_T( MBS_MCBIST01_MCBEMA1Q_0x0201166a 		, ULL(0x0201166a) );
-CONST_UINT64_T( MBS_MCBIST01_MCBEMA2Q_0x0201166b 		, ULL(0x0201166b) );
-CONST_UINT64_T( MBS_MCBIST01_MCBEMA3Q_0x0201166c 		, ULL(0x0201166c) );
-CONST_UINT64_T( MBS_MCBIST01_MCBEMB1Q_0x0201166d 		, ULL(0x0201166d) );
-CONST_UINT64_T( MBS_MCBIST01_MCBEMB2Q_0x0201166e 		, ULL(0x0201166e) );
-CONST_UINT64_T( MBS_MCBIST01_MCBEMB3Q_0x0201166f 		, ULL(0x0201166f) );
+CONST_UINT64_T( MBS_MCBIST01_MCBEMA1Q_0x0201166a 		, ULL(0x0201166a) ); 
+CONST_UINT64_T( MBS_MCBIST01_MCBEMA2Q_0x0201166b 		, ULL(0x0201166b) ); 
+CONST_UINT64_T( MBS_MCBIST01_MCBEMA3Q_0x0201166c 		, ULL(0x0201166c) ); 
+CONST_UINT64_T( MBS_MCBIST01_MCBEMB1Q_0x0201166d 		, ULL(0x0201166d) ); 
+CONST_UINT64_T( MBS_MCBIST01_MCBEMB2Q_0x0201166e 		, ULL(0x0201166e) ); 
+CONST_UINT64_T( MBS_MCBIST01_MCBEMB3Q_0x0201166f 		, ULL(0x0201166f) ); 
 //------------------------------------------------------------------------------
 //     MBA MCBIST Memory Register
 
 //------------------------------------------------------------------------------
-CONST_UINT64_T( MBA01_MCBIST_MCBMR0Q_0x030106a8  		, ULL(0x030106a8) );
-CONST_UINT64_T( MBA01_MCBIST_MCBMR1Q_0x030106a9  		, ULL(0x030106a9) );
-CONST_UINT64_T( MBA01_MCBIST_MCBMR2Q_0x030106aa  		, ULL(0x030106aa) );
-CONST_UINT64_T( MBA01_MCBIST_MCBMR3Q_0x030106ab  		, ULL(0x030106ab) );
-CONST_UINT64_T( MBA01_MCBIST_MCBMR4Q_0x030106ac  		, ULL(0x030106ac) );
-CONST_UINT64_T( MBA01_MCBIST_MCBMR5Q_0x030106ad  		, ULL(0x030106ad) );
-CONST_UINT64_T( MBA01_MCBIST_MCBMR6Q_0x030106ae  		, ULL(0x030106ae) );
-CONST_UINT64_T( MBA01_MCBIST_MCBMR7Q_0x030106df  		, ULL(0x030106df) );
-CONST_UINT64_T( MBA01_MCBIST_RUNTIMECTRQ_0x030106b0		, ULL(0x030106b0) );
+CONST_UINT64_T( MBA01_MCBIST_MCBMR0Q_0x030106a8  		, ULL(0x030106a8) );         
+CONST_UINT64_T( MBA01_MCBIST_MCBMR1Q_0x030106a9  		, ULL(0x030106a9) );         
+CONST_UINT64_T( MBA01_MCBIST_MCBMR2Q_0x030106aa  		, ULL(0x030106aa) );         
+CONST_UINT64_T( MBA01_MCBIST_MCBMR3Q_0x030106ab  		, ULL(0x030106ab) );   
+CONST_UINT64_T( MBA01_MCBIST_MCBMR4Q_0x030106ac  		, ULL(0x030106ac) );      
+CONST_UINT64_T( MBA01_MCBIST_MCBMR5Q_0x030106ad  		, ULL(0x030106ad) );      
+CONST_UINT64_T( MBA01_MCBIST_MCBMR6Q_0x030106ae  		, ULL(0x030106ae) );  
+CONST_UINT64_T( MBA01_MCBIST_MCBMR7Q_0x030106df  		, ULL(0x030106df) ); 
+CONST_UINT64_T( MBA01_MCBIST_RUNTIMECTRQ_0x030106b0		, ULL(0x030106b0) ); 
 //------------------------------------------------------------------------------
 //     MBA Fixed Data Seed Registers
 
 //------------------------------------------------------------------------------
 CONST_UINT64_T( MBA01_MCBIST_MCBFD0Q_0x030106be  		, ULL(0x030106be) );
-CONST_UINT64_T( MBA01_MCBIST_MCBFD1Q_0x030106bf  		, ULL(0x030106bf) );
-CONST_UINT64_T( MBA01_MCBIST_MCBFD2Q_0x030106c0  		, ULL(0x030106c0) );
-CONST_UINT64_T( MBA01_MCBIST_MCBFD3Q_0x030106c1  		, ULL(0x030106c1) );
-CONST_UINT64_T( MBA01_MCBIST_MCBFD4Q_0x030106c2  		, ULL(0x030106c2) );
-CONST_UINT64_T( MBA01_MCBIST_MCBFD5Q_0x030106c3  		, ULL(0x030106c3) );
-CONST_UINT64_T( MBA01_MCBIST_MCBFD6Q_0x030106c4  		, ULL(0x030106c4) );
-CONST_UINT64_T( MBA01_MCBIST_MCBFD7Q_0x030106c5  		, ULL(0x030106c5) );
-CONST_UINT64_T( MBA01_MCBIST_MCBFDQ_0x030106c6   		, ULL(0x030106c6) );
-CONST_UINT64_T( MBA01_MCBIST_MCBFDSPQ_0x030106c7 		, ULL(0x030106c7) );
+CONST_UINT64_T( MBA01_MCBIST_MCBFD1Q_0x030106bf  		, ULL(0x030106bf) );      
+CONST_UINT64_T( MBA01_MCBIST_MCBFD2Q_0x030106c0  		, ULL(0x030106c0) );         
+CONST_UINT64_T( MBA01_MCBIST_MCBFD3Q_0x030106c1  		, ULL(0x030106c1) );         
+CONST_UINT64_T( MBA01_MCBIST_MCBFD4Q_0x030106c2  		, ULL(0x030106c2) );         
+CONST_UINT64_T( MBA01_MCBIST_MCBFD5Q_0x030106c3  		, ULL(0x030106c3) );   
+CONST_UINT64_T( MBA01_MCBIST_MCBFD6Q_0x030106c4  		, ULL(0x030106c4) );   
+CONST_UINT64_T( MBA01_MCBIST_MCBFD7Q_0x030106c5  		, ULL(0x030106c5) );   
+CONST_UINT64_T( MBA01_MCBIST_MCBFDQ_0x030106c6   		, ULL(0x030106c6) );   
+CONST_UINT64_T( MBA01_MCBIST_MCBFDSPQ_0x030106c7 		, ULL(0x030106c7) ); 
 //------------------------------------------------------------------------------
 //     MBA Data Rotate Configuration Register
 
@@ -1417,7 +1425,7 @@ CONST_UINT64_T( MBA01_MCBIST_MCBDRCRQ_0x030106bd 		, ULL(0x030106bd) );
 //------------------------------------------------------------------------------
 CONST_UINT64_T( MBS_MCBIST01_MCBCMA1Q_0x02011672 		, ULL(0x02011672) );
 
-CONST_UINT64_T( MBS_MCBIST01_MCBCMB1Q_0x02011673 		, ULL(0x02011673) );
+CONST_UINT64_T( MBS_MCBIST01_MCBCMB1Q_0x02011673 		, ULL(0x02011673) );      
 CONST_UINT64_T( MBS_MCBIST01_MCBCMABQ_0x02011674 		, ULL(0x02011674) );
 //------------------------------------------------------------------------------
 //    MBA MCBIST Control Register
@@ -1428,60 +1436,60 @@ CONST_UINT64_T( MBA01_MCBIST_MCB_CNTLQ_0x030106db		, ULL(0x030106db) );
 //    MBA MCBIST Memory Parameter Register
 
 //------------------------------------------------------------------------------
-CONST_UINT64_T( MBA01_MCBIST_MCBPARMQ_0x030106af 		, ULL(0x030106af) );
+CONST_UINT64_T( MBA01_MCBIST_MCBPARMQ_0x030106af 		, ULL(0x030106af) ); 
 //------------------------------------------------------------------------------
 //    MBA Address Map Registers
 
 //------------------------------------------------------------------------------
-CONST_UINT64_T( MBA01_MCBIST_MCBAMR0A0Q_0x030106c8, ULL(0x030106c8) );
-CONST_UINT64_T( MBA01_MCBIST_MCBAMR1A0Q_0x030106c9, ULL(0x030106c9) );
-CONST_UINT64_T( MBA01_MCBIST_MCBAMR2A0Q_0x030106ca, ULL(0x030106ca) );
-CONST_UINT64_T( MBA01_MCBIST_MCBAMR3A0Q_0x030106cb, ULL(0x030106cb) );
-
-CONST_UINT64_T( MBA01_MCBIST_MCBAMR0A1Q_0x030106d7, ULL(0x030106d7) );
-
-CONST_UINT64_T( MBA01_MCBIST_MCBAMR1A1Q_0x030106d8, ULL(0x030106d8) );
-CONST_UINT64_T( MBA01_MCBIST_MCBAMR2A1Q_0x030106d9, ULL(0x030106d9) );
-CONST_UINT64_T( MBA01_MCBIST_MCBAMR3A1Q_0x030106da, ULL(0x030106da) );
-
-CONST_UINT64_T( MBA01_MCBIST_MCBLFSRA0Q_0x030106d4, ULL(0x030106d4) );
-CONST_UINT64_T( MBA01_MCBIST_MCBLFSRA1Q_0x030106d5, ULL(0x030106d5) );
-CONST_UINT64_T( MBA01_MCBIST_MCBSEARA0Q_0x030106d2, ULL(0x030106d2) );
-CONST_UINT64_T( MBA01_MCBIST_MCBSEARA1Q_0x030106d3, ULL(0x030106d3) );
-CONST_UINT64_T( MBA01_MCBIST_MCBRSARA0Q_0x030106cc, ULL(0x030106cc) );
-
-CONST_UINT64_T( MBA01_MCBIST_MCBRSARA1Q_0x030106cd, ULL(0x030106cd) );
-
-CONST_UINT64_T( MBA01_MCBIST_MCBREARA0Q_0x030106ce, ULL(0x030106ce) );
-CONST_UINT64_T( MBA01_MCBIST_MCBREARA1Q_0x030106cf, ULL(0x030106cf) );
-CONST_UINT64_T( MBA01_MCBIST_MCBSSARA0Q_0x030106d0, ULL(0x030106d0) );
-CONST_UINT64_T( MBA01_MCBIST_MCBSSARA1Q_0x030106d1, ULL(0x030106d1) );
+CONST_UINT64_T( MBA01_MCBIST_MCBAMR0A0Q_0x030106c8, ULL(0x030106c8) );      
+CONST_UINT64_T( MBA01_MCBIST_MCBAMR1A0Q_0x030106c9, ULL(0x030106c9) );    
+CONST_UINT64_T( MBA01_MCBIST_MCBAMR2A0Q_0x030106ca, ULL(0x030106ca) );       
+CONST_UINT64_T( MBA01_MCBIST_MCBAMR3A0Q_0x030106cb, ULL(0x030106cb) ); 
+      
+CONST_UINT64_T( MBA01_MCBIST_MCBAMR0A1Q_0x030106d7, ULL(0x030106d7) );  
+  
+CONST_UINT64_T( MBA01_MCBIST_MCBAMR1A1Q_0x030106d8, ULL(0x030106d8) );   
+CONST_UINT64_T( MBA01_MCBIST_MCBAMR2A1Q_0x030106d9, ULL(0x030106d9) );   
+CONST_UINT64_T( MBA01_MCBIST_MCBAMR3A1Q_0x030106da, ULL(0x030106da) ); 
+  
+CONST_UINT64_T( MBA01_MCBIST_MCBLFSRA0Q_0x030106d4, ULL(0x030106d4) );  
+CONST_UINT64_T( MBA01_MCBIST_MCBLFSRA1Q_0x030106d5, ULL(0x030106d5) );   
+CONST_UINT64_T( MBA01_MCBIST_MCBSEARA0Q_0x030106d2, ULL(0x030106d2) );  
+CONST_UINT64_T( MBA01_MCBIST_MCBSEARA1Q_0x030106d3, ULL(0x030106d3) );   
+CONST_UINT64_T( MBA01_MCBIST_MCBRSARA0Q_0x030106cc, ULL(0x030106cc) );   
+
+CONST_UINT64_T( MBA01_MCBIST_MCBRSARA1Q_0x030106cd, ULL(0x030106cd) ); 
+  
+CONST_UINT64_T( MBA01_MCBIST_MCBREARA0Q_0x030106ce, ULL(0x030106ce) );   
+CONST_UINT64_T( MBA01_MCBIST_MCBREARA1Q_0x030106cf, ULL(0x030106cf) );   
+CONST_UINT64_T( MBA01_MCBIST_MCBSSARA0Q_0x030106d0, ULL(0x030106d0) );   
+CONST_UINT64_T( MBA01_MCBIST_MCBSSARA1Q_0x030106d1, ULL(0x030106d1) ); 
 CONST_UINT64_T( MBA01_MCBIST_MCBAGRAQ_0x030106d6  , ULL(0x030106d6) );
 //------------------------------------------------------------------------------
 //    MBA Performance monitor  Registers
 
 //------------------------------------------------------------------------------
-CONST_UINT64_T( MBA01_MBA_PMU0Q_0x03010437        , ULL(0x03010437) );
+CONST_UINT64_T( MBA01_MBA_PMU0Q_0x03010437        , ULL(0x03010437) );  
 //------------------------------------------------------------------------------
 //    MBA Maintenance Buffer Registers
 
 //------------------------------------------------------------------------------
-CONST_UINT64_T( MBS_MCBIST01_MCB_ERRCNTA1Q_0x02011664, ULL(0x02011664) );
-CONST_UINT64_T( MBS_MCBIST01_MCB_ERRCNTA2Q_0x02011665, ULL(0x02011665) );
-CONST_UINT64_T( MBS_MCBIST01_MCB_ERRCNTB1Q_0x02011667, ULL(0x02011667) );
-CONST_UINT64_T( MBS_MCBIST01_MCB_ERRCNTB2Q_0x02011668, ULL(0x02011668) );
+CONST_UINT64_T( MBS_MCBIST01_MCB_ERRCNTA1Q_0x02011664, ULL(0x02011664) );   
+CONST_UINT64_T( MBS_MCBIST01_MCB_ERRCNTA2Q_0x02011665, ULL(0x02011665) );   
+CONST_UINT64_T( MBS_MCBIST01_MCB_ERRCNTB1Q_0x02011667, ULL(0x02011667) );   
+CONST_UINT64_T( MBS_MCBIST01_MCB_ERRCNTB2Q_0x02011668, ULL(0x02011668) );   
 //------------------------------------------------------------------------------
 //    DPHY01 PC Rank Pair Registers
 
 //------------------------------------------------------------------------------
-CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR0_P0, ULL(0x8000c0020301143f) );
-CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR0_P1, ULL(0x8001c0020301143f) );
-CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR1_P0, ULL(0x8000c0030301143f) );
-CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR1_P1, ULL(0x8001c0030301143f) );
-CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR2_P0, ULL(0x8000c0300301143f) );
-CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR2_P1, ULL(0x8001c0300301143f) );
-CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR3_P0, ULL(0x8000c0310301143f) );
-CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR3_P1, ULL(0x8001c0310301143f) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR0_P0, ULL(0x8000c0020301143f) );   
+CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR0_P1, ULL(0x8001c0020301143f) );   
+CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR1_P0, ULL(0x8000c0030301143f) );   
+CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR1_P1, ULL(0x8001c0030301143f) );   
+CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR2_P0, ULL(0x8000c0300301143f) );   
+CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR2_P1, ULL(0x8001c0300301143f) ); 
+CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR3_P0, ULL(0x8000c0310301143f) ); 
+CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR3_P1, ULL(0x8001c0310301143f) ); 
 //------------------------------------------------------------------------------
 //    MCBIST Random Data Seed Registers
 
@@ -1522,6 +1530,9 @@ This section is automatically updated by CVS when you check in this file.
 Be sure to create CVS comments when you commit so that they can be included here.
 
 $Log: cen_scom_addresses.H,v $
+Revision 1.49  2013/01/24 00:56:27  jdsloat
+Added PC_RANK_GROUP and PC_RANK_GROUP_EXT
+
 Revision 1.48  2013/01/09 20:32:14  jdsloat
 
 Fixed typos.  Excuse me.
diff --git a/src/usr/hwpf/hwp/initfiles/cen.dmi.custom.scom.initfile b/src/usr/hwpf/hwp/initfiles/cen.dmi.custom.scom.initfile
new file mode 100644
index 000000000..ba8e45593
--- /dev/null
+++ b/src/usr/hwpf/hwp/initfiles/cen.dmi.custom.scom.initfile
@@ -0,0 +1,442 @@
+#-- $Id: cen.dmi.custom.scom.initfile,v 1.1 2013/01/24 20:17:06 thomsen Exp $
+#-- CHANGE HISTORY:
+#--------------------------------------------------------------------------------
+#-- Version:|Author: | Date:  | Comment:
+#-- --------|--------|--------|--------------------------------------------------
+#--     1.1 |thomsen |01/23/13|Created initial version
+#-- --------|--------|--------|--------------------------------------------------
+#--------------------------------------------------------------------------------
+# End of revision history
+#--------------------------------------------------------------------------------
+
+#--Master list of variables that can be used in this file is at:
+#--<Attribute Definition Location>
+
+SyntaxVersion = 1
+
+#-- -----------------------------------------------------------------------------
+#--******************************************************************************
+#-- -----------------------------------------------------------------------------
+#--
+#-- Includes
+#-- Note:  Must include the path to the .define file.
+#-- -----------------------------------------------------------------------------
+#--******************************************************************************
+#-- -----------------------------------------------------------------------------
+include edi.io.define
+
+#-- -----------------------------------------------------------------------------
+#--******************************************************************************
+#-- -----------------------------------------------------------------------------
+#--
+#-- Defines
+#--
+#-- -----------------------------------------------------------------------------
+#--******************************************************************************
+#-- -----------------------------------------------------------------------------
+
+# ./iotk put rx_fence=1
+# 0x
+scom 0x800.0b(rx_fence_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr) {
+bits,                     scom_data;
+rx_fence,                 0b1;
+}
+
+# ./iotk put rx_c4_sel=00
+# ./iotk put rx_prot_speed_slct=1
+# 0x8009C0000201043F 
+scom 0x800.0b(rx_misc_analog_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr) {
+bits,                     scom_data;
+rx_c4_sel,                0b00;
+rx_prot_speed_slct,       0b1;
+}
+# ./iotk put rx_servo_timeout_sel_D=1001
+# 0x800B60000201043F 
+scom 0x800.0b(rx_servo_to1_pp)(rx_grp0)(lane_na).0x(cn_gcr_addr) {
+bits,                     scom_data;
+rx_servo_timeout_sel_d,   0b1001;
+}
+# ./iotk put rx_servo_timeout_sel_H=1110
+# 0x800B68000201043F 
+scom 0x800.0b(rx_servo_to2_pp)(rx_grp0)(lane_na).0x(cn_gcr_addr) {
+bits,                     scom_data;
+rx_servo_timeout_sel_h,   0b1110;
+}
+# ./iotk put rx_servo_timeout_sel_I=1011
+# ./iotk put rx_servo_timeout_sel_J=1100
+# 0x800B70000201043F 
+scom 0x800.0b(rx_servo_to3_pp)(rx_grp0)(lane_na).0x(cn_gcr_addr) {
+bits,                     scom_data;
+rx_servo_timeout_sel_i,   0b1011;
+rx_servo_timeout_sel_j,   0b1100;
+rx_servo_timeout_sel_k,   0b1101;
+}
+# ./iotk put rx_wt_timeout_sel=111
+# ./iotk put rx_ds_bl_timeout_sel=101
+# ./iotk put rx_ds_timeout_sel=110
+#./iotk put rx_sls_timeout_sel=111
+# 0x800898000201043F 
+scom 0x800.0b(rx_timeout_sel_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr) {
+bits,                     scom_data;
+rx_wt_timeout_sel,        0b111;
+rx_ds_bl_timeout_sel,     0b101;
+rx_ds_timeout_sel,        0b110;
+rx_sls_timeout_sel,       0b001;
+}
+
+# ./iotk put rx_bit_lock_timeout_sel=110
+# 0x800B08000201043F 
+scom 0x800.0b(rx_mode1_pp)(rx_grp0)(lane_na).0x(cn_gcr_addr) {
+bits,                     scom_data;
+rx_bit_lock_timeout_sel,  0b110;
+}
+# ./iotk put rx_eo_offset_timeout_sel=111
+# ./iotk put rx_eo_amp_timeout_sel=111
+# ./iotk put rx_eo_ctle_timeout_sel=111
+# ./iotk put rx_eo_h1ap_timeout_sel=111
+# ./iotk put rx_eo_ddc_timeout_sel=111
+# 0x800910000201043F 
+scom 0x800.0b(rx_timeout_sel1_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr) {
+bits,                     scom_data;
+rx_eo_offset_timeout_sel, 0b111;
+rx_eo_amp_timeout_sel,    0b111;
+rx_eo_ctle_timeout_sel,   0b111;
+rx_eo_h1ap_timeout_sel,   0b111;
+rx_eo_ddc_timeout_sel,    0b111;
+}
+
+#./iotk put tx_zcal_sm_min_val=0010101
+#./iotk put tx_zcal_sm_max_val=1000110
+# 0x800F2C000201043F 
+scom 0x800.0b(tx_impcal_swo2_pb)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_na).0x(cn_gcr_addr) {
+bits,                     scom_data;
+tx_zcal_sm_min_val,       0b0010101;
+tx_zcal_sm_max_val,       0b1000110;
+}
+#./iotk put tx_zcal_p_4x=00100
+# 0x800F1C000201043F 
+scom 0x800.0b(tx_impcal_p_4x_pb)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_na).0x(cn_gcr_addr) {
+bits,                     scom_data;
+tx_zcal_p_4x,             0b00100;
+}
+
+# 800A380002011E3F
+scom 0x800.0b(rx_eo_step_cntl_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr) {
+bits,                               scom_data;
+rx_eo_enable_latch_offset_cal,      0b1;
+rx_eo_enable_ctle_cal,              0b1;
+rx_eo_enable_vga_cal,               0b1;
+rx_eo_enable_dfe_h1_cal,            0b1;
+rx_eo_enable_h1ap_tweak,            0b1;
+rx_eo_enable_ddc,                   0b1;
+rx_eo_enable_final_l2u_adj,         0b1;
+rx_eo_enable_ber_test,              0b1;
+rx_eo_enable_result_check,          0b1;
+}
+
+scom 0x800.0b(rx_eo_convergence_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr) {
+bits,                               scom_data;
+rx_eo_converged_end_count,          0b111;
+}
+
+# 0x800AB8000201043F
+scom 0x800.0b(rx_rc_step_cntl_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr) {
+bits,                               scom_data;
+rx_rc_enable_latch_offset_cal,      0b1;
+rx_rc_enable_ctle_cal,              0b1;
+rx_rc_enable_vga_cal,               0b1;
+rx_rc_enable_h1ap_tweak,            0b1;
+rx_rc_enable_ddc,                   0b1;
+rx_rc_enable_ber_test,              0b1;
+rx_rc_enable_result_check,          0b1;
+#rx_rc_enable_dfe_h1_cal,           0b0; # Leave DFE off during recal for now
+}
+
+
+#--******************************************************************************
+#-------------------------------------------------------------------------------------
+#   _______  __    __    ___    _   ________   _____   ___    ____________  ______
+#  /_  __/ |/ /   / /   /   |  / | / / ____/  /  _/ | / / |  / / ____/ __ \/_  __/
+#   / /  |   /   / /   / /| | /  |/ / __/     / //  |/ /| | / / __/ / /_/ / / /   
+#  / /  /   |   / /___/ ___ |/ /|  / /___   _/ // /|  / | |/ / /___/ _, _/ / /    
+# /_/  /_/|_|  /_____/_/  |_/_/ |_/_____/  /___/_/ |_/  |___/_____/_/ |_| /_/     
+#                                        figlet -fslant
+#-------------------------------------------------------------------------------------
+#--******************************************************************************
+
+# These need to come as attributes from the MRW rather than be hardcoded here
+define  def_EI_TX_LANE_INVERT_VEC_CEN4 = 0x60003500;  # MSBSWAP=0 ON TULETA
+define  def_EI_TX_LANE_INVERT_VEC_CEN5 = 0x7FE4FF00;  # MSBSWAP=1 ON TULETA
+define  def_EI_TX_LANE_INVERT_VEC_CEN6 = 0xED937F00;  # MSBSWAP=1 ON TULETA
+define  def_EI_TX_LANE_INVERT_VEC_CEN7 = 0xFFF4FF00;  # MSBSWAP=1 ON TULETA
+
+# These only do a scom if the invert attribute is set (saves scom's). The default scanflush value of tx_lane_invert for each lane is '0'.
+# Lane 0
+# scom 0x800404000201043F 
+scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_0).0x(cn_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN4 & 0x80000000) > 0) && (ATTR_POS % 4 == 0); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN5 & 0x80000000) > 0) && (ATTR_POS % 4 == 1); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN6 & 0x80000000) > 0) && (ATTR_POS % 4 == 2); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN7 & 0x80000000) > 0) && (ATTR_POS % 4 == 3); 
+#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x80000000) > 0; 
+}
+# Lane 1
+# 0x800404010201043F 
+scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_1).0x(cn_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN4 & 0x40000000) > 0) && (ATTR_POS % 4 == 0); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN5 & 0x40000000) > 0) && (ATTR_POS % 4 == 1); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN6 & 0x40000000) > 0) && (ATTR_POS % 4 == 2); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN7 & 0x40000000) > 0) && (ATTR_POS % 4 == 3); 
+#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x40000000) > 0; 
+}
+# Lane 2
+# 0x800404020201043F 
+scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_2).0x(cn_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN4 & 0x20000000) > 0) && (ATTR_POS % 4 == 0); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN5 & 0x20000000) > 0) && (ATTR_POS % 4 == 1); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN6 & 0x20000000) > 0) && (ATTR_POS % 4 == 2); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN7 & 0x20000000) > 0) && (ATTR_POS % 4 == 3); 
+#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x20000000) > 0; 
+}
+# Lane 3
+# 0x800404030201043F 
+scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_3).0x(cn_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN4 & 0x10000000) > 0) && (ATTR_POS % 4 == 0); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN5 & 0x10000000) > 0) && (ATTR_POS % 4 == 1); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN6 & 0x10000000) > 0) && (ATTR_POS % 4 == 2); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN7 & 0x10000000) > 0) && (ATTR_POS % 4 == 3); 
+#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x10000000) > 0; 
+}
+# Lane 4
+# 0x800404040201043F 
+scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_4).0x(cn_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN4 & 0x08000000) > 0) && (ATTR_POS % 4 == 0); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN5 & 0x08000000) > 0) && (ATTR_POS % 4 == 1); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN6 & 0x08000000) > 0) && (ATTR_POS % 4 == 2); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN7 & 0x08000000) > 0) && (ATTR_POS % 4 == 3); 
+#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x08000000) > 0; 
+}
+# Lane 5
+# 0x800404050201043F
+scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_5).0x(cn_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN4 & 0x04000000) > 0) && (ATTR_POS % 4 == 0); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN5 & 0x04000000) > 0) && (ATTR_POS % 4 == 1); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN6 & 0x04000000) > 0) && (ATTR_POS % 4 == 2); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN7 & 0x04000000) > 0) && (ATTR_POS % 4 == 3); 
+#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x04000000) > 0; 
+}
+# Lane 6
+# 0x800404060201043F
+scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_6).0x(cn_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN4 & 0x02000000) > 0) && (ATTR_POS % 4 == 0); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN5 & 0x02000000) > 0) && (ATTR_POS % 4 == 1); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN6 & 0x02000000) > 0) && (ATTR_POS % 4 == 2); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN7 & 0x02000000) > 0) && (ATTR_POS % 4 == 3); 
+#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x02000000) > 0; 
+}
+# Lane 7
+# 0x800404070201043F
+scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_7).0x(cn_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN4 & 0x01000000) > 0) && (ATTR_POS % 4 == 0); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN5 & 0x01000000) > 0) && (ATTR_POS % 4 == 1); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN6 & 0x01000000) > 0) && (ATTR_POS % 4 == 2); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN7 & 0x01000000) > 0) && (ATTR_POS % 4 == 3); 
+#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x01000000) > 0; 
+}
+# Lane 8
+# 0x800404080201043F
+scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_8).0x(cn_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN4 & 0x00800000) > 0) && (ATTR_POS % 4 == 0); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN5 & 0x00800000) > 0) && (ATTR_POS % 4 == 1); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN6 & 0x00800000) > 0) && (ATTR_POS % 4 == 2); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN7 & 0x00800000) > 0) && (ATTR_POS % 4 == 3); 
+#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00800000) > 0; 
+}
+# Lane 9
+# 0x800404090201043F
+scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_9).0x(cn_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN4 & 0x00400000) > 0) && (ATTR_POS % 4 == 0); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN5 & 0x00400000) > 0) && (ATTR_POS % 4 == 1); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN6 & 0x00400000) > 0) && (ATTR_POS % 4 == 2); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN7 & 0x00400000) > 0) && (ATTR_POS % 4 == 3); 
+#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00400000) > 0; 
+}
+# Lane 10
+# 0x8004040A0201043F
+scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_10).0x(cn_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN4 & 0x00200000) > 0) && (ATTR_POS % 4 == 0); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN5 & 0x00200000) > 0) && (ATTR_POS % 4 == 1); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN6 & 0x00200000) > 0) && (ATTR_POS % 4 == 2); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN7 & 0x00200000) > 0) && (ATTR_POS % 4 == 3); 
+#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00200000) > 0; 
+}
+# Lane 11
+# 0x8004040B0201043F
+scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_11).0x(cn_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN4 & 0x00100000) > 0) && (ATTR_POS % 4 == 0); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN5 & 0x00100000) > 0) && (ATTR_POS % 4 == 1); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN6 & 0x00100000) > 0) && (ATTR_POS % 4 == 2); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN7 & 0x00100000) > 0) && (ATTR_POS % 4 == 3); 
+#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00100000) > 0; 
+}
+# Lane 12
+# 0x8004040C0201043F
+scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_12).0x(cn_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN4 & 0x00080000) > 0) && (ATTR_POS % 4 == 0); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN5 & 0x00080000) > 0) && (ATTR_POS % 4 == 1); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN6 & 0x00080000) > 0) && (ATTR_POS % 4 == 2); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN7 & 0x00080000) > 0) && (ATTR_POS % 4 == 3); 
+#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00080000) > 0; 
+}
+# Lane 13
+# 0x8004040D0201043F
+scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_13).0x(cn_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN4 & 0x00040000) > 0) && (ATTR_POS % 4 == 0); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN5 & 0x00040000) > 0) && (ATTR_POS % 4 == 1); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN6 & 0x00040000) > 0) && (ATTR_POS % 4 == 2); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN7 & 0x00040000) > 0) && (ATTR_POS % 4 == 3); 
+#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00040000) > 0; 
+}
+# Lane 14
+# 0x8004040E0201043F
+scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_14).0x(cn_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN4 & 0x00020000) > 0) && (ATTR_POS % 4 == 0); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN5 & 0x00020000) > 0) && (ATTR_POS % 4 == 1); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN6 & 0x00020000) > 0) && (ATTR_POS % 4 == 2); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN7 & 0x00020000) > 0) && (ATTR_POS % 4 == 3); 
+#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00020000) > 0; 
+}
+# Lane 15
+# 0x8004040F0201043F
+scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_15).0x(cn_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN4 & 0x00010000) > 0) && (ATTR_POS % 4 == 0); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN5 & 0x00010000) > 0) && (ATTR_POS % 4 == 1); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN6 & 0x00010000) > 0) && (ATTR_POS % 4 == 2); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN7 & 0x00010000) > 0) && (ATTR_POS % 4 == 3); 
+#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00010000) > 0; 
+}
+# Lane 16
+# 0x800404100201043F
+scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_16).0x(cn_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN4 & 0x00008000) > 0) && (ATTR_POS % 4 == 0); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN5 & 0x00008000) > 0) && (ATTR_POS % 4 == 1); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN6 & 0x00008000) > 0) && (ATTR_POS % 4 == 2); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN7 & 0x00008000) > 0) && (ATTR_POS % 4 == 3); 
+#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00008000) > 0; 
+}
+# Lane 17
+# 0x800404110201043F
+scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_17).0x(cn_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN4 & 0x00004000) > 0) && (ATTR_POS % 4 == 0); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN5 & 0x00004000) > 0) && (ATTR_POS % 4 == 1); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN6 & 0x00004000) > 0) && (ATTR_POS % 4 == 2); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN7 & 0x00004000) > 0) && (ATTR_POS % 4 == 3); 
+#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00004000) > 0; 
+}
+# Lane 18
+# 0x800404120201043F
+scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_18).0x(cn_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN4 & 0x00002000) > 0) && (ATTR_POS % 4 == 0); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN5 & 0x00002000) > 0) && (ATTR_POS % 4 == 1); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN6 & 0x00002000) > 0) && (ATTR_POS % 4 == 2); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN7 & 0x00002000) > 0) && (ATTR_POS % 4 == 3); 
+#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00002000) > 0; 
+}
+# Lane 19
+# 0x800404130201043F
+scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_19).0x(cn_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN4 & 0x00001000) > 0) && (ATTR_POS % 4 == 0); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN5 & 0x00001000) > 0) && (ATTR_POS % 4 == 1); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN6 & 0x00001000) > 0) && (ATTR_POS % 4 == 2); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN7 & 0x00001000) > 0) && (ATTR_POS % 4 == 3); 
+#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00001000) > 0; 
+}
+# Lane 20
+# 0x800404140201043F
+scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_20).0x(cn_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN4 & 0x00000800) > 0) && (ATTR_POS % 4 == 0); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN5 & 0x00000800) > 0) && (ATTR_POS % 4 == 1); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN6 & 0x00000800) > 0) && (ATTR_POS % 4 == 2); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN7 & 0x00000800) > 0) && (ATTR_POS % 4 == 3); 
+#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00000800) > 0; 
+}
+# Lane 21
+# 0x800404150201043F
+scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_21).0x(cn_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN4 & 0x00000400) > 0) && (ATTR_POS % 4 == 0); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN5 & 0x00000400) > 0) && (ATTR_POS % 4 == 1); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN6 & 0x00000400) > 0) && (ATTR_POS % 4 == 2); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN7 & 0x00000400) > 0) && (ATTR_POS % 4 == 3); 
+#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00000400) > 0; 
+}
+# Lane 22
+# 0x800404160201043F
+scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_22).0x(cn_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN4 & 0x00000200) > 0) && (ATTR_POS % 4 == 0); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN5 & 0x00000200) > 0) && (ATTR_POS % 4 == 1); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN6 & 0x00000200) > 0) && (ATTR_POS % 4 == 2); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN7 & 0x00000200) > 0) && (ATTR_POS % 4 == 3); 
+#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00000200) > 0; 
+}
+# Lane 23
+# 0x800404170201043F
+scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_23).0x(cn_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN4 & 0x00000100) > 0) && (ATTR_POS % 4 == 0); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN5 & 0x00000100) > 0) && (ATTR_POS % 4 == 1); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN6 & 0x00000100) > 0) && (ATTR_POS % 4 == 2); 
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_CEN7 & 0x00000100) > 0) && (ATTR_POS % 4 == 3); 
+#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00000100) > 0; 
+}
+
+#--***********************************************************************************
+#-------------------------------------------------------------------------------------
+#     __  ________ ____     _____                   
+#    /  |/  / ___// __ )   / ___/      ______ _____ 
+#   / /|_/ /\__ \/ __  |   \__ \ | /| / / __ `/ __ \
+#  / /  / /___/ / /_/ /   ___/ / |/ |/ / /_/ / /_/ /
+# /_/  /_//____/_____/   /____/|__/|__/\__,_/ .___/ 
+#                                         /_/      
+#                                        figlet -fslant
+#-------------------------------------------------------------------------------------
+#--***********************************************************************************
+
+# TX_MSBSWAP setting via manaual SCOM overrides
+# ./iotk put tx_msbswap=1 (only when p# mod 4 = 3 for centaur or mcs mod 4 = 0, ie. grp0)
+# 0x800C1C000201043F 
+scom 0x800.0b(tx_mode_pg)(tx_grp0)(lane_na).0x(cn_gcr_addr) {
+bits,                     scom_data, expr;
+tx_msbswap,               0b0,       (ATTR_POS % 4 == 0); # P4
+tx_msbswap,               0b1,       (ATTR_POS % 4 == 1); # P5
+tx_msbswap,               0b1,       (ATTR_POS % 4 == 2); # P6
+tx_msbswap,               0b1,       (ATTR_POS % 4 == 3); # P7
+#tx_msbswap,               0b1,       (ATTR_EI_BUS_TX_MSBSWAP == 0x01);
+}
+
+
+############################################################################################
+# END OF FILE
+############################################################################################
diff --git a/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile b/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile
index 5768a4397..3cb9706d8 100755
--- a/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile
+++ b/src/usr/hwpf/hwp/initfiles/cen_ddrphy.initfile
@@ -1,8 +1,14 @@
-#-- $Id: cen_ddrphy.initfile,v 1.19 2012/12/12 20:46:54 mwuu Exp $
+#-- $Id: cen_ddrphy.initfile,v 1.20 2013/01/16 21:07:47 mwuu Exp $
 #-- CHANGE HISTORY:
 #--------------------------------------------------------------------------------
 #-- Version:|Author: | Date:  | Comment:
 #-- --------|--------|--------|--------------------------------------------------
+#--     1.20|mwuu    |01/16/12|Updated TWTR & TRTP define for FW_WR_RD field in
+#           |        |        |WC_CONFIG0 and FW_RD_WR in WC_CONFIG2 in 0W spec.
+#           |        |        |Thin Oxide hibernation disabled in ATEST & BIT_DIR1
+#           |		 |		  |registers.
+#			|		 |		  |Changed Bang-Bang Margin in ADR32_SYSCLK_ROT_OVERRIDE
+#			|		 |		  |field of DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0
 #--     1.19|mwuu    |12/12/12|Commented out settings for SIM, changed attribute
 #           |        |        |to CEN.ATTR_CENTAUR_EC_WRITE_FIR_MASK_FEATURE
 #--		1.18|mwuu	 |12/03/12|Changed DP18_PLL_CONFIG1 VCO setting
@@ -261,11 +267,13 @@ define def_cdi_spcke_ohm40_p1	=	(ATTR_EFF_CEN_DRV_IMP_SPCKE[1] == ENUM_ATTR_EFF_
 # SIMPLIFY
 # ================================================================================
 # test if AL is disabled
-define def_AL_ena	= (ATTR_EFF_DRAM_AL != 0);		#!! need to fix if AL == 0 then formulas below have problems
+define def_AL_ena	= (ATTR_EFF_DRAM_AL != 0);
+define def_AL_dis	= (ATTR_EFF_DRAM_AL == 0);
 
 # for calculating FW_RD_WR delay...  NOTE: AL could be disabled(=0)
-define def_TWTR_PLUS_8	= (ATTR_EFF_DRAM_TWTR + 8)	;
-define def_TRTP_PLUS_AL	= (ATTR_EFF_DRAM_TRTP + ATTR_EFF_DRAM_CL - ATTR_EFF_DRAM_AL)	;
+define def_TWTR_PLUS_OFF = (ATTR_EFF_DRAM_TWTR + 11)	;	# change from +8 on reg spec 
+define def_TRTP_PLUS_AL	= (ATTR_EFF_DRAM_TRTP + ATTR_EFF_DRAM_CL - ATTR_EFF_DRAM_AL + 3)	;
+define def_TRTP_PLUS_NOAL = (ATTR_EFF_DRAM_TRTP + 3)	;
 
 # for ODT on/off time calculation
 # 2tCK = DDR4 feature for extended write preamble, should be defined by attribute if used.
@@ -2388,8 +2396,8 @@ scom 0x80003C060301143f {	# _P[0:1]_[0:4] via broadcast
 	60		,	0b0			,	any				;	# else (DDR3), POD=0.5*VDD
 	61		,	0b0			,	any				;	# 1=DISABLE_TERMINATION, for dq/dqs pins
 	# READ_CENTERING_MODE
-	# (00=MPR_PATTERN_BIT or staggered, custom [01=serial, 10=parallel, 11=custom] using SEQ rd/wr data
-	62:63	,	0b11		,	def_is_ddr4		;	# for DDR4
+	# (00=MPR_PATTERN_BIT or staggered, custom [11=snooped, 00=custom] using SEQ rd/wr data
+	62:63	,	0b11		,	(def_is_ddr4)	;	# for DDR4
 	62:63	,	0b00		,	any				;	#
 }
 
@@ -2422,8 +2430,8 @@ scom 0x80013C060301143f {	# _P1_[0:4] via broadcast
 	60		,	0b0			,	any				;	# else (DDR3), POD=0.5*VDD
 	61		,	0b0			,	any				;	# 1=DISABLE_TERMINATION, for dq/dqs pins
 	# READ_CENTERING_MODE
-	# (00=MPR_PATTERN_BIT or staggered, custom [01=serial, 10=parallel, 11=custom] using SEQ rd/wr data
-	62:63	,	0b11		,	def_is_ddr4		;	# for DDR4
+	# (00=MPR_PATTERN_BIT or staggered, custom [11=snooped, 00=custom] using SEQ rd/wr data
+	62:63	,	0b11		,	(def_is_ddr4)	;	# for DDR4
 	62:63	,	0b00		,	any				;	#
 }
 
@@ -2597,24 +2605,41 @@ scom 0x8001c0150301143f {
 # beats. Each bit lane can have a different pattern, but the composite pattern should have
 # transitions at each beat.
 #
+#	48:63	,	0x0000		,	(def_is_sim)	;	# to match dials
+#
+#  in DDR3 only bits 48:55 are used as pattern, and 56:63 must match 48:55.
 #						    [0:1]
 # DPHY01_DDRPHY_SEQ_RD_WR_DATA0_P0		0x000-0x001		0x8000c4000301143f
-# DPHY01_DDRPHY_SEQ_RD_WR_DATA1_P0
 # PHYW.PHYX.SYNTHX.D3SIDEA.SEQX.U_SEQ_APB.RD_WR_DATA0_L2
-scom 0x8000c40(0,1)0301143f {
+scom 0x8000c4000301143f {
 	bits	,	scom_data	,	expr			;	#				beat 12345678
 #	0:47	,	0x000000000000,	any				;	# reserved
-#	48:63	,	0x0000		,	(def_is_sim)	;	# to match dials
+# if DDR4 = 0:7 (MPR0), 8:15 (MPR1)
+	48:63	,	0x5555		,	any				;	# MPR_PATTERN_BIT of 0F0F0F0F pattern
+#	48:63	,	0xD896		,	any				;	# 1st half-nibble of EA0CA653 pattern
+}
+# DPHY01_DDRPHY_SEQ_RD_WR_DATA1_P0
+scom 0x8000c4010301143f {
+	bits	,	scom_data	,	expr			;	#				beat 12345678
+#	0:47	,	0x000000000000,	any				;	# reserved
+# if DDR4 = 0:7 (MPR2), 8:15 (MPR3)
 	48:63	,	0x5555		,	any				;	# MPR_PATTERN_BIT of 0F0F0F0F pattern
 #	48:63	,	0xD896		,	any				;	# 1st half-nibble of EA0CA653 pattern
 }
 
 # DPHY01_DDRPHY_SEQ_RD_WR_DATA0_P1
+scom 0x8001c4000301143f {
+	bits	,	scom_data	,	expr			;	#				beat 12345678
+#	0:47	,	0x000000000000,	any				;	# reserved
+# if DDR4 = 0:7 (MPR0), 8:15 (MPR1)
+	48:63	,	0x5555		,	any				;	# MPR_PATTERN_BIT of 0F0F0F0F pattern
+#	48:63	,	0xCD03		,	any				;	# 2st half-nibble of EA0CA653 pattern
+}
 # DPHY01_DDRPHY_SEQ_RD_WR_DATA1_P1
-scom 0x8001c40(0,1)0301143f {
+scom 0x8001c4010301143f {
 	bits	,	scom_data	,	expr			;	#				beat 12345678
 #	0:47	,	0x000000000000,	any				;	# reserved
-#	48:63	,	0x0000		,	(def_is_sim)	;	# to match dials
+# if DDR4 = 0:7 (MPR2), 8:15 (MPR3)
 	48:63	,	0x5555		,	any				;	# MPR_PATTERN_BIT of 0F0F0F0F pattern
 #	48:63	,	0xCD03		,	any				;	# 2st half-nibble of EA0CA653 pattern
 }
@@ -3005,6 +3030,8 @@ scom 0x800(0,1)3C370301143f {	# _P[0:1]_[0:4]
 # leveling algorithm does not reset this register. The write eye centering algorithm uses this
 # register value as a starting point for the algorithm.
 #
+# Note: This register must be reset prior to re-running initial calibration.
+#
 # DPHY01_DP18_WR_DELAY_VALUE_0_RP0_REG_P0_0		0x038-0x04F		0x800000380301143f
 # PHYW.PHYX.GEN_DP#0.DPX.HC.HC.D3PHY_WRDP18WRAP.D3PHY_WRDP18CNTL_MAC.DP18_WR_DELAY_VALUE_0_RP0_REG_L2
 #
@@ -3061,9 +3088,9 @@ scom 0x800(0,1)3C370301143f {	# _P[0:1]_[0:4]
 #
 
 # ---------------------------------------------------------------------------------------
-# DP18 Read Diagnostic Configuration 3 Register		!! need to set this?
+# DP18 Read Diagnostic Configuration 3 Register		default=0x0806	!! need to set this?
 #
-# !! can't find address in DB
+# DDRPHY_DP18_RD_DIA_CONFIG3		0x06D		0x8000
 
 # ---------------------------------------------------------------------------------------
 # Initial calibration sequence Config0 register		default=0	sim = 0xBF2?
@@ -3155,7 +3182,7 @@ scom 0x800(0,1)C0170301143F {	# _P[0:1]
 #	0:47	,	0x000000000000	,	any				;	# reserved
 	48:51	,	0b0000			,	any				;	# REFRESH_COUNT, num of refreshes before cal
 	52:53	,	0b00			,	any				;	# REFRESH_CONTROL during initial calibration
-	54		,	0b0				,	any				;	# REFRESH_ALL_RANKS, during calibration
+	54		,	0b0				,	any				;	# REFRESH_ALL_RANKS, 1 issued to each rank seq.
 #	55:56	,	0b00			,	any				;	# reserved
 	# REFRESH_INTERVAL, defaults to 6 if value < 6, value*256=num clks between refreshes
 	# ATTR_EFF_DRAM_TRFI = refresh interval in clocks
@@ -3185,16 +3212,17 @@ scom 0x8000C00B0301143F {	# Port 0
 
 	52		,	0b1			,	any						;	# PER_ENA_ZCAL
 	53		,	0b1			,	any						;	# PER_ENA_SYSCLK_ALIGN
-	54		,	0b1			,	any						;	# ENA_PER_RDCLK_ALIGN
-	55		,	0b1			,	any						;	# ENA_PER_DQS_ALIGN
-	56		,	0b1			,	any						;	# ENA_PER_READ_CTR
+	54		,	0b1			,	any						;	# ENA_PER_READ_CTR
+	55		,	0b1			,	any						;	# ENA_PER_RDCLK_ALIGN
+	56		,	0b1			,	any						;	# ENA_PER_DQS_ALIGN
 	57:58	,	0b00		,	any						;	# PER_NEXT_RANK_PAIR
 	59		,	0b1			,	(def_FAST_SIM_PC==1)	;	# FAST_SIM_PER_CNTR
 	59		,	0b0			,	(def_FAST_SIM_PC==0)	;	# FAST_SIM_PER_CNTR
 	60		,	0b0			,	any						;	# START_INIT_CAL
 	61		,	0b0			,	any						;	# START_PER_CAL
 	62		,	0b0			,	any						;	# ABORT_ON_ERR_EN
-	63		,	0b0			,	any						;	# ZCAL_UPDATE_MODE
+	63		,	0b0			,	any						;	# DD2_FIX_DIS
+#63		,	0b0			,	any						;	# ZCAL_UPDATE_MODE
 }
 # DPHY01.DDRPHY_PC_PER_CAL_CONFIG_P1
 scom 0x8001C00B0301143F {	# Port 1
@@ -3653,10 +3681,10 @@ scom 0x800(0,1)C8000301143F {	# _P[0:1]
 	#
 	# min GPO = 5 + max(rndUp(System_delay)) - RLO + ADVANCE_RD_VALID + SPAM_EN
 	# max GPO = 11 if in 2:1, 13 if in 4:1
-	48:51	,	0b0101		,	any				;	# GLOBAL_PHY_OFFSET (GPO), 2:1 max=11, 4:1 max=13
+	48:51	,	0b0101		,	any				;	# GLOBAL_PHY_OFFSET (GPO), ideally 2:1 max=11, 4:1 max=13
 	52		,	0b0			,	any				;	# ADVANCE_RD_VALID	ask Yuen
-	53		,	0b0			,	any				;	# ERS_MODE, reserved
-	54:56	,	0b000		,	any				;	# PER_REPEAT_COUNT, (value+1)=num bits per peridic cal
+	53		,	0b0			,	any				;	# PER_DUTY_CYCLE_SW, 0=rd cmds 50% duty cycle during per.cal, 1=continuously 
+	54:56	,	0b000		,	any				;	# NUM_PERIODIC_CAL, (value+1)=num bits per peridic cal
 	57		,	0b0			,	any				;	# SINGLE_BIT_MPR_RP0
 	58		,	0b0			,	any				;	# SINGLE_BIT_MPR_RP1
 	59		,	0b0			,	any				;	# SINGLE_BIT_MPR_RP2
@@ -3664,7 +3692,7 @@ scom 0x800(0,1)C8000301143F {	# _P[0:1]
 	61		,	0b0			,	any				;	# ALIGN_ON_EVEN_CYCLES
 # !! switched to '1' to match SIM
 	62		,	0b1			,	any				;	# PERFORM_RDCLK_ALIGN
-	63		,	0b0			,	any				;	# STAGGERED_PATTERN
+	63		,	0b0			,	any				;	# STAGGERED_PATTERN		# for DDR4, 0=serial, 1=staggered
 }
 
 # ---------------------------------------------------------------------------------------
@@ -3749,8 +3777,8 @@ scom 0x800(0,1)C4020301143F {	# _P[0:1]
 	50:53	,	0b0000			;	# MR_MASK_EN (mode register[0:3] mask during calibration)
 	54		,	0b0				;	# DELAYED_PARITY (only for DDR4, DDR3 don't care)
 	55		,	0b0				;	# LRDIMM_CONTEXT
-	56		,	0b0				;	# FORCE_RESERVED
-	57		,	0b0				;	# HALT_ROTATION
+	56		,	0b0				;	# FORCE_RESERVED	# for DDR4
+	57		,	0b0				;	# HALT_ROTATION, for DDR4 staggered pattern
 	58		,	0b0				;	# FORCE_MPR
 #	59:63	,	0b00000			;	# reserved
 }
@@ -3847,7 +3875,7 @@ scom 0x800(0,1)C4120301143F {	# _P[0:1]
 #
 # 	[01:23]					   [0:2] [0:1]
 # DPHY01_DDRPHY_SEQ_MEM_TIMING_PARAM1_P0	CTL	0x013	0x8000c4130301143f
-# PHYW.PHYX.SYNTHX.D3SIDEA.SEQX.U_SEQ_APB.MEM_TIMING_PARAM1_L2
+# PHYW.PHYX.SYNHX.D3SIDEA.SEQX.U_SEQ_APB.MEM_TIMING_PARAM1_L2T
 scom 0x800(0,1)C4130301143F {	# _P[0:1]
 	bits	,	scom_data	,	expr											;
 #	0:47	,	0x000000000000,	any												;	# reserved
@@ -3981,11 +4009,18 @@ scom 0x800(0,1)CC000301143F {	# _P[0:1]
 	#48:55	,	0x1B				,	any										;	# TWLO_TWLOE = 27
 	#48:55	,	(25+ldqs+ldq)		,	(CEN.ATTR_MSS_FREQ > 1460)				;	# TWLO_TWLOE	(> 1333)
 	56		,	0b1					,	any										;	# WL_ONE_DQS_PULSE = enable
-	# FW_WR_RD = max(tWTR+8,AL+tRTP), AL=ATTR_EFF_DRAM_CL-ATTR_EFF_DRAM_AL when ATTR_EFF_DRAM_AL != 0
+
+	# FW_WR_RD = max(tWTR+11,AL+tRTP+3), ATTR_EFF_DRAM_AL(0,1,2)
 	57:62	,	0b000000			,	(def_is_sim)							;
-	57:62	,	0b010001			,	any										;	# same as DD0, right aligned here, 17d
-	57:62	,	(def_TWTR_PLUS_8)	,	(def_TWTR_PLUS_8 >= def_TRTP_PLUS_AL)	;	# TWTR + 8 >= TRTP + AL
-	57:62	,	(def_TRTP_PLUS_AL)	,	(def_TWTR_PLUS_8 < def_TRTP_PLUS_AL)	;	# TWTR + 8 < TRTP + AL
+	57:62	,	0b010001			,	any										;	# same as dd0
+	
+	# AL={1,2};	max (TWTR + 11, TRTP + AL + 3)
+	57:62	,	(def_TWTR_PLUS_OFF)	,	(def_AL_ena && (def_TWTR_PLUS_OFF >= def_TRTP_PLUS_AL) )	;	# TWTR + 11
+	57:62	,	(def_TRTP_PLUS_AL)	,	(def_AL_ena && (def_TWTR_PLUS_OFF < def_TRTP_PLUS_AL) )		;	# TRTP + AL + 3
+
+	# AL=0, 	max (TWTR + 11, TRTP + 3)
+	57:62	,	(def_TWTR_PLUS_OFF)	,	(def_AL_dis && (def_TWTR_PLUS_OFF >= def_TRTP_PLUS_NOAL) )	;	# TWTR + 11
+	57:62	,	(def_TRTP_PLUS_NOAL),	(def_AL_dis && (def_TWTR_PLUS_OFF < def_TRTP_PLUS_NOAL)	)	;	# TRTP + 3
 
 	63		,	0b0					,	any										;	# CUSTOM_INIT_WRITE
 }
@@ -4016,19 +4051,18 @@ scom 0x800(0,1)CC020301143F {	# _P[0:1]
 	48:51	,	0x3					,	(def_is_sim)	;	# NUM_VALID_SAMPLES = 3 (changed from defaults)
 	48:51	,	0x5					,	any				;	# NUM_VALID_SAMPLES = 5 (defaults)
 
-	# FW_RD_WR = max(tWTR+8,AL+tRTP), AL=ATTR_EFF_DRAM_CL-ATTR_EFF_DRAM_AL when ATTR_EFF_DRAM_AL != 0
-	52:57	,	(def_TWTR_PLUS_8)	,	(def_TWTR_PLUS_8 >= def_TRTP_PLUS_AL)	;	# TWTR + 8 >= TRTP + AL
-	52:57	,	(def_TRTP_PLUS_AL)	,	(def_TWTR_PLUS_8 < def_TRTP_PLUS_AL)	;	# TWTR + 8 < TRTP + AL
-
-# RL=CL+AL, WL=CWL+AL	!! Need to fix
-# = CL + 2tCK + tCCD/x   x=1 if
-# Read to write = RL + tCCD + 2tCK - WL (in DDR3 JEDEC for Read BL8 to Write BL8)
-# Read to write = RL + tCCD/2 + 2tCK - WL (in DDR3 JEDEC for Read BC4 to Write BC4/BL8 OTF)
-#	52:57	,	def_fw_rd_wr,		,	(def_TWTR_PLUS_8 < def_TRTP_PLUS_AL)	;	# TWTR + 8 < TRTP + AL
-
+	# FW_RD_WR = max(tWTR+11,AL+tRTP+3), AL=ATTR_EFF_DRAM_CL-ATTR_EFF_DRAM_AL when ATTR_EFF_DRAM_AL != 0
+	# AL={1,2};	max (TWTR + 11, TRTP + AL + 3)
+	52:57	,	(def_TWTR_PLUS_OFF)	,	(def_AL_ena && (def_TWTR_PLUS_OFF >= def_TRTP_PLUS_AL) )	;	# TWTR + 11
+	52:57	,	(def_TRTP_PLUS_AL)	,	(def_AL_ena && (def_TWTR_PLUS_OFF < def_TRTP_PLUS_AL) )		;	# TRTP + AL + 3
 
-#	58:62	,	0b00000				,	any				;	# reserved
+	# AL=0, 	max (TWTR + 11, TRTP + 3)
+	52:57	,	(def_TWTR_PLUS_OFF)	,	(def_AL_dis && (def_TWTR_PLUS_OFF >= def_TRTP_PLUS_NOAL) )	;	# TWTR + 11
+	52:57	,	(def_TRTP_PLUS_NOAL),	(def_AL_dis && (def_TWTR_PLUS_OFF < def_TRTP_PLUS_NOAL)	)	;	# TRTP + 3
 
+#	58:61	,	0b00000				,	any				;	# reserved
+	# DD2_FIX_DIS
+	62		,	0b0					,	any				;	# 0=disable 1=enable DD2 fixes in WC logic
 	# DP18_WR_DELAY_VALUE_{0-23}_RP{0-3}_REG are reset to 0 at the start of WL cal for rank pair 0 when '1'
 	63		,	0b0					,	any				;	# EN_RESET_WR_DELAY_WL = disabled
 }
@@ -4072,7 +4106,9 @@ scom 0x800(0,1)CC050301143F {	# _P[0:1]
 scom 0x800(0,1)3C030301143f {	# DIR1_P[0:1]_[0:4] via broadcast
 	bits	,	scom_data	,	expr			;
 #	0:47	,	0x000000000000,	any				;	# reserved
-#	48:54	,	0b0000000	,	any				;	# reserved... used to be DATA_BIT_DIR_16_23
+#	48:52	,	0b000000	,	any				;	# reserved... used to be DATA_BIT_DIR_16_23
+	53		,	0b0			,	any				;	# DD2_FIX_DIS
+	54		,	0b1			,	any				;	# TOXDRV_HIBERNATE	# Thin oxide driver hibernation disable.
 	55		,	0b0			,	any				;	# ATEST_MUX_CTL_EN
 	56		,	0b0			,	any				;	# WL_ADVANCE_DISABLE
 	57		,	0b0			,	any				;	# DISABLE_PING_PONG
@@ -4082,6 +4118,28 @@ scom 0x800(0,1)3C030301143f {	# DIR1_P[0:1]_[0:4] via broadcast
 }
 
 # ---------------------------------------------------------------------------------------
+# ADR Output Driver Force and ATEST Control Register
+# 
+# DPHY01_DDRPHY_ADR_OUTPUT_FORCE_ATEST_CNTL_P0_ADR32S0	0x035	0x800080350301143f
+#scom 0x800(0,1)(80,84)350301143f {	# P[0:1]_ADR32S[0:1]
+scom 0x800(0,1)BC350301143f {	# DIR1_P[0:1]_[0:4] via broadcast
+	bits	,	scom_data	,	expr			;
+#	0:47	,	0x000000000000,	any				;	# reserved
+#	48		,	0b0			,	any				;	# FLUSH control to ANALOG during Manufacturing Macro Test - reserved.
+#	49		,	0b0			,	any				;	# FORCE_EN			output Force Enable Bit.
+	50		,	0b1			,	any				;	# TOXDRV_HIBERNATE	thin oxide driver hibernation disable.
+#	51		,	0b0			,	any				;	# ATEST1CTL_EN		Enable ATEST1 output.
+#	52:55	,	0b0000		,	any				;	# HS_PROBE_A_SEL	High Speed Probe A Select - reserved.
+#	56:59	,	0b0000		,	any				;	# HS_PROBE_B_SEL	High Speed Probe B Select - reserved.
+#	60		,	0b0			,	any				;	# ATEST1CTL0		bit 0 of ATEST1CTL value  - reserved
+#	61		,	0b0			,	any				;	# ATEST1CTL1		bit 1 of ATEST1CTL value  - reserved
+#	62		,	0b0			,	any				;	# ATEST1CTL2		bit 2 of ATEST1CTL value  - reserved.
+#	63		,	0b0			,	any				;	# ATEST1CTL3		bit 3 of ATEST1CTL value  - reserved.
+}
+
+#
+#
+# ---------------------------------------------------------------------------------------
 # DP18 Data Bit Enable 0	(defaults to 0's)	Affects ALL Ranks
 #
 # DP18 24 single ended data (tx/rx) pins enable(1)/disable(0).
@@ -4773,7 +4831,7 @@ scom 0x800(0,1)BC320301143F {		# _P[0:1]_ADR32S[0:1] via broadcast
 # old dials value = 0x0080
 	48		,	0b1			,	any				;	# ADR32_SYSCLK_ENABLE
 
-	49:55	,	0b0000000	,	any				;	# ADR32_SYSCLK_ROT_OVERRIDE
+	49:55	,	0b0000010	,	any				;	# ADR32_SYSCLK_ROT_OVERRIDE
 
 	56		,	0b0			,	any				;	# ADR32_SYSCLK_ROT_OVERRIDE_EN
 
diff --git a/src/usr/hwpf/hwp/initfiles/mba_def.initfile b/src/usr/hwpf/hwp/initfiles/mba_def.initfile
index 27e0f37b2..465704046 100644
--- a/src/usr/hwpf/hwp/initfiles/mba_def.initfile
+++ b/src/usr/hwpf/hwp/initfiles/mba_def.initfile
@@ -1,9 +1,15 @@
 
-#-- $Id: mba_def.initfile,v 1.24 2013/01/04 20:38:58 yctschan Exp $
+#-- $Id: mba_def.initfile,v 1.26 2013/01/23 14:55:47 yctschan Exp $
 #-- CHANGE HISTORY:
 #--------------------------------------------------------------------------------
 #-- Version:|Author: | Date:  | Comment:
 #-- --------|--------|--------|--------------------------------------------------
+#--     1.26|tschang | 1/23/13|Write Latency equation changed for mba_tmr0 register - define def_WL = (ATTR_EFF_DRAM_CWL + ATTR_EFF_DRAM_CL - 1 - 7)
+#--     1.25|tschang | 1/17/13|added def_margin constant to increment mba tmr0 register by the value of def_margin - current setting of margin is 2
+#--     1.24|tschang | 1/04/13|added code to detect and overrun condition with periodic cal and choose a larger timebase when that happens
+#--                           |fixed periodic cal type to properly choose periodic cal
+#--     1.23|tschang |12/18/12|changed SYS.ATTR_IS_SIMULATION ==0 to CENTAUR.ATTR_MSS_FREQ ==1400 to cause a false coniditon place holder
+#--                            changed rdtag to be 36 for all configurations
 #--     1.22|menlowuu|12/04/12|changed CCS_Mode register to set RAS, CAS, WE to high on idles
 #--     1.21|tschang |11/14/12|added throttle control for n/m
 #--     1.20|tschang |11/13/12|updated file for new IBM_TYPE defnitions and added MCBIST ADDR and ADDR mapping fro SCHMOO
@@ -225,12 +231,16 @@ define def_equal_test     =  (SYS.ATTR_SCRATCH_UINT32_1 == SYS.ATTR_SCRATCH_UINT
 #};
 
 
+# mba tmr0 register timings are added to the value below
+define def_margin      = (2);
+
+
 define def_no_spare     =   (SYS.ATTR_IS_SIMULATION==1) ;
 define def_has_spare    =   (SYS.ATTR_IS_SIMULATION==0) ;
 
 #define def_ATTR_EFF_IBM_TYPE = 1;
 #define def_ATTR_EFF_NUM_DROPS_PER_PORT = 1;
-#define  def_ATTR_EFF_DRAM_2N_MODE = 0;
+#define  def_ATTR_EFF_DRAM_2N_MODE = (0);
 #define def_ATTR_EFF_IBM_TYPE           = (SYS.ATTR_IS_SIMULATION==0) ;   # will evaluate to false
 #define def_ATTR_EFF_NUM_DROPS_PER_PORT = (SYS.ATTR_IS_SIMULATION==0) ;   # will evaluate to false
 define def_ATTR_EFF_DRAM_2N_MODE       = (CENTAUR.ATTR_MSS_FREQ == 1400) ;   # will evaluate to false
@@ -1868,9 +1878,6 @@ scom 0x03010415     {
 
 
 
-
-
-
 ###########################
 # MBA timer values        #
 ###########################
@@ -1884,79 +1891,79 @@ scom 0x03010415     {
 #
 scom 0x0301040B     {
     bits    ,   scom_data   ,       ATTR_FUNCTIONAL,    expr;
-    0:3     ,   0b0100     ,             1            ,   any; # RRSMSR_dly is 4 for all cfgs     1                                                      D
-    4:7     ,   0b0100     ,             1            ,   any; # RRSMDR_dly is 4 for all cfgs     2                                                      D
-    8:11    ,   0b0111     ,             1            ,   (CENTAUR.ATTR_MSS_FREQ == 1066) || (CENTAUR.ATTR_MSS_FREQ == 1333) || (CENTAUR.ATTR_MSS_FREQ == 1600); # RRDM_dly     3    D
-    8:11    ,   0b1000     ,             1            ,   (CENTAUR.ATTR_MSS_FREQ == 1866) || (CENTAUR.ATTR_MSS_FREQ == 2133); # RRDM_dly     3                             D
-    8:11    ,   0b1001     ,             1            ,   (CENTAUR.ATTR_MSS_FREQ == 2400); # RRDM_dly     3                                                      D
-    12:15   ,   0b0001     ,             1            ,   (def_mba_tmr0q_RW_dlys7  == 1); # RWSMSR_dly   4
-    12:15   ,   0b1000     ,             1            ,   (def_mba_tmr0q_RW_dlys8  == 1); # RWSMSR_dly   4
-    12:15   ,   0b1001     ,             1            ,   (def_mba_tmr0q_RW_dlys9  == 1); # RWSMSR_dly   4
-    12:15   ,   0b1010     ,             1            ,   (def_mba_tmr0q_RW_dlys10 == 1); # RWSMSR_dly   4
-    12:15   ,   0b1011     ,             1            ,   (def_mba_tmr0q_RW_dlys11 == 1); # RWSMSR_dly   4
-    12:15   ,   0b1100     ,             1            ,   (def_mba_tmr0q_RW_dlys12 == 1); # RWSMSR_dly   4
-    12:15   ,   0b1101     ,             1            ,   (def_mba_tmr0q_RW_dlys13 == 1); # RWSMSR_dly   4
-    12:15   ,   0b1110     ,             1            ,   (def_mba_tmr0q_RW_dlys14 == 1); # RWSMSR_dly   4
-    12:15   ,   0b1111     ,             1            ,   (def_mba_tmr0q_RW_dlys15 == 1); # RWSMSR_dly   4
-    16:19   ,   0b0001     ,             1            ,   (def_mba_tmr0q_RW_dlys7  == 1); # RWSMDR_dly   5
-    16:19   ,   0b1000     ,             1            ,   (def_mba_tmr0q_RW_dlys8  == 1); # RWSMDR_dly   5
-    16:19   ,   0b1001     ,             1            ,   (def_mba_tmr0q_RW_dlys9  == 1); # RWSMDR_dly   5
-    16:19   ,   0b1010     ,             1            ,   (def_mba_tmr0q_RW_dlys10 == 1); # RWSMDR_dly   5
-    16:19   ,   0b1011     ,             1            ,   (def_mba_tmr0q_RW_dlys11 == 1); # RWSMDR_dly   5
-    16:19   ,   0b1100     ,             1            ,   (def_mba_tmr0q_RW_dlys12 == 1); # RWSMDR_dly   5
-    16:19   ,   0b1101     ,             1            ,   (def_mba_tmr0q_RW_dlys13 == 1); # RWSMDR_dly   5
-    16:19   ,   0b1110     ,             1            ,   (def_mba_tmr0q_RW_dlys14 == 1); # RWSMDR_dly   5
-    16:19   ,   0b1111     ,             1            ,   (def_mba_tmr0q_RW_dlys15 == 1); # RWSMDR_dly   5
-    20:23   ,   0b0001     ,             1            ,   (def_mba_tmr0q_RW_dlys7  == 1); # RWDM_dly	 6
-    20:23   ,   0b1000     ,             1            ,   (def_mba_tmr0q_RW_dlys8  == 1); # RWDM_dly	 6
-    20:23   ,   0b1001     ,             1            ,   (def_mba_tmr0q_RW_dlys9  == 1); # RWDM_dly	 6
-    20:23   ,   0b1010     ,             1            ,   (def_mba_tmr0q_RW_dlys10 == 1); # RWDM_dly	 6
-    20:23   ,   0b1011     ,             1            ,   (def_mba_tmr0q_RW_dlys11 == 1); # RWDM_dly	 6
-    20:23   ,   0b1100     ,             1            ,   (def_mba_tmr0q_RW_dlys12 == 1); # RWDM_dly	 6
-    20:23   ,   0b1101     ,             1            ,   (def_mba_tmr0q_RW_dlys13 == 1); # RWDM_dly	 6
-    20:23   ,   0b1110     ,             1            ,   (def_mba_tmr0q_RW_dlys14 == 1); # RWDM_dly	 6
-    20:23   ,   0b1111     ,             1            ,   (def_mba_tmr0q_RW_dlys15 == 1); # RWDM_dly	 6
-    24:29   ,   0b010011   ,             1            ,   (def_mba_tmr0q_WRSM_dlys19 == 1); # WRSMSR_dly   7
-    24:29   ,   0b010100   ,             1            ,   (def_mba_tmr0q_WRSM_dlys20 == 1); # WRSMSR_dly   7
-    24:29   ,   0b010101   ,             1            ,   (def_mba_tmr0q_WRSM_dlys21 == 1); # WRSMSR_dly   7
-    24:29   ,   0b010111   ,             1            ,   (def_mba_tmr0q_WRSM_dlys23 == 1); # WRSMSR_dly   7
-    24:29   ,   0b011000   ,             1            ,   (def_mba_tmr0q_WRSM_dlys24 == 1); # WRSMSR_dly   7
-    24:29   ,   0b011001   ,             1            ,   (def_mba_tmr0q_WRSM_dlys25 == 1); # WRSMSR_dly   7
-    24:29   ,   0b011010   ,             1            ,   (def_mba_tmr0q_WRSM_dlys26 == 1); # WRSMSR_dly   7
-    24:29   ,   0b011011   ,             1            ,   (def_mba_tmr0q_WRSM_dlys27 == 1); # WRSMSR_dly   7
-    24:29   ,   0b011100   ,             1            ,   (def_mba_tmr0q_WRSM_dlys28 == 1); # WRSMSR_dly   7
-    24:29   ,   0b011101   ,             1            ,   (def_mba_tmr0q_WRSM_dlys29 == 1); # WRSMSR_dly   7
-    24:29   ,   0b011110   ,             1            ,   (def_mba_tmr0q_WRSM_dlys30 == 1); # WRSMSR_dly   7
-    24:29   ,   0b011111   ,             1            ,   (def_mba_tmr0q_WRSM_dlys31 == 1); # WRSMSR_dly   7
-    24:29   ,   0b100000   ,             1            ,   (def_mba_tmr0q_WRSM_dlys32 == 1); # WRSMSR_dly   7
-    24:29   ,   0b100001   ,             1            ,   (def_mba_tmr0q_WRSM_dlys33 == 1); # WRSMSR_dly   7
-    30:35   ,   0b010111   ,             1            ,   (def_mba_tmr0q_WRSM_dlys23 == 1); # WRSMDR_dly   8
-    30:35   ,   0b011000   ,             1            ,   (def_mba_tmr0q_WRSM_dlys24 == 1); # WRSMDR_dly   8
-    30:35   ,   0b011001   ,             1            ,   (def_mba_tmr0q_WRSM_dlys25 == 1); # WRSMDR_dly   8
-    30:35   ,   0b011010   ,             1            ,   (def_mba_tmr0q_WRSM_dlys26 == 1); # WRSMDR_dly   8
-    30:35   ,   0b011011   ,             1            ,   (def_mba_tmr0q_WRSM_dlys27 == 1); # WRSMDR_dly   8
-    30:35   ,   0b011100   ,             1            ,   (def_mba_tmr0q_WRSM_dlys28 == 1); # WRSMDR_dly   8
-    30:35   ,   0b011101   ,             1            ,   (def_mba_tmr0q_WRSM_dlys29 == 1); # WRSMDR_dly   8
-    30:35   ,   0b011110   ,             1            ,   (def_mba_tmr0q_WRSM_dlys30 == 1); # WRSMDR_dly   8
-    30:35   ,   0b011111   ,             1            ,   (def_mba_tmr0q_WRSM_dlys31 == 1); # WRSMDR_dly   8
-    30:35   ,   0b100000   ,             1            ,   (def_mba_tmr0q_WRSM_dlys32 == 1); # WRSMDR_dly   8
-    30:35   ,   0b100001   ,             1            ,   (def_mba_tmr0q_WRSM_dlys33 == 1); # WRSMDR_dly   8
-    36:39   ,   0b0100     ,             1            ,   (def_mba_tmr0q_WRDM_dlys4 == 1); # WRDM_dly     9
-    36:39   ,   0b0101     ,             1            ,   (def_mba_tmr0q_WRDM_dlys5 == 1); # WRDM_dly     9
-    36:39   ,   0b0110     ,             1            ,   (def_mba_tmr0q_WRDM_dlys6 == 1); # WRDM_dly     9
-    36:39   ,   0b0111     ,             1            ,   (def_mba_tmr0q_WRDM_dlys7 == 1); # WRDM_dly     9
-    36:39   ,   0b1000     ,             1            ,   (def_mba_tmr0q_WRDM_dlys8 == 1); # WRDM_dly     9
-    40:43   ,   0b0100     ,             1            ,   any; # WWSMSR_dly is 4 for all cfgs     10                                      D
-    44:47   ,   0b0100     ,             1            ,   any; # WWSMDR_dly is 4 for all cfgs     11                                      D
-    48:51   ,   0b0111     ,             1            ,   (CENTAUR.ATTR_MSS_FREQ == 1066) || (CENTAUR.ATTR_MSS_FREQ == 1333) || (CENTAUR.ATTR_MSS_FREQ == 1600);  # WWDM_dly     12     D
-    48:51   ,   0b1000     ,             1            ,   (CENTAUR.ATTR_MSS_FREQ == 1866) || (CENTAUR.ATTR_MSS_FREQ == 2133);  # WWDM_dly     12                              D
-    48:51   ,   0b1001     ,             1            ,   (CENTAUR.ATTR_MSS_FREQ == 2400);                           # WWDM_dly     12                              D
-    52:55   ,   0b0100     ,             1            ,   any; # RROP_dly is 4 for all cfgs       13                                                        D
-    56:59   ,   0b0100     ,             1            ,   any; # WWOP_dly is 4 for all cfgs       14                                                        D
-    60:63   ,   0b0100     ,             1            ,   (def_MBA_TMR0Q_Trrd_dly4 == 1); # TMR0Q_Trrd     15
-    60:63   ,   0b0101     ,             1            ,   (def_MBA_TMR0Q_Trrd_dly5 == 1); # TMR0Q_Trrd     15
-    60:63   ,   0b0110     ,             1            ,   (def_MBA_TMR0Q_Trrd_dly6 == 1); # TMR0Q_Trrd     15
-    60:63   ,   0b0111     ,             1            ,   (def_MBA_TMR0Q_Trrd_dly7 == 1); # TMR0Q_Trrd     15
+    0:3     ,   0b0100   + def_margin  ,             1            ,   any; # RRSMSR_dly is 4 for all cfgs     1                                                      D
+    4:7     ,   0b0100   + def_margin  ,             1            ,   any; # RRSMDR_dly is 4 for all cfgs     2                                                      D
+    8:11    ,   0b0111   + def_margin  ,             1            ,   (CENTAUR.ATTR_MSS_FREQ == 1066) || (CENTAUR.ATTR_MSS_FREQ == 1333) || (CENTAUR.ATTR_MSS_FREQ == 1600); # RRDM_dly     3    D
+    8:11    ,   0b1000   + def_margin  ,             1            ,   (CENTAUR.ATTR_MSS_FREQ == 1866) || (CENTAUR.ATTR_MSS_FREQ == 2133); # RRDM_dly     3                             D
+    8:11    ,   0b1001   + def_margin  ,             1            ,   (CENTAUR.ATTR_MSS_FREQ == 2400); # RRDM_dly     3                                                      D
+    12:15   ,   0b0001   + def_margin  ,             1            ,   (def_mba_tmr0q_RW_dlys7  == 1); # RWSMSR_dly   4
+    12:15   ,   0b1000   + def_margin  ,             1            ,   (def_mba_tmr0q_RW_dlys8  == 1); # RWSMSR_dly   4
+    12:15   ,   0b1001   + def_margin  ,             1            ,   (def_mba_tmr0q_RW_dlys9  == 1); # RWSMSR_dly   4
+    12:15   ,   0b1010   + def_margin  ,             1            ,   (def_mba_tmr0q_RW_dlys10 == 1); # RWSMSR_dly   4
+    12:15   ,   0b1011   + def_margin  ,             1            ,   (def_mba_tmr0q_RW_dlys11 == 1); # RWSMSR_dly   4
+    12:15   ,   0b1100   + def_margin  ,             1            ,   (def_mba_tmr0q_RW_dlys12 == 1); # RWSMSR_dly   4
+    12:15   ,   0b1101   + def_margin  ,             1            ,   (def_mba_tmr0q_RW_dlys13 == 1); # RWSMSR_dly   4
+    12:15   ,   0b1110   + def_margin  ,             1            ,   (def_mba_tmr0q_RW_dlys14 == 1); # RWSMSR_dly   4
+    12:15   ,   0b1111   + def_margin  ,             1            ,   (def_mba_tmr0q_RW_dlys15 == 1); # RWSMSR_dly   4
+    16:19   ,   0b0001   + def_margin  ,             1            ,   (def_mba_tmr0q_RW_dlys7  == 1); # RWSMDR_dly   5
+    16:19   ,   0b1000   + def_margin  ,             1            ,   (def_mba_tmr0q_RW_dlys8  == 1); # RWSMDR_dly   5
+    16:19   ,   0b1001   + def_margin  ,             1            ,   (def_mba_tmr0q_RW_dlys9  == 1); # RWSMDR_dly   5
+    16:19   ,   0b1010   + def_margin  ,             1            ,   (def_mba_tmr0q_RW_dlys10 == 1); # RWSMDR_dly   5
+    16:19   ,   0b1011   + def_margin  ,             1            ,   (def_mba_tmr0q_RW_dlys11 == 1); # RWSMDR_dly   5
+    16:19   ,   0b1100   + def_margin  ,             1            ,   (def_mba_tmr0q_RW_dlys12 == 1); # RWSMDR_dly   5
+    16:19   ,   0b1101   + def_margin  ,             1            ,   (def_mba_tmr0q_RW_dlys13 == 1); # RWSMDR_dly   5
+    16:19   ,   0b1110   + def_margin  ,             1            ,   (def_mba_tmr0q_RW_dlys14 == 1); # RWSMDR_dly   5
+    16:19   ,   0b1111   + def_margin  ,             1            ,   (def_mba_tmr0q_RW_dlys15 == 1); # RWSMDR_dly   5
+    20:23   ,   0b0001   + def_margin  ,             1            ,   (def_mba_tmr0q_RW_dlys7  == 1); # RWDM_dly	 6
+    20:23   ,   0b1000   + def_margin  ,             1            ,   (def_mba_tmr0q_RW_dlys8  == 1); # RWDM_dly	 6
+    20:23   ,   0b1001   + def_margin  ,             1            ,   (def_mba_tmr0q_RW_dlys9  == 1); # RWDM_dly	 6
+    20:23   ,   0b1010   + def_margin  ,             1            ,   (def_mba_tmr0q_RW_dlys10 == 1); # RWDM_dly	 6
+    20:23   ,   0b1011   + def_margin  ,             1            ,   (def_mba_tmr0q_RW_dlys11 == 1); # RWDM_dly	 6
+    20:23   ,   0b1100   + def_margin  ,             1            ,   (def_mba_tmr0q_RW_dlys12 == 1); # RWDM_dly	 6
+    20:23   ,   0b1101   + def_margin  ,             1            ,   (def_mba_tmr0q_RW_dlys13 == 1); # RWDM_dly	 6
+    20:23   ,   0b1110   + def_margin  ,             1            ,   (def_mba_tmr0q_RW_dlys14 == 1); # RWDM_dly	 6
+    20:23   ,   0b1111   + def_margin  ,             1            ,   (def_mba_tmr0q_RW_dlys15 == 1); # RWDM_dly	 6
+    24:29   ,   0b010011 + def_margin  ,             1            ,   (def_mba_tmr0q_WRSM_dlys19 == 1); # WRSMSR_dly   7
+    24:29   ,   0b010100 + def_margin  ,             1            ,   (def_mba_tmr0q_WRSM_dlys20 == 1); # WRSMSR_dly   7
+    24:29   ,   0b010101 + def_margin  ,             1            ,   (def_mba_tmr0q_WRSM_dlys21 == 1); # WRSMSR_dly   7
+    24:29   ,   0b010111 + def_margin  ,             1            ,   (def_mba_tmr0q_WRSM_dlys23 == 1); # WRSMSR_dly   7
+    24:29   ,   0b011000 + def_margin  ,             1            ,   (def_mba_tmr0q_WRSM_dlys24 == 1); # WRSMSR_dly   7
+    24:29   ,   0b011001 + def_margin  ,             1            ,   (def_mba_tmr0q_WRSM_dlys25 == 1); # WRSMSR_dly   7
+    24:29   ,   0b011010 + def_margin  ,             1            ,   (def_mba_tmr0q_WRSM_dlys26 == 1); # WRSMSR_dly   7
+    24:29   ,   0b011011 + def_margin  ,             1            ,   (def_mba_tmr0q_WRSM_dlys27 == 1); # WRSMSR_dly   7
+    24:29   ,   0b011100 + def_margin  ,             1            ,   (def_mba_tmr0q_WRSM_dlys28 == 1); # WRSMSR_dly   7
+    24:29   ,   0b011101 + def_margin  ,             1            ,   (def_mba_tmr0q_WRSM_dlys29 == 1); # WRSMSR_dly   7
+    24:29   ,   0b011110 + def_margin  ,             1            ,   (def_mba_tmr0q_WRSM_dlys30 == 1); # WRSMSR_dly   7
+    24:29   ,   0b011111 + def_margin  ,             1            ,   (def_mba_tmr0q_WRSM_dlys31 == 1); # WRSMSR_dly   7
+    24:29   ,   0b100000 + def_margin  ,             1            ,   (def_mba_tmr0q_WRSM_dlys32 == 1); # WRSMSR_dly   7
+    24:29   ,   0b100001 + def_margin  ,             1            ,   (def_mba_tmr0q_WRSM_dlys33 == 1); # WRSMSR_dly   7
+    30:35   ,   0b010111 + def_margin  ,             1            ,   (def_mba_tmr0q_WRSM_dlys23 == 1); # WRSMDR_dly   8
+    30:35   ,   0b011000 + def_margin  ,             1            ,   (def_mba_tmr0q_WRSM_dlys24 == 1); # WRSMDR_dly   8
+    30:35   ,   0b011001 + def_margin  ,             1            ,   (def_mba_tmr0q_WRSM_dlys25 == 1); # WRSMDR_dly   8
+    30:35   ,   0b011010 + def_margin  ,             1            ,   (def_mba_tmr0q_WRSM_dlys26 == 1); # WRSMDR_dly   8
+    30:35   ,   0b011011 + def_margin  ,             1            ,   (def_mba_tmr0q_WRSM_dlys27 == 1); # WRSMDR_dly   8
+    30:35   ,   0b011100 + def_margin  ,             1            ,   (def_mba_tmr0q_WRSM_dlys28 == 1); # WRSMDR_dly   8
+    30:35   ,   0b011101 + def_margin  ,             1            ,   (def_mba_tmr0q_WRSM_dlys29 == 1); # WRSMDR_dly   8
+    30:35   ,   0b011110 + def_margin  ,             1            ,   (def_mba_tmr0q_WRSM_dlys30 == 1); # WRSMDR_dly   8
+    30:35   ,   0b011111 + def_margin  ,             1            ,   (def_mba_tmr0q_WRSM_dlys31 == 1); # WRSMDR_dly   8
+    30:35   ,   0b100000 + def_margin  ,             1            ,   (def_mba_tmr0q_WRSM_dlys32 == 1); # WRSMDR_dly   8
+    30:35   ,   0b100001 + def_margin  ,             1            ,   (def_mba_tmr0q_WRSM_dlys33 == 1); # WRSMDR_dly   8
+    36:39   ,   0b0100   + def_margin  ,             1            ,   (def_mba_tmr0q_WRDM_dlys4 == 1); # WRDM_dly     9
+    36:39   ,   0b0101   + def_margin  ,             1            ,   (def_mba_tmr0q_WRDM_dlys5 == 1); # WRDM_dly     9
+    36:39   ,   0b0110   + def_margin  ,             1            ,   (def_mba_tmr0q_WRDM_dlys6 == 1); # WRDM_dly     9
+    36:39   ,   0b0111   + def_margin  ,             1            ,   (def_mba_tmr0q_WRDM_dlys7 == 1); # WRDM_dly     9
+    36:39   ,   0b1000   + def_margin  ,             1            ,   (def_mba_tmr0q_WRDM_dlys8 == 1); # WRDM_dly     9
+    40:43   ,   0b0100   + def_margin  ,             1            ,   any; # WWSMSR_dly is 4 for all cfgs     10                                      D
+    44:47   ,   0b0100   + def_margin  ,             1            ,   any; # WWSMDR_dly is 4 for all cfgs     11                                      D
+    48:51   ,   0b0111   + def_margin  ,             1            ,   (CENTAUR.ATTR_MSS_FREQ == 1066) || (CENTAUR.ATTR_MSS_FREQ == 1333) || (CENTAUR.ATTR_MSS_FREQ == 1600);  # WWDM_dly     12     D
+    48:51   ,   0b1000   + def_margin  ,             1            ,   (CENTAUR.ATTR_MSS_FREQ == 1866) || (CENTAUR.ATTR_MSS_FREQ == 2133);  # WWDM_dly     12                              D
+    48:51   ,   0b1001   + def_margin  ,             1            ,   (CENTAUR.ATTR_MSS_FREQ == 2400);                           # WWDM_dly     12                              D
+    52:55   ,   0b0100   + def_margin  ,             1            ,   any; # RROP_dly is 4 for all cfgs       13                                                        D
+    56:59   ,   0b0100   + def_margin  ,             1            ,   any; # WWOP_dly is 4 for all cfgs       14                                                        D
+    60:63   ,   0b0100   + def_margin  ,             1            ,   (def_MBA_TMR0Q_Trrd_dly4 == 1); # TMR0Q_Trrd     15
+    60:63   ,   0b0101   + def_margin  ,             1            ,   (def_MBA_TMR0Q_Trrd_dly5 == 1); # TMR0Q_Trrd     15
+    60:63   ,   0b0110   + def_margin  ,             1            ,   (def_MBA_TMR0Q_Trrd_dly6 == 1); # TMR0Q_Trrd     15
+    60:63   ,   0b0111   + def_margin  ,             1            ,   (def_MBA_TMR0Q_Trrd_dly7 == 1); # TMR0Q_Trrd     15
 }
 
 # MBA_TMR1Q  mba01 timer settings
@@ -2021,6 +2028,17 @@ scom 0x0301040C     {
 #    24:28   ,   0b00000     ,          1             ,   (def_mba_tmr1q_WRSBG_dlys37 == 1); # WRSBG_dly  ## 2133 and 2400 DRM not supported  20
 }
 
+# 1333Mbps RDIMM WL = Setting + 7 = CWL + AL[CL-1] + 1= 16
+#putscom cen.mba 301040a 30 6 001001 -ib -pall -call
+# 1600Mbps RDIMM WL = Setting + 7 = CWL + AL[CL-1] + 1= 19
+#putscom cen.mba 301040a 30 6 001100 -ib -pall -call
+# 1333Mbps CDIMM WL = Setting + 7 = CWL + AL[CL-1] = 15
+#putscom cen.mba 301040a 30 6 001000 -ib -pall -call
+# 1600Mbps CDIMM WL = Setting + 7 = CWL + AL[CL-1] = 18
+#putscom cen.mba 301040a 30 6 001011 -ib -pall -call
+
+define def_WL = (ATTR_EFF_DRAM_CWL + ATTR_EFF_DRAM_CL - 1 - 7);
+
 # MBA_DSM0Q  mba01 data state machine settings
 #< B0.C0.M00A.CENTAUR.MBU.MBA01.MBA_SRQ.MBA_DSM0Q(0:63) = 0x0870466094038800
 #> B0.C0.M00A.CENTAUR.MBU.MBA01.MBA_SRQ.MBA_DSM0Q(0:63) = 0x08704660A4838800
@@ -2040,23 +2058,25 @@ scom 0x0301040A     {
     12:17   ,   0b000001    ,           1            ,    any; # CFG_WODT_start_dly is 1 for all cfgs   23                     D
     18:23   ,   0b000110    ,           1            ,    any; # CFG_WODT_end_dly is 6 for all cfgs     24                     D
     24:29   ,   0b011000    ,           1            ,    any; # wrdone_dly is 24 for all cfgs 25                              D
-    30:35   ,   0b000011    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly3  == 1); # wrdata_dly		26
-    30:35   ,   0b000100    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly4  == 1); # wrdata_dly		26
-    30:35   ,   0b000101    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly5  == 1); # wrdata_dly		26
-    30:35   ,   0b000110    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly6  == 1); # wrdata_dly		26
-    30:35   ,   0b000111    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly7  == 1); # wrdata_dly		26
-    30:35   ,   0b001000    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly8  == 1); # wrdata_dly		26
-    30:35   ,   0b001001    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly9  == 1); # wrdata_dly		26
-    30:35   ,   0b001010    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly10 == 1); # wrdata_dly		26
-    30:35   ,   0b001011    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly11 == 1); # wrdata_dly		26
-    30:35   ,   0b001100    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly12 == 1); # wrdata_dly		26
-    30:35   ,   0b001101    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly13 == 1); # wrdata_dly		26
-    30:35   ,   0b001110    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly14 == 1); # wrdata_dly		26
-    30:35   ,   0b001111    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly15 == 1); # wrdata_dly		26
-    30:35   ,   0b010000    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly16 == 1); # wrdata_dly		26
-    30:35   ,   0b010001    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly17 == 1); # wrdata_dly		26
-    30:35   ,   0b010010    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly18 == 1); # wrdata_dly		26
-    30:35   ,   0b010011    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly19 == 1); # wrdata_dly		26
+    30:35   ,   def_WL + 1  ,           1            ,    (ATTR_EFF_DIMM_TYPE == 1); # wrdata_dly = CWL + AL[CL-1] + 1	
+    30:35   ,   def_WL      ,           1            ,    (ATTR_EFF_DIMM_TYPE == 0) || (ATTR_EFF_DIMM_TYPE == 2); # wrdata_dly = CWL + AL[CL-1] 		
+#    30:35   ,   0b000011    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly3  == 1); # wrdata_dly		26
+#    30:35   ,   0b000100    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly4  == 1); # wrdata_dly		26
+#    30:35   ,   0b000101    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly5  == 1); # wrdata_dly		26
+#    30:35   ,   0b000110    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly6  == 1); # wrdata_dly		26
+#    30:35   ,   0b000111    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly7  == 1); # wrdata_dly		26
+#    30:35   ,   0b001000    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly8  == 1); # wrdata_dly		26
+#    30:35   ,   0b001001    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly9  == 1); # wrdata_dly		26
+#    30:35   ,   0b001010    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly10 == 1); # wrdata_dly		26
+#    30:35   ,   0b001011    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly11 == 1); # wrdata_dly		26
+#    30:35   ,   0b001100    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly12 == 1); # wrdata_dly		26
+#    30:35   ,   0b001101    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly13 == 1); # wrdata_dly		26
+#    30:35   ,   0b001110    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly14 == 1); # wrdata_dly		26
+#    30:35   ,   0b001111    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly15 == 1); # wrdata_dly		26
+#    30:35   ,   0b010000    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly16 == 1); # wrdata_dly		26
+#    30:35   ,   0b010001    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly17 == 1); # wrdata_dly		26
+#    30:35   ,   0b010010    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly18 == 1); # wrdata_dly		26
+#    30:35   ,   0b010011    ,           1            ,    (def_mba_dsm0q_cfg_wrdata_dly19 == 1); # wrdata_dly		26
 #    36:41   ,   0b001100    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly12 == 1); # rdtag_dly		27
 #    36:41   ,   0b001101    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly13 == 1); # rdtag_dly		27
 #    36:41   ,   0b001110    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly14 == 1); # rdtag_dly		27
@@ -2075,7 +2095,8 @@ scom 0x0301040A     {
 #    36:41   ,   0b011011    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly27 == 1); # rdtag_dly		27
 #    36:41   ,   0b011100    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly28 == 1); # rdtag_dly		27
 #    36:41   ,   0b011101    ,           1            ,    (def_mba_dsm0q_cfg_rdtag_dly29 == 1); # rdtag_dly		27
-    36:41   ,   0b100100    ,           1            ,    any                                 ; # rdtag_dly		36  temporary fix for testfloor
+#    36:41   ,   0b100100    ,           1            ,    any                                 ; # rdtag_dly		36  temporary fix for testfloor
+    36:41   ,   0b011000    ,           1            ,    any                                 ; # rdtag_dly		24  temporary fix for testfloor
     43:48   ,   0b000101    ,           1            ,    (def_mba_dsm0q_CFG_RODT_BC4_END_DLY5 == 1); # CFG_RODT_BC4_END_DLY 28
     43:48   ,   0b000110    ,           1            ,    (def_mba_dsm0q_CFG_RODT_BC4_END_DLY6 == 1); # CFG_RODT_BC4_END_DLY 28
     43:48   ,   0b000111    ,           1            ,    (def_mba_dsm0q_CFG_RODT_BC4_END_DLY7 == 1); # CFG_RODT_BC4_END_DLY 28
diff --git a/src/usr/hwpf/hwp/initfiles/mbs_def.initfile b/src/usr/hwpf/hwp/initfiles/mbs_def.initfile
index 86d6b08a6..bf6bd970d 100644
--- a/src/usr/hwpf/hwp/initfiles/mbs_def.initfile
+++ b/src/usr/hwpf/hwp/initfiles/mbs_def.initfile
@@ -1,8 +1,9 @@
-#-- $Id: mbs_def.initfile,v 1.24 2012/12/18 23:26:51 yctschan Exp $
+#-- $Id: mbs_def.initfile,v 1.25 2013/01/17 15:41:30 yctschan Exp $
 #-- CHANGE HISTORY:
 #--------------------------------------------------------------------------------
 #-- Version:|Author: | Date:  | Comment:
 #-- --------|--------|--------|--------------------------------------------------
+#--   1.25  |tschang |01/17/13| cache enabled when (ATTR_MSS_CACHE_ENABLE != 0) - enabled cache when 1/2 cache mode is choosen
 #--   1.21  |tschang |10/23/12| disable interleaving when one or both MBA are disabled (partial good tests)
 #--   1.20  |tschang |09/27/12| added partial good support for the SCOM write using ATTR_FUNCTIONAL
 #--   1.19  |menlowuu|08/21/12| fixed 2 address typo's
@@ -438,7 +439,7 @@ scom 0x02011411   {
 scom 0x0201140F   {
     bits,       scom_data   , expr;
     0   ,       0b0     , (ATTR_MSS_CACHE_ENABLE == 0);   # MBCCFGQ_cache_enable
-    0   ,       0b1     , (ATTR_MSS_CACHE_ENABLE == 1);   # MBCCFGQ_cache_enable
+    0   ,       0b1     , (ATTR_MSS_CACHE_ENABLE != 0);   # MBCCFGQ_cache_enable
 #    1   ,       0b0     , any                       ;        # -MW match dials
     1   ,       0b0     , any                       ;         # MBCCFGQ_cfg_dyn_whap_en
     2   ,       0b0     , (SYS.ATTR_MSS_CLEANER_ENABLE == 0); # MBCCFGQ_cleaner_enable
diff --git a/src/usr/hwpf/hwp/initfiles/p8.dmi.custom.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.dmi.custom.scom.initfile
new file mode 100644
index 000000000..c574d6a69
--- /dev/null
+++ b/src/usr/hwpf/hwp/initfiles/p8.dmi.custom.scom.initfile
@@ -0,0 +1,551 @@
+#-- $Id: p8.dmi.custom.scom.initfile,v 1.2 2013/01/24 23:46:35 thomsen Exp $
+#-- CHANGE HISTORY:
+#--------------------------------------------------------------------------------
+#-- Version:|Author: | Date:  | Comment:
+#-- --------|--------|--------|--------------------------------------------------
+#--     1.2 |thomsen |01/24/13|Fixed tx_msbswap for groups 1,2,3
+#--     1.1 |thomsen |01/23/13|Created initial version
+#-- --------|--------|--------|--------------------------------------------------
+#--------------------------------------------------------------------------------
+# End of revision history
+#--------------------------------------------------------------------------------
+
+#--Master list of variables that can be used in this file is at:
+#--<Attribute Definition Location>
+
+#-- TGT1.ATTR_CHIP_UNIT_POS is the MCS unit number (0-7 on Venice, 4-7 on Murano) and corresponds to the scom address translation done in
+#--  the p8.chipunit.scominfo file. It is used to be able to select a specific clock group number.
+#--  Chip     UNIT_POS  DMI_UNIT  CLOCKGRP
+#--  ----     --------  --------  --------
+#--  Venice:  0-3       DMI0      3-0
+#--           4-7       DMI1      3-0
+#--  Murano:  4-7       DMI1      3-0
+
+
+SyntaxVersion = 1
+
+#-- -----------------------------------------------------------------------------
+#--******************************************************************************
+#-- -----------------------------------------------------------------------------
+#--
+#-- Includes
+#-- Note:  Must include the path to the .define file.
+#-- -----------------------------------------------------------------------------
+#--******************************************************************************
+#-- -----------------------------------------------------------------------------
+include edi.io.define
+
+#-- -----------------------------------------------------------------------------
+#--******************************************************************************
+#-- -----------------------------------------------------------------------------
+#--
+#-- Defines
+#--
+#-- -----------------------------------------------------------------------------
+#--******************************************************************************
+#-- -----------------------------------------------------------------------------
+
+# ./iotk put rx_fence=1
+# 0x
+scom 0x800.0b(rx_fence_pg)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(dmi1_gcr_addr) {
+bits,                     scom_data;
+rx_fence,                 0b1;
+}
+
+# ./iotk put rx_c4_sel=00
+# ./iotk put rx_prot_speed_slct=1
+# 0x8009C00002011E3F 
+scom 0x800.0b(rx_misc_analog_pg)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(dmi1_gcr_addr) {
+bits,                     scom_data;
+rx_c4_sel,                0b00;
+rx_prot_speed_slct,       0b1;
+}
+# ./iotk put rx_servo_timeout_sel_D=1001
+# 0x800B600002011E3F 
+scom 0x800.0b(rx_servo_to1_pp)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(dmi1_gcr_addr) {
+bits,                     scom_data;
+rx_servo_timeout_sel_d,   0b1001;
+}
+# ./iotk put rx_servo_timeout_sel_H=1110
+# 0x800B680002011E3F 
+scom 0x800.0b(rx_servo_to2_pp)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(dmi1_gcr_addr) {
+bits,                     scom_data;
+rx_servo_timeout_sel_h,   0b1110;
+}
+# ./iotk put rx_servo_timeout_sel_I=1011
+# ./iotk put rx_servo_timeout_sel_J=1100
+# 0x800B700002011E3F 
+scom 0x800.0b(rx_servo_to3_pp)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(dmi1_gcr_addr) {
+bits,                     scom_data;
+rx_servo_timeout_sel_i,   0b1011;
+rx_servo_timeout_sel_j,   0b1100;
+rx_servo_timeout_sel_k,   0b1101;
+}
+# ./iotk put rx_wt_timeout_sel=111
+# ./iotk put rx_ds_bl_timeout_sel=101
+# ./iotk put rx_ds_timeout_sel=110
+#./iotk put rx_sls_timeout_sel=111
+# 0x8008980002011E3F 
+scom 0x800.0b(rx_timeout_sel_pg)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(dmi1_gcr_addr) {
+bits,                     scom_data;
+rx_wt_timeout_sel,        0b111;
+rx_ds_bl_timeout_sel,     0b101;
+rx_ds_timeout_sel,        0b110;
+rx_sls_timeout_sel,       0b001;
+}
+
+# ./iotk put rx_bit_lock_timeout_sel=110
+# 0x800B080002011E3F 
+scom 0x800.0b(rx_mode1_pp)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(dmi1_gcr_addr) {
+bits,                     scom_data;
+rx_bit_lock_timeout_sel,  0b110;
+}
+# ./iotk put rx_eo_offset_timeout_sel=111
+# ./iotk put rx_eo_amp_timeout_sel=111
+# ./iotk put rx_eo_ctle_timeout_sel=111
+# ./iotk put rx_eo_h1ap_timeout_sel=111
+# ./iotk put rx_eo_ddc_timeout_sel=111
+# 0x8009100002011E3F 
+scom 0x800.0b(rx_timeout_sel1_pg)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(dmi1_gcr_addr) {
+bits,                     scom_data;
+rx_eo_offset_timeout_sel, 0b111;
+rx_eo_amp_timeout_sel,    0b111;
+rx_eo_ctle_timeout_sel,   0b111;
+rx_eo_h1ap_timeout_sel,   0b111;
+rx_eo_ddc_timeout_sel,    0b111;
+}
+
+#./iotk put tx_zcal_sm_min_val=0010101
+#./iotk put tx_zcal_sm_max_val=1000110
+# 0x800F2C0002011E3F 
+scom 0x800.0b(tx_impcal_swo2_pb)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_na).0x(dmi1_gcr_addr) {
+bits,                     scom_data;
+tx_zcal_sm_min_val,       0b0010101;
+tx_zcal_sm_max_val,       0b1000110;
+}
+#./iotk put tx_zcal_p_4x=00100
+# 0x800F1C0002011E3F 
+scom 0x800.0b(tx_impcal_p_4x_pb)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_na).0x(dmi1_gcr_addr) {
+bits,                     scom_data;
+tx_zcal_p_4x,             0b00100;
+}
+
+# 800A380002011E3F
+scom 0x800.0b(rx_eo_step_cntl_pg)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(dmi1_gcr_addr) {
+bits,                               scom_data;
+rx_eo_enable_latch_offset_cal,      0b1;
+rx_eo_enable_ctle_cal,              0b1;
+rx_eo_enable_vga_cal,               0b1;
+rx_eo_enable_dfe_h1_cal,            0b1;
+rx_eo_enable_h1ap_tweak,            0b1;
+rx_eo_enable_ddc,                   0b1;
+rx_eo_enable_final_l2u_adj,         0b1;
+rx_eo_enable_ber_test,              0b1;
+rx_eo_enable_result_check,          0b1;
+}
+
+scom 0x800.0b(rx_eo_convergence_pg)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(dmi1_gcr_addr) {
+bits,                               scom_data;
+rx_eo_converged_end_count,          0b111;
+}
+
+# 0x800AB80002011E3F
+scom 0x800.0b(rx_rc_step_cntl_pg)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(dmi1_gcr_addr) {
+bits,                               scom_data;
+rx_rc_enable_latch_offset_cal,      0b1;
+rx_rc_enable_ctle_cal,              0b1;
+rx_rc_enable_vga_cal,               0b1;
+rx_rc_enable_h1ap_tweak,            0b1;
+rx_rc_enable_ddc,                   0b1;
+rx_rc_enable_ber_test,              0b1;
+rx_rc_enable_result_check,          0b1;
+#rx_rc_enable_dfe_h1_cal,           0b0; # Leave DFE off during recal for now
+}
+
+
+#--******************************************************************************
+#-------------------------------------------------------------------------------------
+#   _______  __    __    ___    _   ________   _____   ___    ____________  ______
+#  /_  __/ |/ /   / /   /   |  / | / / ____/  /  _/ | / / |  / / ____/ __ \/_  __/
+#   / /  |   /   / /   / /| | /  |/ / __/     / //  |/ /| | / / __/ / /_/ / / /   
+#  / /  /   |   / /___/ ___ |/ /|  / /___   _/ // /|  / | |/ / /___/ _, _/ / /    
+# /_/  /_/|_|  /_____/_/  |_/_/ |_/_____/  /___/_/ |_/  |___/_____/_/ |_| /_/     
+#                                        figlet -fslant
+#-------------------------------------------------------------------------------------
+#--******************************************************************************
+
+# These need to come as attributes from the MRW rather than be hardcoded here
+define  def_EI_TX_LANE_INVERT_VEC_MCS4 = 0x00F80000;  # MSBSWAP=0 ON TULETA  # TX3
+define  def_EI_TX_LANE_INVERT_VEC_MCS5 = 0xF7FF8000;  # MSBSWAP=1 ON TULETA  # TX2
+#define  def_EI_TX_LANE_INVERT_VEC_MCS5 = 0x7FF40000;  # MSBSWAP=1 ON TULETA
+define  def_EI_TX_LANE_INVERT_VEC_MCS6 = 0xFEFF8000;  # MSBSWAP=1 ON TULETA  # TX1
+define  def_EI_TX_LANE_INVERT_VEC_MCS7 = 0x96CF8000;  # MSBSWAP=1 ON TULETA  # TX0
+
+# These only do a scom if the invert attribute is set (saves scom's). The default scanflush value of tx_lane_invert for each lane is '0'.
+# Lane 0
+# 0x8004040002011E3F
+scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_0).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS4 & 0x80000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==0; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp2)(lane_0).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS5 & 0x80000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==1; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp1)(lane_0).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS6 & 0x80000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==2; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_0).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS7 & 0x80000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==3; 
+#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x80000000) > 0; 
+}
+# Lane 1
+# 0x8004040102011E3F
+scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_1).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS4 & 0x40000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==0; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp2)(lane_1).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS5 & 0x40000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==1; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp1)(lane_1).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS6 & 0x40000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==2; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_1).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS7 & 0x40000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==3; 
+#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x40000000) > 0; 
+}
+# Lane 2
+# 0x8004040202011E3F 
+scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_2).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS4 & 0x20000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==0; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp2)(lane_2).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS5 & 0x20000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==1; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp1)(lane_2).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS6 & 0x20000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==2; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_2).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS7 & 0x20000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==3; 
+#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x20000000) > 0; 
+}
+# Lane 3
+# 0x8004040302011E3F 
+scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_3).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS4 & 0x10000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==0; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp2)(lane_3).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS5 & 0x10000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==1; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp1)(lane_3).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS6 & 0x10000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==2; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_3).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS7 & 0x10000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==3; 
+#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x10000000) > 0; 
+}
+# Lane 4
+# 0x8004040402011E3F 
+scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_4).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS4 & 0x08000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==0; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp2)(lane_4).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS5 & 0x08000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==1; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp1)(lane_4).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS6 & 0x08000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==2; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_4).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS7 & 0x08000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==3; 
+#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x08000000) > 0; 
+}
+# Lane 5
+# 0x8004040502011E3F 
+scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_5).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS4 & 0x04000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==0; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp2)(lane_5).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS5 & 0x04000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==1; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp1)(lane_5).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS6 & 0x04000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==2; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_5).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS7 & 0x04000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==3; 
+#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x04000000) > 0; 
+}
+# Lane 6
+# 0x8004040602011E3F 
+scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_6).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS4 & 0x02000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==0; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp2)(lane_6).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS5 & 0x02000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==1; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp1)(lane_6).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS6 & 0x02000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==2; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_6).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS7 & 0x02000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==3; 
+#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x02000000) > 0; 
+}
+# Lane 7
+# 0x8004040702011E3F 
+scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_7).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS4 & 0x01000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==0; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp2)(lane_7).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS5 & 0x01000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==1; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp1)(lane_7).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS6 & 0x01000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==2; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_7).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS7 & 0x01000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==3; 
+#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x01000000) > 0; 
+}
+# Lane 8
+# 0x8004040802011E3F 
+scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_8).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS4 & 0x00800000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==0; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp2)(lane_8).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS5 & 0x00800000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==1; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp1)(lane_8).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS6 & 0x00800000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==2; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_8).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS7 & 0x00800000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==3; 
+#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00800000) > 0; 
+}
+# Lane 9
+# 0x8004040902011E3F {
+scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_9).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS4 & 0x00400000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==0; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp2)(lane_9).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS5 & 0x00400000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==1; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp1)(lane_9).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS6 & 0x00400000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==2; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_9).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS7 & 0x00400000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==3; 
+#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00400000) > 0; 
+}
+# Lane 10
+# 0x8004040A02011E3F 
+scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_10).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS4 & 0x00200000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==0; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp2)(lane_10).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS5 & 0x00200000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==1; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp1)(lane_10).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS6 & 0x00200000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==2; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_10).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS7 & 0x00200000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==3; 
+#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00200000) > 0; 
+}
+# Lane 11
+# 0x8004040B02011E3F 
+scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_11).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS4 & 0x00100000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==0; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp2)(lane_11).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS5 & 0x00100000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==1; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp1)(lane_11).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS6 & 0x00100000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==2; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_11).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS7 & 0x00100000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==3; 
+#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00100000) > 0; 
+}
+# Lane 12
+# 0x8004040C02011E3F 
+scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_12).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS4 & 0x00080000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==0; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp2)(lane_12).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS5 & 0x00080000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==1; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp1)(lane_12).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS6 & 0x00080000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==2; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_12).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS7 & 0x00080000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==3; 
+#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00080000) > 0; 
+}
+# Lane 13
+# 0x8004040D02011E3F 
+scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_13).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS4 & 0x00040000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==0; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp2)(lane_13).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS5 & 0x00040000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==1; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp1)(lane_13).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS6 & 0x00040000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==2; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_13).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS7 & 0x00040000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==3; 
+#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00040000) > 0; 
+}
+# Lane 14
+# 0x8004040E02011E3F 
+scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_14).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS4 & 0x00020000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==0; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp2)(lane_14).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS5 & 0x00020000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==1; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp1)(lane_14).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS6 & 0x00020000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==2; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_14).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS7 & 0x00020000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==3; 
+#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00020000) > 0; 
+}
+# Lane 15
+# 0x8004040F02011E3F 
+scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_15).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS4 & 0x00010000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==0; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp2)(lane_15).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS5 & 0x00010000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==1; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp1)(lane_15).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS6 & 0x00010000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==2; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_15).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS7 & 0x00010000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==3; 
+#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00010000) > 0; 
+}
+# Lane 16
+# 0x8004041002011E3F 
+scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_16).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS4 & 0x00008000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==0; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp2)(lane_16).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS5 & 0x00008000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==1; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp1)(lane_16).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS6 & 0x00008000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==2; 
+}
+scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_16).0x(dmi1_gcr_addr) {
+bits,            scom_data, expr;
+tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS7 & 0x00008000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==3; 
+#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00008000) > 0; 
+}
+
+#--***********************************************************************************
+#-------------------------------------------------------------------------------------
+#     __  ________ ____     _____                   
+#    /  |/  / ___// __ )   / ___/      ______ _____ 
+#   / /|_/ /\__ \/ __  |   \__ \ | /| / / __ `/ __ \
+#  / /  / /___/ / /_/ /   ___/ / |/ |/ / /_/ / /_/ /
+# /_/  /_//____/_____/   /____/|__/|__/\__,_/ .___/ 
+#                                         /_/      
+#                                        figlet -fslant
+#-------------------------------------------------------------------------------------
+#--***********************************************************************************
+
+# TX_MSBSWAP setting via manaual SCOM overrides
+# ./iotk put tx_msbswap=1 (only when p# mod 4 = 3 for centaur or mcs mod 4 = 0, ie. grp0)
+# 0x800C1C0002011E3F 
+scom 0x800.0b(tx_mode_pg)(tx_grp3)(lane_na).0x(dmi1_gcr_addr) {
+bits,                     scom_data, expr;
+tx_msbswap,               0b0,       (TGT1.ATTR_CHIP_UNIT_POS % 4 == 0); # MCS4
+#tx_msbswap,               0b1,       (TGT1.ATTR_CHIP_UNIT_POS % 4 == 1); # MCS5
+#tx_msbswap,               0b1,       (TGT1.ATTR_CHIP_UNIT_POS % 4 == 2); # MCS6
+#tx_msbswap,               0b1,       (TGT1.ATTR_CHIP_UNIT_POS % 4 == 3); # MCS7
+#tx_msbswap,               0b1,       (ATTR_EI_BUS_TX_MSBSWAP == 0x01);
+}
+scom 0x800.0b(tx_mode_pg)(tx_grp2)(lane_na).0x(dmi1_gcr_addr) {
+bits,                     scom_data, expr;
+tx_msbswap,               0b1,       (TGT1.ATTR_CHIP_UNIT_POS % 4 == 1); # MCS5
+#tx_msbswap,               0b1,       (ATTR_EI_BUS_TX_MSBSWAP == 0x01);
+}
+scom 0x800.0b(tx_mode_pg)(tx_grp1)(lane_na).0x(dmi1_gcr_addr) {
+bits,                     scom_data, expr;
+tx_msbswap,               0b1,       (TGT1.ATTR_CHIP_UNIT_POS % 4 == 2); # MCS6
+#tx_msbswap,               0b1,       (ATTR_EI_BUS_TX_MSBSWAP == 0x01);
+}
+scom 0x800.0b(tx_mode_pg)(tx_grp0)(lane_na).0x(dmi1_gcr_addr) {
+bits,                     scom_data, expr;
+tx_msbswap,               0b1,       (TGT1.ATTR_CHIP_UNIT_POS % 4 == 3); # MCS7
+#tx_msbswap,               0b1,       (ATTR_EI_BUS_TX_MSBSWAP == 0x01);
+}
+
+
+############################################################################################
+# END OF FILE
+############################################################################################
diff --git a/src/usr/hwpf/hwp/initfiles/p8.dmi.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.dmi.scom.initfile
index 4d77cb378..d12b0e139 100644
--- a/src/usr/hwpf/hwp/initfiles/p8.dmi.scom.initfile
+++ b/src/usr/hwpf/hwp/initfiles/p8.dmi.scom.initfile
@@ -1,481 +1,2081 @@
-#-- $Id: p8.dmi.scom.initfile,v 1.11 2013/01/22 02:46:58 thomsen Exp $
-#-- CHANGE HISTORY:
-#--------------------------------------------------------------------------------
-#-- Version:|Author: | Date:  | Comment:
-#-- --------|--------|--------|--------------------------------------------------
-#--    1.11 |thomsen |01/21/13|Removed ATTR_EI_BUS_RX_MSB_LSB_SWAP & ATTR_EI_BUS_TX_MSB_LSB_SWAP as those are old now
-#--         |        |        |Removed non-mirrored mode settings in PRBS tap id's                                   
-#--    1.10 |pmegan  |10/02/12|Removed rx_sls_extend_sel entry since its needed for slave chip only (Processor is always master on DMI)
-#--     1.9 |pmegan  |09/27/12|Set rx_sls_timeout_sel entry to 0b001 per defect HW220752
-#--                           |Set rx_sls_extend_sel entry to 0b100 per defect HW220806
-#--     1.8 |thomsen |07/13/12|Updated non-mirrored PRBS_TAP_ID's to have abcdefgabcdefgabc... pattern
-#--     1.7 |jmcgill |06/21/12|Update tx_clk_cntl_gcrmsg_pg to use def_tx_base_grp instead of def_rx_base_grp
-#--     1.6 |jmcgill |06/21/12|Updates to match dials
-#--     1.5 |thomsen |06/19/12|Changed name of rx_grp3 to be def_rx_base_grp in order to be more generic
-#--                           |Updated PRBS_TAP_ID's to match Centaur
-#--     1.4 |jmcgill |06/16/12|Update to generate MCS0 chipunit addresses required for translation
-#--     1.3 |thomsen |06/16/12|Added attribute comments
-#--     1.2 |thomsen |06/16/12|Rewrote to use target bus number in the expression fields to allow address translation for group # 
-#--     1.1 |thomsen |06/15/12|Created initial version
-#-- --------|--------|--------|--------------------------------------------------
-#--------------------------------------------------------------------------------
-# End of revision history
-#--------------------------------------------------------------------------------
-
-#--Master list of variables that can be used in this file is at:
-#--<Attribute Definition Location>
-
-#-- ATTR_CHIP_UNIT_POS is the MCS unit number (0-7 on Venice, 4-7 on Murano) and corresponds to the scom address translation done in
-#--  the p8.chipunit.scominfo file. It is used to be able to select a specific clock group number.
-#--  Chip     UNIT_POS  DMI_UNIT  CLOCKGRP
-#--  ----     --------  --------  --------
-#--  Venice:  0-3       DMI0      3-0
-#--           4-7       DMI1      3-0
-#--  Murano:  4-7       DMI1      3-0
+#-- $Id: p8.dmi.scom.initfile,v 1.12 2013/01/26 18:16:08 thomsen Exp $ 
+
+
+####################################################################
+##  
+##  Auto-genrated by fig2scominit.pl
+##      Based on SETUP_ID_MODE DMI_BUS_TR_HW
+##      from ../../logic/mesa_sim/fusion/run/IODPV_MC_WRAP.IODPV_MC_WRAP.figdb
+##
+##   Created on Thu Jan 24 14:48:02 EST 2013, by derrin
+####################################################################
+
+## -- CHANGE HISTORY:
+ ## --------------------------------------------------------------------------------
+ ## -- VersionID: |Author:  | Date:  | Comment:
+ ## -- -----------|---------|--------|-------------------------------------------------
+ ## -- mbs13011802| mbs     |01-18-13| Added rx_fence to run_mode dial (HW236326)
+ ## -- mbs12121100| mbs     |12-11-12| Added rx_prot_speed_slct and rx_c4_sel
+ ## -- smr12112700| SMR     |11-27-12| Added rx_dyn_recal_overall_timeout_sel init to 0b001
+ ## -- jfg12112101| jfg     |11-21-12| Added Zcal inits
+ ## -- jfg12112100| jfg     |11-21-12| Added CU pll modes
+ ## -- 12111300| berger  |11-13-12| Updated with HW eyeopt and recal settings
+ ## -- 12062500| SMR     |06-25-12| HW210654: Added rx_sls_timeout_sel default of 1
+ ## -- 11012500| mbs     |01-25-12| Swizzle and typo fixes for HW191494, HW191518, HW188304
+ ## -- 11011912| RJR     |01-17-12| Added RX_CTL2_REGS FILE REFERENCES
+ ## -- 12011800| berger  |01-19-12| Added SETUP_ID_MODE dials
+ ## -- 11121500| thomsen |12-15-11| Added Per-Pack GCR SCOM Addresses for Regchk (HW188381,HW182867)
+ ## --         |         |        | Removed 0x0000040000000000 from TX address definitions since it is in the lower level figtree files (HW187781,HW187893)
+ ## -- 11102100| SMR     |10-21-11| HW181193: Added rx_dyn_rpr_enc_bad_data_lane_width register
+ ## -- 11102500| jfg     |10-25-11| HW181485,HW181791: swizzle updates for scramble
+ ## -- 11092900| SMR     |09-29-11| HW171978: Added dyn rpr error tallying defaults
+ ## -- 11050300| SMR     |05-02-11| Added tx_max_bad_lanes
+ ## -- 11032200| jg      |02-17-11| Added RX PLLREG register offsets
+ ## -- 11022800| thomsen |02-28-11| Fixed RX/TX scramble tap pattern match problem between driver and receiver. Also fixed in iodnc_mb_top.fig.
+ ## -- 11021700| thomsen |02-17-11| Fixed RX_BUS_WIDTH from 17 to 24
+ ## -- 11021600| thomsen |02-16-11| Added Per-Bus, Per-Lane and Per-Group GCR SCOM addresses so Regchk would pass
+ ## -- 11020200| thomsen |02-02-11| Added RX & TX scramble/descramble tap ID settings
+ ## -- 11012500| berger  |01-25-11| added TX lane disable and rx_bus_width fields, added missing SETUP_ID fields
+ ## -- 11010600| smc     |01-06-11| changed prefix (generic vhdl only) to iodpv to match post generic
+ ## -- 11010600| berger  |01-06-11| added lane disable and max bad lane
+ ## -- 10121600| thomsen |12-16-10| Added RX_FENCE
+ ## -- 10121300| thomsen |12-13-10| Fixed END_LANE_ID values per HW133020
+ ## -- 10120800| thomsen |12-08-10| Added TX_BUS_WIDTH
+ ## -- 10102601| thomsen |10-26-10| Renamed gdial enum names from MC_BUS to DMI_BUS
+ ## -- 10102600| thomsen |10-26-10| Initial version
+ ## --------------------------------------------------------------------------------
+ ## -- TODO: These need to be modified for Z
+ ## -- TODO: Not sure how to handle gdials since Z has extra the extra group, ie. P won't acknowledge RX4.RXCTL.RX_CTL_REGS.RX_* dials exist.
 
 
 SyntaxVersion = 1
 
-#-- -----------------------------------------------------------------------------
-#--******************************************************************************
-#-- -----------------------------------------------------------------------------
-#--
-#-- Includes
-#-- Note:  Must include the path to the .define file.
-#-- -----------------------------------------------------------------------------
-#--******************************************************************************
-#-- -----------------------------------------------------------------------------
+
+
+####################################################################
+#  Define File
+####################################################################
 include edi.io.define
-#-- -----------------------------------------------------------------------------
-#--******************************************************************************
-#-- -----------------------------------------------------------------------------
-#--
-#-- Defines
-#--
-#-- -----------------------------------------------------------------------------
-#--******************************************************************************
-#-- -----------------------------------------------------------------------------
-
-define def_bus_id3 = ((ATTR_CHIP_UNIT_POS == 0) || (ATTR_CHIP_UNIT_POS == 4));
-define def_bus_id2 = ((ATTR_CHIP_UNIT_POS == 1) || (ATTR_CHIP_UNIT_POS == 5));
-define def_bus_id1 = ((ATTR_CHIP_UNIT_POS == 2) || (ATTR_CHIP_UNIT_POS == 6));
-define def_bus_id0 = ((ATTR_CHIP_UNIT_POS == 3) || (ATTR_CHIP_UNIT_POS == 7));
-
-# See p8.chipunit.scominfo file for details of how SCOM addresses are translated by Cronus and FW based on the target unit number
-define def_rx_base_grp = rx_grp3;   # Venice and Murano wire clkgrp3 to Cen0, clkgrp2 to Cen1, clkgrp1 to Cen2 and clkgrp0 to Cen3
-define def_tx_base_grp = tx_grp3;   # Venice and Murano wire clkgrp3 to Cen0, clkgrp2 to Cen1, clkgrp1 to Cen2 and clkgrp0 to Cen3
-
-#--******************************************************************************
-#-------------------------------------------------------------------------------------
-#    _____      __                 ________
-#   / ___/___  / /___  ______     /  _/ __ \
-#   \__ \/ _ \/ __/ / / / __ \    / // / / /
-#  ___/ /  __/ /_/ /_/ / /_/ /  _/ // /_/ /
-# /____/\___/\__/\__,_/ .___/  /___/_____/
-#                    /_/                    banner2 -fslant
-#-------------------------------------------------------------------------------------
-#--******************************************************************************
-#### X bus -> 4 CG's, 20 lanes, A bus -> 3 CG's, 23 lanes , DMI bus -> 4 CG's, 24 lanes
-#
-# Target unit number based address translation method - fAPI translates group address and lower scom address based on target unit num passed in
-#      - So the scom address group number must be 000011 for RX and 100011 for TX and lower 32-bits of scom address needs to be DMI0 address
-#--********************************************************************************************
-#-- rx_bus_id, tx_bus_id
-#--********************************************************************************************
-scom 0x800.0b(rx_id1_pg)(def_rx_base_grp)(lane_na).0x(dmi0_gcr_addr){
-        bits,                    scom_data,            expr;
-        rx_bus_id ,              0b000000,             (def_bus_id0);    # BusId equals the channel number on DMI (or equivalently the MCS#)
-        rx_bus_id ,              0b000001,             (def_bus_id1);    # DMI0 contains MCS0-3 and DMI1 MCS4-7. However, the relative bus_id is always 0-3 
-        rx_bus_id ,              0b000010,             (def_bus_id2);           
-        rx_bus_id ,              0b000011,             (def_bus_id3);           
-        rx_group_id,             0b000000,             any;              # GroupID is always 000000 on all RX DMI channels
-}
-scom 0x800.0b(tx_id1_pg)(def_tx_base_grp)(lane_na).0x(dmi0_gcr_addr){
-        bits,                    scom_data,            expr;
-        tx_bus_id ,              0b000000,             (def_bus_id0);    # BusId equals the channel number on DMI (or equivalently the MCS#)
-        tx_bus_id ,              0b000001,             (def_bus_id1);    # DMI0 contains MCS0-3 and DMI1 MCS4-7. However, the relative bus_id is always 0-3 
-        tx_bus_id ,              0b000010,             (def_bus_id2);
-        tx_bus_id ,              0b000011,             (def_bus_id3);
-        tx_group_id,             0b100000,             any;                        # GroupID is always 100000 on all TX DMI channels
-}
-#--********************************************************************************************
-#-- rx_last_group_id, tx_last_group_id
-#--********************************************************************************************
-scom 0x800.0b(rx_id2_pg)(def_rx_base_grp)(lane_na).0x(dmi0_gcr_addr){
-        bits,                   scom_data;
-        rx_last_group_id ,      0b000000;    # Each "bus/channel" on DMI consists only of one clock group so the last group is 000000 for RX
-}
-scom 0x800.0b(tx_id2_pg)(def_tx_base_grp)(lane_na).0x(dmi0_gcr_addr){
-        bits,                   scom_data;
-        tx_last_group_id ,      0b100000;    # Each "bus/channel" on DMI consists only of one clock group so the last group is 100000 for TX	
-}
-#--*********************************************************************************************
-#-- rx_start_lane_id, rx_end_lane_id
-#--*********************************************************************************************
-# Upstream = 24-bits
-scom 0x800.0b(rx_id3_pg)(def_rx_base_grp)(lane_na).0x(dmi0_gcr_addr){
-        bits,                   scom_data;
-        rx_start_lane_id ,      0b0000000;    # Each RX CG or "bus/channel" on DMI starts with lane 0
-        rx_end_lane_id,         0b0010111;    # Each RX CG or "bus/channel" on DMI ends with lane 23 
-}
-# Downstream = 17-bits
-scom 0x800.0b(tx_id3_pg)(def_tx_base_grp)(lane_na).0x(dmi0_gcr_addr){
-        bits,                   scom_data;
-        tx_start_lane_id ,      0b0000000;    # Each TX CG or "bus/channel" on DMI starts with lane 0
-        tx_end_lane_id,         0b0010000;    # Each TX CG or "bus/channel" on DMI ends with lane 16 
-}
-#--*********************************************************************************************
-#-- rx_tx_bus_width, rx_rx_bus_width
-#--*********************************************************************************************
-# Upstream = 24-bits
-scom 0x800.0b(rx_tx_bus_info_pg)(def_rx_base_grp)(lane_na).0x(dmi0_gcr_addr){
-        bits,                   scom_data;
-        rx_tx_bus_width,        0b0010001;    # Each TX CG or "bus/channel" on DMI is 17-bits
-        rx_rx_bus_width,        0b0011000;    # Each RX CG or "bus/channel" on DMI is 24-bits
-}
-#-----------------------------------------------------------------------------------------------
-#     ______
-#    / ____/__  ____  ________                  #### TODO: This needs to be set in the scaninit file and io_hard_reset factored into all reinit scenarios
-#   / /_  / _ \/ __ \/ ___/ _ \
-#  / __/ /  __/ / / / /__/  __/
-# /_/    \___/_/ /_/\___/\___/  banner2 -fslant
-#----------------------------------------------------------------------------------------------
-scom 0x800.0b(rx_fence_pg)(def_rx_base_grp)(lane_na).0x(dmi0_gcr_addr) {
-        bits ,         scom_data;
-        rx_fence,       0b1;
-}
-#----------------------------------------------------------------------------------------------
-#     __                        ____  _            __    __
-#    / /   ____ _____  ___     / __ \(_)________ _/ /_  / /__  _____
-#   / /   / __ `/ __ \/ _ \   / / / / / ___/ __ `/ __ \/ / _ \/ ___/
-#  / /___/ /_/ / / / /  __/  / /_/ / (__  ) /_/ / /_/ / /  __(__  )
-# /_____/\__,_/_/ /_/\___/  /_____/_/____/\__,_/_.___/_/\___/____/   banner2 -fslant
-#----------------------------------------------------------------------------------------------
-#--*********************************************************************************************
-#-- rx_lane_disabled_vec_0_15, rx_lane_disabled_vec_16_31
-#--*********************************************************************************************
-# Upstream = 24-bits
-scom 0x800.0b(rx_lane_disabled_vec_0_15_pg)(def_rx_base_grp)(lane_na).0x(dmi0_gcr_addr){
-        bits,                        scom_data;
-        rx_lane_disabled_vec_0_15,   0b0000000000000000;    # Each RX CG or "bus/channel" on DMI has lanes 0-15 enabled (ie. disabled=0)
-}
-scom 0x800.0b(rx_lane_disabled_vec_16_31_pg)(def_rx_base_grp)(lane_na).0x(dmi0_gcr_addr){
-        bits,                        scom_data;
-        rx_lane_disabled_vec_16_31,  0b0000000011111111;    # Each RX CG or "bus/channel" on DMI has lanes 16-23 enabled (ie. disabled=0)
-}
-#--*********************************************************************************************
-#-- tx_lane_disabled_vec_0_15, tx_lane_disabled_vec_16_31
-#--*********************************************************************************************
-# Downstream = 17-bits
-scom 0x800.0b(tx_lane_disabled_vec_0_15_pg)(def_tx_base_grp)(lane_na).0x(dmi0_gcr_addr){
-        bits,                        scom_data;
-        tx_lane_disabled_vec_0_15,   0b0000000000000000;    # Each RX CG or "bus/channel" on DMI has lanes 0-15 enabled (ie. disabled=0)
-}
-scom 0x800.0b(tx_lane_disabled_vec_16_31_pg)(def_tx_base_grp)(lane_na).0x(dmi0_gcr_addr){
-        bits,                        scom_data;
-        tx_lane_disabled_vec_16_31,  0b0111111111111111;    # Each RX CG or "bus/channel" on DMI has lane 16 enabled (ie. disabled=0)
-}
-#-------------------------------------------------------------------------------------
-#     __  ___              ____            __   __
-#    /  |/  /___ __  __   / __ )____ _____/ /  / /   ____ _____  ___  _____
-#   / /|_/ / __ `/ |/_/  / __  / __ `/ __  /  / /   / __ `/ __ \/ _ \/ ___/
-#  / /  / / /_/ />  <   / /_/ / /_/ / /_/ /  / /___/ /_/ / / / /  __(__  )
-# /_/  /_/\__,_/_/|_|  /_____/\__,_/\__,_/  /_____/\__,_/_/ /_/\___/____/  banner2 -fslant
-#-------------------------------------------------------------------------------------
-#--*********************************************************************************************
-#-- rx_wtr_max_bad_lanes, tx_max_bad_lanes
-#--*********************************************************************************************
-# Upstream = 2 spares
-scom 0x800.0b(rx_wiretest_laneinfo_pg)(def_rx_base_grp)(lane_na).0x(dmi0_gcr_addr){
-        bits,                        scom_data;
-        rx_wtr_max_bad_lanes,        0b00010;    # Each RX CG or "bus/channel" on DMI has 2 spare lanes
-}
-# Downstream = 2 spares
-scom 0x800.0b(tx_mode_pg)(def_tx_base_grp)(lane_na).0x(dmi0_gcr_addr){
-        bits,                        scom_data;
-        tx_max_bad_lanes,            0b00010;    # Each TX CG or "bus/channel" on DMI has 2 spare lanes
-}
-#-------------------------------------------------------------------------------------
-#     ____                 ____                   _         ______      ____      _
-#    / __ \__  ______     / __ \___  ____  ____ _(_)____   /_  __/___ _/ / /_  __(_)___  ____ _
-#   / / / / / / / __ \   / /_/ / _ \/ __ \/ __ `/ / ___/    / / / __ `/ / / / / / / __ \/ __ `/
-#  / /_/ / /_/ / / / /  / _, _/  __/ /_/ / /_/ / / /       / / / /_/ / / / /_/ / / / / / /_/ /
-# /_____/\__, /_/ /_/  /_/ |_|\___/ .___/\__,_/_/_/       /_/  \__,_/_/_/\__, /_/_/ /_/\__, /
-#       /____/                   /_/                                    /____/        /____/   banner2 -fslant
-#-------------------------------------------------------------------------------------
-#--*********************************************************************************************
-#-- rx_dyn_rpr_err_tallying1_pg: rx_dyn_rpr_bad_lane_max, rx_dyn_rpr_err_cntr1_duration, rx_dyn_rpr_enc_bad_data_lane_width
-#--*********************************************************************************************
-scom 0x800.0b(rx_dyn_rpr_err_tallying1_pg)(def_rx_base_grp)(lane_na).0x(dmi0_gcr_addr){
-        bits,                               scom_data;
-        rx_dyn_rpr_bad_lane_max,            0b0001111;    # 
-        rx_dyn_rpr_err_cntr1_duration,      0b0111;       # 
-        rx_dyn_rpr_enc_bad_data_lane_width, 0b101;        # 
-}
-#--*********************************************************************************************
-#-- rx_dyn_rpr_err_tallying2_pg: rx_dyn_rpr_bad_bus_max, rx_dyn_rpr_err_cntr2_duration
-#--*********************************************************************************************
-scom 0x800.0b(rx_dyn_rpr_err_tallying2_pg)(def_rx_base_grp)(lane_na).0x(dmi0_gcr_addr){
-        bits,                               scom_data;
-        rx_dyn_rpr_bad_bus_max,             0b0111111;    # 
-        rx_dyn_rpr_err_cntr2_duration,      0b0111;       # 
-}
-#-------------------------------------------------------------------------------------
-#     __  ___           __               __  ___          __
-#    /  |/  /___ ______/ /____  _____   /  |/  /___  ____/ /__
-#   / /|_/ / __ `/ ___/ __/ _ \/ ___/  / /|_/ / __ \/ __  / _ \
-#  / /  / / /_/ (__  ) /_/  __/ /     / /  / / /_/ / /_/ /  __/
-# /_/  /_/\__,_/____/\__/\___/_/     /_/  /_/\____/\__,_/\___/
-#-------------------------------------------------------------------------------------
-#--*********************************************************************************************
-#-- rx_mode_pg: rx_master_mode
-#--*********************************************************************************************
-scom 0x800.0b(rx_mode_pg)(def_rx_base_grp)(lane_na).0x(dmi0_gcr_addr){
-        bits,                               scom_data;
-        rx_master_mode,                     0b1;    # Processor is always master on DMI 
-}
-#-------------------------------------------------------------------------------------
-#     ____  ____  ____ _____    ______               _____      __          __
-#    / __ \/ __ \/ __ ) ___/   /_  __/___ _____     / ___/___  / /__  _____/ /______
-#   / /_/ / /_/ / __  \__ \     / / / __ `/ __ \    \__ \/ _ \/ / _ \/ ___/ __/ ___/
-#  / ____/ _, _/ /_/ /__/ /    / / / /_/ / /_/ /   ___/ /  __/ /  __/ /__/ /_(__  )
-# /_/   /_/ |_/_____/____/    /_/  \__,_/ .___/   /____/\___/_/\___/\___/\__/____/  banner2 -fslant
-#                                      /_/
-#-------------------------------------------------------------------------------------
-# PER-LANE (RX: 24 lanes)
-#-------------------------------------------------------------------------------------
-#--*********************************************************************************************
-#-- rx_prbs_mode_pl: rx_prbs_tap_id
-#--*********************************************************************************************
-scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_0).0x(dmi0_gcr_addr){
-        bits,                  scom_data;
-        rx_prbs_tap_id,        rx_prbs_tap_id_pattern_a;
-}
-scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_1).0x(dmi0_gcr_addr){
-        bits,                  scom_data;
-        rx_prbs_tap_id,        rx_prbs_tap_id_pattern_b;    
-}
-scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_2).0x(dmi0_gcr_addr){
-        bits,                  scom_data;
-        rx_prbs_tap_id,        rx_prbs_tap_id_pattern_c;    
-}
-scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_3).0x(dmi0_gcr_addr){
-        bits,                  scom_data;
-        rx_prbs_tap_id,        rx_prbs_tap_id_pattern_d;    
-}
-scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_4).0x(dmi0_gcr_addr){
-        bits,                  scom_data;
-        rx_prbs_tap_id,        rx_prbs_tap_id_pattern_e;    
-}
-scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_5).0x(dmi0_gcr_addr){
-        bits,                  scom_data;
-        rx_prbs_tap_id,        rx_prbs_tap_id_pattern_f;    
-}
-scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_6).0x(dmi0_gcr_addr){
-        bits,                  scom_data;
-        rx_prbs_tap_id,        rx_prbs_tap_id_pattern_g;    
-}
-scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_7).0x(dmi0_gcr_addr){
-        bits,                  scom_data;
-        rx_prbs_tap_id,        rx_prbs_tap_id_pattern_h;    
-}
-scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_8).0x(dmi0_gcr_addr){
-        bits,                  scom_data;
-        rx_prbs_tap_id,        rx_prbs_tap_id_pattern_a;    
-}
-scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_9).0x(dmi0_gcr_addr){
-        bits,                  scom_data;
-        rx_prbs_tap_id,        rx_prbs_tap_id_pattern_b;    
-}
-scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_10).0x(dmi0_gcr_addr){
-        bits,                  scom_data;
-        rx_prbs_tap_id,        rx_prbs_tap_id_pattern_c;    
-}
-scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_11).0x(dmi0_gcr_addr){
-        bits,                  scom_data;
-        rx_prbs_tap_id,        rx_prbs_tap_id_pattern_d;    
-}
-scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_12).0x(dmi0_gcr_addr){
-        bits,                  scom_data;
-        rx_prbs_tap_id,        rx_prbs_tap_id_pattern_d;    
-}
-scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_13).0x(dmi0_gcr_addr){
-        bits,                  scom_data;
-        rx_prbs_tap_id,        rx_prbs_tap_id_pattern_c;    
-}
-scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_14).0x(dmi0_gcr_addr){
-        bits,                  scom_data;
-        rx_prbs_tap_id,        rx_prbs_tap_id_pattern_b;    
-}
-scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_15).0x(dmi0_gcr_addr){
-        bits,                  scom_data;
-        rx_prbs_tap_id,        rx_prbs_tap_id_pattern_a;    
-}
-scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_16).0x(dmi0_gcr_addr){
-        bits,                  scom_data;
-        rx_prbs_tap_id,        rx_prbs_tap_id_pattern_h;    
-}
-scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_17).0x(dmi0_gcr_addr){
-        bits,                  scom_data;
-        rx_prbs_tap_id,        rx_prbs_tap_id_pattern_g;    
-}
-scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_18).0x(dmi0_gcr_addr){
-        bits,                  scom_data;
-        rx_prbs_tap_id,        rx_prbs_tap_id_pattern_f;    
-}
-scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_19).0x(dmi0_gcr_addr){
-        bits,                  scom_data;
-        rx_prbs_tap_id,        rx_prbs_tap_id_pattern_e;    
-}
-scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_20).0x(dmi0_gcr_addr){
-        bits,                  scom_data;
-        rx_prbs_tap_id,        rx_prbs_tap_id_pattern_d;    
-}
-scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_21).0x(dmi0_gcr_addr){
-        bits,                  scom_data;
-        rx_prbs_tap_id,        rx_prbs_tap_id_pattern_c;    
-}
-scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_22).0x(dmi0_gcr_addr){
-        bits,                  scom_data;
-        rx_prbs_tap_id,        rx_prbs_tap_id_pattern_b;    
-}
-scom 0x800.0b(rx_prbs_mode_pl)(def_rx_base_grp)(lane_23).0x(dmi0_gcr_addr){
-        bits,                  scom_data;
-        rx_prbs_tap_id,        rx_prbs_tap_id_pattern_a;    
-}
-#-------------------------------------------------------------------------------------
-# PER-LANE (TX: 17 lanes)
-#-------------------------------------------------------------------------------------
-#--*********************************************************************************************
-#-- tx_prbs_mode_pl: tx_prbs_tap_id
-#--*********************************************************************************************
-scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_0).0x(dmi0_gcr_addr){
-        bits,                  scom_data;
-        tx_prbs_tap_id,        tx_prbs_tap_id_pattern_a;
-}
-scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_1).0x(dmi0_gcr_addr){
-        bits,                  scom_data;
-        tx_prbs_tap_id,        tx_prbs_tap_id_pattern_b;    
-}
-scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_2).0x(dmi0_gcr_addr){
-        bits,                  scom_data;
-        tx_prbs_tap_id,        tx_prbs_tap_id_pattern_c;    
-}
-scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_3).0x(dmi0_gcr_addr){
-        bits,                  scom_data;
-        tx_prbs_tap_id,        tx_prbs_tap_id_pattern_d;    
-}
-scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_4).0x(dmi0_gcr_addr){
-        bits,                  scom_data;
-        tx_prbs_tap_id,        tx_prbs_tap_id_pattern_e;    
-}
-scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_5).0x(dmi0_gcr_addr){
-        bits,                  scom_data;
-        tx_prbs_tap_id,        tx_prbs_tap_id_pattern_f;    
-}
-scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_6).0x(dmi0_gcr_addr){
-        bits,                  scom_data;
-        tx_prbs_tap_id,        tx_prbs_tap_id_pattern_g;    
-}
-scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_7).0x(dmi0_gcr_addr){
-        bits,                  scom_data;
-        tx_prbs_tap_id,        tx_prbs_tap_id_pattern_h;    
-}
-scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_8).0x(dmi0_gcr_addr){
-        bits,                  scom_data;
-        tx_prbs_tap_id,        tx_prbs_tap_id_pattern_a;    
-}
-scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_9).0x(dmi0_gcr_addr){
-        bits,                  scom_data;
-        tx_prbs_tap_id,        tx_prbs_tap_id_pattern_h;    
-}
-scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_10).0x(dmi0_gcr_addr){
-        bits,                  scom_data;
-        tx_prbs_tap_id,        tx_prbs_tap_id_pattern_g;    
-}
-scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_11).0x(dmi0_gcr_addr){
-        bits,                  scom_data;
-        tx_prbs_tap_id,        tx_prbs_tap_id_pattern_f;    
-}
-scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_12).0x(dmi0_gcr_addr){
-        bits,                  scom_data;
-        tx_prbs_tap_id,        tx_prbs_tap_id_pattern_e;    
-}
-scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_13).0x(dmi0_gcr_addr){
-        bits,                  scom_data;
-        tx_prbs_tap_id,        tx_prbs_tap_id_pattern_d;    
-}
-scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_14).0x(dmi0_gcr_addr){
-        bits,                  scom_data;
-        tx_prbs_tap_id,        tx_prbs_tap_id_pattern_c;    
-}
-scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_15).0x(dmi0_gcr_addr){
-        bits,                  scom_data;
-        tx_prbs_tap_id,        tx_prbs_tap_id_pattern_b;    
-}
-scom 0x800.0b(tx_prbs_mode_pl)(def_tx_base_grp)(lane_16).0x(dmi0_gcr_addr){
-        bits,                  scom_data;
-        tx_prbs_tap_id,        tx_prbs_tap_id_pattern_a;    
-}
-#-------------------------------------------------------------------------------------
-#     ____  __    __
-#    / __ \/ /   / /
-#   / /_/ / /   / /
-#  / ____/ /___/ /___
-# /_/   /_____/_____/  banner2 -fslant
-#-------------------------------------------------------------------------------------
-#--*********************************************************************************************
-#-- rx_wiretest_pll_cntl_pg: rx_wt_cu_pll_reset, rx_wt_cu_pll_pgooddly
-#--*********************************************************************************************
-scom 0x800.0b(rx_wiretest_pll_cntl_pg)(def_rx_base_grp)(lane_na).0x(dmi0_gcr_addr){
-        bits,                  scom_data;
-        rx_wt_cu_pll_reset,    0b0;    
-        rx_wt_cu_pll_pgooddly, 0b001;  # 50ns delay
-}
-#-------------------------------------------------------------------------------------
-#     ____       _               __________      ____        __  __
-#    / __ \_____(_)   _____     / ____/ / /__   / __ \____ _/ /_/ /____  _________
-#   / / / / ___/ / | / / _ \   / /   / / //_/  / /_/ / __ `/ __/ __/ _ \/ ___/ __ \
-#  / /_/ / /  / /| |/ /  __/  / /___/ / ,<    / ____/ /_/ / /_/ /_/  __/ /  / / / /
-# /_____/_/  /_/ |___/\___/   \____/_/_/|_|  /_/    \__,_/\__/\__/\___/_/  /_/ /_/
-#-------------------------------------------------------------------------------------
-#--*********************************************************************************************
-#-- tx_clk_cntl_gcrmsg_pg: tx_drv_clk_pattern_gcrmsg
-#--*********************************************************************************************
-scom 0x800.0b(tx_clk_cntl_gcrmsg_pg)(def_tx_base_grp)(lane_na).0x(dmi0_gcr_addr){
-        bits,                         scom_data;
-        tx_drv_clk_pattern_gcrmsg,    0b00;    # Drive 0's to start out
-}
-#-------------------------------------------------------------------------------------
-#    ____ _  __    _______                        _____      __
-#   / __ \ |/ /   /_  __(_)___ ___  ___  _____   / ___/___  / /
-#  / /_/ /   /     / / / / __ `__ \/ _ \/ ___/   \__ \/ _ \/ / 
-# / _, _/   |     / / / / / / / / /  __/ /      ___/ /  __/ /  
-#/_/ |_/_/|_|    /_/ /_/_/ /_/ /_/\___/_/      /____/\___/_/   
-#-------------------------------------------------------------------------------------
-#--*********************************************************************************************
-#-- rx_timeout_sel_pg: rx_sls_timeout_sel        
-#--*********************************************************************************************
-scom 0x800.0b(rx_timeout_sel_pg)(def_rx_base_grp)(lane_na).0x(dmi0_gcr_addr){
-        bits,                   scom_data;
-        rx_sls_timeout_sel,     0b001;    # Set this entry to 0b001 per defect HW220752
-}
-                                                              
-#-------------------------------------------------------------------------------------
-#    ____ _  __    _____ __   _____    ______     __                 __   _____      __
-#   / __ \ |/ /   / ___// /  / ___/   / ____/  __/ /____  ____  ____/ /  / ___/___  / /
-#  / /_/ /   /    \__ \/ /   \__ \   / __/ | |/_/ __/ _ \/ __ \/ __  /   \__ \/ _ \/ / 
-# / _, _/   |    ___/ / /______/ /  / /____>  </ /_/  __/ / / / /_/ /   ___/ /  __/ /  
-#/_/ |_/_/|_|   /____/_____/____/  /_____/_/|_|\__/\___/_/ /_/\__,_/   /____/\___/_/   
-#-------------------------------------------------------------------------------------
-#--*********************************************************************************************
-#-- rx_spare_mode_pg: rx_sls_extend_sel                      
-#--*********************************************************************************************
-#scom 0x800.0b(rx_spare_mode_pg)(def_rx_base_grp)(lane_na).0x(dmi0_gcr_addr){
-#        bits,                   scom_data;
-#        rx_sls_extend_sel,     0b100;    # Set this entry to 0b100 per defect HW220806
-#}
-
-############################################################################################
-# END OF FILE
-############################################################################################
+
+                    define HW_EXPRESS = SYS.ATTR_IS_SIMULATION == 0;
+                    define VBU_EXPRESS = SYS.ATTR_IS_SIMULATION == 1;
+                
+
+
+define def_bus_id3 = ((TGT1.ATTR_CHIP_UNIT_POS == 0) || (TGT1.ATTR_CHIP_UNIT_POS == 4));
+define def_bus_id2 = ((TGT1.ATTR_CHIP_UNIT_POS == 1) || (TGT1.ATTR_CHIP_UNIT_POS == 5));
+define def_bus_id1 = ((TGT1.ATTR_CHIP_UNIT_POS == 2) || (TGT1.ATTR_CHIP_UNIT_POS == 6));
+define def_bus_id0 = ((TGT1.ATTR_CHIP_UNIT_POS == 3) || (TGT1.ATTR_CHIP_UNIT_POS == 7));
+
+
+
+#BUSCTL.BUS_CTL_REGS.TX_IMPCAL_P_4X_PB
+scom 0x800F1C0002011E3F { 
+	bits, scom_data, expr;
+	tx_zcal_p_4x, 0b00100, any;
+}
+
+#BUSCTL.BUS_CTL_REGS.TX_IMPCAL_SWO2_PB
+scom 0x800F2C0002011E3F { 
+	bits, scom_data, expr;
+	tx_zcal_sm_max_val, 0b1000110, any;
+     tx_zcal_sm_min_val,  0b0010101   , HW_EXPRESS;
+     tx_zcal_sm_min_val,  0b0010110  , VBU_EXPRESS;
+}
+
+#RX0.RXCTL.RX_CTL_REGS.RX_DFE_CONFIG_PP
+scom 0x800B780002011E3F { 
+	bits, scom_data, expr;
+     rx_amin_cfg,  0b010,   HW_EXPRESS && def_bus_id0;
+     rx_amin_cfg,  0b000,  VBU_EXPRESS && def_bus_id0;
+     rx_anap_cfg,  0b10,   HW_EXPRESS && def_bus_id0;
+     rx_anap_cfg,  0b00,  VBU_EXPRESS && def_bus_id0;
+     rx_h1ap_cfg,  0b011,   HW_EXPRESS && def_bus_id0;
+     rx_h1ap_cfg,  0b000,  VBU_EXPRESS && def_bus_id0;
+     rx_peak_cfg,  0b10,   HW_EXPRESS && def_bus_id0;
+     rx_peak_cfg,  0b00,  VBU_EXPRESS && def_bus_id0;
+}
+
+#RX0.RXCTL.RX_CTL_REGS.RX_DFE_TIMERS_PP
+scom 0x800B800002011E3F { 
+	bits, scom_data, expr;
+     rx_init_tmr_cfg,  0b100,   HW_EXPRESS && def_bus_id0;
+     rx_init_tmr_cfg,  0b000,  VBU_EXPRESS && def_bus_id0;
+}
+
+#RX0.RXCTL.RX_CTL_REGS.RX_DYN_RECAL_CONFIG_PG
+scom 0x800A180002011E3F { 
+	bits, scom_data, expr;
+	rx_dyn_recal_overall_timeout_sel, 0b001, def_bus_id0;
+}
+
+#RX0.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING1_PG
+scom 0x8009D80002011E3F { 
+	bits, scom_data, expr;
+	rx_dyn_rpr_bad_lane_max, 0b0001111, def_bus_id0;
+	rx_dyn_rpr_enc_bad_data_lane_width, 0b101, def_bus_id0;
+	rx_dyn_rpr_err_cntr1_duration, 0b0111, def_bus_id0;
+}
+
+#RX0.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING2_PG
+scom 0x800AE00002011E3F { 
+	bits, scom_data, expr;
+	rx_dyn_rpr_bad_bus_max, 0b0111111, def_bus_id0;
+	rx_dyn_rpr_err_cntr2_duration, 0b0111, def_bus_id0;
+}
+
+#RX0.RXCTL.RX_CTL_REGS.RX_EO_STEP_CNTL_PG
+scom 0x800A380002011E3F { 
+	bits, scom_data, expr;
+     rx_eo_enable_ber_test,  0b1,   HW_EXPRESS && def_bus_id0;
+     rx_eo_enable_ber_test,  0b0,  VBU_EXPRESS && def_bus_id0;
+     rx_eo_enable_ctle_cal,  0b1,   HW_EXPRESS && def_bus_id0;
+     rx_eo_enable_ctle_cal,  0b0,  VBU_EXPRESS && def_bus_id0;
+     rx_eo_enable_ddc,  0b1,   HW_EXPRESS && def_bus_id0;
+     rx_eo_enable_ddc,  0b0,  VBU_EXPRESS && def_bus_id0;
+     rx_eo_enable_dfe_h1_cal,  0b1,   HW_EXPRESS && def_bus_id0;
+     rx_eo_enable_dfe_h1_cal,  0b0,  VBU_EXPRESS && def_bus_id0;
+	rx_eo_enable_final_l2u_adj, 0b1, def_bus_id0;
+     rx_eo_enable_h1ap_tweak,  0b1,   HW_EXPRESS && def_bus_id0;
+     rx_eo_enable_h1ap_tweak,  0b0,  VBU_EXPRESS && def_bus_id0;
+     rx_eo_enable_latch_offset_cal,  0b1,   HW_EXPRESS && def_bus_id0;
+     rx_eo_enable_latch_offset_cal,  0b0,  VBU_EXPRESS && def_bus_id0;
+     rx_eo_enable_result_check,  0b1,   HW_EXPRESS && def_bus_id0;
+     rx_eo_enable_result_check,  0b0,  VBU_EXPRESS && def_bus_id0;
+     rx_eo_enable_vga_cal,  0b1,   HW_EXPRESS && def_bus_id0;
+     rx_eo_enable_vga_cal,  0b0,  VBU_EXPRESS && def_bus_id0;
+}
+
+#RX0.RXCTL.RX_CTL_REGS.RX_FENCE_PG
+scom 0x8009A80002011E3F { 
+	bits, scom_data, expr;
+	rx_fence, 0b1, def_bus_id0;
+}
+
+#RX0.RXCTL.RX_CTL_REGS.RX_ID1_PG
+scom 0x8008500002011E3F { 
+	bits, scom_data, expr;
+	rx_bus_id, 0b000000, def_bus_id0;
+	rx_group_id, 0b000000, def_bus_id0;
+}
+
+#RX0.RXCTL.RX_CTL_REGS.RX_ID2_PG
+scom 0x8008580002011E3F { 
+	bits, scom_data, expr;
+	rx_last_group_id, 0b000000, def_bus_id0;
+}
+
+#RX0.RXCTL.RX_CTL_REGS.RX_ID3_PG
+scom 0x8008600002011E3F { 
+	bits, scom_data, expr;
+	rx_end_lane_id, 0b0010111, def_bus_id0;
+	rx_start_lane_id, 0b0000000, def_bus_id0;
+}
+
+#RX0.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_0_15_PG
+scom 0x8009280002011E3F { 
+	bits, scom_data, expr;
+	rx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id0;
+}
+
+#RX0.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_16_31_PG
+scom 0x8009300002011E3F { 
+	bits, scom_data, expr;
+	rx_lane_disabled_vec_16_31, 0b0000000011111111, def_bus_id0;
+}
+
+#RX0.RXCTL.RX_CTL_REGS.RX_MISC_ANALOG_PG
+scom 0x8009C00002011E3F { 
+	bits, scom_data, expr;
+     rx_c4_sel,  0b00,   HW_EXPRESS && def_bus_id0;
+     rx_c4_sel,  0b11,  VBU_EXPRESS && def_bus_id0;
+     rx_prot_speed_slct,  0b1,   HW_EXPRESS && def_bus_id0;
+     rx_prot_speed_slct,  0b0,  VBU_EXPRESS && def_bus_id0;
+}
+
+#RX0.RXCTL.RX_CTL_REGS.RX_MODE_PG
+scom 0x8008180002011E3F { 
+	bits, scom_data, expr;
+	rx_master_mode, 0b1, def_bus_id0;
+}
+
+#RX0.RXCTL.RX_CTL_REGS.RX_RC_STEP_CNTL_PG
+scom 0x800AB80002011E3F { 
+	bits, scom_data, expr;
+     rx_rc_enable_ber_test,  0b1,   HW_EXPRESS && def_bus_id0;
+     rx_rc_enable_ber_test,  0b0,  VBU_EXPRESS && def_bus_id0;
+     rx_rc_enable_ctle_cal,  0b1,   HW_EXPRESS && def_bus_id0;
+     rx_rc_enable_ctle_cal,  0b0,  VBU_EXPRESS && def_bus_id0;
+     rx_rc_enable_ddc,  0b1,   HW_EXPRESS && def_bus_id0;
+     rx_rc_enable_ddc,  0b0,  VBU_EXPRESS && def_bus_id0;
+     rx_rc_enable_dfe_h1_cal,  0b1,   HW_EXPRESS && def_bus_id0;
+     rx_rc_enable_dfe_h1_cal,  0b0,  VBU_EXPRESS && def_bus_id0;
+     rx_rc_enable_h1ap_tweak,  0b1,   HW_EXPRESS && def_bus_id0;
+     rx_rc_enable_h1ap_tweak,  0b0,  VBU_EXPRESS && def_bus_id0;
+     rx_rc_enable_latch_offset_cal,  0b1,   HW_EXPRESS && def_bus_id0;
+     rx_rc_enable_latch_offset_cal,  0b0,  VBU_EXPRESS && def_bus_id0;
+     rx_rc_enable_result_check,  0b1,   HW_EXPRESS && def_bus_id0;
+     rx_rc_enable_result_check,  0b0,  VBU_EXPRESS && def_bus_id0;
+     rx_rc_enable_vga_cal,  0b1,   HW_EXPRESS && def_bus_id0;
+     rx_rc_enable_vga_cal,  0b0,  VBU_EXPRESS && def_bus_id0;
+}
+
+#RX0.RXCTL.RX_CTL_REGS.RX_RECAL_TO2_PP
+scom 0x800B980002011E3F { 
+	bits, scom_data, expr;
+     rx_recal_timeout_sel_g,  0b0111,   HW_EXPRESS && def_bus_id0;
+     rx_recal_timeout_sel_g,  0b0110,  VBU_EXPRESS && def_bus_id0;
+     rx_recal_timeout_sel_h,  0b0110,   HW_EXPRESS && def_bus_id0;
+     rx_recal_timeout_sel_h,  0b1000,  VBU_EXPRESS && def_bus_id0;
+}
+
+#RX0.RXCTL.RX_CTL_REGS.RX_RECAL_TO3_PP
+scom 0x800BA00002011E3F { 
+	bits, scom_data, expr;
+     rx_recal_timeout_sel_i,  0b0111,   HW_EXPRESS && def_bus_id0;
+     rx_recal_timeout_sel_i,  0b1000,  VBU_EXPRESS && def_bus_id0;
+     rx_recal_timeout_sel_l,  0b0100,   HW_EXPRESS && def_bus_id0;
+     rx_recal_timeout_sel_l,  0b0110,  VBU_EXPRESS && def_bus_id0;
+}
+
+#RX0.RXCTL.RX_CTL_REGS.RX_SERVO_TO1_PP
+scom 0x800B600002011E3F { 
+	bits, scom_data, expr;
+     rx_servo_timeout_sel_d,  0b1010,   HW_EXPRESS && def_bus_id0;
+     rx_servo_timeout_sel_d,  0b1000,  VBU_EXPRESS && def_bus_id0;
+}
+
+#RX0.RXCTL.RX_CTL_REGS.RX_SERVO_TO2_PP
+scom 0x800B680002011E3F { 
+	bits, scom_data, expr;
+     rx_servo_timeout_sel_f,  0b0001,   HW_EXPRESS && def_bus_id0;
+     rx_servo_timeout_sel_f,  0b0110,  VBU_EXPRESS && def_bus_id0;
+     rx_servo_timeout_sel_g,  0b0111,   HW_EXPRESS && def_bus_id0;
+     rx_servo_timeout_sel_g,  0b0100,  VBU_EXPRESS && def_bus_id0;
+}
+
+#RX0.RXCTL.RX_CTL_REGS.RX_SERVO_TO3_PP
+scom 0x800B700002011E3F { 
+	bits, scom_data, expr;
+     rx_servo_timeout_sel_i,  0b0111,   HW_EXPRESS && def_bus_id0;
+     rx_servo_timeout_sel_i,  0b1000,  VBU_EXPRESS && def_bus_id0;
+     rx_servo_timeout_sel_k,  0b0111,   HW_EXPRESS && def_bus_id0;
+     rx_servo_timeout_sel_k,  0b1000,  VBU_EXPRESS && def_bus_id0;
+}
+
+#RX0.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL_PG
+scom 0x8008980002011E3F { 
+	bits, scom_data, expr;
+	rx_sls_timeout_sel, 0b001, def_bus_id0;
+}
+
+#RX0.RXCTL.RX_CTL_REGS.RX_TX_BUS_INFO_PG
+scom 0x8009980002011E3F { 
+	bits, scom_data, expr;
+	rx_rx_bus_width, 0b0011000, def_bus_id0;
+	rx_tx_bus_width, 0b0010001, def_bus_id0;
+}
+
+#RX0.RXCTL.RX_CTL_REGS.RX_WIRETEST_LANEINFO_PG
+scom 0x8009580002011E3F { 
+	bits, scom_data, expr;
+	rx_wtr_max_bad_lanes, 0b00010, def_bus_id0;
+}
+
+#RX0.RXCTL.RX_CTL_REGS.RX_WIRETEST_PLL_CNTL_PG
+scom 0x800A300002011E3F { 
+	bits, scom_data, expr;
+     rx_wt_cu_pll_pgooddly,  0b001,   HW_EXPRESS && def_bus_id0;
+     rx_wt_cu_pll_pgooddly,  0b000,  VBU_EXPRESS && def_bus_id0;
+     rx_wt_cu_pll_reset,  0b0,   HW_EXPRESS && def_bus_id0;
+     rx_wt_cu_pll_reset,  0b1,  VBU_EXPRESS && def_bus_id0;
+}
+
+#RX0.RXPACKS#0.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B00002011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b000, def_bus_id0;
+}
+
+#RX0.RXPACKS#0.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B00102011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b001, def_bus_id0;
+}
+
+#RX0.RXPACKS#0.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B00202011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b010, def_bus_id0;
+}
+
+#RX0.RXPACKS#0.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B00302011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b011, def_bus_id0;
+}
+
+#RX0.RXPACKS#1.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B00402011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b100, def_bus_id0;
+}
+
+#RX0.RXPACKS#1.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B00502011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b101, def_bus_id0;
+}
+
+#RX0.RXPACKS#1.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B00602011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b110, def_bus_id0;
+}
+
+#RX0.RXPACKS#1.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B00702011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b111, def_bus_id0;
+}
+
+#RX0.RXPACKS#2.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B01402011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b011, def_bus_id0;
+}
+
+#RX0.RXPACKS#2.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B01502011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b010, def_bus_id0;
+}
+
+#RX0.RXPACKS#2.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B01602011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b001, def_bus_id0;
+}
+
+#RX0.RXPACKS#2.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B01702011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b000, def_bus_id0;
+}
+
+#RX0.RXPACKS#3.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B01002011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b111, def_bus_id0;
+}
+
+#RX0.RXPACKS#3.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B01102011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b110, def_bus_id0;
+}
+
+#RX0.RXPACKS#3.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B01202011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b101, def_bus_id0;
+}
+
+#RX0.RXPACKS#3.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B01302011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b100, def_bus_id0;
+}
+
+#RX0.RXPACKS#4.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B00E02011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b001, def_bus_id0;
+}
+
+#RX0.RXPACKS#4.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B00F02011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b000, def_bus_id0;
+}
+
+#RX0.RXPACKS#4.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B00C02011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b011, def_bus_id0;
+}
+
+#RX0.RXPACKS#4.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B00D02011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b010, def_bus_id0;
+}
+
+#RX0.RXPACKS#5.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B00A02011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b010, def_bus_id0;
+}
+
+#RX0.RXPACKS#5.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B00B02011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b011, def_bus_id0;
+}
+
+#RX0.RXPACKS#5.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B00802011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b000, def_bus_id0;
+}
+
+#RX0.RXPACKS#5.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B00902011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b001, def_bus_id0;
+}
+
+#RX1.RXCTL.RX_CTL_REGS.RX_DFE_CONFIG_PP
+scom 0x800B782002011E3F { 
+	bits, scom_data, expr;
+     rx_amin_cfg,  0b010,   HW_EXPRESS && def_bus_id1;
+     rx_amin_cfg,  0b000,  VBU_EXPRESS && def_bus_id1;
+     rx_anap_cfg,  0b10,   HW_EXPRESS && def_bus_id1;
+     rx_anap_cfg,  0b00,  VBU_EXPRESS && def_bus_id1;
+     rx_h1ap_cfg,  0b011,   HW_EXPRESS && def_bus_id1;
+     rx_h1ap_cfg,  0b000,  VBU_EXPRESS && def_bus_id1;
+     rx_peak_cfg,  0b10,   HW_EXPRESS && def_bus_id1;
+     rx_peak_cfg,  0b00,  VBU_EXPRESS && def_bus_id1;
+}
+
+#RX1.RXCTL.RX_CTL_REGS.RX_DFE_TIMERS_PP
+scom 0x800B802002011E3F { 
+	bits, scom_data, expr;
+     rx_init_tmr_cfg,  0b100,   HW_EXPRESS && def_bus_id1;
+     rx_init_tmr_cfg,  0b000,  VBU_EXPRESS && def_bus_id1;
+}
+
+#RX1.RXCTL.RX_CTL_REGS.RX_DYN_RECAL_CONFIG_PG
+scom 0x800A182002011E3F { 
+	bits, scom_data, expr;
+	rx_dyn_recal_overall_timeout_sel, 0b001, def_bus_id1;
+}
+
+#RX1.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING1_PG
+scom 0x8009D82002011E3F { 
+	bits, scom_data, expr;
+	rx_dyn_rpr_bad_lane_max, 0b0001111, def_bus_id1;
+	rx_dyn_rpr_enc_bad_data_lane_width, 0b101, def_bus_id1;
+	rx_dyn_rpr_err_cntr1_duration, 0b0111, def_bus_id1;
+}
+
+#RX1.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING2_PG
+scom 0x800AE02002011E3F { 
+	bits, scom_data, expr;
+	rx_dyn_rpr_bad_bus_max, 0b0111111, def_bus_id1;
+	rx_dyn_rpr_err_cntr2_duration, 0b0111, def_bus_id1;
+}
+
+#RX1.RXCTL.RX_CTL_REGS.RX_EO_STEP_CNTL_PG
+scom 0x800A382002011E3F { 
+	bits, scom_data, expr;
+     rx_eo_enable_ber_test,  0b1,   HW_EXPRESS && def_bus_id1;
+     rx_eo_enable_ber_test,  0b0,  VBU_EXPRESS && def_bus_id1;
+     rx_eo_enable_ctle_cal,  0b1,   HW_EXPRESS && def_bus_id1;
+     rx_eo_enable_ctle_cal,  0b0,  VBU_EXPRESS && def_bus_id1;
+     rx_eo_enable_ddc,  0b1,   HW_EXPRESS && def_bus_id1;
+     rx_eo_enable_ddc,  0b0,  VBU_EXPRESS && def_bus_id1;
+     rx_eo_enable_dfe_h1_cal,  0b1,   HW_EXPRESS && def_bus_id1;
+     rx_eo_enable_dfe_h1_cal,  0b0,  VBU_EXPRESS && def_bus_id1;
+	rx_eo_enable_final_l2u_adj, 0b1, def_bus_id1;
+     rx_eo_enable_h1ap_tweak,  0b1,   HW_EXPRESS && def_bus_id1;
+     rx_eo_enable_h1ap_tweak,  0b0,  VBU_EXPRESS && def_bus_id1;
+     rx_eo_enable_latch_offset_cal,  0b1,   HW_EXPRESS && def_bus_id1;
+     rx_eo_enable_latch_offset_cal,  0b0,  VBU_EXPRESS && def_bus_id1;
+     rx_eo_enable_result_check,  0b1,   HW_EXPRESS && def_bus_id1;
+     rx_eo_enable_result_check,  0b0,  VBU_EXPRESS && def_bus_id1;
+     rx_eo_enable_vga_cal,  0b1,   HW_EXPRESS && def_bus_id1;
+     rx_eo_enable_vga_cal,  0b0,  VBU_EXPRESS && def_bus_id1;
+}
+
+#RX1.RXCTL.RX_CTL_REGS.RX_FENCE_PG
+scom 0x8009A82002011E3F { 
+	bits, scom_data, expr;
+	rx_fence, 0b1, def_bus_id1;
+}
+
+#RX1.RXCTL.RX_CTL_REGS.RX_ID1_PG
+scom 0x8008502002011E3F { 
+	bits, scom_data, expr;
+	rx_bus_id, 0b000001, def_bus_id1;
+	rx_group_id, 0b000000, def_bus_id1;
+}
+
+#RX1.RXCTL.RX_CTL_REGS.RX_ID2_PG
+scom 0x8008582002011E3F { 
+	bits, scom_data, expr;
+	rx_last_group_id, 0b000000, def_bus_id1;
+}
+
+#RX1.RXCTL.RX_CTL_REGS.RX_ID3_PG
+scom 0x8008602002011E3F { 
+	bits, scom_data, expr;
+	rx_end_lane_id, 0b0010111, def_bus_id1;
+	rx_start_lane_id, 0b0000000, def_bus_id1;
+}
+
+#RX1.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_0_15_PG
+scom 0x8009282002011E3F { 
+	bits, scom_data, expr;
+	rx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id1;
+}
+
+#RX1.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_16_31_PG
+scom 0x8009302002011E3F { 
+	bits, scom_data, expr;
+	rx_lane_disabled_vec_16_31, 0b0000000011111111, def_bus_id1;
+}
+
+#RX1.RXCTL.RX_CTL_REGS.RX_MISC_ANALOG_PG
+scom 0x8009C02002011E3F { 
+	bits, scom_data, expr;
+     rx_c4_sel,  0b00,   HW_EXPRESS && def_bus_id1;
+     rx_c4_sel,  0b11,  VBU_EXPRESS && def_bus_id1;
+     rx_prot_speed_slct,  0b1,   HW_EXPRESS && def_bus_id1;
+     rx_prot_speed_slct,  0b0,  VBU_EXPRESS && def_bus_id1;
+}
+
+#RX1.RXCTL.RX_CTL_REGS.RX_MODE_PG
+scom 0x8008182002011E3F { 
+	bits, scom_data, expr;
+	rx_master_mode, 0b1, def_bus_id1;
+}
+
+#RX1.RXCTL.RX_CTL_REGS.RX_RC_STEP_CNTL_PG
+scom 0x800AB82002011E3F { 
+	bits, scom_data, expr;
+     rx_rc_enable_ber_test,  0b1,   HW_EXPRESS && def_bus_id1;
+     rx_rc_enable_ber_test,  0b0,  VBU_EXPRESS && def_bus_id1;
+     rx_rc_enable_ctle_cal,  0b1,   HW_EXPRESS && def_bus_id1;
+     rx_rc_enable_ctle_cal,  0b0,  VBU_EXPRESS && def_bus_id1;
+     rx_rc_enable_ddc,  0b1,   HW_EXPRESS && def_bus_id1;
+     rx_rc_enable_ddc,  0b0,  VBU_EXPRESS && def_bus_id1;
+     rx_rc_enable_dfe_h1_cal,  0b1,   HW_EXPRESS && def_bus_id1;
+     rx_rc_enable_dfe_h1_cal,  0b0,  VBU_EXPRESS && def_bus_id1;
+     rx_rc_enable_h1ap_tweak,  0b1,   HW_EXPRESS && def_bus_id1;
+     rx_rc_enable_h1ap_tweak,  0b0,  VBU_EXPRESS && def_bus_id1;
+     rx_rc_enable_latch_offset_cal,  0b1,   HW_EXPRESS && def_bus_id1;
+     rx_rc_enable_latch_offset_cal,  0b0,  VBU_EXPRESS && def_bus_id1;
+     rx_rc_enable_result_check,  0b1,   HW_EXPRESS && def_bus_id1;
+     rx_rc_enable_result_check,  0b0,  VBU_EXPRESS && def_bus_id1;
+     rx_rc_enable_vga_cal,  0b1,   HW_EXPRESS && def_bus_id1;
+     rx_rc_enable_vga_cal,  0b0,  VBU_EXPRESS && def_bus_id1;
+}
+
+#RX1.RXCTL.RX_CTL_REGS.RX_RECAL_TO2_PP
+scom 0x800B982002011E3F { 
+	bits, scom_data, expr;
+     rx_recal_timeout_sel_g,  0b0111,   HW_EXPRESS && def_bus_id1;
+     rx_recal_timeout_sel_g,  0b0110,  VBU_EXPRESS && def_bus_id1;
+     rx_recal_timeout_sel_h,  0b0110,   HW_EXPRESS && def_bus_id1;
+     rx_recal_timeout_sel_h,  0b1000,  VBU_EXPRESS && def_bus_id1;
+}
+
+#RX1.RXCTL.RX_CTL_REGS.RX_RECAL_TO3_PP
+scom 0x800BA02002011E3F { 
+	bits, scom_data, expr;
+     rx_recal_timeout_sel_i,  0b0111,   HW_EXPRESS && def_bus_id1;
+     rx_recal_timeout_sel_i,  0b1000,  VBU_EXPRESS && def_bus_id1;
+     rx_recal_timeout_sel_l,  0b0100,   HW_EXPRESS && def_bus_id1;
+     rx_recal_timeout_sel_l,  0b0110,  VBU_EXPRESS && def_bus_id1;
+}
+
+#RX1.RXCTL.RX_CTL_REGS.RX_SERVO_TO1_PP
+scom 0x800B602002011E3F { 
+	bits, scom_data, expr;
+     rx_servo_timeout_sel_d,  0b1010,   HW_EXPRESS && def_bus_id1;
+     rx_servo_timeout_sel_d,  0b1000,  VBU_EXPRESS && def_bus_id1;
+}
+
+#RX1.RXCTL.RX_CTL_REGS.RX_SERVO_TO2_PP
+scom 0x800B682002011E3F { 
+	bits, scom_data, expr;
+     rx_servo_timeout_sel_f,  0b0001,   HW_EXPRESS && def_bus_id1;
+     rx_servo_timeout_sel_f,  0b0110,  VBU_EXPRESS && def_bus_id1;
+     rx_servo_timeout_sel_g,  0b0111,   HW_EXPRESS && def_bus_id1;
+     rx_servo_timeout_sel_g,  0b0100,  VBU_EXPRESS && def_bus_id1;
+}
+
+#RX1.RXCTL.RX_CTL_REGS.RX_SERVO_TO3_PP
+scom 0x800B702002011E3F { 
+	bits, scom_data, expr;
+     rx_servo_timeout_sel_i,  0b0111,   HW_EXPRESS && def_bus_id1;
+     rx_servo_timeout_sel_i,  0b1000,  VBU_EXPRESS && def_bus_id1;
+     rx_servo_timeout_sel_k,  0b0111,   HW_EXPRESS && def_bus_id1;
+     rx_servo_timeout_sel_k,  0b1000,  VBU_EXPRESS && def_bus_id1;
+}
+
+#RX1.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL_PG
+scom 0x8008982002011E3F { 
+	bits, scom_data, expr;
+	rx_sls_timeout_sel, 0b001, def_bus_id1;
+}
+
+#RX1.RXCTL.RX_CTL_REGS.RX_TX_BUS_INFO_PG
+scom 0x8009982002011E3F { 
+	bits, scom_data, expr;
+	rx_rx_bus_width, 0b0011000, def_bus_id1;
+	rx_tx_bus_width, 0b0010001, def_bus_id1;
+}
+
+#RX1.RXCTL.RX_CTL_REGS.RX_WIRETEST_LANEINFO_PG
+scom 0x8009582002011E3F { 
+	bits, scom_data, expr;
+	rx_wtr_max_bad_lanes, 0b00010, def_bus_id1;
+}
+
+#RX1.RXCTL.RX_CTL_REGS.RX_WIRETEST_PLL_CNTL_PG
+scom 0x800A302002011E3F { 
+	bits, scom_data, expr;
+     rx_wt_cu_pll_pgooddly,  0b001,   HW_EXPRESS && def_bus_id1;
+     rx_wt_cu_pll_pgooddly,  0b000,  VBU_EXPRESS && def_bus_id1;
+     rx_wt_cu_pll_reset,  0b0,   HW_EXPRESS && def_bus_id1;
+     rx_wt_cu_pll_reset,  0b1,  VBU_EXPRESS && def_bus_id1;
+}
+
+#RX1.RXPACKS#0.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B02002011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b000, def_bus_id1;
+}
+
+#RX1.RXPACKS#0.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B02102011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b001, def_bus_id1;
+}
+
+#RX1.RXPACKS#0.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B02202011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b010, def_bus_id1;
+}
+
+#RX1.RXPACKS#0.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B02302011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b011, def_bus_id1;
+}
+
+#RX1.RXPACKS#1.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B02402011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b100, def_bus_id1;
+}
+
+#RX1.RXPACKS#1.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B02502011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b101, def_bus_id1;
+}
+
+#RX1.RXPACKS#1.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B02602011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b110, def_bus_id1;
+}
+
+#RX1.RXPACKS#1.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B02702011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b111, def_bus_id1;
+}
+
+#RX1.RXPACKS#2.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B03402011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b011, def_bus_id1;
+}
+
+#RX1.RXPACKS#2.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B03502011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b010, def_bus_id1;
+}
+
+#RX1.RXPACKS#2.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B03602011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b001, def_bus_id1;
+}
+
+#RX1.RXPACKS#2.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B03702011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b000, def_bus_id1;
+}
+
+#RX1.RXPACKS#3.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B03002011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b111, def_bus_id1;
+}
+
+#RX1.RXPACKS#3.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B03102011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b110, def_bus_id1;
+}
+
+#RX1.RXPACKS#3.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B03202011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b101, def_bus_id1;
+}
+
+#RX1.RXPACKS#3.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B03302011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b100, def_bus_id1;
+}
+
+#RX1.RXPACKS#4.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B02E02011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b001, def_bus_id1;
+}
+
+#RX1.RXPACKS#4.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B02F02011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b000, def_bus_id1;
+}
+
+#RX1.RXPACKS#4.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B02C02011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b011, def_bus_id1;
+}
+
+#RX1.RXPACKS#4.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B02D02011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b010, def_bus_id1;
+}
+
+#RX1.RXPACKS#5.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B02A02011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b010, def_bus_id1;
+}
+
+#RX1.RXPACKS#5.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B02B02011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b011, def_bus_id1;
+}
+
+#RX1.RXPACKS#5.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B02802011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b000, def_bus_id1;
+}
+
+#RX1.RXPACKS#5.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B02902011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b001, def_bus_id1;
+}
+
+#RX2.RXCTL.RX_CTL_REGS.RX_DFE_CONFIG_PP
+scom 0x800B784002011E3F { 
+	bits, scom_data, expr;
+     rx_amin_cfg,  0b010,   HW_EXPRESS && def_bus_id2;
+     rx_amin_cfg,  0b000,  VBU_EXPRESS && def_bus_id2;
+     rx_anap_cfg,  0b10,   HW_EXPRESS && def_bus_id2;
+     rx_anap_cfg,  0b00,  VBU_EXPRESS && def_bus_id2;
+     rx_h1ap_cfg,  0b011,   HW_EXPRESS && def_bus_id2;
+     rx_h1ap_cfg,  0b000,  VBU_EXPRESS && def_bus_id2;
+     rx_peak_cfg,  0b10,   HW_EXPRESS && def_bus_id2;
+     rx_peak_cfg,  0b00,  VBU_EXPRESS && def_bus_id2;
+}
+
+#RX2.RXCTL.RX_CTL_REGS.RX_DFE_TIMERS_PP
+scom 0x800B804002011E3F { 
+	bits, scom_data, expr;
+     rx_init_tmr_cfg,  0b100,   HW_EXPRESS && def_bus_id2;
+     rx_init_tmr_cfg,  0b000,  VBU_EXPRESS && def_bus_id2;
+}
+
+#RX2.RXCTL.RX_CTL_REGS.RX_DYN_RECAL_CONFIG_PG
+scom 0x800A184002011E3F { 
+	bits, scom_data, expr;
+	rx_dyn_recal_overall_timeout_sel, 0b001, def_bus_id2;
+}
+
+#RX2.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING1_PG
+scom 0x8009D84002011E3F { 
+	bits, scom_data, expr;
+	rx_dyn_rpr_bad_lane_max, 0b0001111, def_bus_id2;
+	rx_dyn_rpr_enc_bad_data_lane_width, 0b101, def_bus_id2;
+	rx_dyn_rpr_err_cntr1_duration, 0b0111, def_bus_id2;
+}
+
+#RX2.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING2_PG
+scom 0x800AE04002011E3F { 
+	bits, scom_data, expr;
+	rx_dyn_rpr_bad_bus_max, 0b0111111, def_bus_id2;
+	rx_dyn_rpr_err_cntr2_duration, 0b0111, def_bus_id2;
+}
+
+#RX2.RXCTL.RX_CTL_REGS.RX_EO_STEP_CNTL_PG
+scom 0x800A384002011E3F { 
+	bits, scom_data, expr;
+     rx_eo_enable_ber_test,  0b1,   HW_EXPRESS && def_bus_id2;
+     rx_eo_enable_ber_test,  0b0,  VBU_EXPRESS && def_bus_id2;
+     rx_eo_enable_ctle_cal,  0b1,   HW_EXPRESS && def_bus_id2;
+     rx_eo_enable_ctle_cal,  0b0,  VBU_EXPRESS && def_bus_id2;
+     rx_eo_enable_ddc,  0b1,   HW_EXPRESS && def_bus_id2;
+     rx_eo_enable_ddc,  0b0,  VBU_EXPRESS && def_bus_id2;
+     rx_eo_enable_dfe_h1_cal,  0b1,   HW_EXPRESS && def_bus_id2;
+     rx_eo_enable_dfe_h1_cal,  0b0,  VBU_EXPRESS && def_bus_id2;
+	rx_eo_enable_final_l2u_adj, 0b1, def_bus_id2;
+     rx_eo_enable_h1ap_tweak,  0b1,   HW_EXPRESS && def_bus_id2;
+     rx_eo_enable_h1ap_tweak,  0b0,  VBU_EXPRESS && def_bus_id2;
+     rx_eo_enable_latch_offset_cal,  0b1,   HW_EXPRESS && def_bus_id2;
+     rx_eo_enable_latch_offset_cal,  0b0,  VBU_EXPRESS && def_bus_id2;
+     rx_eo_enable_result_check,  0b1,   HW_EXPRESS && def_bus_id2;
+     rx_eo_enable_result_check,  0b0,  VBU_EXPRESS && def_bus_id2;
+     rx_eo_enable_vga_cal,  0b1,   HW_EXPRESS && def_bus_id2;
+     rx_eo_enable_vga_cal,  0b0,  VBU_EXPRESS && def_bus_id2;
+}
+
+#RX2.RXCTL.RX_CTL_REGS.RX_FENCE_PG
+scom 0x8009A84002011E3F { 
+	bits, scom_data, expr;
+	rx_fence, 0b1, def_bus_id2;
+}
+
+#RX2.RXCTL.RX_CTL_REGS.RX_ID1_PG
+scom 0x8008504002011E3F { 
+	bits, scom_data, expr;
+	rx_bus_id, 0b000010, def_bus_id2;
+	rx_group_id, 0b000000, def_bus_id2;
+}
+
+#RX2.RXCTL.RX_CTL_REGS.RX_ID2_PG
+scom 0x8008584002011E3F { 
+	bits, scom_data, expr;
+	rx_last_group_id, 0b000000, def_bus_id2;
+}
+
+#RX2.RXCTL.RX_CTL_REGS.RX_ID3_PG
+scom 0x8008604002011E3F { 
+	bits, scom_data, expr;
+	rx_end_lane_id, 0b0010111, def_bus_id2;
+	rx_start_lane_id, 0b0000000, def_bus_id2;
+}
+
+#RX2.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_0_15_PG
+scom 0x8009284002011E3F { 
+	bits, scom_data, expr;
+	rx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id2;
+}
+
+#RX2.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_16_31_PG
+scom 0x8009304002011E3F { 
+	bits, scom_data, expr;
+	rx_lane_disabled_vec_16_31, 0b0000000011111111, def_bus_id2;
+}
+
+#RX2.RXCTL.RX_CTL_REGS.RX_MISC_ANALOG_PG
+scom 0x8009C04002011E3F { 
+	bits, scom_data, expr;
+     rx_c4_sel,  0b00,   HW_EXPRESS && def_bus_id2;
+     rx_c4_sel,  0b11,  VBU_EXPRESS && def_bus_id2;
+     rx_prot_speed_slct,  0b1,   HW_EXPRESS && def_bus_id2;
+     rx_prot_speed_slct,  0b0,  VBU_EXPRESS && def_bus_id2;
+}
+
+#RX2.RXCTL.RX_CTL_REGS.RX_MODE_PG
+scom 0x8008184002011E3F { 
+	bits, scom_data, expr;
+	rx_master_mode, 0b1, def_bus_id2;
+}
+
+#RX2.RXCTL.RX_CTL_REGS.RX_RC_STEP_CNTL_PG
+scom 0x800AB84002011E3F { 
+	bits, scom_data, expr;
+     rx_rc_enable_ber_test,  0b1,   HW_EXPRESS && def_bus_id2;
+     rx_rc_enable_ber_test,  0b0,  VBU_EXPRESS && def_bus_id2;
+     rx_rc_enable_ctle_cal,  0b1,   HW_EXPRESS && def_bus_id2;
+     rx_rc_enable_ctle_cal,  0b0,  VBU_EXPRESS && def_bus_id2;
+     rx_rc_enable_ddc,  0b1,   HW_EXPRESS && def_bus_id2;
+     rx_rc_enable_ddc,  0b0,  VBU_EXPRESS && def_bus_id2;
+     rx_rc_enable_dfe_h1_cal,  0b1,   HW_EXPRESS && def_bus_id2;
+     rx_rc_enable_dfe_h1_cal,  0b0,  VBU_EXPRESS && def_bus_id2;
+     rx_rc_enable_h1ap_tweak,  0b1,   HW_EXPRESS && def_bus_id2;
+     rx_rc_enable_h1ap_tweak,  0b0,  VBU_EXPRESS && def_bus_id2;
+     rx_rc_enable_latch_offset_cal,  0b1,   HW_EXPRESS && def_bus_id2;
+     rx_rc_enable_latch_offset_cal,  0b0,  VBU_EXPRESS && def_bus_id2;
+     rx_rc_enable_result_check,  0b1,   HW_EXPRESS && def_bus_id2;
+     rx_rc_enable_result_check,  0b0,  VBU_EXPRESS && def_bus_id2;
+     rx_rc_enable_vga_cal,  0b1,   HW_EXPRESS && def_bus_id2;
+     rx_rc_enable_vga_cal,  0b0,  VBU_EXPRESS && def_bus_id2;
+}
+
+#RX2.RXCTL.RX_CTL_REGS.RX_RECAL_TO2_PP
+scom 0x800B984002011E3F { 
+	bits, scom_data, expr;
+     rx_recal_timeout_sel_g,  0b0111,   HW_EXPRESS && def_bus_id2;
+     rx_recal_timeout_sel_g,  0b0110,  VBU_EXPRESS && def_bus_id2;
+     rx_recal_timeout_sel_h,  0b0110,   HW_EXPRESS && def_bus_id2;
+     rx_recal_timeout_sel_h,  0b1000,  VBU_EXPRESS && def_bus_id2;
+}
+
+#RX2.RXCTL.RX_CTL_REGS.RX_RECAL_TO3_PP
+scom 0x800BA04002011E3F { 
+	bits, scom_data, expr;
+     rx_recal_timeout_sel_i,  0b0111,   HW_EXPRESS && def_bus_id2;
+     rx_recal_timeout_sel_i,  0b1000,  VBU_EXPRESS && def_bus_id2;
+     rx_recal_timeout_sel_l,  0b0100,   HW_EXPRESS && def_bus_id2;
+     rx_recal_timeout_sel_l,  0b0110,  VBU_EXPRESS && def_bus_id2;
+}
+
+#RX2.RXCTL.RX_CTL_REGS.RX_SERVO_TO1_PP
+scom 0x800B604002011E3F { 
+	bits, scom_data, expr;
+     rx_servo_timeout_sel_d,  0b1010,   HW_EXPRESS && def_bus_id2;
+     rx_servo_timeout_sel_d,  0b1000,  VBU_EXPRESS && def_bus_id2;
+}
+
+#RX2.RXCTL.RX_CTL_REGS.RX_SERVO_TO2_PP
+scom 0x800B684002011E3F { 
+	bits, scom_data, expr;
+     rx_servo_timeout_sel_f,  0b0001,   HW_EXPRESS && def_bus_id2;
+     rx_servo_timeout_sel_f,  0b0110,  VBU_EXPRESS && def_bus_id2;
+     rx_servo_timeout_sel_g,  0b0111,   HW_EXPRESS && def_bus_id2;
+     rx_servo_timeout_sel_g,  0b0100,  VBU_EXPRESS && def_bus_id2;
+}
+
+#RX2.RXCTL.RX_CTL_REGS.RX_SERVO_TO3_PP
+scom 0x800B704002011E3F { 
+	bits, scom_data, expr;
+     rx_servo_timeout_sel_i,  0b0111,   HW_EXPRESS && def_bus_id2;
+     rx_servo_timeout_sel_i,  0b1000,  VBU_EXPRESS && def_bus_id2;
+     rx_servo_timeout_sel_k,  0b0111,   HW_EXPRESS && def_bus_id2;
+     rx_servo_timeout_sel_k,  0b1000,  VBU_EXPRESS && def_bus_id2;
+}
+
+#RX2.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL_PG
+scom 0x8008984002011E3F { 
+	bits, scom_data, expr;
+	rx_sls_timeout_sel, 0b001, def_bus_id2;
+}
+
+#RX2.RXCTL.RX_CTL_REGS.RX_TX_BUS_INFO_PG
+scom 0x8009984002011E3F { 
+	bits, scom_data, expr;
+	rx_rx_bus_width, 0b0011000, def_bus_id2;
+	rx_tx_bus_width, 0b0010001, def_bus_id2;
+}
+
+#RX2.RXCTL.RX_CTL_REGS.RX_WIRETEST_LANEINFO_PG
+scom 0x8009584002011E3F { 
+	bits, scom_data, expr;
+	rx_wtr_max_bad_lanes, 0b00010, def_bus_id2;
+}
+
+#RX2.RXCTL.RX_CTL_REGS.RX_WIRETEST_PLL_CNTL_PG
+scom 0x800A304002011E3F { 
+	bits, scom_data, expr;
+     rx_wt_cu_pll_pgooddly,  0b001,   HW_EXPRESS && def_bus_id2;
+     rx_wt_cu_pll_pgooddly,  0b000,  VBU_EXPRESS && def_bus_id2;
+     rx_wt_cu_pll_reset,  0b0,   HW_EXPRESS && def_bus_id2;
+     rx_wt_cu_pll_reset,  0b1,  VBU_EXPRESS && def_bus_id2;
+}
+
+#RX2.RXPACKS#0.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B04002011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b000, def_bus_id2;
+}
+
+#RX2.RXPACKS#0.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B04102011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b001, def_bus_id2;
+}
+
+#RX2.RXPACKS#0.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B04202011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b010, def_bus_id2;
+}
+
+#RX2.RXPACKS#0.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B04302011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b011, def_bus_id2;
+}
+
+#RX2.RXPACKS#1.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B04402011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b100, def_bus_id2;
+}
+
+#RX2.RXPACKS#1.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B04502011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b101, def_bus_id2;
+}
+
+#RX2.RXPACKS#1.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B04602011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b110, def_bus_id2;
+}
+
+#RX2.RXPACKS#1.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B04702011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b111, def_bus_id2;
+}
+
+#RX2.RXPACKS#2.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B05402011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b011, def_bus_id2;
+}
+
+#RX2.RXPACKS#2.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B05502011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b010, def_bus_id2;
+}
+
+#RX2.RXPACKS#2.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B05602011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b001, def_bus_id2;
+}
+
+#RX2.RXPACKS#2.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B05702011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b000, def_bus_id2;
+}
+
+#RX2.RXPACKS#3.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B05002011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b111, def_bus_id2;
+}
+
+#RX2.RXPACKS#3.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B05102011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b110, def_bus_id2;
+}
+
+#RX2.RXPACKS#3.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B05202011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b101, def_bus_id2;
+}
+
+#RX2.RXPACKS#3.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B05302011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b100, def_bus_id2;
+}
+
+#RX2.RXPACKS#4.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B04E02011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b001, def_bus_id2;
+}
+
+#RX2.RXPACKS#4.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B04F02011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b000, def_bus_id2;
+}
+
+#RX2.RXPACKS#4.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B04C02011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b011, def_bus_id2;
+}
+
+#RX2.RXPACKS#4.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B04D02011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b010, def_bus_id2;
+}
+
+#RX2.RXPACKS#5.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B04A02011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b010, def_bus_id2;
+}
+
+#RX2.RXPACKS#5.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B04B02011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b011, def_bus_id2;
+}
+
+#RX2.RXPACKS#5.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B04802011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b000, def_bus_id2;
+}
+
+#RX2.RXPACKS#5.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B04902011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b001, def_bus_id2;
+}
+
+#RX3.RXCTL.RX_CTL_REGS.RX_DFE_CONFIG_PP
+scom 0x800B786002011E3F { 
+	bits, scom_data, expr;
+     rx_amin_cfg,  0b010,   HW_EXPRESS && def_bus_id3;
+     rx_amin_cfg,  0b000,  VBU_EXPRESS && def_bus_id3;
+     rx_anap_cfg,  0b10,   HW_EXPRESS && def_bus_id3;
+     rx_anap_cfg,  0b00,  VBU_EXPRESS && def_bus_id3;
+     rx_h1ap_cfg,  0b011,   HW_EXPRESS && def_bus_id3;
+     rx_h1ap_cfg,  0b000,  VBU_EXPRESS && def_bus_id3;
+     rx_peak_cfg,  0b10,   HW_EXPRESS && def_bus_id3;
+     rx_peak_cfg,  0b00,  VBU_EXPRESS && def_bus_id3;
+}
+
+#RX3.RXCTL.RX_CTL_REGS.RX_DFE_TIMERS_PP
+scom 0x800B806002011E3F { 
+	bits, scom_data, expr;
+     rx_init_tmr_cfg,  0b100,   HW_EXPRESS && def_bus_id3;
+     rx_init_tmr_cfg,  0b000,  VBU_EXPRESS && def_bus_id3;
+}
+
+#RX3.RXCTL.RX_CTL_REGS.RX_DYN_RECAL_CONFIG_PG
+scom 0x800A186002011E3F { 
+	bits, scom_data, expr;
+	rx_dyn_recal_overall_timeout_sel, 0b001, def_bus_id3;
+}
+
+#RX3.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING1_PG
+scom 0x8009D86002011E3F { 
+	bits, scom_data, expr;
+	rx_dyn_rpr_bad_lane_max, 0b0001111, def_bus_id3;
+	rx_dyn_rpr_enc_bad_data_lane_width, 0b101, def_bus_id3;
+	rx_dyn_rpr_err_cntr1_duration, 0b0111, def_bus_id3;
+}
+
+#RX3.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING2_PG
+scom 0x800AE06002011E3F { 
+	bits, scom_data, expr;
+	rx_dyn_rpr_bad_bus_max, 0b0111111, def_bus_id3;
+	rx_dyn_rpr_err_cntr2_duration, 0b0111, def_bus_id3;
+}
+
+#RX3.RXCTL.RX_CTL_REGS.RX_EO_STEP_CNTL_PG
+scom 0x800A386002011E3F { 
+	bits, scom_data, expr;
+     rx_eo_enable_ber_test,  0b1,   HW_EXPRESS && def_bus_id3;
+     rx_eo_enable_ber_test,  0b0,  VBU_EXPRESS && def_bus_id3;
+     rx_eo_enable_ctle_cal,  0b1,   HW_EXPRESS && def_bus_id3;
+     rx_eo_enable_ctle_cal,  0b0,  VBU_EXPRESS && def_bus_id3;
+     rx_eo_enable_ddc,  0b1,   HW_EXPRESS && def_bus_id3;
+     rx_eo_enable_ddc,  0b0,  VBU_EXPRESS && def_bus_id3;
+     rx_eo_enable_dfe_h1_cal,  0b1,   HW_EXPRESS && def_bus_id3;
+     rx_eo_enable_dfe_h1_cal,  0b0,  VBU_EXPRESS && def_bus_id3;
+	rx_eo_enable_final_l2u_adj, 0b1, def_bus_id3;
+     rx_eo_enable_h1ap_tweak,  0b1,   HW_EXPRESS && def_bus_id3;
+     rx_eo_enable_h1ap_tweak,  0b0,  VBU_EXPRESS && def_bus_id3;
+     rx_eo_enable_latch_offset_cal,  0b1,   HW_EXPRESS && def_bus_id3;
+     rx_eo_enable_latch_offset_cal,  0b0,  VBU_EXPRESS && def_bus_id3;
+     rx_eo_enable_result_check,  0b1,   HW_EXPRESS && def_bus_id3;
+     rx_eo_enable_result_check,  0b0,  VBU_EXPRESS && def_bus_id3;
+     rx_eo_enable_vga_cal,  0b1,   HW_EXPRESS && def_bus_id3;
+     rx_eo_enable_vga_cal,  0b0,  VBU_EXPRESS && def_bus_id3;
+}
+
+#RX3.RXCTL.RX_CTL_REGS.RX_FENCE_PG
+scom 0x8009A86002011E3F { 
+	bits, scom_data, expr;
+	rx_fence, 0b1, def_bus_id3;
+}
+
+#RX3.RXCTL.RX_CTL_REGS.RX_ID1_PG
+scom 0x8008506002011E3F { 
+	bits, scom_data, expr;
+	rx_bus_id, 0b000011, def_bus_id3;
+	rx_group_id, 0b000000, def_bus_id3;
+}
+
+#RX3.RXCTL.RX_CTL_REGS.RX_ID2_PG
+scom 0x8008586002011E3F { 
+	bits, scom_data, expr;
+	rx_last_group_id, 0b000000, def_bus_id3;
+}
+
+#RX3.RXCTL.RX_CTL_REGS.RX_ID3_PG
+scom 0x8008606002011E3F { 
+	bits, scom_data, expr;
+	rx_end_lane_id, 0b0010111, def_bus_id3;
+	rx_start_lane_id, 0b0000000, def_bus_id3;
+}
+
+#RX3.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_0_15_PG
+scom 0x8009286002011E3F { 
+	bits, scom_data, expr;
+	rx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id3;
+}
+
+#RX3.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_16_31_PG
+scom 0x8009306002011E3F { 
+	bits, scom_data, expr;
+	rx_lane_disabled_vec_16_31, 0b0000000011111111, def_bus_id3;
+}
+
+#RX3.RXCTL.RX_CTL_REGS.RX_MISC_ANALOG_PG
+scom 0x8009C06002011E3F { 
+	bits, scom_data, expr;
+     rx_c4_sel,  0b00,   HW_EXPRESS && def_bus_id3;
+     rx_c4_sel,  0b11,  VBU_EXPRESS && def_bus_id3;
+     rx_prot_speed_slct,  0b1,   HW_EXPRESS && def_bus_id3;
+     rx_prot_speed_slct,  0b0,  VBU_EXPRESS && def_bus_id3;
+}
+
+#RX3.RXCTL.RX_CTL_REGS.RX_MODE_PG
+scom 0x8008186002011E3F { 
+	bits, scom_data, expr;
+	rx_master_mode, 0b1, def_bus_id3;
+}
+
+#RX3.RXCTL.RX_CTL_REGS.RX_RC_STEP_CNTL_PG
+scom 0x800AB86002011E3F { 
+	bits, scom_data, expr;
+     rx_rc_enable_ber_test,  0b1,   HW_EXPRESS && def_bus_id3;
+     rx_rc_enable_ber_test,  0b0,  VBU_EXPRESS && def_bus_id3;
+     rx_rc_enable_ctle_cal,  0b1,   HW_EXPRESS && def_bus_id3;
+     rx_rc_enable_ctle_cal,  0b0,  VBU_EXPRESS && def_bus_id3;
+     rx_rc_enable_ddc,  0b1,   HW_EXPRESS && def_bus_id3;
+     rx_rc_enable_ddc,  0b0,  VBU_EXPRESS && def_bus_id3;
+     rx_rc_enable_dfe_h1_cal,  0b1,   HW_EXPRESS && def_bus_id3;
+     rx_rc_enable_dfe_h1_cal,  0b0,  VBU_EXPRESS && def_bus_id3;
+     rx_rc_enable_h1ap_tweak,  0b1,   HW_EXPRESS && def_bus_id3;
+     rx_rc_enable_h1ap_tweak,  0b0,  VBU_EXPRESS && def_bus_id3;
+     rx_rc_enable_latch_offset_cal,  0b1,   HW_EXPRESS && def_bus_id3;
+     rx_rc_enable_latch_offset_cal,  0b0,  VBU_EXPRESS && def_bus_id3;
+     rx_rc_enable_result_check,  0b1,   HW_EXPRESS && def_bus_id3;
+     rx_rc_enable_result_check,  0b0,  VBU_EXPRESS && def_bus_id3;
+     rx_rc_enable_vga_cal,  0b1,   HW_EXPRESS && def_bus_id3;
+     rx_rc_enable_vga_cal,  0b0,  VBU_EXPRESS && def_bus_id3;
+}
+
+#RX3.RXCTL.RX_CTL_REGS.RX_RECAL_TO2_PP
+scom 0x800B986002011E3F { 
+	bits, scom_data, expr;
+     rx_recal_timeout_sel_g,  0b0111,   HW_EXPRESS && def_bus_id3;
+     rx_recal_timeout_sel_g,  0b0110,  VBU_EXPRESS && def_bus_id3;
+     rx_recal_timeout_sel_h,  0b0110,   HW_EXPRESS && def_bus_id3;
+     rx_recal_timeout_sel_h,  0b1000,  VBU_EXPRESS && def_bus_id3;
+}
+
+#RX3.RXCTL.RX_CTL_REGS.RX_RECAL_TO3_PP
+scom 0x800BA06002011E3F { 
+	bits, scom_data, expr;
+     rx_recal_timeout_sel_i,  0b0111,   HW_EXPRESS && def_bus_id3;
+     rx_recal_timeout_sel_i,  0b1000,  VBU_EXPRESS && def_bus_id3;
+     rx_recal_timeout_sel_l,  0b0100,   HW_EXPRESS && def_bus_id3;
+     rx_recal_timeout_sel_l,  0b0110,  VBU_EXPRESS && def_bus_id3;
+}
+
+#RX3.RXCTL.RX_CTL_REGS.RX_SERVO_TO1_PP
+scom 0x800B606002011E3F { 
+	bits, scom_data, expr;
+     rx_servo_timeout_sel_d,  0b1010,   HW_EXPRESS && def_bus_id3;
+     rx_servo_timeout_sel_d,  0b1000,  VBU_EXPRESS && def_bus_id3;
+}
+
+#RX3.RXCTL.RX_CTL_REGS.RX_SERVO_TO2_PP
+scom 0x800B686002011E3F { 
+	bits, scom_data, expr;
+     rx_servo_timeout_sel_f,  0b0001,   HW_EXPRESS && def_bus_id3;
+     rx_servo_timeout_sel_f,  0b0110,  VBU_EXPRESS && def_bus_id3;
+     rx_servo_timeout_sel_g,  0b0111,   HW_EXPRESS && def_bus_id3;
+     rx_servo_timeout_sel_g,  0b0100,  VBU_EXPRESS && def_bus_id3;
+}
+
+#RX3.RXCTL.RX_CTL_REGS.RX_SERVO_TO3_PP
+scom 0x800B706002011E3F { 
+	bits, scom_data, expr;
+     rx_servo_timeout_sel_i,  0b0111,   HW_EXPRESS && def_bus_id3;
+     rx_servo_timeout_sel_i,  0b1000,  VBU_EXPRESS && def_bus_id3;
+     rx_servo_timeout_sel_k,  0b0111,   HW_EXPRESS && def_bus_id3;
+     rx_servo_timeout_sel_k,  0b1000,  VBU_EXPRESS && def_bus_id3;
+}
+
+#RX3.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL_PG
+scom 0x8008986002011E3F { 
+	bits, scom_data, expr;
+	rx_sls_timeout_sel, 0b001, def_bus_id3;
+}
+
+#RX3.RXCTL.RX_CTL_REGS.RX_TX_BUS_INFO_PG
+scom 0x8009986002011E3F { 
+	bits, scom_data, expr;
+	rx_rx_bus_width, 0b0011000, def_bus_id3;
+	rx_tx_bus_width, 0b0010001, def_bus_id3;
+}
+
+#RX3.RXCTL.RX_CTL_REGS.RX_WIRETEST_LANEINFO_PG
+scom 0x8009586002011E3F { 
+	bits, scom_data, expr;
+	rx_wtr_max_bad_lanes, 0b00010, def_bus_id3;
+}
+
+#RX3.RXCTL.RX_CTL_REGS.RX_WIRETEST_PLL_CNTL_PG
+scom 0x800A306002011E3F { 
+	bits, scom_data, expr;
+     rx_wt_cu_pll_pgooddly,  0b001,   HW_EXPRESS && def_bus_id3;
+     rx_wt_cu_pll_pgooddly,  0b000,  VBU_EXPRESS && def_bus_id3;
+     rx_wt_cu_pll_reset,  0b0,   HW_EXPRESS && def_bus_id3;
+     rx_wt_cu_pll_reset,  0b1,  VBU_EXPRESS && def_bus_id3;
+}
+
+#RX3.RXPACKS#0.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B06002011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b000, def_bus_id3;
+}
+
+#RX3.RXPACKS#0.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B06102011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b001, def_bus_id3;
+}
+
+#RX3.RXPACKS#0.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B06202011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b010, def_bus_id3;
+}
+
+#RX3.RXPACKS#0.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B06302011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b011, def_bus_id3;
+}
+
+#RX3.RXPACKS#1.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B06402011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b100, def_bus_id3;
+}
+
+#RX3.RXPACKS#1.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B06502011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b101, def_bus_id3;
+}
+
+#RX3.RXPACKS#1.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B06602011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b110, def_bus_id3;
+}
+
+#RX3.RXPACKS#1.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B06702011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b111, def_bus_id3;
+}
+
+#RX3.RXPACKS#2.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B07402011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b011, def_bus_id3;
+}
+
+#RX3.RXPACKS#2.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B07502011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b010, def_bus_id3;
+}
+
+#RX3.RXPACKS#2.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B07602011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b001, def_bus_id3;
+}
+
+#RX3.RXPACKS#2.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B07702011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b000, def_bus_id3;
+}
+
+#RX3.RXPACKS#3.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B07002011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b111, def_bus_id3;
+}
+
+#RX3.RXPACKS#3.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B07102011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b110, def_bus_id3;
+}
+
+#RX3.RXPACKS#3.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B07202011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b101, def_bus_id3;
+}
+
+#RX3.RXPACKS#3.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B07302011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b100, def_bus_id3;
+}
+
+#RX3.RXPACKS#4.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B06E02011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b001, def_bus_id3;
+}
+
+#RX3.RXPACKS#4.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B06F02011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b000, def_bus_id3;
+}
+
+#RX3.RXPACKS#4.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B06C02011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b011, def_bus_id3;
+}
+
+#RX3.RXPACKS#4.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B06D02011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b010, def_bus_id3;
+}
+
+#RX3.RXPACKS#5.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B06A02011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b010, def_bus_id3;
+}
+
+#RX3.RXPACKS#5.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B06B02011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b011, def_bus_id3;
+}
+
+#RX3.RXPACKS#5.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B06802011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b000, def_bus_id3;
+}
+
+#RX3.RXPACKS#5.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
+scom 0x8000B06902011E3F { 
+	bits, scom_data, expr;
+	rx_prbs_tap_id, 0b001, def_bus_id3;
+}
+
+#TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_CLK_CNTL_GCRMSG_PG
+scom 0x800CC40002011E3F { 
+	bits, scom_data, expr;
+	tx_drv_clk_pattern_gcrmsg, 0b00, def_bus_id0;
+}
+
+#TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_ID1_PG
+scom 0x800C940002011E3F { 
+	bits, scom_data, expr;
+	tx_bus_id, 0b000000, def_bus_id0;
+	tx_group_id, 0b100000, def_bus_id0;
+}
+
+#TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_ID2_PG
+scom 0x800C9C0002011E3F { 
+	bits, scom_data, expr;
+	tx_last_group_id, 0b100000, def_bus_id0;
+}
+
+#TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_ID3_PG
+scom 0x800CA40002011E3F { 
+	bits, scom_data, expr;
+	tx_end_lane_id, 0b0010000, def_bus_id0;
+	tx_start_lane_id, 0b0000000, def_bus_id0;
+}
+
+#TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_0_15_PG
+scom 0x800D1C0002011E3F { 
+	bits, scom_data, expr;
+	tx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id0;
+}
+
+#TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_16_31_PG
+scom 0x800D240002011E3F { 
+	bits, scom_data, expr;
+	tx_lane_disabled_vec_16_31, 0b0111111111111111, def_bus_id0;
+}
+
+#TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_MODE_PG
+scom 0x800C1C0002011E3F { 
+	bits, scom_data, expr;
+	tx_max_bad_lanes, 0b00010, def_bus_id0;
+}
+
+#TX_WRAP.TX0.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004340002011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b000, def_bus_id0;
+}
+
+#TX_WRAP.TX0.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004340102011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b001, def_bus_id0;
+}
+
+#TX_WRAP.TX0.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004340202011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b010, def_bus_id0;
+}
+
+#TX_WRAP.TX0.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004340302011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b011, def_bus_id0;
+}
+
+#TX_WRAP.TX0.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004340402011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b100, def_bus_id0;
+}
+
+#TX_WRAP.TX0.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004340502011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b101, def_bus_id0;
+}
+
+#TX_WRAP.TX0.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004340602011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b110, def_bus_id0;
+}
+
+#TX_WRAP.TX0.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004340702011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b111, def_bus_id0;
+}
+
+#TX_WRAP.TX0.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004341002011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b000, def_bus_id0;
+}
+
+#TX_WRAP.TX0.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004340F02011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b001, def_bus_id0;
+}
+
+#TX_WRAP.TX0.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004340E02011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b010, def_bus_id0;
+}
+
+#TX_WRAP.TX0.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004340D02011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b011, def_bus_id0;
+}
+
+#TX_WRAP.TX0.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004340C02011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b100, def_bus_id0;
+}
+
+#TX_WRAP.TX0.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004340B02011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b101, def_bus_id0;
+}
+
+#TX_WRAP.TX0.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004340A02011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b110, def_bus_id0;
+}
+
+#TX_WRAP.TX0.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004340902011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b111, def_bus_id0;
+}
+
+#TX_WRAP.TX0.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#4.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004340802011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b000, def_bus_id0;
+}
+
+#TX_WRAP.TX1.TXCTL.TX_CTL_REGS.TX_CLK_CNTL_GCRMSG_PG
+scom 0x800CC42002011E3F { 
+	bits, scom_data, expr;
+	tx_drv_clk_pattern_gcrmsg, 0b00, def_bus_id1;
+}
+
+#TX_WRAP.TX1.TXCTL.TX_CTL_REGS.TX_ID1_PG
+scom 0x800C942002011E3F { 
+	bits, scom_data, expr;
+	tx_bus_id, 0b000001, def_bus_id1;
+	tx_group_id, 0b100000, def_bus_id1;
+}
+
+#TX_WRAP.TX1.TXCTL.TX_CTL_REGS.TX_ID2_PG
+scom 0x800C9C2002011E3F { 
+	bits, scom_data, expr;
+	tx_last_group_id, 0b100000, def_bus_id1;
+}
+
+#TX_WRAP.TX1.TXCTL.TX_CTL_REGS.TX_ID3_PG
+scom 0x800CA42002011E3F { 
+	bits, scom_data, expr;
+	tx_end_lane_id, 0b0010000, def_bus_id1;
+	tx_start_lane_id, 0b0000000, def_bus_id1;
+}
+
+#TX_WRAP.TX1.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_0_15_PG
+scom 0x800D1C2002011E3F { 
+	bits, scom_data, expr;
+	tx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id1;
+}
+
+#TX_WRAP.TX1.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_16_31_PG
+scom 0x800D242002011E3F { 
+	bits, scom_data, expr;
+	tx_lane_disabled_vec_16_31, 0b0111111111111111, def_bus_id1;
+}
+
+#TX_WRAP.TX1.TXCTL.TX_CTL_REGS.TX_MODE_PG
+scom 0x800C1C2002011E3F { 
+	bits, scom_data, expr;
+	tx_max_bad_lanes, 0b00010, def_bus_id1;
+}
+
+#TX_WRAP.TX1.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004342002011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b000, def_bus_id1;
+}
+
+#TX_WRAP.TX1.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004342102011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b001, def_bus_id1;
+}
+
+#TX_WRAP.TX1.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004342202011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b010, def_bus_id1;
+}
+
+#TX_WRAP.TX1.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004342302011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b011, def_bus_id1;
+}
+
+#TX_WRAP.TX1.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004342402011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b100, def_bus_id1;
+}
+
+#TX_WRAP.TX1.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004342502011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b101, def_bus_id1;
+}
+
+#TX_WRAP.TX1.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004342602011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b110, def_bus_id1;
+}
+
+#TX_WRAP.TX1.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004342702011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b111, def_bus_id1;
+}
+
+#TX_WRAP.TX1.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004343002011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b000, def_bus_id1;
+}
+
+#TX_WRAP.TX1.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004342F02011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b001, def_bus_id1;
+}
+
+#TX_WRAP.TX1.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004342E02011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b010, def_bus_id1;
+}
+
+#TX_WRAP.TX1.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004342D02011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b011, def_bus_id1;
+}
+
+#TX_WRAP.TX1.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004342C02011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b100, def_bus_id1;
+}
+
+#TX_WRAP.TX1.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004342B02011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b101, def_bus_id1;
+}
+
+#TX_WRAP.TX1.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004342A02011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b110, def_bus_id1;
+}
+
+#TX_WRAP.TX1.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004342902011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b111, def_bus_id1;
+}
+
+#TX_WRAP.TX1.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#4.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004342802011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b000, def_bus_id1;
+}
+
+#TX_WRAP.TX2.TXCTL.TX_CTL_REGS.TX_CLK_CNTL_GCRMSG_PG
+scom 0x800CC44002011E3F { 
+	bits, scom_data, expr;
+	tx_drv_clk_pattern_gcrmsg, 0b00, def_bus_id2;
+}
+
+#TX_WRAP.TX2.TXCTL.TX_CTL_REGS.TX_ID1_PG
+scom 0x800C944002011E3F { 
+	bits, scom_data, expr;
+	tx_bus_id, 0b000010, def_bus_id2;
+	tx_group_id, 0b100000, def_bus_id2;
+}
+
+#TX_WRAP.TX2.TXCTL.TX_CTL_REGS.TX_ID2_PG
+scom 0x800C9C4002011E3F { 
+	bits, scom_data, expr;
+	tx_last_group_id, 0b100000, def_bus_id2;
+}
+
+#TX_WRAP.TX2.TXCTL.TX_CTL_REGS.TX_ID3_PG
+scom 0x800CA44002011E3F { 
+	bits, scom_data, expr;
+	tx_end_lane_id, 0b0010000, def_bus_id2;
+	tx_start_lane_id, 0b0000000, def_bus_id2;
+}
+
+#TX_WRAP.TX2.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_0_15_PG
+scom 0x800D1C4002011E3F { 
+	bits, scom_data, expr;
+	tx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id2;
+}
+
+#TX_WRAP.TX2.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_16_31_PG
+scom 0x800D244002011E3F { 
+	bits, scom_data, expr;
+	tx_lane_disabled_vec_16_31, 0b0111111111111111, def_bus_id2;
+}
+
+#TX_WRAP.TX2.TXCTL.TX_CTL_REGS.TX_MODE_PG
+scom 0x800C1C4002011E3F { 
+	bits, scom_data, expr;
+	tx_max_bad_lanes, 0b00010, def_bus_id2;
+}
+
+#TX_WRAP.TX2.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004344002011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b000, def_bus_id2;
+}
+
+#TX_WRAP.TX2.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004344102011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b001, def_bus_id2;
+}
+
+#TX_WRAP.TX2.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004344202011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b010, def_bus_id2;
+}
+
+#TX_WRAP.TX2.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004344302011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b011, def_bus_id2;
+}
+
+#TX_WRAP.TX2.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004344402011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b100, def_bus_id2;
+}
+
+#TX_WRAP.TX2.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004344502011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b101, def_bus_id2;
+}
+
+#TX_WRAP.TX2.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004344602011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b110, def_bus_id2;
+}
+
+#TX_WRAP.TX2.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004344702011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b111, def_bus_id2;
+}
+
+#TX_WRAP.TX2.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004345002011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b000, def_bus_id2;
+}
+
+#TX_WRAP.TX2.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004344F02011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b001, def_bus_id2;
+}
+
+#TX_WRAP.TX2.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004344E02011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b010, def_bus_id2;
+}
+
+#TX_WRAP.TX2.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004344D02011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b011, def_bus_id2;
+}
+
+#TX_WRAP.TX2.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004344C02011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b100, def_bus_id2;
+}
+
+#TX_WRAP.TX2.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004344B02011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b101, def_bus_id2;
+}
+
+#TX_WRAP.TX2.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004344A02011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b110, def_bus_id2;
+}
+
+#TX_WRAP.TX2.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004344902011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b111, def_bus_id2;
+}
+
+#TX_WRAP.TX2.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#4.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004344802011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b000, def_bus_id2;
+}
+
+#TX_WRAP.TX3.TXCTL.TX_CTL_REGS.TX_CLK_CNTL_GCRMSG_PG
+scom 0x800CC46002011E3F { 
+	bits, scom_data, expr;
+	tx_drv_clk_pattern_gcrmsg, 0b00, def_bus_id3;
+}
+
+#TX_WRAP.TX3.TXCTL.TX_CTL_REGS.TX_ID1_PG
+scom 0x800C946002011E3F { 
+	bits, scom_data, expr;
+	tx_bus_id, 0b000011, def_bus_id3;
+	tx_group_id, 0b100000, def_bus_id3;
+}
+
+#TX_WRAP.TX3.TXCTL.TX_CTL_REGS.TX_ID2_PG
+scom 0x800C9C6002011E3F { 
+	bits, scom_data, expr;
+	tx_last_group_id, 0b100000, def_bus_id3;
+}
+
+#TX_WRAP.TX3.TXCTL.TX_CTL_REGS.TX_ID3_PG
+scom 0x800CA46002011E3F { 
+	bits, scom_data, expr;
+	tx_end_lane_id, 0b0010000, def_bus_id3;
+	tx_start_lane_id, 0b0000000, def_bus_id3;
+}
+
+#TX_WRAP.TX3.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_0_15_PG
+scom 0x800D1C6002011E3F { 
+	bits, scom_data, expr;
+	tx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id3;
+}
+
+#TX_WRAP.TX3.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_16_31_PG
+scom 0x800D246002011E3F { 
+	bits, scom_data, expr;
+	tx_lane_disabled_vec_16_31, 0b0111111111111111, def_bus_id3;
+}
+
+#TX_WRAP.TX3.TXCTL.TX_CTL_REGS.TX_MODE_PG
+scom 0x800C1C6002011E3F { 
+	bits, scom_data, expr;
+	tx_max_bad_lanes, 0b00010, def_bus_id3;
+}
+
+#TX_WRAP.TX3.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004346002011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b000, def_bus_id3;
+}
+
+#TX_WRAP.TX3.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004346102011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b001, def_bus_id3;
+}
+
+#TX_WRAP.TX3.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004346202011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b010, def_bus_id3;
+}
+
+#TX_WRAP.TX3.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004346302011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b011, def_bus_id3;
+}
+
+#TX_WRAP.TX3.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004346402011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b100, def_bus_id3;
+}
+
+#TX_WRAP.TX3.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004346502011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b101, def_bus_id3;
+}
+
+#TX_WRAP.TX3.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004346602011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b110, def_bus_id3;
+}
+
+#TX_WRAP.TX3.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004346702011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b111, def_bus_id3;
+}
+
+#TX_WRAP.TX3.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004347002011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b000, def_bus_id3;
+}
+
+#TX_WRAP.TX3.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004346F02011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b001, def_bus_id3;
+}
+
+#TX_WRAP.TX3.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004346E02011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b010, def_bus_id3;
+}
+
+#TX_WRAP.TX3.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004346D02011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b011, def_bus_id3;
+}
+
+#TX_WRAP.TX3.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004346C02011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b100, def_bus_id3;
+}
+
+#TX_WRAP.TX3.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004346B02011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b101, def_bus_id3;
+}
+
+#TX_WRAP.TX3.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004346A02011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b110, def_bus_id3;
+}
+
+#TX_WRAP.TX3.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004346902011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b111, def_bus_id3;
+}
+
+#TX_WRAP.TX3.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#4.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
+scom 0x8004346802011E3F { 
+	bits, scom_data, expr;
+	tx_prbs_tap_id, 0b000, def_bus_id3;
+}
+
+
+######################################
+##      END OF FILE
+#######################################
diff --git a/src/usr/hwpf/hwp/initfiles/p8.nx.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.nx.scom.initfile
index 379e3c945..fb1836b0a 100644
--- a/src/usr/hwpf/hwp/initfiles/p8.nx.scom.initfile
+++ b/src/usr/hwpf/hwp/initfiles/p8.nx.scom.initfile
@@ -1,4 +1,4 @@
-#-- $Id: p8.nx.scom.initfile,v 1.2 2013/01/10 21:31:50 johnre Exp $
+#-- $Id: p8.nx.scom.initfile,v 1.3 2013/01/25 16:23:46 johnre Exp $
 #-------------------------------------------------------------------------------
 #--
 #-- (C) Copyright International Business Machines Corp. 2011
@@ -122,8 +122,8 @@ scom 0x0201308E {
      0    ,  0b0                 ;  #-- BUID enable
      1:2  ,  ATTR_FABRIC_NODE_ID ;  #-- BUID Base(0:1) Node Id  ????
      3:5  ,  ATTR_FABRIC_CHIP_ID ;  #-- BUID Base(2:4) Chip Id  ????
-     6:19 ,  0x00000             ;  #-- BUID Base(5:18)   ????
-    20:32 ,  0b0000              ;  #-- BUID Mask(6:18).  Mask(0:5)=0b111111
+     6:19 ,  0b00000000000000    ;  #-- BUID Base(5:18)   ????
+    20:32 ,   0b1111111100000    ;  #-- BUID Mask(6:18).  Mask(0:5) implied 0b111111
 }
 
 
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.C
index 51abb1a37..2152d137e 100644
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.C
+++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012                   */
+/* COPYRIGHT International Business Machines Corp. 2012,2013              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_eff_config.C,v 1.15 2012/11/16 14:44:04 asaetow Exp $
+// $Id: mss_eff_config.C,v 1.16 2013/01/24 18:33:16 bellows Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/
 //          centaur/working/procedures/ipl/fapi/mss_eff_config.C,v $
 //------------------------------------------------------------------------------
@@ -44,7 +44,9 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
-//   1.16  |          |         |
+//   1.17  |          |         |
+//   1.16  | bellows  |24-JAN-13| Added in CUSTOM bit of SPD and CUSTOM Attr
+//         |          |         | settings.  
 //   1.15  | asaetow  |15-NOV-12| Added call to mss_eff_config_cke_map().
 //         |          |         | NOTE: DO NOT pick-up without
 //         |          |         | mss_eff_config_cke_map.C v1.3 or newer.
@@ -179,6 +181,7 @@ struct mss_eff_config_spd_data
 {
     uint8_t dram_device_type[PORT_SIZE][DIMM_SIZE];
     uint8_t module_type[PORT_SIZE][DIMM_SIZE];
+    uint8_t custom[PORT_SIZE][DIMM_SIZE];
     uint8_t sdram_banks[PORT_SIZE][DIMM_SIZE];
     uint8_t sdram_density[PORT_SIZE][DIMM_SIZE];
     uint8_t sdram_rows[PORT_SIZE][DIMM_SIZE];
@@ -246,6 +249,7 @@ struct mss_eff_config_atts
     uint8_t eff_dimm_size[PORT_SIZE][DIMM_SIZE];
     uint8_t eff_dimm_spare[PORT_SIZE][DIMM_SIZE][RANK_SIZE];
     uint8_t eff_dimm_type;
+    uint8_t eff_custom_dimm;
     uint8_t eff_dram_al; // initialized to 1
     uint8_t eff_dram_asr;
     uint8_t eff_dram_bl;
@@ -424,6 +428,9 @@ fapi::ReturnCode mss_eff_config_read_spd_data(fapi::Target i_target_dimm,
         rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_TYPE, &i_target_dimm,
             p_o_spd_data->module_type[i_port][i_dimm]);
         if(rc) break;
+        rc = FAPI_ATTR_GET(ATTR_SPD_CUSTOM, &i_target_dimm,
+            p_o_spd_data->custom[i_port][i_dimm]);
+        if(rc) break;
         rc = FAPI_ATTR_GET(ATTR_SPD_SDRAM_BANKS, &i_target_dimm,
             p_o_spd_data->sdram_banks[i_port][i_dimm]);
         if(rc) break;
@@ -1076,25 +1083,18 @@ fapi::ReturnCode mss_eff_config_setup_eff_atts(
     {
         case fapi::ENUM_ATTR_SPD_MODULE_TYPE_CDIMM:
             p_o_atts->eff_dimm_type = fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM;
+            FAPI_ERR("ATTR_SPD_MODULE_TYPE_CDIMM is obsolete.  Check your VPD for correct definition on %s!", i_target_mba.toEcmdString());
             break;
         case fapi::ENUM_ATTR_SPD_MODULE_TYPE_RDIMM:
             p_o_atts->eff_dimm_type = fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM;
             break;
         case fapi::ENUM_ATTR_SPD_MODULE_TYPE_UDIMM:
-            // TODO RTC Task 60572
-            // DIMM SPD Module Type in byte 3 can be 0x82.
-            // 0x80 is CDIMM, 0x02 is unbuffered
-            // Problem 1: Firmware SPD DD only returns the lower 4 bits because
-            //   the top 4 bits are reserved in the spec. There needs to be a
-            //   new SPD attribute for the top bit that can be queried by this
-            //   HWP. HW team to provide updated dimm_spd_attributes.xml. FW
-            //   team to support the new attribute.
-            // Problem 2: This HWP and mss_eff_config_termination fail if
-            //   eff_dimm_type is not CDIMM or RDIMM. Depending on the fix for
-            //   Problem 1, the HWPs need fixing to recognize Unbuffered-CDIMM
-            // The workaround is to treat UDIMM(0x02) as a CDIMM
-            //OLD: p_o_atts->eff_dimm_type = fapi::ENUM_ATTR_EFF_DIMM_TYPE_UDIMM;
-            p_o_atts->eff_dimm_type = fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM;
+            if(p_i_data->custom[0][0]) {
+              p_o_atts->eff_dimm_type = fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM;
+            }
+            else {
+              p_o_atts->eff_dimm_type = fapi::ENUM_ATTR_EFF_DIMM_TYPE_UDIMM;
+            }
             break;
         case fapi::ENUM_ATTR_SPD_MODULE_TYPE_LRDIMM:
             p_o_atts->eff_dimm_type = fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM;
@@ -1105,6 +1105,13 @@ fapi::ReturnCode mss_eff_config_setup_eff_atts(
             return rc;
     }
 //------------------------------------------------------------------------------
+    if(p_i_data->custom[0][0] == fapi::ENUM_ATTR_SPD_CUSTOM_YES) {
+      p_o_atts->eff_custom_dimm = fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES;
+    }
+    else {
+      p_o_atts->eff_custom_dimm = fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_NO;
+    }
+//------------------------------------------------------------------------------
     switch(p_i_data->sdram_banks[0][0])
     {
         case fapi::ENUM_ATTR_SPD_SDRAM_BANKS_B8:
@@ -1734,6 +1741,9 @@ fapi::ReturnCode mss_eff_config_write_eff_atts(
         rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_TYPE, &i_target_mba,
                 p_i_atts->eff_dimm_type);
         if(rc) break;
+        rc = FAPI_ATTR_SET(ATTR_EFF_CUSTOM_DIMM, &i_target_mba,
+                p_i_atts->eff_custom_dimm);
+        if(rc) break;
         rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_AL, &i_target_mba,
                 p_i_atts->eff_dram_al);
         if(rc) break;
diff --git a/src/usr/hwpf/hwp/memory_attributes.xml b/src/usr/hwpf/hwp/memory_attributes.xml
index ebb2227cb..e6222ef5b 100644
--- a/src/usr/hwpf/hwp/memory_attributes.xml
+++ b/src/usr/hwpf/hwp/memory_attributes.xml
@@ -5,7 +5,7 @@
 <!--                                                                        -->
 <!-- IBM CONFIDENTIAL                                                       -->
 <!--                                                                        -->
-<!-- COPYRIGHT International Business Machines Corp. 2012                   -->
+<!-- COPYRIGHT International Business Machines Corp. 2012,2013              -->
 <!--                                                                        -->
 <!-- p1                                                                     -->
 <!--                                                                        -->
@@ -19,8 +19,8 @@
 <!--                                                                        -->
 <!-- Origin: 30                                                             -->
 <!--                                                                        -->
-<!-- IBM_PROLOG_END_TAG                                                     -->
 <attributes>
+<!-- IBM_PROLOG_END_TAG                                                     -->
 <!-- DO NOT EDIT THIS FILE DIRECTLY PLEASE UPDATE THE ODS FILE AND FOLLOW THE INSTRUCTION TAB -->
 <!-- PLEASE SEE MARK BELLOWS (BELLOWS.IBM.COM) OR OTHERS ON MEMORY TEAM FOR HELP -->
 <!-- *********************************************************************** -->
@@ -100,7 +100,8 @@ firmware notes: none</description>
     <description>Type of DIMM: CDIMM, RDIMM, UDIMM, LRDIMM. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
 creator: mss_eff_cnfg
 consumer: various
-firmware notes: none</description>
+firmware notes: none
+NOTE: the type CDIMM is being defined as a Custom DIMM based on an unbuffered solution. A related attribute is the EFF_CUSTOM_DIMM</description>
     <valueType>uint8</valueType>
     <enum>CDIMM = 0, RDIMM = 1, UDIMM = 2, LRDIMM = 3</enum>
     <writeable/>
@@ -110,6 +111,19 @@ firmware notes: none</description>
 </attribute>
 
 <attribute>
+    <id>ATTR_EFF_CUSTOM_DIMM</id>
+    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
+    <description>DIMM is a custom DIMM. Sometimes this is known as a CDIMM, but technically, we could support Custom DIMMs of different types than an UDIMM, such as RDIMM and LRDIMM.  Created in mss_eff_cnfg</description>
+    <valueType>uint8</valueType>
+    <enum>NO = 0, YES = 1</enum>
+    <platActionWrite/>
+    <writeable/>
+    <odmVisable/>
+    <odmChangeable/>
+    <persistRuntime/>
+</attribute>
+
+<attribute>
     <id>ATTR_EFF_DRAM_WIDTH</id>
     <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
     <description>DRAM Device Width: X4, X8, X16, X32. Used in various locations and is computed in mss_eff_cnfg.
@@ -1792,8 +1806,8 @@ firmware notes: none</description>
     <persistRuntime/>
 </attribute>
 
-<!-- Comment out until HWP integrated that uses these attributes. Platform needs to initialize
 
+<!-- Comment out until HWP integrated that uses these attributes. Platform needs to initialize
 <attribute>
     <id>ATTR_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_MBA</id>
     <targetType>TARGET_TYPE_SYSTEM</targetType>
@@ -1880,14 +1894,10 @@ Hash modes values are 0,1 and 2. Used in the intifile </description>
 <attribute>
     <id>ATTR_MSS_CACHE_ENABLE</id>
     <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
-    <description>Value of on or off.  Determines if the L4 is enabled or not. See chapter 6 of the Centaur Workbook.  On means the full cache is enabled.  HALF_A means only A is enabled and HALF_B means only B is enabled. These values are set in the mss_get_cen_ecid.</description>
+    <description>Value of on or off.  Determines if the L4 is enabled or not. See chapter 6 of the Centaur Workbook.  On means the full cache is enabled.  HALF_A (EVEN) means only A is enabled and HALF_B (ODD) means only B is enabled. This value is set by the platform which can get the chips value by running the mss_cen_get_ecid function.</description>
     <valueType>uint8</valueType>
     <enum>OFF = 0, ON = 1, HALF_A = 3, HALF_B = 5</enum>
-    <!-- TODO RTC 58012. This attribute is not platInit in the master file in eKB/cvs.
-         It is setup by the mss_get_cen_ecid HWP. Before that HWP is integrated, this
-         attribute is platInit and Hostboot firmware defaults the value to ON -->
     <platInit/>
-    <writeable/>
     <odmVisable/>
     <odmChangeable/>
 </attribute>
@@ -2644,6 +2654,49 @@ Created from running the mss_get_cen_ecid.C</description>
     <odmChangeable/>
 </attribute>
 
+<attribute>
+    <id>ATTR_MSS_ZSERIES</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>Determines if the code is Zseries type or P Series.  The platform determines this and this attribute is mostly used in the initfiles so that we can share the same initialization code with the zSeries team</description>
+    <valueType>uint8</valueType>
+    <enum>FALSE = 0, TRUE = 1</enum>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_MSS_PSRO</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Set by the centaur mss_get_cen_ecid function used diagnostic and chip characterization reporting</description>
+    <valueType>uint8</valueType>
+    <writeable/>
+    <odmVisable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_MSS_NWELL_MISPLACEMENT</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Set by the platform depending on DD1 vs DD1.01.  If true, then SI settings affected by the NWELL problem are adjusted.  Used in eff_config</description>
+    <valueType>uint8</valueType>
+    <enum>FALSE = 0, TRUE = 1</enum>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
+<!-- Comment out until HWP integrated that uses these attributes. Platform needs to initialize
+
+<attribute>
+    <id>ATTR_MSS_READ_PHASE_SELECT</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Set by the platform depending on DD1 vs DD1.01.  If true, then training and periodic training needs to make adjustments to the read phase select.</description>
+    <valueType>uint8</valueType>
+    <enum>FALSE =0, TRUE = 1</enum>
+    <platInit/>
+    <odmVisable/>
+</attribute>
+
+-->
+
 <!-- DO NOT EDIT THIS FILE DIRECTLY PLEASE UPDATE THE ODS FILE AND FOLLOW THE INSTRUCTION TAB -->
 <!-- PLEASE SEE MARK BELLOWS (BELLOWS.IBM.COM) OR OTHERS ON MEMORY TEAM FOR HELP -->
 </attributes>
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_initf.C b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_initf.C
index a50fb1382..c665d7ccc 100644
--- a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_initf.C
+++ b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_initf.C
@@ -21,7 +21,7 @@
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
 // -*- mode: C++; c-file-style: "linux";  -*-
-// $Id: proc_a_x_pci_dmi_pll_initf.C,v 1.9 2013/01/20 19:21:03 jmcgill Exp $
+// $Id: proc_a_x_pci_dmi_pll_initf.C,v 1.11 2013/01/24 16:34:45 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_a_x_pci_dmi_pll_initf.C,v $
 //------------------------------------------------------------------------------
 // *|
@@ -97,7 +97,7 @@ extern "C"
         uint8_t            abus_enable_attr;
         uint32_t           ring_length     = 0;
         uint8_t            attrABRingData[80]  ={0};  // Set to 80 bytes to match length in XML file, not actual scan ring length.
-        uint8_t            attrDMIRingData[192]={0};  // Set to 192 bytes to match length in XML file, not actual scan ring length.
+        uint8_t            attrDMIRingData[231]={0};  // Set to 231 bytes to match length in XML file, not actual scan ring length.
         uint8_t            attrPCIRingData[80] ={0};  // Set to 80 bytes to match length in XML file, not actual scan ring length.
 
         // return codes
@@ -710,6 +710,12 @@ extern "C"
 This section is automatically updated by CVS when you check in this file.
 Be sure to create CVS comments when you commit so that they can be included here.
 $Log: proc_a_x_pci_dmi_pll_initf.C,v $
+Revision 1.11  2013/01/24 16:34:45  jmcgill
+fix comment as well...
+
+Revision 1.10  2013/01/24 16:33:40  jmcgill
+adjust for DMI attribute change
+
 Revision 1.9  2013/01/20 19:21:03  jmcgill
 update for A chiplet partial good support
 
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.C b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.C
index 97a75d9aa..b824ff03a 100644
--- a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.C
+++ b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.C
@@ -21,7 +21,7 @@
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
 // -*- mode: C++; c-file-style: "linux";  -*-
-// $Id: proc_a_x_pci_dmi_pll_setup.C,v 1.9 2013/01/20 19:22:44 jmcgill Exp $
+// $Id: proc_a_x_pci_dmi_pll_setup.C,v 1.10 2013/01/25 19:30:22 mfred Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_a_x_pci_dmi_pll_setup.C,v $
 //------------------------------------------------------------------------------
 // *|
@@ -61,6 +61,7 @@ const uint8_t GP3_PLL_RESET = 4;
 const uint8_t GP3_PLL_BYPASS = 5;
 const uint8_t FSI_GP4_PLL_TEST_BYPASS1 = 22;
 const uint8_t PLLLOCK = 0;
+const uint8_t PLLLOCK2 = 1;
 
 
 
@@ -219,6 +220,24 @@ extern "C"
 
 
 
+                FAPI_INF("ABUS GP3: Release PLL bypass of A-BUS ");
+                rc_ecmd |= gp_data.flushTo1();
+                rc_ecmd |= gp_data.clearBit(GP3_PLL_BYPASS);
+                if (rc_ecmd)
+                {
+                    FAPI_ERR("Error 0x%x setting up data buffer to clear GP3_PLL_BYPASS", rc_ecmd);
+                    rc.setEcmdError(rc_ecmd);
+                    break;
+                }
+                rc = fapiPutScom(i_target, A_GP3_AND_0x080F0013, gp_data);
+                if (rc)
+                {
+                    FAPI_ERR("fapiPutScom error (A_GP3_AND_0x080F0013)");
+                    break;
+                }
+
+
+
                 FAPI_INF("CHIPLET PLLLK: Check the PLL lock of A-BUS ");
                 num = 0;
                 do
@@ -248,24 +267,6 @@ extern "C"
 
 
 
-                FAPI_INF("ABUS GP3: Release PLL bypass of A-BUS ");
-                rc_ecmd |= gp_data.flushTo1();
-                rc_ecmd |= gp_data.clearBit(GP3_PLL_BYPASS);
-                if (rc_ecmd)
-                {
-                    FAPI_ERR("Error 0x%x setting up data buffer to clear GP3_PLL_BYPASS", rc_ecmd);
-                    rc.setEcmdError(rc_ecmd);
-                    break;
-                }
-                rc = fapiPutScom(i_target, A_GP3_AND_0x080F0013, gp_data);
-                if (rc)
-                {
-                    FAPI_ERR("fapiPutScom error (A_GP3_AND_0x080F0013)");
-                    break;
-                }
-
-
-
                 FAPI_INF("Done setting up A-Bus PLL. ");
             }  // end A PLL
 
@@ -319,6 +320,24 @@ extern "C"
 
 
 
+                FAPI_INF("NEST GP3: Release PLL bypass of for DMI PLL.");
+                rc_ecmd |= gp_data.flushTo1();
+                rc_ecmd |= gp_data.clearBit(GP3_PLL_BYPASS);
+                if (rc_ecmd)
+                {
+                    FAPI_ERR("Error 0x%x setting up data buffer to clear GP3_PLL_BYPASS", rc_ecmd);
+                    rc.setEcmdError(rc_ecmd);
+                    break;
+                }
+                rc = fapiPutScom(i_target, NEST_GP3_AND_0x020F0013, gp_data);
+                if (rc)
+                {
+                    FAPI_ERR("fapiPutScom error (NEST_GP3_AND_0x020F0013)");
+                    break;
+                }
+
+
+
                 FAPI_INF("CHIPLET PLLLK: Check the PLL lock of DMI PLL.");
                 num = 0;
                 do
@@ -336,7 +355,10 @@ extern "C"
                         break;
                     }
                     // sleep (10); // not accurate anymore for P8
-                } while ( !timeout && !gp_data.isBitSet(PLLLOCK) ); // Poll until PLL is locked or max count is reached.
+
+                    // Check two lock bits because there are two DMI PLLs in Venice.   Unused bit defaults to '1' in Murano.
+                } while ( !timeout && ( !gp_data.isBitSet(PLLLOCK) || !gp_data.isBitSet(PLLLOCK2) ) ); // Poll until PLL is locked or max count is reached.
+
                 if (rc) break;    // Go to end of proc if error found inside polling loop.
                 if (timeout)
                 {
@@ -348,24 +370,6 @@ extern "C"
 
 
 
-                FAPI_INF("NEST GP3: Release PLL bypass of for DMI PLL.");
-                rc_ecmd |= gp_data.flushTo1();
-                rc_ecmd |= gp_data.clearBit(GP3_PLL_BYPASS);
-                if (rc_ecmd)
-                {
-                    FAPI_ERR("Error 0x%x setting up data buffer to clear GP3_PLL_BYPASS", rc_ecmd);
-                    rc.setEcmdError(rc_ecmd);
-                    break;
-                }
-                rc = fapiPutScom(i_target, NEST_GP3_AND_0x020F0013, gp_data);
-                if (rc)
-                {
-                    FAPI_ERR("fapiPutScom error (NEST_GP3_AND_0x020F0013)");
-                    break;
-                }
-
-
-
                 FAPI_INF("Done setting up DMI PLL. ");
             }  // end DMI PLL
 
@@ -500,6 +504,9 @@ extern "C"
 This section is automatically updated by CVS when you check in this file.
 Be sure to create CVS comments when you commit so that they can be included here.
 $Log: proc_a_x_pci_dmi_pll_setup.C,v $
+Revision 1.10  2013/01/25 19:30:22  mfred
+Release PLLs from bypass before checking for PLL lock.  Also, check for two lock bits on DMI PLL to support Venice.
+
 Revision 1.9  2013/01/20 19:22:44  jmcgill
 update for A chiplet partial good support
 
diff --git a/src/usr/hwpf/makefile b/src/usr/hwpf/makefile
index f10e97d44..e489de90e 100644
--- a/src/usr/hwpf/makefile
+++ b/src/usr/hwpf/makefile
@@ -78,9 +78,10 @@ HWP_ERROR_XML_FILES = hwp/fapiHwpErrorInfo.xml   \
     hwp/poreve_errors.xml \
     hwp/proc_fab_iovalid_errors.xml \
     hwp/nest_chiplets/proc_chiplet_scominit/proc_abus_scominit_errors.xml \
-    hwp/nest_chiplets/proc_chiplet_scominit/proc_xbus_scominit_errors.xml
-
-
+    hwp/nest_chiplets/proc_chiplet_scominit/proc_xbus_scominit_errors.xml \
+    hwp/dmi_training/proc_dmi_scominit_errors.xml \
+    hwp/dmi_training/cen_dmi_scominit_errors.xml
+    
 ## these get generated into obj/genfiles/AttributeIds.H
 HWP_ATTR_XML_FILES = hwp/memory_attributes.xml \
                      hwp/L2_L3_attributes.xml \
@@ -125,7 +126,9 @@ HWP_INITFILES = hwp/initfiles/sample.initfile \
                 hwp/initfiles/p8.xbus.scom.initfile \
                 hwp/initfiles/p8.mcs.scom.initfile \
                 hwp/initfiles/p8.as.scom.initfile \
-                hwp/initfiles/p8.nx.scom.initfile
+                hwp/initfiles/p8.nx.scom.initfile \
+                hwp/initfiles/p8.dmi.custom.scom.initfile \
+		hwp/initfiles/cen.dmi.custom.scom.initfile
 
 HWP_IF_DEFINE_DIR = hwp/initfiles
 
diff --git a/src/usr/pore/makefile b/src/usr/pore/makefile
index 19f493725..9ef7025c2 100644
--- a/src/usr/pore/makefile
+++ b/src/usr/pore/makefile
@@ -23,5 +23,5 @@
 ROOTPATH = ../../..
 
 SUBDIRS = fapiporeve.d poreve.d test.d
-BINARY_FILES = $(IMGDIR)/centaur.sbe_pnor.bin:d532ebcca1b967c86ea76ac8608eeeb4ad9d514f
+BINARY_FILES = $(IMGDIR)/centaur.sbe_pnor.bin:3a1eb6f314797eccb14376cd368b6b41f070ac4e
 include ${ROOTPATH}/config.mk
diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml
index e9223c7a7..1aac2a445 100644
--- a/src/usr/targeting/common/xmltohb/attribute_types.xml
+++ b/src/usr/targeting/common/xmltohb/attribute_types.xml
@@ -5953,6 +5953,23 @@ firmware notes: Used as override attribute for pstate procedure
 </attribute>
 
 <attribute>
+    <id>EFF_CUSTOM_DIMM</id>
+    <description>DIMM is a custom DIMM. Sometimes this is known as a CDIMM, but technically, we could support Custom DIMMs of different types than an UDIMM, such as RDIMM and LRDIMM.  Created in mss_eff_cnfg</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_CUSTOM_DIMM</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
     <id>EFF_DRAM_WIDTH</id>
     <description>DRAM Device Width. Initialized and used by HWPs.</description>
     <simpleType>
@@ -8113,6 +8130,41 @@ firmware notes: Used as override attribute for pstate procedure
 </attribute>
 
 <attribute>
+    <id>MSS_ZSERIES</id>
+    <description>Determines if the code is Zseries type or P Series.  The platform determines this and this attribute is mostly used in the initfiles so that we can share the same initialization code with the zSeries team</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_ZSERIES</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<!-- Note: This looks incorrect because memory_attributes.xml says it is platInit (therefore we should set it up to a sensible value),
+     but recent discussions have concluded that a HWP will fill this in, this implementation is correct, memory_attributes.xml will eventually change. -->
+<attribute>
+    <id>MSS_NWELL_MISPLACEMENT</id>
+    <description>Set by the platform depending on DD1 vs DD1.01.  If true, then SI settings affected by the NWELL problem are adjusted.  Used in eff_config</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_NWELL_MISPLACEMENT</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
     <id>MSS_INTERLEAVE_ENABLE</id>
     <description>Used in the setting of groups.  It is a bit vector.  If the value  BITWISE_AND  1 = 1 then groups of 1 are enabled with special checkerboard modes needed, if the value  BITWISE_AND  2 = 2, then groups of 2 are possible; if value  BITWISE_AND  4, the groups of 4 are possible; if value  BITWISE_AND  8, the groups of 8 are possible.  If no groups can formed according to this input, then an error will be thrown.</description>
     <simpleType>
@@ -9280,6 +9332,23 @@ Measured in GB</description>
     </hwpfToHbAttrMap>
 </attribute>
 
+<attribute>
+    <id>MSS_PSRO</id>
+    <description>Set by the centaur mss_get_cen_ecid function used diagnostic and chip characterization reporting</description>
+    <simpleType>
+        <uint8_t>
+            <default>0</default>
+        </uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_MSS_PSRO</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
 <!-- ===== End Attributes supporting memory_attributes.xml HWPF Attributes ===== -->
 
 <attribute>
@@ -9346,29 +9415,33 @@ Measured in GB</description>
     <simpleType>
         <uint8_t>
             <default>
-                0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-                0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-                0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-                0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-                0x3f,0x44,0x11,0x00,0x00,0x00,0x7e,0x88,0x22,0x00,
-                0x00,0x00,0xfd,0x10,0x44,0x00,0x00,0x01,0xfa,0x20,
-                0x88,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-                0x40,0x00,0x40,0x00,0xe0,0x00,0x00,0xa5,0x83,0xa0,
-                0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-                0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-                0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-                0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-                0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-                0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-                0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-                0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-                0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-                0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-                0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
-                0x00,0x00
+                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                 0x3F,0x44,0x11,0x00,0x00,0x00,0x7E,0x88,0x22,0x00,
+                 0x00,0x00,0xFD,0x10,0x44,0x00,0x00,0x01,0xFA,0x20,
+                 0x88,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                 0x40,0x00,0x40,0x00,0xE0,0x01,0x00,0xA5,0x88,0x60,
+                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+                 0x00
             </default>
         </uint8_t>
-        <array>192</array>
+        <array>231</array>
     </simpleType>
     <persistency>volatile</persistency>
     <readable/>
diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml
index 5376ab19c..cc326aa98 100644
--- a/src/usr/targeting/common/xmltohb/target_types.xml
+++ b/src/usr/targeting/common/xmltohb/target_types.xml
@@ -145,6 +145,7 @@
     <!-- End proc_select_boot_master attributes  -->
 
     <attribute><id>ENABLED_THREADS</id></attribute>
+    <attribute><id>MSS_ZSERIES</id></attribute>
 </targetType>
 
 <targetType>
@@ -338,12 +339,12 @@
      <attribute><id>SBE_SEEPROM_I2C_DEVICE_ADDRESS</id></attribute>
      <attribute><id>SBE_SEEPROM_I2C_PORT</id></attribute>
      <attribute><id>PNOR_I2C_ADDRESS_BYTES</id></attribute>
-     <!-- End Supporting poreve_memory_attributes.xml -->

-     <!-- ===== Begin supporting A/X bus enable in p8_xip_customize_attributes.xml ===== -->

+     <!-- End Supporting poreve_memory_attributes.xml -->
+     <!-- ===== Begin supporting A/X bus enable in p8_xip_customize_attributes.xml ===== -->
      <attribute><id>PROC_A_ENABLE</id></attribute>
      <attribute><id>PROC_X_ENABLE</id></attribute>
-     <!-- ===== End supporting A/X bus enable in p8_xip_customize_attributes.xml ===== -->

-
+     <!-- ===== End supporting A/X bus enable in p8_xip_customize_attributes.xml ===== -->
+     
 </targetType>
 
 <targetType>
@@ -684,6 +685,7 @@
     <attribute><id>EFF_DIMM_RANKS_CONFIGED</id></attribute>
     <attribute><id>EFF_NUM_RANKS_PER_DIMM</id></attribute>
     <attribute><id>EFF_DIMM_TYPE</id></attribute>
+    <attribute><id>EFF_CUSTOM_DIMM</id></attribute>
     <attribute><id>EFF_DRAM_WIDTH</id></attribute>
     <attribute><id>EFF_DRAM_GEN</id></attribute>
     <attribute><id>EFF_PRIMARY_RANK_GROUP0</id></attribute>
@@ -996,6 +998,8 @@
      <attribute><id>PNOR_I2C_ADDRESS_BYTES</id></attribute>
      <!-- End poreve_memory_attributes.xml -->
     <attribute><id>VPD_REC_NUM</id></attribute>
+    <attribute><id>MSS_PSRO</id></attribute>
+    <attribute><id>MSS_NWELL_MISPLACEMENT</id></attribute>
 </targetType>
 
 <!-- Centaur MBS -->
diff --git a/src/usr/vpd/spdDDR3.H b/src/usr/vpd/spdDDR3.H
index bc2909312..76d608e5b 100755..100644
--- a/src/usr/vpd/spdDDR3.H
+++ b/src/usr/vpd/spdDDR3.H
@@ -123,6 +123,7 @@ KeywordData ddr3Data[] =
     { DIMM_BAD_DQ_DATA,              0xb0,   0x50,   false,  0x00,   0x00, false, true,  NA },
     { SDRAM_DIE_COUNT,               0x21,   0x01,   true,   0x70,   0x04, false, false, NA },
     { SDRAM_DEVICE_TYPE_SIGNAL_LOADING,0x21, 0x01,   true,   0x03,   0x00, false, false, NA },
+    { CUSTOM,                        0x03,   0x01,   true,   0x80,   0x07, false, false, NA },
     { MODSPEC_COM_NOM_HEIGHT_MAX,    0x3c,   0x01,   true,   0x0f,   0x00, false, false, ALL },
     { MODSPEC_COM_MAX_THICK_BACK,    0x3d,   0x01,   true,   0xf0,   0x04, false, false, ALL },
     { MODSPEC_COM_MAX_THICK_FRONT,   0x3d,   0x01,   true,   0x0f,   0x00, false, false, ALL },