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| author | Elizabeth Liner <eliner@us.ibm.com> | 2017-03-04 23:44:23 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-03-27 17:40:33 -0400 |
| commit | 9b8fa8b5e9aa26aca004e9eb5e2ea13ceb6cefea (patch) | |
| tree | 8ad0290340f5b46562d58453dea21a213d179c73 /src/usr | |
| parent | 035518d841ac1393571ed4c82451c89b2f8a852b (diff) | |
| download | talos-hostboot-9b8fa8b5e9aa26aca004e9eb5e2ea13ceb6cefea.tar.gz talos-hostboot-9b8fa8b5e9aa26aca004e9eb5e2ea13ceb6cefea.zip | |
Clearing SRAM flag before starting payload
Change-Id: Ib86d848778de5b54677c4f660609150e36e50e44
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37513
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/usr')
| -rw-r--r-- | src/usr/isteps/istep21/call_host_runtime_setup.C | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/src/usr/isteps/istep21/call_host_runtime_setup.C b/src/usr/isteps/istep21/call_host_runtime_setup.C index 06b606ab2..1348fb832 100644 --- a/src/usr/isteps/istep21/call_host_runtime_setup.C +++ b/src/usr/isteps/istep21/call_host_runtime_setup.C @@ -45,6 +45,9 @@ #include <hbotcompid.H> +#include <occ/occ_common.H> +#include <occ/occAccess.H> + using namespace ERRORLOG; using namespace ISTEP; using namespace ISTEP_ERROR; @@ -199,6 +202,33 @@ void* call_host_runtime_setup (void *io_pArgs) #endif } +#ifdef CONFIG_IPLTIME_CHECKSTOP_ANALYSIS + if(TARGETING::is_phyp_load() ) + { + //Explicity clearing the SRAM flag before starting Payload. + //This tells the OCC bootloader where to pull the OCC image from + //0: mainstore, 1: SRAM. We want to use mainstore after this point + + //Get master proc + TargetService & tS = targetService(); + TARGETING::Target* masterproc = NULL; + tS.masterProcChipTargetHandle( masterproc ); + + //Clear (up to and including the IPL flag) + const uint32_t l_SramAddrApp = HBOCC::OCC_SRAM_ADDRESS; + ecmdDataBufferBase l_occAppData((HBOCC::OCC_OFFSET_IPL_FLAG + 6) + * 8 /* bits */); + l_err = HBOCC::writeSRAM(masterproc, l_SramAddrApp, l_occAppData); + if(l_err) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "Error in writeSRAM of 0"); + break; + } + } +#endif + + #if 0 //@TODO-RTC:164022-Support max pstate without OCC #ifdef CONFIG_SET_NOMINAL_PSTATE // Speed up processors. |
