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author | Sachin Gupta <sgupta2m@in.ibm.com> | 2014-04-25 15:26:39 +0530 |
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committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2014-05-01 09:41:11 -0500 |
commit | 9a663ac9e4672fa4ddeea79f56ecc9b30c1b70c8 (patch) | |
tree | 880a7450fa86ce02eaf5189c22b0a781e1f93f9c /src/usr | |
parent | 20891b30a1d24061a9545f27bb642095395196b5 (diff) | |
download | talos-hostboot-9a663ac9e4672fa4ddeea79f56ecc9b30c1b70c8.tar.gz talos-hostboot-9a663ac9e4672fa4ddeea79f56ecc9b30c1b70c8.zip |
PRD: Mask secondary FIR bits for L4 UE errors.
Change-Id: I5e1d621af6b2d8c50651ae8da28a2bce1269df63
CQ: SW258607
Backport: release-fips810
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/10758
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Reviewed-by: Zane Shelley <zshelle@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/10804
Diffstat (limited to 'src/usr')
4 files changed, 124 insertions, 30 deletions
diff --git a/src/usr/diag/prdf/common/plat/pegasus/Mba.rule b/src/usr/diag/prdf/common/plat/pegasus/Mba.rule index 40a2187ca..08f5f1c18 100755 --- a/src/usr/diag/prdf/common/plat/pegasus/Mba.rule +++ b/src/usr/diag/prdf/common/plat/pegasus/Mba.rule @@ -190,6 +190,14 @@ chip Mba capture group MemChipletRegs; }; + register MBACALFIR_MASK_OR + { + name "MBU.MBA01.MBA_SRQ.MBACALFIR_MASK OR"; + scomaddr 0x03010405; + capture group never; + access write_only; + }; + register MBACALFIR_ACT0 { name "MBU.MBA01.MBA_SRQ.MBACALFIR_ACTION0"; diff --git a/src/usr/diag/prdf/common/plat/pegasus/Membuf_acts_NEST.rule b/src/usr/diag/prdf/common/plat/pegasus/Membuf_acts_NEST.rule index 3b6fe7ba1..032521b7a 100755 --- a/src/usr/diag/prdf/common/plat/pegasus/Membuf_acts_NEST.rule +++ b/src/usr/diag/prdf/common/plat/pegasus/Membuf_acts_NEST.rule @@ -614,7 +614,7 @@ group gMbsFir filter singlebit /** MBSFIR[10] * MBS_FIR_REG_CACHE_SRW_UE */ - (MbsFir, bit(10)) ? clearSecMbsBitsAndConnL4UE; + (MbsFir, bit(10)) ? maskSecMbsBitsAndConnL4UE; /** MBSFIR[11] * MBS_FIR_REG_CACHE_SRW_SUE @@ -629,7 +629,7 @@ group gMbsFir filter singlebit /** MBSFIR[13] * MBS_FIR_REG_CACHE_CO_UE */ - (MbsFir, bit(13)) ? clearSecMbaCalBitsAndConnL4UE; + (MbsFir, bit(13)) ? maskSecMbaCalBitsAndConnL4UE; /** MBSFIR[14] * MBS_FIR_REG_CACHE_CO_SUE @@ -1406,21 +1406,21 @@ actionclass clearSecMbaCalBitsAndLineDelete funccall("ClearMbaCalSecondaryBits"); }; -/** Clear MBACAL SecondaryBits and callout Connected L4*/ -actionclass clearSecMbaCalBitsAndConnL4UE +/** Mask MBACAL SecondaryBits and callout Connected L4*/ +actionclass maskSecMbaCalBitsAndConnL4UE { - funccall("ClearMbaCalSecondaryBits"); calloutL4; threshold1; + funccall("MaskMbaCalSecondaryBits"); SUEGenerationPoint; }; -/** Clear MBS SecondaryBits and callout Connected L4*/ -actionclass clearSecMbsBitsAndConnL4UE +/** Mask MBS SecondaryBits and callout Connected L4*/ +actionclass maskSecMbsBitsAndConnL4UE { - funccall("ClearMbsSecondaryBits"); calloutL4; threshold1; + funccall("MaskMbsSecondaryBits"); SUEGenerationPoint; }; diff --git a/src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_NEST.rule b/src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_NEST.rule index 754c99649..6a89a5457 100755 --- a/src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_NEST.rule +++ b/src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_NEST.rule @@ -205,6 +205,14 @@ capture group FirRegs; }; + register MBSFIR_MASK_OR + { + name "MBU.MBS.MBS_FIR_MASK_REG OR"; + scomaddr 0x02011405; + capture group never; + access write_only; + }; + register MBSFIR_ACT0 { name "MBU.MBS.MBS_FIR_ACTION0_REG"; diff --git a/src/usr/diag/prdf/common/plat/pegasus/prdfCenMembuf.C b/src/usr/diag/prdf/common/plat/pegasus/prdfCenMembuf.C index a04717de4..a579395d3 100755 --- a/src/usr/diag/prdf/common/plat/pegasus/prdfCenMembuf.C +++ b/src/usr/diag/prdf/common/plat/pegasus/prdfCenMembuf.C @@ -884,12 +884,6 @@ int32_t ClearMbsSecondaryBits( ExtensibleChip * i_chip, mbsFirAnd->ClearBit(26); } - if ( mbsFir->IsBitSet(27) - && mbsFir->IsBitSet(10) && ( ! mbsFirMask->IsBitSet(10))) - { - mbsFirAnd->ClearBit(27); - } - if( mbsFir->IsBitSet(3) || mbsFir->IsBitSet(4) ) { SCAN_COMM_REGISTER_CLASS * mbiFir = i_chip->getRegister("MBIFIR"); @@ -925,6 +919,7 @@ int32_t ClearMbsSecondaryBits( ExtensibleChip * i_chip, #undef PRDF_FUNC } PRDF_PLUGIN_DEFINE( Membuf, ClearMbsSecondaryBits ); + //------------------------------------------------------------------------------ /** @@ -962,27 +957,28 @@ int32_t ClearMbaCalSecondaryBits( ExtensibleChip * i_chip, ExtensibleChip * mbaChip = membdb->getMbaChip(i); if ( NULL == mbaChip ) continue; - SCAN_COMM_REGISTER_CLASS * mbaCalAndFir = - mbaChip->getRegister("MBACALFIR_AND"); + SCAN_COMM_REGISTER_CLASS * mbaCalFir = + mbaChip->getRegister("MBACALFIR"); - if( NULL == mbaCalAndFir ) continue; + if( SUCCESS != mbaCalFir->Read() ) + { + // Do not break. Just print error trace and look for + // other MBA. + PRDF_ERR( PRDF_FUNC"MBACALFIR read failed" + "for 0x%08x", mbaChip->GetId()); + continue; + } - mbaCalAndFir->setAllBits(); + if( !( mbaCalFir->IsBitSet( 10 ) || mbaCalFir->IsBitSet( 14 ) )) + continue; - // Not checking if MBACALFir bits are set or not. - // Clearing them blindly as it will give better performance. + SCAN_COMM_REGISTER_CLASS * mbaCalAndFir = + mbaChip->getRegister("MBACALFIR_AND"); - if( mbsFir->IsBitSet(12) && ( ! mbsFirMask->IsBitSet(12) ) ) - { - mbaCalAndFir->ClearBit(10); - mbaCalAndFir->ClearBit(14); - } + mbaCalAndFir->setAllBits(); - if( mbsFir->IsBitSet(13) && ( ! mbsFirMask->IsBitSet(13) ) ) - { - mbaCalAndFir->ClearBit(9); - mbaCalAndFir->ClearBit(15); - } + mbaCalAndFir->ClearBit(10); + mbaCalAndFir->ClearBit(14); l_rc = mbaCalAndFir->Write(); if ( SUCCESS != l_rc ) @@ -1001,6 +997,88 @@ int32_t ClearMbaCalSecondaryBits( ExtensibleChip * i_chip, } PRDF_PLUGIN_DEFINE( Membuf, ClearMbaCalSecondaryBits ); +//------------------------------------------------------------------------------ + +/** + * @fn MaskMbsSecondaryBits + * @brief Mask MBS secondary Fir bits which may come up because of L4 UE. + * @param i_chip The Centaur chip. + * @param i_sc ServiceDataColector. + * @return SUCCESS. + */ +int32_t MaskMbsSecondaryBits( ExtensibleChip * i_chip, + STEP_CODE_DATA_STRUCT & i_sc ) +{ + #define PRDF_FUNC "[MaskMbsSecondaryBits] " + + int32_t l_rc = SUCCESS; + do + { + SCAN_COMM_REGISTER_CLASS * mbsFirMaskOr = + i_chip->getRegister("MBSFIR_MASK_OR"); + mbsFirMaskOr->SetBit(27); + l_rc = mbsFirMaskOr->Write(); + if ( SUCCESS != l_rc ) + { + PRDF_ERR( PRDF_FUNC"MBSFIR_MASK_OR write failed" + "for 0x%08x", i_chip->GetId()); + break; + } + + }while( 0 ); + + return SUCCESS; + #undef PRDF_FUNC + +} PRDF_PLUGIN_DEFINE( Membuf, MaskMbsSecondaryBits ); + +//------------------------------------------------------------------------------ + +/** + * @fn MaskMbaCalSecondaryBits + * @brief Mask MBACAL secondary Fir bits which may come up because of L4 UE. + * @param i_chip The Centaur chip. + * @param i_sc ServiceDataColector. + * @return SUCCESS. + */ +int32_t MaskMbaCalSecondaryBits( ExtensibleChip * i_chip, + STEP_CODE_DATA_STRUCT & i_sc ) +{ + #define PRDF_FUNC "[MaskMbaCalSecondaryBits ] " + int32_t l_rc = SUCCESS; + + do + { + CenMembufDataBundle * membdb = getMembufDataBundle( i_chip ); + + for( uint32_t i = 0; i < MAX_MBA_PER_MEMBUF; i++ ) + { + ExtensibleChip * mbaChip = membdb->getMbaChip(i); + if ( NULL == mbaChip ) continue; + + SCAN_COMM_REGISTER_CLASS * mbaCalFirMaskOr = + mbaChip->getRegister("MBACALFIR_MASK_OR"); + + mbaCalFirMaskOr->SetBit(9); + mbaCalFirMaskOr->SetBit(15); + l_rc = mbaCalFirMaskOr->Write(); + if ( SUCCESS != l_rc ) + { + // Do not break. Just print error trace and look for + // other MBA. + PRDF_ERR( PRDF_FUNC"MBACALFIR_MASK_OR write failed" + "for 0x%08x", mbaChip->GetId()); + } + } + }while( 0 ); + + return SUCCESS; + #undef PRDF_FUNC + +} PRDF_PLUGIN_DEFINE( Membuf, MaskMbaCalSecondaryBits ); + +//------------------------------------------------------------------------------ + /** * @fn checkChnlReplayTimeOut * @brief Check if channel Replay Timeout is present |