INITPROC: Hostboot SW247747 PCBS FSM & Global Xstop/Recoverable Tracing

Change-Id: I3dc94c6c6064c112c08857f816bb234e3dc34535
CQ:SW247747
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/9002
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

9 files changed, 784 insertions, 344 deletions

diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_init.C b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_init.C
index 12235dd58..df994b01a 100644
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_init.C
+++ b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_init.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_pfet_init.C,v 1.13 2014/01/27 22:37:15 cmolsen Exp $
+// $Id: p8_pfet_init.C,v 1.14 2014/02/17 02:56:59 stillgs Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pfet_init.C,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -70,6 +70,7 @@
 // Includes
 // ----------------------------------------------------------------------
 #include "p8_pm.H"
+#include "p8_pm_utils.H"
 #include "p8_pfet_init.H"
 #include "p8_pfet_control.H"
 
@@ -593,6 +594,10 @@ pfet_init(const Target& i_target, uint32_t i_mode)
             // Functional - run any work-arounds necessary
             if (l_functional)
             {
+                l_rc = p8_pm_pcbs_fsm_trace (i_target, l_ex_number, 
+                                "before p8_pfet_control functional");
+                if (!l_rc.ok()) { break; }
+            
                 // \todo:  make DD1 relevent
                 FAPI_INF("Perform iVRM work-around on configured EX %d", l_ex_number);
 
@@ -605,6 +610,10 @@ pfet_init(const Target& i_target, uint32_t i_mode)
                     FAPI_ERR("iVRM / PFET Controller error");
                     break;
                 }
+                
+                l_rc = p8_pm_pcbs_fsm_trace (i_target, l_ex_number, 
+                                "after p8_pfet_control functional");
+                if (!l_rc.ok()) { break; }
 
             }
             // Not Functional - disable the PFETs
@@ -623,6 +632,11 @@ pfet_init(const Target& i_target, uint32_t i_mode)
             {
                 if (!l_functional )
                 {
+                
+                    l_rc = p8_pm_pcbs_fsm_trace (i_target, l_ex_number, 
+                                "before p8_pfet_control non-functional");
+                    if (!l_rc.ok()) { break; }
+                
                     FAPI_INF("Turn off PFETs on EX %d", l_ex_number);
                     off_mode = VOFF;
                     if (i_mode == PM_INIT_SPECIAL)
@@ -636,13 +650,15 @@ pfet_init(const Target& i_target, uint32_t i_mode)
                        BOTH,
                        off_mode);
 
-
-
                     if(l_rc)
                     {
                         FAPI_ERR("PFET Controller error");
                         break;
                     }
+                    
+                    l_rc = p8_pm_pcbs_fsm_trace (i_target, l_ex_number, 
+                                "after p8_pfet_control non-functional");
+                    if (!l_rc.ok()) { break; }
                 }
             }
             else
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_poreslw_init.C b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_poreslw_init.C
index 709f24edf..c31eaafd4 100644
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_poreslw_init.C
+++ b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_poreslw_init.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_poreslw_init.C,v 1.19 2014/01/19 19:19:42 cmolsen Exp $
+// $Id: p8_poreslw_init.C,v 1.21 2014/02/17 18:30:20 stillgs Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_poreslw_init.C,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -30,7 +30,7 @@
 // *! OWNER NAME: Greg Still         Email: stillgs@us.ibm.com
 // *! BACKUP:     Mike Olsen         Email: cmolsen@us.ibm.com
 // *!
-// *! Build cmd:  buildfapiprcd -e "../../xml/error_info/p8_poreslw_errors.xml,../../xml/error_info/p8_slw_registers.xml" p8_poreslw_init.C
+// *! Build cmd:  buildfapiprcd -e "../../xml/error_info/p8_poreslw_errors.xml,../../xml/error_info/p8_slw_registers.xml" -C p8_pm_utils.C p8_poreslw_init.C
 // *!
 /// \file p8_poreslw_init.C
 /// \brief Configure or reset the SLW PORE and related functions to enable idle
@@ -65,13 +65,13 @@
 // Includes
 // ----------------------------------------------------------------------
 #include "p8_pm.H"
+#include "p8_pm_utils.H"
 #include "p8_poreslw_init.H"
 #include "p8_pfet_init.H"
 #include "p8_pmc_deconfig_setup.H"
 #include "p8_cpu_special_wakeup.H"
 #include "p8_pcb_scom_errors.H"
 
-
 extern "C" {
 
 using namespace fapi;
@@ -88,9 +88,18 @@ using namespace fapi;
 // Function prototypes
 // ----------------------------------------------------------------------
 
-fapi::ReturnCode poreslw_init(const Target& i_target, uint32_t i_mode);
-fapi::ReturnCode poreslw_reset(const Target& i_target);
-fapi::ReturnCode poreslw_ex_setup(const Target& i_target);
+fapi::ReturnCode 
+poreslw_init(const Target& i_target, uint32_t i_mode);
+
+fapi::ReturnCode 
+poreslw_reset(const Target& i_target);
+
+fapi::ReturnCode 
+poreslw_ex_setup(const Target& i_target);
+
+fapi::ReturnCode
+p8_pm_pcbs_fsm_trace_chip(const fapi::Target& i_target,           
+                            const char *        i_msg);
 
 // ----------------------------------------------------------------------
 // Function definitions
@@ -176,6 +185,34 @@ poreslw_init(const Target& i_target, uint32_t i_mode)
     do
     {
 
+        uint8_t ipl_mode = 0;
+        rc = FAPI_ATTR_GET(ATTR_IS_MPIPL, NULL, ipl_mode);
+        if (!rc.ok())
+        {
+            FAPI_ERR("fapiGetAttribute of ATTR_IS_MPIPL rc = 0x%x", (uint32_t)rc);
+            break;
+        }
+        
+        FAPI_INF("IPL mode = %s", ipl_mode ? "MPIPL" : "NORMAL");
+                
+        uint8_t trace_en_flag = 1;  
+        FAPI_INF("PM FAPI Global FIR Tracing set to ENABLED");    
+        SETATTR(rc,
+                ATTR_PM_GLOBAL_FIR_TRACE_EN,
+                "ATTR_PM_GLOBAL_FIR_TRACE_EN",
+                NULL,
+                trace_en_flag);
+        
+        FAPI_INF("PM FAPI PCBS FSM Tracing set to ENABLED");   
+        SETATTR(rc,
+                ATTR_PM_PCBS_FSM_TRACE_EN,
+                "ATTR_PM_PCBS_FSM_TRACE_EN",
+                NULL,
+                trace_en_flag);               
+
+        rc = p8_pm_pcbs_fsm_trace_chip(i_target, "poreslw_init at entry");
+        if (!rc.ok()) { break; }
+
         // Synchronize the PMC Deconfiguration Register with the currently
         // enabled EX chiplets.
         FAPI_EXEC_HWP(rc,  p8_pmc_deconfig_setup, i_target);
@@ -376,6 +413,8 @@ poreslw_ex_setup(const Target& i_target)
     uint8_t                         pm_winkle_type  ;
     uint8_t                         pm_winkle_entry ;
     uint8_t                         pm_winkle_exit ;
+    
+
 
 
     // These enums must match the enum values in pm_hwp_attributes.xml
@@ -406,12 +445,15 @@ poreslw_ex_setup(const Target& i_target)
     {
 
         FAPI_INF("Executing poreslw_ex_setup...");
-
+        
         // --------------------------------------
         // Initialize the PFET controllers
         //   This HWP loops across the chiplet but uses chip level attributes so
         //   it is invoked prior to the chiplet loop below.
         FAPI_INF("\tInitialize the PFET controllers");
+        
+        rc = p8_pm_pcbs_fsm_trace_chip(i_target, "poreslw_init before PFET initialization");
+        if (!rc.ok()) { break; }
 
         FAPI_EXEC_HWP(rc,  p8_pfet_init, i_target, PM_INIT);
         if(rc)
@@ -419,6 +461,9 @@ poreslw_ex_setup(const Target& i_target)
             FAPI_ERR("PFET Controller Setup error");
             break;
         }
+        
+        rc = p8_pm_pcbs_fsm_trace_chip(i_target, "poreslw_init after PFET init");
+        if (!rc.ok()) { break; }
 
         // Read the attributes
 
@@ -701,7 +746,10 @@ poreslw_ex_setup(const Target& i_target)
             {
                 FAPI_ERR("Scom error reading PMGP0");
                 break;
-            }
+            }           
+
+            rc = p8_pm_pcbs_fsm_trace_chip(i_target, "poreslw_init before PM enablement check");
+            if (!rc.ok()) { break; }
 
             if (data.isBitSet(PM_DISABLE))
             {
@@ -717,7 +765,7 @@ poreslw_ex_setup(const Target& i_target)
                     rc.setEcmdError(e_rc);
                     break;
                 }
-
+                                
                 address = EX_PMGP0_AND_0x100F0101 + (l_ex_number * 0x01000000);
                 rc=fapiPutScom(i_target, address, data);
                 if(!rc.ok())
@@ -725,6 +773,10 @@ poreslw_ex_setup(const Target& i_target)
                     FAPI_ERR("Scom error writing EX_PMGP0_OR");
                     break;
                 }
+                
+                rc = p8_pm_pcbs_fsm_trace_chip(i_target, "poreslw_init after PM enablement");
+                if (!rc.ok()) { break; }
+
             }
 
             // --------------------------------------
@@ -737,6 +789,9 @@ poreslw_ex_setup(const Target& i_target)
                 break;
             }
 
+            rc = p8_pm_pcbs_fsm_trace_chip(i_target, "poreslw_init before OCC clearing Special Wakeup check");
+            if (!rc.ok()) { break; }
+
             if (data.isBitSet(0))
             {
                 FAPI_INF("\tClear OCC Special Wake-up for EX %x", l_ex_number);
@@ -754,6 +809,9 @@ poreslw_ex_setup(const Target& i_target)
                     FAPI_ERR("Scom error clearing EX_OCC_SPWKUP");
                     break;
                 }
+                
+                rc = p8_pm_pcbs_fsm_trace_chip(i_target, "poreslw_init after OCC clearing Special Wakeup");
+                if (!rc.ok()) { break; }
             }
 
             // --------------------------------------
@@ -776,5 +834,6 @@ poreslw_ex_setup(const Target& i_target)
     return rc;
 }
 
+
 } //end extern
 
diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pcbs_init.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pcbs_init.C
index 415346551..a487cbfa9 100644
--- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pcbs_init.C
+++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pcbs_init.C
@@ -20,8 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-
-// $Id: p8_pcbs_init.C,v 1.26 2014/01/29 17:54:51 cswenson Exp $
+// $Id: p8_pcbs_init.C,v 1.27 2014/02/17 03:00:35 stillgs Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pcbs_init.C,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -41,68 +40,15 @@
 // *!
 // *! Procedure Prereq:
 // *!   o System clocks are running
+// *|
+// *| buildfapiprcd -e "../../xml/error_info/p8_pcbs_init_errors.xml" -C p8_pm_utils.C p8_pcbs_init.C
 // *!
 //------------------------------------------------------------------------------
 /// \file p8_pcbs_init.C
 /// \brief Establish the Pstate 0 frequency from VPD
 ///
-///
-///
-/// \version --------------------------------------------------------------------------
-/// \version 1.8  rmaier 12/07/12 Removed PFET delay value calculation from pcbs_config since this is moved to p8_pfet_init.C
-/// \version --------------------------------------------------------------------------
-/// \version 1.7  rmaier 10/25/12 Removed PMGP1_REG Idle-Configuration since this function moved to p8_poreslw_init.C
-/// \version --------------------------------------------------------------------------
-/// \version 1.6  rmaier 10/12/12 Removed not needed scan0 writes to EX_PCBS_Pstate_Step_Target_Register EX_PCBS_OCC_Heartbeat_Reg
-/// \version --------------------------------------------------------------------------
-/// \version 1.5  rmaier 10/10/12 Changed value of EX_PCBS_Resonant_Clock_Control_Reg0_0x100F0165_scan0
-/// \version --------------------------------------------------------------------------
-/// \version 1.4  rmaier 10/08/12 Removed genBinStr and <string> function
-/// \version --------------------------------------------------------------------------
-/// \version 1.3  rmaier 10/04/12 Replacing genHex*Str function
-/// \version --------------------------------------------------------------------------
-/// \version 1.2  rmaier 09/20/12 Updated with new PCBS-addressing method
-/// \version --------------------------------------------------------------------------
-/// \version 1.1  rmaier 08/23/12 Renaming proc_ to p8_
-/// \version --------------------------------------------------------------------------
-/// \version 1.15 rmaier 08/15/12 Included review feedback Set7 (removed conditional compile statements )
-/// \version --------------------------------------------------------------------------
-/// \version 1.14 rmaier 08/03/12 Included review feedback Set4
-/// \version --------------------------------------------------------------------------
-/// \version 1.13 rmaier 08/02/12 Included review feedback Set4 partial
-/// \version --------------------------------------------------------------------------
-/// \version 1.12 rmaier 07/30/12 Included review feedback Set3 partial
-/// \version --------------------------------------------------------------------------
-/// \version 1.11 rmaier 07/23/12 Included review feedback Set2 partial
-/// \version --------------------------------------------------------------------------
-/// \version 1.10 rmaier 07/17/12 Included review feedback Set1
-/// \version --------------------------------------------------------------------------
-/// \version 1.7 rmaier 05/24/12 Included review feedback
-/// \version --------------------------------------------------------------------------
-/// \version 1.6 rmaier 03/27/12 Coded CONFIG mode
-/// \version --------------------------------------------------------------------------
-/// \version 1.5 rmaier 03/20/12 Coded INIT mode
-/// \version --------------------------------------------------------------------------
-/// \version 1.4 rmaier 03/13/12 Added modes-structure
-/// \version --------------------------------------------------------------------------
-/// \version 1.3 rmaier 01/11/12 Removed PFET values
-/// \version --------------------------------------------------------------------------
-/// \version 1.2 rmaier 12/05/11 Hardcoded valid chiplets ... need to be removed again fapiGetExistingChiplets  =>  fapiGetChildChiplets
-/// \version --------------------------------------------------------------------------
-/// \version 1.1 rmaier 11/30/11 eCMD 12.2 adaptions. fapiGetExistingChiplets  =>  fapiGetChildChiplets , Scan0 values set
-/// \version --------------------------------------------------------------------------
-/// \version 1.0 rmaier 10/17/11 Initial Version - RESET mode
-/// \version ---------------------------------------------------------------------------
-///
-/// \todo   command order
-/// \todo   next --  > initialize all pm_reg with scan-zero values upfront
-/// \todo   Clear definition/doc of parms and attributes required  at the beginning.
-/// \todo   GP3 Changes Winkle fence changes
-/// \todo   Review
-///
-/// High-level procedure flow:
-///
 /// \verbatim
+/// High-level procedure flow:
 ///
 ///  Procedure Prereq:
 ///  - completed istep procedure
@@ -311,7 +257,7 @@
 /// OLD-DOC - Restore to Deep Sleep and Deep Winkle upon reset
 /// OLD-DOC - PMCR default value adjustment (Hardware flush 0 -> restore to 0 for
 ///     reset case) SCAN0
-/// OLD-DOC     -For reset case, disable all “global_en” bits in PMCR and PMICR;
+/// OLD-DOC     -For reset case, disable all “global_en” bits in PMCR and PMICR;
 ///                 this keeps Global Pstate Request from occuring to the PMC until
 ///                 it has been initialized.  OCCFW to be do this
 /// OLD-DOC - PMICR default value adjustment (Hardware flush 0 -> restore to 0 for
@@ -326,6 +272,7 @@
 // Includes
 // -----------------------------------------------------------------------------
 #include "p8_pm.H"
+#include "p8_pm_utils.H"
 #include "p8_pcbs_init.H"
 
 
@@ -404,7 +351,7 @@ CONST_UINT64_T( EX_ECOPFPUDly_REG_0x100F014C_scan0                      ,  ULL(0
 CONST_UINT64_T( EX_ECOPFPDDly_REG_0x100F014D_scan0                      ,  ULL(0x00000000));
 CONST_UINT64_T( EX_ECOPFVRET_REG_0x100F0150_scan0                       ,  ULL(0x00000000));
 CONST_UINT64_T( EX_FREQCNTL_0x100F0151_scan0                            ,  ULL(0x32320000));   // "0011 0010 0011 0010 000000000000" ;
-CONST_UINT64_T( EX_DPLL_CPM_PARM_REG_0x100F0152_scan0                   ,  ULL(0x00000200));   // "0000 0000 0000 0000 0000 0010 0000000" ;
+CONST_UINT64_T( EX_DPLL_CPM_PARM_REG_0x100F0152_scan0                   ,  ULL(0x00004000));   // 64us for DPLL Lock replacement
 CONST_UINT64_T( EX_PCBS_iVRM_Control_Status_Reg_0x100F0154_scan0        ,  ULL(0x00000000));
 CONST_UINT64_T( EX_PCBS_iVRM_Value_Setting_Reg_0x100F0155_scan0         ,  ULL(0x00000000));
 CONST_UINT64_T( EX_PCBSPM_MODE_REG_0x100F0156_scan0                     ,  ULL(0x01000000));    //"0000 0001 0000 0000 00" ;
@@ -449,16 +396,10 @@ pcbs_init  (  const fapi::Target& i_target);
 fapi::ReturnCode
 pcbs_scan0(const Target &i_target, uint8_t i_ex_number);
 
-// FIR trace function
-fapi::ReturnCode
-glob_fir_trace  (   const fapi::Target& i_target,
-                    const char * i_msg);
-
 // ----------------------------------------------------------------------
 // Function definitions
 // ----------------------------------------------------------------------
 
-
 // ----------------------------------------------------------------------
 /**
  * p8_pcbs_init calls the underlying routine based on mode parameter
@@ -482,6 +423,15 @@ p8_pcbs_init( const Target& i_target, uint32_t i_mode)
 
     do
     {
+        uint8_t ipl_mode = 0;
+        rc = FAPI_ATTR_GET(ATTR_IS_MPIPL, NULL, ipl_mode);
+        if (!rc.ok())
+        {
+            FAPI_ERR("fapiGetAttribute of ATTR_IS_MPIPL rc = 0x%x", (uint32_t)rc);
+            break;
+        }
+        
+        FAPI_INF("IPL mode = %s", ipl_mode ? "MPIPL" : "NORMAL");
 
         if ( i_mode == PM_CONFIG )
         {
@@ -626,31 +576,41 @@ pcbs_init(const Target& i_target)
             FAPI_DBG("Core number = %d", l_ex_number);
 
             ex_offset = l_ex_number * 0x01000000;
-
-            // Set DPLL Lock Replacement value (15:23) = 2 (eg bit 22 = 1)
-            FAPI_INF ("Set DPLL Lock Replacement value of EX_DPLL_CPM_PARM_REG_0x1*0F0152 ");
-
-            address =  EX_DPLL_CPM_PARM_REG_0x100F0152 + ex_offset;
-            GETSCOM(rc, i_target, address, data);
-
-            e_rc  = data.setBit(22);
-            E_RC_CHECK(e_rc, rc);
-
-            PUTSCOM(rc, i_target, address, data);
-
+            
             //  ******************************************************************
-            //  - Enable DPLL Lock Replacement mode
+            //  FSM trace
             //  ******************************************************************
-            FAPI_INF("Set DPLL Lock Replacement mode");
-
-            address = EX_PCBSPM_MODE_REG_0x100F0156 + ex_offset;
-
-            GETSCOM(rc, i_target, address, data );
-
-            e_rc |= data.setBit(7);
-            E_RC_CHECK(e_rc, rc);
+            rc = p8_pm_pcbs_fsm_trace (i_target, l_ex_number, "beginning of pbcs_init");
+            if (!rc.ok()) 
+            {
+                break;
+            }
 
-            PUTSCOM(rc, i_target, address, data );
+// Removed in deference to the setting by SBE code
+//            // Set DPLL Lock Replacement value (15:23) = 2 (eg bit 22 = 1)
+//            FAPI_INF ("Set DPLL Lock Replacement value of EX_DPLL_CPM_PARM_REG_0x1*0F0152 ");
+//
+//            address =  EX_DPLL_CPM_PARM_REG_0x100F0152 + ex_offset;
+//            GETSCOM(rc, i_target, address, data);
+//
+//            e_rc  = data.setBit(22);
+//            E_RC_CHECK(e_rc, rc);
+//
+//            PUTSCOM(rc, i_target, address, data);
+//
+//            //  ******************************************************************
+//            //  - Enable DPLL Lock Replacement mode
+//            //  ******************************************************************
+//            FAPI_INF("Set DPLL Lock Replacement mode");
+//
+//            address = EX_PCBSPM_MODE_REG_0x100F0156 + ex_offset;
+//
+//            GETSCOM(rc, i_target, address, data );
+//
+//            e_rc |= data.setBit(7);
+//            E_RC_CHECK(e_rc, rc);
+//
+//            PUTSCOM(rc, i_target, address, data );
 
             //  ******************************************************************
             //  - set PCBS_PM_PMGP1_REG_1
@@ -700,7 +660,17 @@ pcbs_init(const Target& i_target)
                 PUTSCOM(rc, i_target, address, data);    
                 FAPI_IMP("WARNING: resonant clocking was NOT properly disabled");            
                 FAPI_IMP("  Not currently failing until real resonant disable is available");            
-            }       
+            }    
+            
+            
+            //  ******************************************************************
+            //  FSM trace
+            //  ******************************************************************
+            rc = p8_pm_pcbs_fsm_trace (i_target, l_ex_number, "after ResClk");
+            if (!rc.ok()) 
+            {
+                break;
+            }   
 
             //  ******************************************************************
             //  - Power Management Control Reg
@@ -728,6 +698,15 @@ pcbs_init(const Target& i_target)
 
             FAPI_INF ("PMCR default value adjustment (Hardware flush 0) of EX_PCBS_Power_Management_Idle_Control_Reg_0x1*0F0158 " );
             
+            
+            //  ******************************************************************
+            //  FSM trace
+            //  ******************************************************************
+            rc = p8_pm_pcbs_fsm_trace (i_target, l_ex_number, "after PMCR and PMICR");
+            if (!rc.ok()) 
+            {
+                break;
+            }            
         
             //  ******************************************************************
             //  - Power Management Error Reg
@@ -748,7 +727,7 @@ pcbs_init(const Target& i_target)
                                chipHasPcbsErrReset);
             if(rc)
             {
-                FAPI_ERR("Error querying Chip EC feature: "
+     		    FAPI_ERR("Error querying Chip EC feature: "
                          "ATTR_CHIP_EC_FEATURE_PCBS_ERR_RESET");
                 break;
             }
@@ -761,6 +740,15 @@ pcbs_init(const Target& i_target)
             {
                 // Write anything to the register to clear it.                
                 PUTSCOM(rc, i_target, address, data);            
+            }           
+            
+            //  ******************************************************************
+            //  FSM trace
+            //  ******************************************************************
+            rc = p8_pm_pcbs_fsm_trace (i_target, l_ex_number, "after Power Management Error Reg");
+            if (!rc.ok()) 
+            {
+                break;
             }
 
         }  //END FOR
@@ -863,7 +851,7 @@ pcbs_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_init)
                                chipHasPcbIntrFixed);
         if(rc)
         {
-            FAPI_ERR("Error querying Chip EC feature: "
+     	    FAPI_ERR("Error querying Chip EC feature: "
                      "ATTR_CHIP_EC_FEATURE_PCBS_ERR_RESET");
             break;
         }
@@ -936,7 +924,7 @@ pcbs_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_init)
                     //PUTSCOM(rc, i_target, address, data);
 
 
-                    rc = glob_fir_trace (i_target, "after setting force safe mode bit");
+                    rc = p8_pm_glob_fir_trace (i_target, "after setting force safe mode bit");
                     if (!rc.ok()) 
                     {
                         break;
@@ -1016,10 +1004,19 @@ pcbs_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_init)
             } // Pstates enabled
             
             //  ******************************************************************
+            //  FSM trace
+            //  ******************************************************************
+            rc = p8_pm_pcbs_fsm_trace (i_target, l_ex_number, "after setting force safe mode poll");
+            if (!rc.ok()) 
+            {
+                break;
+            }
+            
+            //  ******************************************************************
             //  Check for xstops and recoverables
             //  ******************************************************************
 
-            rc = glob_fir_trace (i_target, "after force safe mode poll");
+            rc = p8_pm_glob_fir_trace (i_target, "after force safe mode poll");
             if (!rc.ok()) 
             {
                 break;
@@ -1058,9 +1055,18 @@ pcbs_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_init)
             PUTSCOM(rc, i_target, address, data);
             
             //  ******************************************************************
+            //  FSM trace
+            //  ******************************************************************
+            rc = p8_pm_pcbs_fsm_trace (i_target, l_ex_number, "after DPLL settings");
+            if (!rc.ok()) 
+            {
+                break;
+            }
+            
+            //  ******************************************************************
             //  Check for xstops and recoverables
             //  ******************************************************************
-            rc = glob_fir_trace (i_target, "after FREQ_CTRL_REG");
+            rc = p8_pm_glob_fir_trace (i_target, "after FREQ_CTRL_REG");
             if (!rc.ok()) 
             {
                 break;
@@ -1076,9 +1082,18 @@ pcbs_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_init)
             PUTSCOM(rc, i_target, address, data);
             
             //  ******************************************************************
+            //  FSM trace
+            //  ******************************************************************
+            rc = p8_pm_pcbs_fsm_trace (i_target, l_ex_number, "after hold DPLL");
+            if (!rc.ok()) 
+            {
+                break;
+            }
+            
+            //  ******************************************************************
             //  Check for xstops and recoverables
             //  ******************************************************************
-            rc = glob_fir_trace (i_target, "after hold DPLL");
+            rc = p8_pm_glob_fir_trace (i_target, "after hold DPLL");
             if (!rc.ok()) 
             {
                 break;
@@ -1101,9 +1116,18 @@ pcbs_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_init)
             PUTSCOM(rc, i_target, address, data );
             
             //  ******************************************************************
+            //  FSM trace
+            //  ******************************************************************
+            rc = p8_pm_pcbs_fsm_trace (i_target, l_ex_number, "after disable Pstates");
+            if (!rc.ok()) 
+            {
+                break;
+            }
+            
+            //  ******************************************************************
             //  Check for xstops and recoverables
             //  ******************************************************************
-            rc = glob_fir_trace (i_target, "after disable Pstates");
+            rc = p8_pm_glob_fir_trace (i_target, "after disable Pstates");
             if (!rc.ok()) 
             {
                 break;
@@ -1199,9 +1223,18 @@ pcbs_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_init)
             FAPI_INF ("Disabled RESCLK, set bit 22 of GP3_REG_0_RWXx1*0F0012 " );
             
             //  ******************************************************************
+            //  FSM trace
+            //  ******************************************************************
+            rc = p8_pm_pcbs_fsm_trace (i_target, l_ex_number, "after setting force safe mode poll");
+            if (!rc.ok()) 
+            {
+                break;
+            }
+            
+            //  ******************************************************************
             //  Check for xstops and recoverables
             //  ******************************************************************
-            rc = glob_fir_trace (i_target, "after RESCLK");
+            rc = p8_pm_glob_fir_trace (i_target, "after RESCLK");
             if (!rc.ok()) 
             {
                 break;
@@ -1255,9 +1288,18 @@ pcbs_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_init)
             }
             
             //  ******************************************************************
+            //  FSM trace
+            //  ******************************************************************
+            rc = p8_pm_pcbs_fsm_trace (i_target, l_ex_number, "after iVRM disable");
+            if (!rc.ok()) 
+            {
+                break;
+            }
+            
+            //  ******************************************************************
             //  Check for xstops and recoverables
             //  ******************************************************************
-            rc = glob_fir_trace (i_target, "after IVRM Disable");
+            rc = p8_pm_glob_fir_trace (i_target, "after IVRM Disable");
             if (!rc.ok()) 
             {
                 break;
@@ -1313,12 +1355,20 @@ pcbs_reset(const Target &i_target, struct_pcbs_val_init_type &pcbs_val_init)
             //  ******************************************************************
             //  Check for xstops and recoverables
             //  ******************************************************************
-            rc = glob_fir_trace (i_target, "after SCAN0");
+            rc = p8_pm_glob_fir_trace (i_target, "after SCAN0");
             if (!rc.ok()) 
             {
                 break;
             }  
-
+            
+            //  ******************************************************************
+            //  FSM trace
+            //  ******************************************************************
+            rc = p8_pm_pcbs_fsm_trace (i_target, l_ex_number, "after PCBS scan0");
+            if (!rc.ok()) 
+            {
+                break;
+            }
 
         } // Chiplet loop
     } while(0);
@@ -1351,7 +1401,7 @@ pcbs_scan0(const Target &i_target, uint8_t i_ex_number)
     uint64_t                    address;
     uint64_t                    ex_offset;
     uint64_t                    reset_doubleword;
-    uint32_t                    reset_word;
+//    uint32_t                    reset_word;
 
     do
     {
@@ -1385,12 +1435,13 @@ pcbs_scan0(const Target &i_target, uint8_t i_ex_number)
         //      by register accesses
 
         //----
-        address =  EX_PCBS_Resonant_Clock_Control_Reg0_0x100F0165 + ex_offset;
-        reset_doubleword = EX_PCBS_Resonant_Clock_Control_Reg0_0x100F0165_scan0;
-        SETDWSCAN0(i_target, address, data, reset_doubleword );
-        
-        rc = glob_fir_trace (i_target, "after scan0 EX_PCBS_Resonant_Clock_Control_Reg0_0x100F0165");
-        if (!rc.ok()) { break; }  
+// will be setup by GPSM;  not need to reset
+//         address =  EX_PCBS_Resonant_Clock_Control_Reg0_0x100F0165 + ex_offset;
+//         reset_doubleword = EX_PCBS_Resonant_Clock_Control_Reg0_0x100F0165_scan0;
+//         SETDWSCAN0(i_target, address, data, reset_doubleword );
+//         
+//         rc = p8_pm_glob_fir_trace (i_target, "after scan0 EX_PCBS_Resonant_Clock_Control_Reg0_0x100F0165");
+//         if (!rc.ok()) { break; }  
 
         //----
         address =  EX_PMErrMask_REG_0x100F010A + ex_offset;
@@ -1400,155 +1451,95 @@ pcbs_scan0(const Target &i_target, uint8_t i_ex_number)
         reset_doubleword = EX_PMErrMask_REG_0x100F010A_scan0;
         SETDWSCAN0(i_target, address, data, reset_doubleword );
 
-        rc = glob_fir_trace (i_target, "after scan0 EX_PMErrMask_REG_0x100F010A");
+        rc = p8_pm_glob_fir_trace (i_target, "after scan0 EX_PMErrMask_REG_0x100F010A");
         if (!rc.ok()) { break; }  
 
 
         // OCC does not mess with the PFET delays so these are left in tact.
 
         //  This can only be done IF the IVRM is previously  disabled.
-        address =  EX_PCBS_iVRM_Control_Status_Reg_0x100F0154 + ex_offset;
-        reset_word = EX_PCBS_iVRM_Control_Status_Reg_0x100F0154_scan0;
-        SETSCAN0(i_target, address, data, reset_word );
-        
-        rc = glob_fir_trace (i_target, "after scan0 EX_PCBS_iVRM_Control_Status_Reg_0x100F0154");
-        if (!rc.ok()) { break; }  
+// Should be done by an explicit iVRM disable routine as all bits don't really 
+// need to touched
+//         address =  EX_PCBS_iVRM_Control_Status_Reg_0x100F0154 + ex_offset;
+//         reset_word = EX_PCBS_iVRM_Control_Status_Reg_0x100F0154_scan0;
+//         SETSCAN0(i_target, address, data, reset_word );
+//         
+//         rc = p8_pm_glob_fir_trace (i_target, "after scan0 EX_PCBS_iVRM_Control_Status_Reg_0x100F0154");
+//         if (!rc.ok()) { break; }  
+// 
+//         //----
+//         address =  EX_PCBS_iVRM_Value_Setting_Reg_0x100F0155 + ex_offset;
+//         reset_word = EX_PCBS_iVRM_Value_Setting_Reg_0x100F0155_scan0;
+//         SETSCAN0(i_target, address, data, reset_word );
+//         
+//         rc = p8_pm_glob_fir_trace (i_target, "after scan0 EX_PCBS_iVRM_Value_Setting_Reg_0x100F0155");
+//         if (!rc.ok()) { break; }  
 
         //----
-        address =  EX_PCBS_iVRM_Value_Setting_Reg_0x100F0155 + ex_offset;
-        reset_word = EX_PCBS_iVRM_Value_Setting_Reg_0x100F0155_scan0;
-        SETSCAN0(i_target, address, data, reset_word );
-        
-        rc = glob_fir_trace (i_target, "after scan0 EX_PCBS_iVRM_Value_Setting_Reg_0x100F0155");
-        if (!rc.ok()) { break; }  
+// This actually has a danger as Global Actual of 0 is Turbo!!!!
+// 
+//         address =  EX_PCBS_PMC_VF_CTRL_REG_0x100F015A + ex_offset;
+//         reset_word = EX_PCBS_PMC_VF_CTRL_REG_0x100F015A_scan0;
+//         SETSCAN0(i_target, address, data, reset_word );
+//         
+//         rc = p8_pm_glob_fir_trace (i_target, "after scan0 EX_PCBS_PMC_VF_CTRL_REG_0x100F015A");
+//         if (!rc.ok()) { break; }  
 
         //----
-        address =  EX_PCBS_PMC_VF_CTRL_REG_0x100F015A + ex_offset;
-        reset_word = EX_PCBS_PMC_VF_CTRL_REG_0x100F015A_scan0;
-        SETSCAN0(i_target, address, data, reset_word );
-        
-        rc = glob_fir_trace (i_target, "after scan0 EX_PCBS_PMC_VF_CTRL_REG_0x100F015A");
-        if (!rc.ok()) { break; }  
-
-        //----
-        address =  EX_PCBS_Pstate_Index_Bound_Reg_0x100F015C + ex_offset;
-        reset_word = EX_PCBS_Pstate_Index_Bound_Reg_0x100F015C_scan0;
-        SETSCAN0(i_target, address, data, reset_word );
-        
-        rc = glob_fir_trace (i_target, "after scan0 EX_PCBS_Pstate_Index_Bound_Reg_0x100F015C");
-        if (!rc.ok()) { break; }  
+// Applies only to iVRMs. However, this is re-written by GPSM upon LPST installation
+// No real need to clear it.
+//         address =  EX_PCBS_Pstate_Index_Bound_Reg_0x100F015C + ex_offset;
+//         reset_word = EX_PCBS_Pstate_Index_Bound_Reg_0x100F015C_scan0;
+//         SETSCAN0(i_target, address, data, reset_word );
+//         
+//         rc = p8_pm_glob_fir_trace (i_target, "after scan0 EX_PCBS_Pstate_Index_Bound_Reg_0x100F015C");
+//         if (!rc.ok()) { break; }  
 
         //----
-        address =  EX_PCBS_PSTATE_TABLE_CTRL_REG_0x100F015E + ex_offset;
-        reset_word = EX_PCBS_PSTATE_TABLE_CTRL_REG_0x100F015E_scan0;
-        SETSCAN0(i_target, address, data, reset_word );
-        
-        rc = glob_fir_trace (i_target, "after scan0 EX_PCBS_PSTATE_TABLE_CTRL_REG_0x100F015E");
-        if (!rc.ok()) { break; }  
+// Applies only to iVRMs. However, this is re-written by GPSM upon LPST installation
+// No real need to clear it.
+//         address =  EX_PCBS_PSTATE_TABLE_CTRL_REG_0x100F015E + ex_offset;
+//         reset_word = EX_PCBS_PSTATE_TABLE_CTRL_REG_0x100F015E_scan0;
+//         SETSCAN0(i_target, address, data, reset_word );
+//         
+//         rc = p8_pm_glob_fir_trace (i_target, "after scan0 EX_PCBS_PSTATE_TABLE_CTRL_REG_0x100F015E");
+//         if (!rc.ok()) { break; }  
 
         //----
-        address =  EX_PCBS_iVRM_VID_Control_Reg0_0x100F0162  + ex_offset;
-        reset_word = EX_PCBS_iVRM_VID_Control_Reg0_0x100F0162_scan0;
-        SETSCAN0(i_target, address, data, reset_word );
-        
-        rc = glob_fir_trace (i_target, "after scan0 EX_PCBS_iVRM_VID_Control_Reg0_0x100F0162");
-        if (!rc.ok()) { break; }  
+// Applies only to iVRMs. However, this is re-written by GPSM upon LPST installation
+// No real need to clear it.   
+//         address =  EX_PCBS_iVRM_VID_Control_Reg0_0x100F0162  + ex_offset;
+//         reset_word = EX_PCBS_iVRM_VID_Control_Reg0_0x100F0162_scan0;
+//         SETSCAN0(i_target, address, data, reset_word );
+//         
+//         rc = p8_pm_glob_fir_trace (i_target, "after scan0 EX_PCBS_iVRM_VID_Control_Reg0_0x100F0162");
+//         if (!rc.ok()) { break; }  
 
         //----
-        address =  EX_PCBS_iVRM_VID_Control_Reg1_0x100F0163 + ex_offset;
-        reset_word = EX_PCBS_iVRM_VID_Control_Reg1_0x100F0163_scan0;
-        SETSCAN0(i_target, address, data, reset_word );
-        
-        rc = glob_fir_trace (i_target, "after scan0 EX_PCBS_iVRM_VID_Control_Reg1_0x100F0163");
-        if (!rc.ok()) { break; }  
+// Applies only to iVRMs. However, this is re-written by GPSM upon LPST installation
+// No real need to clear it. 
+//         address =  EX_PCBS_iVRM_VID_Control_Reg1_0x100F0163 + ex_offset;
+//         reset_word = EX_PCBS_iVRM_VID_Control_Reg1_0x100F0163_scan0;
+//         SETSCAN0(i_target, address, data, reset_word );
+//         
+//         rc = p8_pm_glob_fir_trace (i_target, "after scan0 EX_PCBS_iVRM_VID_Control_Reg1_0x100F0163");
+//         if (!rc.ok()) { break; }  
 
         //----
-        address =  EX_PCBS_Resonant_Clock_Control_Reg1_0x100F0166 + ex_offset;
-        reset_word = EX_PCBS_Resonant_Clock_Control_Reg1_0x100F0166_scan0;
-        SETSCAN0(i_target, address, data, reset_word );
-        
-        rc = glob_fir_trace (i_target, "after scan0 EX_PCBS_Resonant_Clock_Control_Reg1_0x100F0166");
-        if (!rc.ok()) { break; }  
+// Applies only to resonant clocks only. However, this is re-written by GPSM upon 
+// enalement of resonant clocks. No real need to clear it.
+//         address =  EX_PCBS_Resonant_Clock_Control_Reg1_0x100F0166 + ex_offset;
+//         reset_word = EX_PCBS_Resonant_Clock_Control_Reg1_0x100F0166_scan0;
+//         SETSCAN0(i_target, address, data, reset_word );
+//         
+//         rc = p8_pm_glob_fir_trace (i_target, "after scan0 EX_PCBS_Resonant_Clock_Control_Reg1_0x100F0166");
+//         if (!rc.ok()) { break; }  
      
     } while(0);
     return rc;
 }
 
 
-//------------------------------------------------------------------------------
-/**
- * Trace a set of FIRs (Globals and select Locals)
- *
- * @param[in] i_target Chip target
- * @param[in] i_msg    String to put out in the trace
- *
- * @retval ECMD_SUCCESS
- * @retval ERROR defined in xml
- */
-fapi::ReturnCode
-glob_fir_trace  (   const fapi::Target& i_target,
-                    const char * i_msg)
-{
-    fapi::ReturnCode                rc;
-    ecmdDataBufferBase              data(64);
-    uint64_t                        address;
-    
-    CONST_UINT64_T( GLOB_XSTOP_FIR_0x01040000                                 , ULL(0x01040000) );
-    CONST_UINT64_T( GLOB_RECOV_FIR_0x01040001                                 , ULL(0x01040001) );
-    CONST_UINT64_T( TP_LFIR_0x0104000A                                        , ULL(0x0104000A) );
-
-    do
-    {
-        //  ******************************************************************
-        //  Check for xstops and recoverables and put in the trace
-        //  ******************************************************************
-        address =  READ_GLOBAL_XSTOP_FIR_0x570F001B;
-        GETSCOM(rc, i_target, address, data);
-        if (data.getNumBitsSet(0,64))
-        {
-            FAPI_INF("Xstop is **ACTIVE** %s", i_msg);
-        }           
-
-        address =  READ_GLOBAL_RECOV_FIR_0x570F001C;
-        GETSCOM(rc, i_target, address, data);
-        if (data.getNumBitsSet(0,64))
-        {
-            FAPI_INF("Recoverable attention is **ACTIVE** %s", i_msg);
-        }
-
-        address =  READ_GLOBAL_RECOV_FIR_0x570F001C;
-        GETSCOM(rc, i_target, address, data);
-        if (data.getNumBitsSet(0,64))
-        {
-            FAPI_INF("Recoverable attention is **ACTIVE** %s", i_msg);
-        }
-
-        address =  GLOB_XSTOP_FIR_0x01040000;
-        GETSCOM(rc, i_target, address, data);
-        if (data.getNumBitsSet(0,64))
-        {
-            FAPI_INF("Glob Xstop FIR is **ACTIVE** %s", i_msg);
-        }
-
-        address =  GLOB_RECOV_FIR_0x01040001;
-        GETSCOM(rc, i_target, address, data);
-        if (data.getNumBitsSet(0,64))
-        {
-            FAPI_INF("Glob Recov FIR is **ACTIVE** %s", i_msg);
-        }
-
-        address =  TP_LFIR_0x0104000A;
-        GETSCOM(rc, i_target, address, data);
-        if (data.getNumBitsSet(0,64))
-        {
-            FAPI_INF("TP LFIR is **ACTIVE** %s", i_msg);
-        }
-                        
-    } while(0);
-    return rc;
-}
-
-
 } //end extern C
 
 /*
@@ -1557,8 +1548,15 @@ This section is automatically updated by CVS when you check in this file.
 Be sure to create CVS comments when you commit so that they can be included here.
 
 $Log: p8_pcbs_init.C,v $
+Revision 1.27  2014/02/17 03:00:35  stillgs
+- After review (in dealing with  SW240169), removed most *scan0 statements as they were more detrimental than valuable.
+  The testcase for SW242617 should be run with this change
+- Added PCBS and Global FIR trace points for hang debug using common routines in p8_pm_utils.C
+- Added MPIPL debug message
+- Removed old comments (the *scan0 one above were left in until regressions fully pass)
+
 Revision 1.26  2014/01/29 17:54:51  cswenson
-changed char* to const char* in glob_fir_trace()
+changed char* to const char* in p8_pm_glob_fir_trace()
 
 Revision 1.25  2014/01/22 20:58:31  stillgs
 
diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_init.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_init.C
index 9034b3751..12c273e40 100644
--- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_init.C
+++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_init.C
@@ -20,8 +20,8 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_pm_init.C,v 1.23 2013/12/03 19:42:40 stillgs Exp $
-// $Source: /archive/shadow/ekb/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_init.C,v $
+// $Id: p8_pm_init.C,v 1.24 2014/02/17 02:57:00 stillgs Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_init.C,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
 // *! All Rights Reserved -- Property of IBM
@@ -42,19 +42,16 @@
 // *! Procedure Prereq:
 // *!   o System clocks are running
 // *!
+// *| buildfapiprcd -C p8_pm_utils.C p8_pm_init.C
 //------------------------------------------------------------------------------
 ///
 /// \version -------------------------------------------------------------------
 /// \version 1.0 stillgs 2012/03/06 Initial Version
 /// \version -------------------------------------------------------------------
 ///
-///
-/// \todo   Review
-///
+/// \verbatim
 ///
 /// High-level procedure flow:
-///
-/// \verbatim
 ///     - call p8_pm_prep_for_reset to prepare and perform getting the PM function
 ///         able to be be (re)initialized
 ///
@@ -93,6 +90,7 @@
 // ----------------------------------------------------------------------
 
 #include "p8_pm.H"
+#include "p8_pm_utils.H"
 #include "p8_pm_init.H"
 #include "p8_pm_prep_for_reset.H"
 
@@ -112,14 +110,12 @@ using namespace fapi;
 // Function prototypes
 // ----------------------------------------------------------------------
 
-// ----------------------------------------------------------------------
-// Function definitions
-// ----------------------------------------------------------------------
 fapi::ReturnCode 
 pm_list(const Target& i_target, const Target& i_target2, uint32_t i_mode);
 
 fapi::ReturnCode
 clear_occ_special_wakeups (const fapi::Target &i_target);
+
   
 // ----------------------------------------------------------------------
 // p8_pm_init
@@ -585,7 +581,16 @@ pm_list(const Target& i_target, const Target& i_target2, uint32_t i_mode)
                     break;
                 }                  
             } 
+                        
         } // PM_INIT special stuff
+        
+        //  Check for xstops and recoverables
+        rc = p8_pm_glob_fir_trace (i_target, "end of p8_pm_init_list");
+        if (!rc.ok()) 
+        {
+            break;
+        }  
+
     } while(0);
 
     FAPI_INF("p8_pm_list end in mode %s", PM_MODE_NAME(i_mode));
@@ -660,3 +665,4 @@ clear_occ_special_wakeups (const fapi::Target &i_target)
 
 
 } //end extern C
+
diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_prep_for_reset.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_prep_for_reset.C
index aca25038f..a28e2d873 100644
--- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_prep_for_reset.C
+++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_prep_for_reset.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2013                   */
+/* COPYRIGHT International Business Machines Corp. 2013,2014              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,26 +20,27 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_pm_prep_for_reset.C,v 1.25 2013/10/30 17:13:09 stillgs Exp $
+// $Id: p8_pm_prep_for_reset.C,v 1.27 2014/02/19 16:10:40 stillgs Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_prep_for_reset.C,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
 // *! All Rights Reserved -- Property of IBM
 // *! *** IBM Confidential ***
 //------------------------------------------------------------------------------
+// *! OWNER NAME: Greg Still         Email: stillgs@us.ibm.com
 // *! OWNER NAME: Ralf Maier         Email: ralf.maier@de.ibm.com
 // *!
 /// \file p8_pm_prep_for_reset.C
 /// \brief Initialize powermanagement
-/// *!
-// *! Procedure Prereq:
-// *!   o System clocks are running
-// *!
+/// 
 //------------------------------------------------------------------------------
 ///
 /// High-level procedure flow:
 ///
 /// \verbatim
+///     - call p8_pm_firinit  *chiptarget, 
+///             - Mask the PM FIRs
+///
 ///     - call p8_occ_control.C *chiptarget, ENUM:OCC_STOP      ppc405_reset_ctrl = 2
 ///             - OCC PPC405 put into reset
 ///             - PMC moves to Vsafe value due to heartbeat loss
@@ -64,17 +65,19 @@
 ///     - call p8_ocb_init .C *chiptarget, ENUM:OCC_OCB_RESET
 ///
 ///     SLW engine reset is not done here as this will blow away all setup
-///     in istep 15.  Thus, ALL manipulation of this is done there or by
-///     p8_poreslw_recovery.
+///     in istep 15.  Thus, ALL manipulation of this is via calls to 
+///     p8_poreslw_ioit or by p8_poreslw_recovery.
 ///
 ///  \endverbatim
 ///
-
+///  buildfapiprcd -e "../../xml/error_info/p8_pm_prep_for_reset_errors.xml" -C p8_pm_utils.C p8_pm_prep_for_reset.C
 // ----------------------------------------------------------------------
 // Includes
 // ----------------------------------------------------------------------
 
+#include "fapiUtil.H"
 #include "p8_pm.H"
+#include "p8_pm_utils.H"
 #include "p8_pm_prep_for_reset.H"
 
 extern "C" {
@@ -96,6 +99,12 @@ using namespace fapi;
 fapi::ReturnCode
 special_wakeup_all (const fapi::Target &i_target, bool i_action);
 
+// FSM trace wrapper                 
+fapi::ReturnCode
+p4rs_pcbs_fsm_trace (const fapi::Target& i_primary_target,
+                     const fapi::Target& i_secondary_target,       
+                     const char *        i_msg);
+                   
 // ----------------------------------------------------------------------
 // Function definitions
 // ----------------------------------------------------------------------
@@ -123,12 +132,17 @@ p8_pm_prep_for_reset(   const fapi::Target &i_primary_chip_target,
 {
 
     fapi::ReturnCode                rc;
+    fapi::ReturnCode                rc_hold;
 
     std::vector<fapi::Target>       l_exChiplets;
     ecmdDataBufferBase              data(64);
-    ecmdDataBufferBase              mask(64);
+    ecmdDataBufferBase              mask(64);    
+    uint64_t                        address = 0;
 
     const char *        PM_MODE_NAME_VAR; // Defines storage for PM_MODE_NAME
+    
+    bool                            b_special_wakeup_pri = false;
+    bool                            b_special_wakeup_sec = false;
 
     fapi::Target dummy;
 
@@ -137,6 +151,17 @@ p8_pm_prep_for_reset(   const fapi::Target &i_primary_chip_target,
 
         FAPI_INF("p8_pm_prep_for_reset start  ....");
 
+        uint8_t ipl_mode = 0;
+        rc = FAPI_ATTR_GET(ATTR_IS_MPIPL, NULL, ipl_mode);
+        if (!rc.ok())
+        {
+            FAPI_ERR("fapiGetAttribute of ATTR_IS_MPIPL rc = 0x%x", (uint32_t)rc);
+            break;
+        }
+        
+        FAPI_INF("IPL mode = %s", ipl_mode ? "MPIPL" : "NORMAL");
+
+
         if (i_mode == PM_RESET)
         {
             FAPI_INF("Hard reset detected");
@@ -162,44 +187,27 @@ p8_pm_prep_for_reset(   const fapi::Target &i_primary_chip_target,
                 FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PREP_TARGET_ERR);
                 break;
             }
-            FAPI_DBG("Running on SCM");
+            FAPI_INF("Running on SCM");
         }
         else
         {
-            FAPI_DBG("Running on DCM");
+            FAPI_INF("Running on DCM");
         }
-
-        //  ******************************************************************
-        //  Put OCC PPC405 into reset
-        //  ******************************************************************
+        
         //  ******************************************************************
-        //  - call p8_occ_control.C *chiptarget, ENUM:OCC_STOP      ppc405_reset_ctrl = 2s
-        //
+        //  FSM trace
         //  ******************************************************************
-
-        FAPI_INF("Put OCC PPC405 into reset");
-        FAPI_DBG("Executing: p8_occ_control.C");
-
-        FAPI_EXEC_HWP(rc, p8_occ_control, i_primary_chip_target, PPC405_RESET_ON, 0);
-        if (rc)
+        rc = p4rs_pcbs_fsm_trace (i_primary_chip_target, i_secondary_chip_target, "start of prep for reset");
+        if (!rc.ok()) 
         {
-            FAPI_ERR("p8_occ_control: Failed to prepare OCC for RESET. With rc = 0x%x", (uint32_t)rc);
             break;
         }
-
-        if ( i_secondary_chip_target.getType() != TARGET_TYPE_NONE )
-        {
-            FAPI_EXEC_HWP(rc, p8_occ_control, i_secondary_chip_target, PPC405_RESET_ON, 0);
-            if (rc)
-            {
-              FAPI_ERR("p8_occ_control: Failed to prepare OCC for RESET. With rc = 0x%x", (uint32_t)rc);
-              break;
-            }
-        }
-
+        
         //  ******************************************************************
-        //  Put all EX chiplet special wakeup
+        //  Put all EX chiplets in special wakeup       
         //  *****************************************************************
+        //  This is done before FIR masking to ensure that idle functions
+        //  are properly monitored
                 
         // Primary
         rc = special_wakeup_all (i_primary_chip_target, true);
@@ -208,9 +216,12 @@ p8_pm_prep_for_reset(   const fapi::Target &i_primary_chip_target,
             FAPI_ERR("special_wakeup_all - Enable: Failed for Target %s", 
                         i_primary_chip_target.toEcmdString());
             break;
-        }
+        }        
+        b_special_wakeup_pri = true;
+               
+        rc = p8_pm_glob_fir_trace (i_primary_chip_target, "after SPWKUP");
+        if (!rc.ok()) { break; }  
                 
-
         // Secondary
         if ( i_secondary_chip_target.getType() != TARGET_TYPE_NONE )
         {
@@ -221,13 +232,26 @@ p8_pm_prep_for_reset(   const fapi::Target &i_primary_chip_target,
                             i_secondary_chip_target.toEcmdString());
                 break;
             }
-
+            b_special_wakeup_sec = true;  
+            
+            rc = p8_pm_glob_fir_trace (i_secondary_chip_target, "after SPWKUP");
+            if (!rc.ok()) { break; }  
+            
+        }  
+                       
+        //  ******************************************************************
+        //  FSM trace
+        //  ******************************************************************
+        rc = p4rs_pcbs_fsm_trace (i_primary_chip_target, i_secondary_chip_target, 
+                    "after special wake-up setting");
+        if (!rc.ok()) 
+        {
+            break;
         }
 
         //  ******************************************************************
-        //  Mask the FIRs
+        //  Mask the FIRs as error can occur in what follows
         //  ******************************************************************
-
         FAPI_INF("Executing:p8_pm_firinit in mode PM_RESET");
 
         FAPI_EXEC_HWP(rc, p8_pm_firinit, i_primary_chip_target , i_mode );
@@ -237,6 +261,9 @@ p8_pm_prep_for_reset(   const fapi::Target &i_primary_chip_target,
             break;
         }
 
+        rc = p8_pm_glob_fir_trace (i_primary_chip_target, "after Masking");
+        if (!rc.ok()) { break; }  
+            
         if ( i_secondary_chip_target.getType() != TARGET_TYPE_NONE )
         {
 
@@ -246,15 +273,68 @@ p8_pm_prep_for_reset(   const fapi::Target &i_primary_chip_target,
                 FAPI_ERR("ERROR: p8_pm_firinit detected failed  result");
                 break;
             }
+            
+            rc = p8_pm_glob_fir_trace (i_secondary_chip_target, "after Masking");
+            if (!rc.ok()) { break; }  
+        }
+        
+        //  ******************************************************************
+        //  FSM trace
+        //  ******************************************************************
+        rc = p4rs_pcbs_fsm_trace (i_primary_chip_target, i_secondary_chip_target, 
+                    "after FIR masking");
+        if (!rc.ok()) 
+        {
+            break;
         }
 
         //  ******************************************************************
-        //  Force Vsafe value into voltage controller
+        //  Put OCC PPC405 into reset
+        //  ******************************************************************       
+        FAPI_INF("Put OCC PPC405 into reset");
+        FAPI_DBG("Executing: p8_occ_control.C");
+
+        FAPI_EXEC_HWP(rc, p8_occ_control, i_primary_chip_target, PPC405_RESET_ON, 0);
+        if (rc)
+        {
+            FAPI_ERR("p8_occ_control: Failed to prepare OCC for RESET. With rc = 0x%x", (uint32_t)rc);
+            break;
+        }
+
+        if ( i_secondary_chip_target.getType() != TARGET_TYPE_NONE )
+        {
+            FAPI_EXEC_HWP(rc, p8_occ_control, i_secondary_chip_target, PPC405_RESET_ON, 0);
+            if (rc)
+            {
+              FAPI_ERR("p8_occ_control: Failed to prepare OCC for RESET. With rc = 0x%x", (uint32_t)rc);
+              break;
+            }
+        }
+        
         //  ******************************************************************
-        //     - call p8_pmc_force_vsafe.C  *chiptarget,
-        //                    - Forces the Vsafe value into the voltage controller
-        //
+        //  FSM trace
+        //  ******************************************************************
+        rc = p4rs_pcbs_fsm_trace (i_primary_chip_target, i_secondary_chip_target, 
+                    "after OCC Reset");
+        if (!rc.ok()) 
+        {
+            break;
+        }
+                
+        //  Check for xstops and recoverables
 
+        rc = p8_pm_glob_fir_trace (i_primary_chip_target, "after OCC Reset");
+        if (!rc.ok()) { break; }  
+        
+        if ( i_secondary_chip_target.getType() != TARGET_TYPE_NONE )
+        {                      
+            rc = p8_pm_glob_fir_trace (i_secondary_chip_target, "after OCC Reset");
+            if (!rc.ok()) { break; }  
+        }
+                
+        //  ******************************************************************
+        //  Force Vsafe value into voltage controller
+        //  ******************************************************************
         FAPI_INF("Force Vsafe value into voltage controller");
         FAPI_DBG("Executing: p8_pmc_force_vsafe.C");
 
@@ -266,7 +346,7 @@ p8_pm_prep_for_reset(   const fapi::Target &i_primary_chip_target,
             FAPI_ERR("Failed to force Vsafe value into voltage controller. With rc = 0x%x", (uint32_t)rc);
             break;
         }
-
+        
         // Secondary
         if ( i_secondary_chip_target.getType() != TARGET_TYPE_NONE )
         {
@@ -275,16 +355,33 @@ p8_pm_prep_for_reset(   const fapi::Target &i_primary_chip_target,
             {
               FAPI_ERR("Failed to force Vsafe value into voltage controller. With rc = 0x%x", (uint32_t)rc);
               break;
-            }
+            }           
         }
-
+        
+        //  ******************************************************************
+        //  FSM trace
+        //  ******************************************************************
+        rc = p4rs_pcbs_fsm_trace (i_primary_chip_target, i_secondary_chip_target, 
+                    "after force Vsafe");
+        if (!rc.ok()) 
+        {
+            break;
+        }
+        
+        //  Check for xstops and recoverables
+        rc = p8_pm_glob_fir_trace (i_primary_chip_target, "after Force Vsafe");
+        if (!rc.ok()) { break; }  
+        
+        if ( i_secondary_chip_target.getType() != TARGET_TYPE_NONE )
+        {                      
+            rc = p8_pm_glob_fir_trace (i_secondary_chip_target, "after Force Vsafe");
+            if (!rc.ok()) { break; }  
+        }              
+  
         //  ******************************************************************
         //  Prepare PCBSLV_PM for RESET
         //  ******************************************************************
-        //      - call p8_pcbs_init.C *chiptarget, ENUM:PCBSPM_RESET
-        //
         //      - p8_pcbs_init internally loops over all enabled chiplets
-
         FAPI_INF("Prepare PCBSLV_PM for RESET");
         FAPI_DBG("Executing: p8_pcbs_init.C");
 
@@ -296,6 +393,13 @@ p8_pm_prep_for_reset(   const fapi::Target &i_primary_chip_target,
             break;
         }
 
+        address =  READ_GLOBAL_RECOV_FIR_0x570F001C;
+        GETSCOM(rc, i_primary_chip_target, address, data);
+        if (data.getNumBitsSet(0,64))
+        {
+            FAPI_INF("Recoverable attention is **ACTIVE** in prep_for_reset after PCBS reset");
+        }
+        
         // Secondary
         if ( i_secondary_chip_target.getType() != TARGET_TYPE_NONE )
         {
@@ -306,14 +410,36 @@ p8_pm_prep_for_reset(   const fapi::Target &i_primary_chip_target,
               FAPI_ERR("p8_pcbs_init: Failed to prepare PCBSLV_PM for RESET. With rc = 0x%x", (uint32_t)rc);
               break;
             }
+            
+            GETSCOM(rc, i_secondary_chip_target, address, data);
+            if (data.getNumBitsSet(0,64))
+            {
+                FAPI_INF("Recoverable attention is **ACTIVE** in prep_for_reset after  PCBS reset");
+            }
+        }
+        
+        //  ******************************************************************
+        //  FSM trace
+        //  ******************************************************************
+        rc = p4rs_pcbs_fsm_trace (i_primary_chip_target, i_secondary_chip_target, "after PCBS reset");
+        if (!rc.ok()) 
+        {
+            break;
         }
+        
+        //  Check for xstops and recoverables
+        rc = p8_pm_glob_fir_trace (i_primary_chip_target, "after PCBS reset");
+        if (!rc.ok()) { break; }  
+        
+        if ( i_secondary_chip_target.getType() != TARGET_TYPE_NONE )
+        {                      
+            rc = p8_pm_glob_fir_trace (i_secondary_chip_target, "after PCBS reset");
+            if (!rc.ok()) { break; }  
+        }              
 
         //  ******************************************************************
         //  Reset PMC
         //  ******************************************************************
-        //     - call p8_pmc_init.C *chiptarget, ENUM:PMC_RESET_SOFT
-        //
-
         FAPI_INF("Issue reset to PMC");
         FAPI_DBG("Executing: p8_pmc_init");
 
@@ -325,6 +451,16 @@ p8_pm_prep_for_reset(   const fapi::Target &i_primary_chip_target,
         }
         
         //  ******************************************************************
+        //  FSM trace
+        //  ******************************************************************
+        rc = p4rs_pcbs_fsm_trace (i_primary_chip_target, i_secondary_chip_target, 
+                    "after PMC reset");
+        if (!rc.ok()) 
+        {
+            break;
+        }
+        
+        //  ******************************************************************
         //  As the PMC reset kills ALL of the configuration, the idle portion
         //  must be reestablished to allow that portion to operate.  This is 
         //  what p8_poreslw_init -init does. Additionally, this lets us drop 
@@ -354,15 +490,21 @@ p8_pm_prep_for_reset(   const fapi::Target &i_primary_chip_target,
                 FAPI_ERR("p8_poreslw_init: Failed to to reinialize the idle portion of the PMC. With rc = 0x%x", (uint32_t)rc);
                 break;
             }
-
         }
-
+        
+        //  Check for xstops and recoverables
+        rc = p8_pm_glob_fir_trace (i_primary_chip_target,  "after PMC and SLW reinit");
+        if (!rc.ok()) { break; }  
+        
+        if ( i_secondary_chip_target.getType() != TARGET_TYPE_NONE )
+        {                      
+            rc = p8_pm_glob_fir_trace (i_secondary_chip_target,  "after PMC and SLW reinit");
+            if (!rc.ok()) { break; }  
+        }              
+        
         //  ******************************************************************
         //  Issue reset to PSS macro
         //  ******************************************************************
-        //     - call p8_pss_init.C *chiptarget, ENUM:PM_RESET
-        //
-
         FAPI_INF("Issue reset to PSS macro");
         FAPI_DBG("Executing: p8_pss_init.C");
 
@@ -391,8 +533,6 @@ p8_pm_prep_for_reset(   const fapi::Target &i_primary_chip_target,
         //  ******************************************************************
         //  Issue reset to PORE General Purpose Engine
         //  ******************************************************************
-        //     - call p8_poregpe_init.C *chiptarget, ENUM:POREGPE_RESET
-
         FAPI_INF("Issue reset to PORE General Purpose Engine");
         FAPI_DBG("Executing: p8_poregpe_init.C");
 
@@ -418,9 +558,7 @@ p8_pm_prep_for_reset(   const fapi::Target &i_primary_chip_target,
         //  ******************************************************************
         //  Issue reset to PBA
         //  ******************************************************************
-        //     - call p8_pba_init.C *chiptarget, ENUM:PBA_RESET
-        //
-
+        //  Note:  this voids the channel used by the SLW engine
         FAPI_INF("Issue reset to PBA");
         FAPI_DBG("Executing: p8_pba_init.C");
 
@@ -442,13 +580,19 @@ p8_pm_prep_for_reset(   const fapi::Target &i_primary_chip_target,
                 break;
             }
         }
+        //  Check for xstops and recoverables
+        rc = p8_pm_glob_fir_trace (i_primary_chip_target, "after PBA reset");
+        if (!rc.ok()) { break; }  
+        
+        if ( i_secondary_chip_target.getType() != TARGET_TYPE_NONE )
+        {                      
+            rc = p8_pm_glob_fir_trace (i_secondary_chip_target, "after PBA reset");
+            if (!rc.ok()) { break; }  
+        }            
 
         //  ******************************************************************
         //  Issue reset to OCC-SRAM
         //  ******************************************************************
-        //     - call p8_occ_sram_init.C *chiptarget, ENUM:OCC_SRAM_RESET
-        //
-
         FAPI_INF("Issue reset to OCC-SRAM");
         FAPI_DBG("Executing: p8_occ_sram_init.C");
 
@@ -474,7 +618,6 @@ p8_pm_prep_for_reset(   const fapi::Target &i_primary_chip_target,
         //  ******************************************************************
         //  Issue reset to OCB
         //  ******************************************************************
-        //     - call p8_ocb_init.C *chiptarget, ENUM:OCC_OCB_RESET
 
         FAPI_INF("Issue reset to OCB");
         FAPI_DBG("Executing: p8_ocb_init.C");
@@ -498,6 +641,15 @@ p8_pm_prep_for_reset(   const fapi::Target &i_primary_chip_target,
             }
         }
         
+        //  Check for xstops and recoverables
+        rc = p8_pm_glob_fir_trace (i_primary_chip_target, "after OCB reset");
+        if (!rc.ok()) { break; }  
+        
+        if ( i_secondary_chip_target.getType() != TARGET_TYPE_NONE )
+        {                      
+            rc = p8_pm_glob_fir_trace (i_secondary_chip_target, "after OCB reset");
+            if (!rc.ok()) { break; }  
+        }            
         //  ******************************************************************
         //  Remove the EX chiplet special wakeups
         //  *****************************************************************
@@ -506,10 +658,11 @@ p8_pm_prep_for_reset(   const fapi::Target &i_primary_chip_target,
         rc = special_wakeup_all (i_primary_chip_target, false);
         if (rc)
         {
-            FAPI_ERR("special_wakeup_all - Enable: Failed for Target %s", 
+            FAPI_ERR("special_wakeup_all - Disable: Failed for Target %s", 
                         i_primary_chip_target.toEcmdString());
             break;
         }
+        b_special_wakeup_pri = false;
                 
 
         // Secondary
@@ -518,15 +671,81 @@ p8_pm_prep_for_reset(   const fapi::Target &i_primary_chip_target,
             rc = special_wakeup_all (i_secondary_chip_target, false);
             if (rc)
             {
-                FAPI_ERR("special_wakeup_all - Enable: Failed for Target %s", 
+                FAPI_ERR("special_wakeup_all - Disable: Failed for Target %s", 
                             i_secondary_chip_target.toEcmdString());
                 break;
             }
-
+            
+            b_special_wakeup_sec = false;
         }
-
-
+        
+        
+        //  ******************************************************************
+        //  FSM trace
+        //  ******************************************************************
+        rc = p4rs_pcbs_fsm_trace (i_primary_chip_target, i_secondary_chip_target, 
+                    "after special wake-up clearing");
+        if (!rc.ok()) 
+        {
+            break;
+        }
+        
+        //  Check for xstops and recoverables
+        rc = p8_pm_glob_fir_trace (i_primary_chip_target, "after special wake-up clearing");
+        if (!rc.ok()) { break; }  
+        
+        if ( i_secondary_chip_target.getType() != TARGET_TYPE_NONE )
+        {                      
+            rc = p8_pm_glob_fir_trace (i_secondary_chip_target, "after special wake-up clearing");
+            if (!rc.ok()) { break; }  
+        }            
+        
     } while(0);
+    
+    
+    // Clear special wakeups that might have been set before a subsequent
+    // error occured.  Only attempts them on targets that have the boolean
+    // flag set that they were successfully put into special wakeup.
+    if (!rc.ok())
+    {
+        // Save the original RC
+        rc_hold = rc;
+        
+        do
+        {        
+            // Primary
+            if (b_special_wakeup_pri)
+            {
+                // Primary
+                rc = special_wakeup_all (i_primary_chip_target, false);
+                if (rc)
+                {
+                    FAPI_ERR("special_wakeup_all - Disable: Failed during cleanup from a previous error for Target %s", 
+                                i_primary_chip_target.toEcmdString());
+                    FAPI_ERR("special_wakeup_all - Disable: The original error is being returned"); 
+                    fapiLogError(rc, fapi::FAPI_ERRL_SEV_RECOVERED);
+                    break;
+                }
+            }
+
+            // Secondary
+            if (b_special_wakeup_sec)
+            {
+                rc = special_wakeup_all (i_secondary_chip_target, false);
+                if (rc)
+                {
+                    FAPI_ERR("special_wakeup_all - Disable: Failed during cleanup from a previous error for Target %s", 
+                                i_primary_chip_target.toEcmdString());
+                    FAPI_ERR("special_wakeup_all - Disable: The original error is being returned");
+                    fapiLogError(rc, fapi::FAPI_ERRL_SEV_RECOVERED);
+                    break;
+                }
+            }
+        } while(0);
+        
+        // Restore the original RC
+        rc = rc_hold;
+    }
 
     FAPI_INF("p8_pm_prep_for_reset start  ....");
 
@@ -600,5 +819,51 @@ special_wakeup_all (const fapi::Target &i_target, bool i_action)
 
 
 
+
+//------------------------------------------------------------------------------
+/**
+ * Trace PCBS FSMs across primary and secondary chips
+ *
+ * @param[in] i_target Chip target
+ * @param[in] i_msg    String to put out in the trace
+ *
+ * @retval ECMD_SUCCESS
+ * @retval ERROR defined in xml
+ */
+fapi::ReturnCode
+p4rs_pcbs_fsm_trace(const fapi::Target& i_primary_target,
+                    const fapi::Target& i_secondary_target,          
+                    const char *       i_msg)
+{
+    fapi::ReturnCode                rc;
+
+    do
+    {
+    
+        rc = p8_pm_pcbs_fsm_trace_chip (i_primary_target, i_msg);
+        if (rc)
+        {
+            FAPI_ERR("pcbs_fsm_trace_chip failed for Target %s", 
+                        i_primary_target.toEcmdString());
+            break;
+        }          
+
+        if ( i_secondary_target.getType() != TARGET_TYPE_NONE )
+        {
+            rc = p8_pm_pcbs_fsm_trace_chip (i_secondary_target, i_msg);
+            if (rc)
+            {
+                FAPI_ERR("pcbs_fsm_trace_chip failed for Target %s", 
+                            i_secondary_target.toEcmdString());
+                break;
+            }           
+        }                                    
+    } while(0);
+    return rc;
+}
+
+
+
+
 } //end extern C
 
diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_utils.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_utils.C
index da8b70dd2..25e2291df 100644
--- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_utils.C
+++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pm_utils.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_pm_utils.C,v 1.2 2014/02/09 02:01:59 stillgs Exp $
+// $Id: p8_pm_utils.C,v 1.3 2014/02/17 02:53:07 stillgs Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm_utils.C,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -64,9 +64,10 @@ fapi::ReturnCode
 p8_pm_glob_fir_trace(const fapi::Target& i_target,
                     const char * i_msg)
 {
-    fapi::ReturnCode                rc;
-    ecmdDataBufferBase              data(64);
-    uint64_t                        address;
+    fapi::ReturnCode    rc;
+    ecmdDataBufferBase  data(64);
+    uint64_t            address;
+    uint8_t             trace_en_flag = false;
 
     CONST_UINT64_T( GLOB_XSTOP_FIR_0x01040000                                 , ULL(0x01040000) );
     CONST_UINT64_T( GLOB_RECOV_FIR_0x01040001                                 , ULL(0x01040001) );
@@ -78,6 +79,19 @@ p8_pm_glob_fir_trace(const fapi::Target& i_target,
         //  Note: i_msg is put on on each record to allow for trace "greps"
         //  so as to see the "big picture" across when
 
+        rc = FAPI_ATTR_GET(ATTR_PM_GLOBAL_FIR_TRACE_EN, NULL, trace_en_flag);
+        if (rc)
+        {
+            FAPI_ERR("fapiGetAttribute of ATTR_PM_GLOBAL_FIR_TRACE_EN with rc = 0x%x", (uint32_t)rc);
+            break;
+        }
+
+        // If trace is not enabled, leave.
+        if (!trace_en_flag)
+        {
+            break;
+        }
+
         //  ******************************************************************
         //  Check for xstops and recoverables and put in the trace
         //  ******************************************************************
@@ -144,16 +158,30 @@ p8_pm_pcbs_fsm_trace_chip(const fapi::Target& i_target,
 {
     fapi::ReturnCode                rc;
     ecmdDataBufferBase              data(64);
-    
+    uint8_t                         trace_en_flag = false;
+
     std::vector<fapi::Target>       l_exChiplets;
     uint8_t                         l_ex_number = 0;
 
     do
     {
-         rc = fapiGetChildChiplets(i_target,
-                                    fapi::TARGET_TYPE_EX_CHIPLET,
-                                    l_exChiplets,
-                                    TARGET_STATE_FUNCTIONAL);
+        rc = FAPI_ATTR_GET(ATTR_PM_PCBS_FSM_TRACE_EN, NULL, trace_en_flag);
+        if (rc)
+        {
+            FAPI_ERR("fapiGetAttribute of ATTR_PM_PCBS_FSM_TRACE_EN with rc = 0x%x", (uint32_t)rc);
+            break;
+        }
+
+        // If trace is not enabled, leave.
+        if (!trace_en_flag)
+        {
+            break;
+        }
+
+        rc = fapiGetChildChiplets(i_target,
+                                  fapi::TARGET_TYPE_EX_CHIPLET,
+                                  l_exChiplets,
+                                  TARGET_STATE_FUNCTIONAL);
         if (rc)
         {
             FAPI_ERR("fapiGetChildChiplets with rc = 0x%x", (uint32_t)rc);
@@ -201,10 +229,24 @@ p8_pm_pcbs_fsm_trace  ( const fapi::Target& i_target,
     fapi::ReturnCode                rc;
     ecmdDataBufferBase              data(64);
     uint64_t                        address;
+    uint8_t                         trace_en_flag = false;
     uint64_t                        ex_offset;
 
     do
     {
+        rc = FAPI_ATTR_GET(ATTR_PM_PCBS_FSM_TRACE_EN, NULL, trace_en_flag);
+        if (rc)
+        {
+            FAPI_ERR("fapiGetAttribute of ATTR_PM_PCBS_FSM_TRACE_EN with rc = 0x%x", (uint32_t)rc);
+            break;
+        }
+
+        // If trace is not enabled, leave.
+        if (!trace_en_flag)
+        {
+            break;
+        }
+    
         ex_offset = i_ex_number * 0x01000000;
 
         //  Note: i_msg is put on on each record to allow for trace "greps"
@@ -254,9 +296,6 @@ p8_pm_pcbs_fsm_trace  ( const fapi::Target& i_target,
     return rc;
 }
 
-
-
-
 } //end extern
 
 #endif // _P8_PM_UTILS_H_
diff --git a/src/usr/hwpf/hwp/runtime_attributes/pm_hwp_attributes.xml b/src/usr/hwpf/hwp/runtime_attributes/pm_hwp_attributes.xml
index c9a09f034..9db940c76 100644
--- a/src/usr/hwpf/hwp/runtime_attributes/pm_hwp_attributes.xml
+++ b/src/usr/hwpf/hwp/runtime_attributes/pm_hwp_attributes.xml
@@ -20,7 +20,7 @@
 <!-- Origin: 30                                                             -->
 <!--                                                                        -->
 <!-- IBM_PROLOG_END_TAG                                                     -->
-<!-- $Id: pm_hwp_attributes.xml,v 1.10 2013/12/19 14:43:14 stillgs Exp $ -->
+<!-- $Id: pm_hwp_attributes.xml,v 1.11 2014/02/06 19:08:22 stillgs Exp $ -->
 <!--
     XML file specifying Power Management HWPF attributes.
     These attributes are initialized to zero by the platform and set to a
@@ -818,5 +818,25 @@ Divider for the 1us PBAX hang pulse.  A hang is detected after two divided hang
     <writeable/>
 </attribute>
 
+<attribute>
+    <id>ATTR_PM_PCBS_FSM_TRACE_EN</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>
+    Overridable attribute to allow for PCBS FSM tracing by Power Management procedures
+    </description>
+    <valueType>uint8</valueType>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>ATTR_PM_GLOBAL_FIR_TRACE_EN</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>
+    Overridable attribute to allow for Global checkstop and recoverable FIR tracing by Power Management procedures
+    </description>
+    <valueType>uint8</valueType>
+    <writeable/>
+</attribute>
+
 </attributes>
 
diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml
index f18a56936..2a3a53132 100644
--- a/src/usr/targeting/common/xmltohb/attribute_types.xml
+++ b/src/usr/targeting/common/xmltohb/attribute_types.xml
@@ -13227,8 +13227,6 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript
     </hwpfToHbAttrMap>
 </attribute>
 
-</attributes>
-
 <attribute>
     <id>DISABLE_SCRUB_AFTER_PATTERN_TEST</id>
     <description>
@@ -13246,3 +13244,40 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript
     </hwpfToHbAttrMap>
 </attribute>
 
+<attribute>
+    <id>PM_PCBS_FSM_TRACE_EN</id>
+    <description>
+    Overridable attribute to allow for PCBS FSM tracing by Power Management procedures
+    </description>
+    <simpleType>
+        <uint8_t></uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_PM_PCBS_FSM_TRACE_EN</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>PM_GLOBAL_FIR_TRACE_EN</id>
+    <description>
+    Overridable attribute to allow for Global checkstop and recoverable FIR tracing by Power Management procedures
+    </description>
+    <simpleType>
+        <uint8_t></uint8_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_PM_GLOBAL_FIR_TRACE_EN</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+</attributes>
+
+
diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml
index e8a6a4b17..0aa065e35 100644
--- a/src/usr/targeting/common/xmltohb/target_types.xml
+++ b/src/usr/targeting/common/xmltohb/target_types.xml
@@ -229,6 +229,8 @@
     <attribute><id>MRW_CDIMM_MASTER_I2C_TEMP_SENSOR_ENABLE</id></attribute>
     <attribute><id>MULTI_SCOM_BUFFER_MAX_SIZE</id></attribute>
     <attribute><id>DISABLE_SCRUB_AFTER_PATTERN_TEST</id></attribute>
+    <attribute><id>PM_PCBS_FSM_TRACE_EN</id></attribute>
+    <attribute><id>PM_GLOBAL_FIR_TRACE_EN</id></attribute>
 </targetType>
 
 <targetType>