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authorRichard J. Knight <rjknight@us.ibm.com>2014-04-15 13:45:06 -0500
committerA. Patrick Williams III <iawillia@us.ibm.com>2014-04-17 13:30:33 -0500
commit71799dc06a83063360d593f9f2e3f6977f6ee8ef (patch)
tree467f0e3d637ea241f45f802274a7a702399341bf /src/usr
parent034cc84b0d0a88afc13e716e46560bfafe4deda4 (diff)
downloadtalos-hostboot-71799dc06a83063360d593f9f2e3f6977f6ee8ef.tar.gz
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SW256851: Update HWP from RAS Review Jamie #3
Change-Id: I2342b3cf08a296c04865a182a29b0f465e92a427 CQ:SW256851 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/10557 Reviewed-by: Richard J. Knight <rjknight@us.ibm.com> Tested-by: Richard J. Knight <rjknight@us.ibm.com> Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/10560 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr')
-rwxr-xr-xsrc/usr/hwpf/hwp/core_activate/proc_switch_cfsim/proc_switch_cfsim.H6
-rw-r--r--src/usr/hwpf/hwp/thread_activate/proc_thread_control/proc_thread_control.C30
-rw-r--r--src/usr/hwpf/hwp/thread_activate/proc_thread_control/proc_thread_control.xml82
3 files changed, 108 insertions, 10 deletions
diff --git a/src/usr/hwpf/hwp/core_activate/proc_switch_cfsim/proc_switch_cfsim.H b/src/usr/hwpf/hwp/core_activate/proc_switch_cfsim/proc_switch_cfsim.H
index cf7e211f9..6976b9a63 100755
--- a/src/usr/hwpf/hwp/core_activate/proc_switch_cfsim/proc_switch_cfsim.H
+++ b/src/usr/hwpf/hwp/core_activate/proc_switch_cfsim/proc_switch_cfsim.H
@@ -5,7 +5,7 @@
/* */
/* IBM CONFIDENTIAL */
/* */
-/* COPYRIGHT International Business Machines Corp. 2012 */
+/* COPYRIGHT International Business Machines Corp. 2012,2014 */
/* */
/* p1 */
/* */
@@ -20,7 +20,7 @@
/* Origin: 30 */
/* */
/* IBM_PROLOG_END_TAG */
-// $Id: proc_switch_cfsim.H,v 1.3 2012/05/03 10:41:52 rkoester Exp $
+// $Id: proc_switch_cfsim.H,v 1.4 2014/03/18 12:37:57 bgeukes Exp $
// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_switch_cfsim.H,v $
//------------------------------------------------------------------------------
// *|
@@ -48,7 +48,7 @@
//------------------------------------------------------------------------------
#include <fapi.H>
-#include "p8_scom_addresses.H"
+#include <p8_scom_addresses.H>
//------------------------------------------------------------------------------
diff --git a/src/usr/hwpf/hwp/thread_activate/proc_thread_control/proc_thread_control.C b/src/usr/hwpf/hwp/thread_activate/proc_thread_control/proc_thread_control.C
index b6f086e32..5762f63af 100644
--- a/src/usr/hwpf/hwp/thread_activate/proc_thread_control/proc_thread_control.C
+++ b/src/usr/hwpf/hwp/thread_activate/proc_thread_control/proc_thread_control.C
@@ -5,7 +5,7 @@
/* */
/* IBM CONFIDENTIAL */
/* */
-/* COPYRIGHT International Business Machines Corp. 2012,2013 */
+/* COPYRIGHT International Business Machines Corp. 2012,2014 */
/* */
/* p1 */
/* */
@@ -20,7 +20,7 @@
/* Origin: 30 */
/* */
/* IBM_PROLOG_END_TAG */
-// $Id: proc_thread_control.C,v 1.20 2013/03/15 15:03:58 jklazyns Exp $
+// $Id: proc_thread_control.C,v 1.21 2014/04/07 17:53:56 jklazyns Exp $
//------------------------------------------------------------------------------
// *! (C) Copyright International Business Machines Corp. 2012
// *! All Rights Reserved -- Property of IBM
@@ -33,11 +33,11 @@
// *! Activate is used to put a POR state thread in the proper
// *! state to enable ram prior to starting.
// *! Also used to query the state of a thread.
-// *! OWNER NAME : Lance Karm Email: karm@us.ibm.com
+// *! OWNER NAME : Nick Klazynski Email: jklazyns@us.ibm.com
// *! BACKUP NAME : Sebastien Lafontant Email: slafont@us.ibm.com
//------------------------------------------------------------------------------
#include <fapi.H>
-#include "proc_thread_control.H"
+#include <proc_thread_control.H>
extern "C"
{
@@ -130,6 +130,7 @@ extern "C"
}
FAPI_ERR("proc_thread_control: ERROR - invalid command issued to proc_thread_control");
+ const uint8_t COMMAND = i_command;
FAPI_SET_HWP_ERROR(rc, RC_PROC_THREAD_CONTROL_INV_COMMAND);
}
@@ -202,6 +203,9 @@ extern "C"
else
{
FAPI_ERR("proc_thread_control_sreset: ERROR: Thread SReset issued, but no instructions have completed. SReset might have failed for thread %d", i_thread);
+ const fapi::Target & CORE_TARGET = i_target;
+ const uint8_t THREAD = i_thread;
+ const ecmdDataBufferBase RAS_STATUS = o_ras_status;
FAPI_SET_HWP_ERROR(rc,
RC_PROC_THREAD_CONTROL_SRESET_FAIL);
break;
@@ -265,6 +269,9 @@ extern "C"
else
{
FAPI_ERR("proc_thread_control_start: Start Precondition Check failed: RAS Status Maintenance bit is not on for thread %d", i_thread);
+ const fapi::Target & CORE_TARGET = i_target;
+ const uint8_t THREAD = i_thread;
+ const ecmdDataBufferBase RAS_STATUS = o_ras_status;
FAPI_SET_HWP_ERROR(rc,
RC_PROC_THREAD_CONTROL_START_PRE_NOMAINT);
break;
@@ -305,6 +312,9 @@ extern "C"
else
{
FAPI_ERR("proc_thread_control_start: ERROR: Thread Start issued, but no instructions have completed. Start might have failed for thread %d", i_thread);
+ const fapi::Target & CORE_TARGET = i_target;
+ const uint8_t THREAD = i_thread;
+ const ecmdDataBufferBase RAS_STATUS = o_ras_status;
FAPI_SET_HWP_ERROR(rc,
RC_PROC_THREAD_CONTROL_START_FAIL);
break;
@@ -388,6 +398,9 @@ extern "C"
else
{
FAPI_ERR("proc_thread_control_stop: Thread Stop failed: RAS Status Maintenance bit is not on for thread %d", i_thread);
+ const fapi::Target & CORE_TARGET = i_target;
+ const uint8_t THREAD = i_thread;
+ const ecmdDataBufferBase RAS_STATUS = o_ras_status;
FAPI_SET_HWP_ERROR(rc,
RC_PROC_THREAD_CONTROL_STOP_FAIL);
break;
@@ -447,6 +460,9 @@ extern "C"
if (!(o_state & THREAD_STATE_MAINT))
{
FAPI_ERR("proc_thread_control_step: Step Precondition failed: RAS Status Maintenance bit is not on for thread %d", i_thread);
+ const fapi::Target & CORE_TARGET = i_target;
+ const uint8_t THREAD = i_thread;
+ const ecmdDataBufferBase RAS_STATUS = o_ras_status;
FAPI_SET_HWP_ERROR(rc,
RC_PROC_THREAD_CONTROL_STEP_PRE_NOMAINT);
break;
@@ -518,6 +534,9 @@ extern "C"
else
{
FAPI_ERR("proc_thread_control_step: Thread Step failed: RAS Status Group/Inst Complete bit is not on after %d poll attempts. WARNING: RAS_MODE bit %d still in single instruction mode! Thread %d", PTC_STEP_COMP_POLL_LIMIT, PTC_RAS_MODE_SINGLE, i_thread);
+ const fapi::Target & CORE_TARGET = i_target;
+ const uint8_t THREAD = i_thread;
+ const ecmdDataBufferBase RAS_STATUS = o_ras_status;
FAPI_SET_HWP_ERROR(rc,
RC_PROC_THREAD_CONTROL_STEP_FAIL);
break;
@@ -615,6 +634,9 @@ extern "C"
if (scomData.isBitClear(thd_activate_bit))
{
FAPI_ERR("proc_thread_control_activate: Activate Thread failed: Thread Active bit is still off.");
+ const fapi::Target & CORE_TARGET = i_target;
+ const uint8_t THREAD = i_thread;
+ const ecmdDataBufferBase RAS_STATUS = o_ras_status;
FAPI_SET_HWP_ERROR(rc,
RC_PROC_THREAD_CONTROL_ACTIVATE_FAIL);
break;
diff --git a/src/usr/hwpf/hwp/thread_activate/proc_thread_control/proc_thread_control.xml b/src/usr/hwpf/hwp/thread_activate/proc_thread_control/proc_thread_control.xml
index e6372c795..8e24cbd8e 100644
--- a/src/usr/hwpf/hwp/thread_activate/proc_thread_control/proc_thread_control.xml
+++ b/src/usr/hwpf/hwp/thread_activate/proc_thread_control/proc_thread_control.xml
@@ -5,7 +5,7 @@
<!-- -->
<!-- IBM CONFIDENTIAL -->
<!-- -->
-<!-- COPYRIGHT International Business Machines Corp. 2012,2013 -->
+<!-- COPYRIGHT International Business Machines Corp. 2012,2014 -->
<!-- -->
<!-- p1 -->
<!-- -->
@@ -20,47 +20,123 @@
<!-- Origin: 30 -->
<!-- -->
<!-- IBM_PROLOG_END_TAG -->
-<!-- $Id: proc_thread_control.xml,v 1.6 2012/07/25 18:29:09 karm Exp $ -->
+<!-- $Id: proc_thread_control.xml,v 1.8 2014/04/11 20:28:02 jklazyns Exp $ -->
<!-- Error definitions for proc_thread_control procedure -->
<hwpErrors>
<!-- ********************************************************************* -->
<hwpError>
<rc>RC_PROC_THREAD_CONTROL_INV_COMMAND</rc>
+ <ffdc>COMMAND</ffdc>
<description>Invalid command issued to proc_thread_control procedure</description>
+ <callout>
+ <procedure>CODE</procedure>
+ <priority>HIGH</priority>
+ </callout>
</hwpError>
<!-- ********************************************************************* -->
<hwpError>
<rc>RC_PROC_THREAD_CONTROL_SRESET_FAIL</rc>
+ <ffdc>CORE_TARGET</ffdc>
+ <ffdc>THREAD</ffdc>
+ <ffdc>RAS_STATUS</ffdc>
<description>Sreset command failed: RAS STAT instruction completed bit was not set after sreset command.</description>
+ <callout>
+ <target>CORE_TARGET</target>
+ <priority>HIGH</priority>
+ </callout>
+ <callout>
+ <procedure>CODE</procedure>
+ <priority>LOW</priority>
+ </callout>
+ <deconfigure>
+ <target>CORE_TARGET</target>
+ </deconfigure>
+ <gard>
+ <target>CORE_TARGET</target>
+ </gard>
</hwpError>
<!-- ********************************************************************* -->
<hwpError>
<rc>RC_PROC_THREAD_CONTROL_START_PRE_NOMAINT</rc>
<description>Start command precondition not met: RAS STAT Maintenance bit is not set.</description>
+ <ffdc>CORE_TARGET</ffdc>
+ <ffdc>THREAD</ffdc>
+ <ffdc>RAS_STATUS</ffdc>
+ <callout>
+ <procedure>CODE</procedure>
+ <priority>HIGH</priority>
+ </callout>
</hwpError>
<!-- ********************************************************************* -->
<hwpError>
<rc>RC_PROC_THREAD_CONTROL_START_FAIL</rc>
- <description>Sreset command failed: RAS STAT instruction completed bit was not set after start command.</description>
+ <description>Start command failed: RAS STAT instruction completed bit was not set after start command.</description>
+ <ffdc>CORE_TARGET</ffdc>
+ <ffdc>THREAD</ffdc>
+ <ffdc>RAS_STATUS</ffdc>
+ <callout>
+ <procedure>CODE</procedure>
+ <priority>HIGH</priority>
+ </callout>
</hwpError>
<!-- ********************************************************************* -->
<hwpError>
<rc>RC_PROC_THREAD_CONTROL_STOP_FAIL</rc>
<description>Stop command issued to core PC, but RAS STAT maintenance bit is not set.</description>
+ <ffdc>CORE_TARGET</ffdc>
+ <ffdc>THREAD</ffdc>
+ <ffdc>RAS_STATUS</ffdc>
+ <callout>
+ <procedure>CODE</procedure>
+ <priority>HIGH</priority>
+ </callout>
</hwpError>
<!-- ********************************************************************* -->
<hwpError>
<rc>RC_PROC_THREAD_CONTROL_STEP_PRE_NOMAINT</rc>
<description>Step command precondition not met: RAS STAT Maintenance bit is not set.</description>
+ <ffdc>CORE_TARGET</ffdc>
+ <ffdc>THREAD</ffdc>
+ <ffdc>RAS_STATUS</ffdc>
+ <callout>
+ <procedure>CODE</procedure>
+ <priority>HIGH</priority>
+ </callout>
</hwpError>
<!-- ********************************************************************* -->
<hwpError>
<rc>RC_PROC_THREAD_CONTROL_STEP_FAIL</rc>
<description>Step command issued to core PC, but RAS STAT run bit is still set.</description>
+ <ffdc>CORE_TARGET</ffdc>
+ <ffdc>THREAD</ffdc>
+ <ffdc>RAS_STATUS</ffdc>
+ <ffdc>PTC_STEP_COMP_POLL_LIMIT</ffdc>
+ <ffdc>PTC_RAS_MODE_SINGLE</ffdc>
+ <ffdc>stepCompletePollCount</ffdc>
+ <callout>
+ <target>CORE_TARGET</target>
+ <priority>HIGH</priority>
+ </callout>
+ <callout>
+ <procedure>CODE</procedure>
+ <priority>LOW</priority>
+ </callout>
</hwpError>
<!-- ********************************************************************* -->
<hwpError>
<rc>RC_PROC_THREAD_CONTROL_ACTIVATE_FAIL</rc>
<description>Activate command issued to core PC, but THREAD ACTIVE bit was not set.</description>
+ <ffdc>CORE_TARGET</ffdc>
+ <ffdc>THREAD</ffdc>
+ <ffdc>RAS_STATUS</ffdc>
+ <ffdc>thd_activate_bit</ffdc>
+ <callout>
+ <target>CORE_TARGET</target>
+ <priority>HIGH</priority>
+ </callout>
+ <callout>
+ <procedure>CODE</procedure>
+ <priority>LOW</priority>
+ </callout>
</hwpError>
</hwpErrors>
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