diff options
| author | Thi Tran <thi@us.ibm.com> | 2013-08-17 13:11:04 -0500 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2013-08-19 09:03:02 -0500 |
| commit | 6f2f3aa49961f017af6de723c28cf004ca8fbc36 (patch) | |
| tree | 9cf1fa3d06ab73c8b452089f85c0e2d877a809c2 /src/usr | |
| parent | 70b61b1c5a72e04461e47ea70d7a32cde6bc9dda (diff) | |
| download | talos-hostboot-6f2f3aa49961f017af6de723c28cf004ca8fbc36.tar.gz talos-hostboot-6f2f3aa49961f017af6de723c28cf004ca8fbc36.zip | |
INITPROC: Hostboot - Updated HWPs from defects SW216149/SW216152/SW216153
SW216149 SW216152 SW216153
Change-Id: Iad978323d3383e767dab09e6ff26e0faa9590bd1
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/5821
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr')
17 files changed, 772 insertions, 313 deletions
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_init_errors.xml b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_init_errors.xml index dc91f492c..8c6eef172 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_init_errors.xml +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_init_errors.xml @@ -5,7 +5,7 @@ <!-- --> <!-- IBM CONFIDENTIAL --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2012 --> +<!-- COPYRIGHT International Business Machines Corp. 2012,2013 --> <!-- --> <!-- p1 --> <!-- --> @@ -20,6 +20,7 @@ <!-- Origin: 30 --> <!-- --> <!-- IBM_PROLOG_END_TAG --> +<!-- $Id: p8_pfet_init_errors.xml,v 1.2 2013/05/23 18:44:21 stillgs Exp $ --> <!-- Error definitions for p8_pfet_init procedure --> <hwpErrors> <!-- *********************************************************************** --> diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/proc_pba_bar_config_errors.xml b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pba_bar_config_errors.xml index 21b2ff311..6e2991e0c 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/proc_pba_bar_config_errors.xml +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pba_bar_config_errors.xml @@ -1,11 +1,11 @@ <!-- IBM_PROLOG_BEGIN_TAG --> <!-- This is an automatically generated prolog. --> <!-- --> -<!-- $Source: src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/proc_pba_bar_config_errors.xml $ --> +<!-- $Source: src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pba_bar_config_errors.xml $ --> <!-- --> <!-- IBM CONFIDENTIAL --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2012 --> +<!-- COPYRIGHT International Business Machines Corp. 2013 --> <!-- --> <!-- p1 --> <!-- --> @@ -20,7 +20,7 @@ <!-- Origin: 30 --> <!-- --> <!-- IBM_PROLOG_END_TAG --> -<!-- $Id: proc_pba_bar_config_errors.xml,v 1.4 2012/09/12 21:59:26 wenning Exp $ --> +<!-- $Id: p8_pba_bar_config_errors.xml,v 1.3 2013/02/06 17:47:07 stillgs Exp $ --> <!-- Error definitions for proc_pba_bar_config procedure --> <hwpErrors> <!-- *********************************************************************** --> @@ -40,8 +40,13 @@ </hwpError> <!-- *********************************************************************** --> <hwpError> - <rc>RC_PROC_PBA_BAR_MASK_OUT_OF_RANGE</rc> - <description>pba bar mask out of range. .</description> + <rc>RC_PROC_PBA_ADDR_ALIGNMENT_ERROR</rc> + <description>pba BAR must be on a 1MB boundary</description> + </hwpError> + <!-- *********************************************************************** --> + <hwpError> + <rc>RC_PROC_PBA_BAR_SIZE_INVALID</rc> + <description>Non-zero PBA BAR defined with region size of 0. Size must be 1MB or greater</description> </hwpError> <!-- *********************************************************************** --> <hwpError> diff --git a/src/usr/hwpf/hwp/bus_training/gcr_funcs.C b/src/usr/hwpf/hwp/bus_training/gcr_funcs.C index 6764b00b7..c0197cc56 100644 --- a/src/usr/hwpf/hwp/bus_training/gcr_funcs.C +++ b/src/usr/hwpf/hwp/bus_training/gcr_funcs.C @@ -1,26 +1,26 @@ -/* IBM_PROLOG_BEGIN_TAG - * This is an automatically generated prolog. - * - * $Source: src/usr/hwpf/hwp/bus_training/gcr_funcs.C $ - * - * IBM CONFIDENTIAL - * - * COPYRIGHT International Business Machines Corp. 2012 - * - * p1 - * - * Object Code Only (OCO) source materials - * Licensed Internal Code Source Materials - * IBM HostBoot Licensed Internal Code - * - * The source code for this program is not published or other- - * wise divested of its trade secrets, irrespective of what has - * been deposited with the U.S. Copyright Office. - * - * Origin: 30 - * - * IBM_PROLOG_END_TAG - */ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/bus_training/gcr_funcs.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: gcr_funcs.C,v 1.9 2013/06/06 20:40:50 cswenson Exp $
// *!***************************************************************************
// *! (C) Copyright International Business Machines Corp. 1997, 1998
// *! All Rights Reserved -- Property of IBM
diff --git a/src/usr/hwpf/hwp/bus_training/gcr_funcs.H b/src/usr/hwpf/hwp/bus_training/gcr_funcs.H index 08d6eb355..52da6623f 100644 --- a/src/usr/hwpf/hwp/bus_training/gcr_funcs.H +++ b/src/usr/hwpf/hwp/bus_training/gcr_funcs.H @@ -1,26 +1,26 @@ -/* IBM_PROLOG_BEGIN_TAG - * This is an automatically generated prolog. - * - * $Source: src/usr/hwpf/hwp/bus_training/gcr_funcs.H $ - * - * IBM CONFIDENTIAL - * - * COPYRIGHT International Business Machines Corp. 2012 - * - * p1 - * - * Object Code Only (OCO) source materials - * Licensed Internal Code Source Materials - * IBM HostBoot Licensed Internal Code - * - * The source code for this program is not published or other- - * wise divested of its trade secrets, irrespective of what has - * been deposited with the U.S. Copyright Office. - * - * Origin: 30 - * - * IBM_PROLOG_END_TAG - */ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/hwpf/hwp/bus_training/gcr_funcs.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ +// $Id: gcr_funcs.H,v 1.19 2013/06/06 20:40:52 cswenson Exp $
// *!***************************************************************************
// *! (C) Copyright International Business Machines Corp. 1997, 1998
// *! All Rights Reserved -- Property of IBM
diff --git a/src/usr/hwpf/hwp/initfiles/cen.dmi.custom.scom.initfile b/src/usr/hwpf/hwp/initfiles/cen.dmi.custom.scom.initfile index 6d086b1a8..6b91e7a86 100644 --- a/src/usr/hwpf/hwp/initfiles/cen.dmi.custom.scom.initfile +++ b/src/usr/hwpf/hwp/initfiles/cen.dmi.custom.scom.initfile @@ -1,4 +1,4 @@ -#-- $Id: cen.dmi.custom.scom.initfile,v 1.7 2013/04/18 19:20:50 jgrell Exp $ +#-- $Id: cen.dmi.custom.scom.initfile,v 1.9 2013/06/27 15:07:47 jgrell Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: diff --git a/src/usr/hwpf/hwp/initfiles/p8.abus.custom.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.abus.custom.scom.initfile index 10272238c..43afec5c7 100644 --- a/src/usr/hwpf/hwp/initfiles/p8.abus.custom.scom.initfile +++ b/src/usr/hwpf/hwp/initfiles/p8.abus.custom.scom.initfile @@ -1,8 +1,9 @@ -#-- $Id: p8.abus.custom.scom.initfile,v 1.3 2013/05/01 20:36:16 jgrell Exp $ +#-- $Id: p8.abus.custom.scom.initfile,v 1.4 2013/06/18 18:31:18 jgrell Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- +#-- 1.4 |jgrell |06/18/13|Added Venice specific PRBS tap IDs due to common initfile #-- 1.3 |thomsen |04/30/13|Added TGT1. to ATTR_CHIP_EC* attribute instances to reference a chip target rather than a chiplet target #-- 1.2 |jgrell |04/18/13|Added EC controled Recal enables #-- 1.1 |thomsen |01/29/13|Created initial version @@ -304,6 +305,152 @@ rx_rc_enable_ddc, 0b0, TGT1.ATTR_CHIP_EC_FEATURE_RECAL_DDC_ENABLE==0; rx_rc_enable_ctle_cal, 0b0, TGT1.ATTR_CHIP_EC_FEATURE_RECAL_CTLE_ENABLE==0; } + +#--************************************************************************************************************** +#---------------------------------------------------------------------------------------------------------------- +# Venice Specific Inits +#---------------------------------------------------------------------------------------------------------------- +#--************************************************************************************************************** + +#TX_WRAP.TX0.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004341408010C3F { + bits, scom_data, expr; + tx_prbs_tap_id, 0b010, ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC==1; +} + +#TX_WRAP.TX0.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004341508010C3F { + bits, scom_data, expr; + tx_prbs_tap_id, 0b001, ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC==1; +} + +#TX_WRAP.TX0.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004341308010C3F { + bits, scom_data, expr; + tx_prbs_tap_id, 0b011, ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC==1; +} + +#TX_WRAP.TX0.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004341608010C3F { + bits, scom_data, expr; + tx_prbs_tap_id, 0b000, ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC==1; +} + +#TX_WRAP.TX0.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004341108010C3F { + bits, scom_data, expr; + tx_prbs_tap_id, 0b101, ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC==1; +} + +#TX_WRAP.TX0.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004341008010C3F { + bits, scom_data, expr; + tx_prbs_tap_id, 0b110, ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC==1; +} + +#TX_WRAP.TX0.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004341208010C3F { + bits, scom_data, expr; + tx_prbs_tap_id, 0b100, ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC==1; +} + +#TX_WRAP.TX0.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004340F08010C3F { + bits, scom_data, expr; + tx_prbs_tap_id, 0b111, ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC==1; +} + +#TX_WRAP.TX0.TXPACKS#2.TXPACK_2.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004340C08010C3F { + bits, scom_data, expr; + tx_prbs_tap_id, 0b010, ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC==1; +} + +#TX_WRAP.TX0.TXPACKS#2.TXPACK_2.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004340D08010C3F { + bits, scom_data, expr; + tx_prbs_tap_id, 0b001, ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC==1; +} + +#TX_WRAP.TX0.TXPACKS#2.TXPACK_2.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004340E08010C3F { + bits, scom_data, expr; + tx_prbs_tap_id, 0b000, ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC==1; +} + +#TX_WRAP.TX0.TXPACKS#3.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004340108010C3F { + bits, scom_data, expr; + tx_prbs_tap_id, 0b001, ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC==1; +} + +#TX_WRAP.TX0.TXPACKS#3.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004340208010C3F { + bits, scom_data, expr; + tx_prbs_tap_id, 0b010, ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC==1; +} + +#TX_WRAP.TX0.TXPACKS#3.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004340008010C3F { + bits, scom_data, expr; + tx_prbs_tap_id, 0b000, ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC==1; +} + +#TX_WRAP.TX0.TXPACKS#3.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004340308010C3F { + bits, scom_data, expr; + tx_prbs_tap_id, 0b011, ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC==1; +} + +#TX_WRAP.TX0.TXPACKS#4.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004340608010C3F { + bits, scom_data, expr; + tx_prbs_tap_id, 0b110, ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC==1; +} + +#TX_WRAP.TX0.TXPACKS#4.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004340508010C3F { + bits, scom_data, expr; + tx_prbs_tap_id, 0b101, ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC==1; +} + +#TX_WRAP.TX0.TXPACKS#4.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004340708010C3F { + bits, scom_data, expr; + tx_prbs_tap_id, 0b111, ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC==1; +} + +#TX_WRAP.TX0.TXPACKS#4.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004340408010C3F { + bits, scom_data, expr; + tx_prbs_tap_id, 0b100, ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC==1; +} + +#TX_WRAP.TX0.TXPACKS#5.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004340908010C3F { + bits, scom_data, expr; + tx_prbs_tap_id, 0b001, ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC==1; +} + +#TX_WRAP.TX0.TXPACKS#5.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004340A08010C3F { + bits, scom_data, expr; + tx_prbs_tap_id, 0b010, ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC==1; +} + +#TX_WRAP.TX0.TXPACKS#5.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004340808010C3F { + bits, scom_data, expr; + tx_prbs_tap_id, 0b000, ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC==1; +} + +#TX_WRAP.TX0.TXPACKS#5.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL +scom 0x8004340B08010C3F { + bits, scom_data, expr; + tx_prbs_tap_id, 0b011, ATTR_CHIP_EC_FEATURE_VENICE_SPECIFIC==1; +} + + ############################################################################################ # END OF FILE ############################################################################################ diff --git a/src/usr/hwpf/hwp/initfiles/p8.abus.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.abus.scom.initfile index dcb8a0cf4..4cf4c7bda 100644 --- a/src/usr/hwpf/hwp/initfiles/p8.abus.scom.initfile +++ b/src/usr/hwpf/hwp/initfiles/p8.abus.scom.initfile @@ -1,4 +1,4 @@ -#-- $Id: p8.abus.scom.initfile,v 1.10 2013/04/18 22:28:40 jgrell Exp $ +#-- $Id: p8.abus.scom.initfile,v 1.14 2013/07/30 20:45:32 jgrell Exp $ #################################################################### @@ -7,14 +7,18 @@ ## Based on SETUP_ID_MODE A_BUS_TR_HW ## from ../../logic/mesa_sim/fusion/run/IODUV_ABUS_WRAP.IODUV_ABUS_WRAP.figdb ## -## Created on Mon Apr 15 15:04:01 CDT 2013, by jgrell +## Created on Tue Jul 30 10:22:22 CDT 2013, by jgrell #################################################################### ## -- CHANGE HISTORY: ## -------------------------------------------------------------------------------- ## -- VersionID: |Author: | Date: | Comment: ## -- -----------|---------|--------|------------------------------------------------- + ## -- jfg13072400| jfg |07-24-13| HW253558: change pgooddly to MAX from lab feedback + ## -- mbs13071200| mbs |07-12-13| Updates for HW239870 and HW258990 + ## -- jgr13062500| jgr |06-25-13| Added DFE override settings (HW244323) ## -- jgr13041800| jgr |04-18-13| Added missing entries from rel 0128 + ## -- smr13032500| SMR |03-25-13| Changed rx_dyn_recal_overall_timeout_sel init to 0b100 & rx_sls_timeout_sel init to 0b110 ## -- mbs13021100| mbs |02-11-13| Changed A bus id's to 1,2,3 from 0,1,2 (HW239245) ## -- mbs13011802| mbs |01-18-13| Added rx_fence to run_mode dial (HW236326) ## -- mbs12121100| mbs |12-11-12| Added rx_prot_speed_slct and rx_c4_sel @@ -59,6 +63,31 @@ define def_is_slave = (prim_id > conn_id); +#RX0.RXCTL.RX_CTL_REGS.RX_AMAX_PG +scom 0x800A680008010C3F { + bits, scom_data, expr; + rx_amax_high, 0b01101110, def_IS_HW && def_bus_id0; + rx_amax_high, 0b01101110, def_IS_HW && def_bus_id1; + rx_amax_high, 0b01011010, def_IS_VBU && def_bus_id1; + rx_amax_high, 0b01101110, def_IS_HW && def_bus_id2; + rx_amax_high, 0b01011010, def_IS_VBU && def_bus_id2; + rx_amax_high, 0b01011010, def_IS_VBU && def_bus_id0; + rx_amax_high, 0b01101110, def_IS_HW && def_bus_id1; + rx_amax_high, 0b01011010, def_IS_VBU && def_bus_id1; + rx_amax_high, 0b01101110, def_IS_HW && def_bus_id2; + rx_amax_high, 0b01011010, def_IS_VBU && def_bus_id2; + rx_amax_low, 0b01010000, def_IS_HW && def_bus_id0; + rx_amax_low, 0b01010000, def_IS_HW && def_bus_id1; + rx_amax_low, 0b00111100, def_IS_VBU && def_bus_id1; + rx_amax_low, 0b01010000, def_IS_HW && def_bus_id2; + rx_amax_low, 0b00111100, def_IS_VBU && def_bus_id2; + rx_amax_low, 0b00111100, def_IS_VBU && def_bus_id0; + rx_amax_low, 0b01010000, def_IS_HW && def_bus_id1; + rx_amax_low, 0b00111100, def_IS_VBU && def_bus_id1; + rx_amax_low, 0b01010000, def_IS_HW && def_bus_id2; + rx_amax_low, 0b00111100, def_IS_VBU && def_bus_id2; +} + #RX0.RXCTL.RX_CTL_REGS.RX_BER_CHK_PG scom 0x800AF00008010C3F { bits, scom_data, expr; @@ -77,15 +106,15 @@ scom 0x800AF00008010C3F { #RX0.RXCTL.RX_CTL_REGS.RX_DFE_CONFIG_PP scom 0x800B780008010C3F { bits, scom_data, expr; - rx_amin_cfg, 0b010, def_IS_HW && def_bus_id0; - rx_amin_cfg, 0b010, def_IS_HW && def_bus_id1; + rx_amin_cfg, 0b111, def_IS_HW && def_bus_id0; + rx_amin_cfg, 0b111, def_IS_HW && def_bus_id1; rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id1; - rx_amin_cfg, 0b010, def_IS_HW && def_bus_id2; + rx_amin_cfg, 0b111, def_IS_HW && def_bus_id2; rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id2; rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id0; - rx_amin_cfg, 0b010, def_IS_HW && def_bus_id1; + rx_amin_cfg, 0b111, def_IS_HW && def_bus_id1; rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id1; - rx_amin_cfg, 0b010, def_IS_HW && def_bus_id2; + rx_amin_cfg, 0b111, def_IS_HW && def_bus_id2; rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id2; rx_anap_cfg, 0b10, def_IS_HW && def_bus_id0; rx_anap_cfg, 0b10, def_IS_HW && def_bus_id1; @@ -97,16 +126,16 @@ scom 0x800B780008010C3F { rx_anap_cfg, 0b00, def_IS_VBU && def_bus_id1; rx_anap_cfg, 0b10, def_IS_HW && def_bus_id2; rx_anap_cfg, 0b00, def_IS_VBU && def_bus_id2; - rx_h1ap_cfg, 0b011, def_IS_HW && def_bus_id0; - rx_h1ap_cfg, 0b011, def_IS_HW && def_bus_id1; - rx_h1ap_cfg, 0b000, def_IS_VBU && def_bus_id1; - rx_h1ap_cfg, 0b011, def_IS_HW && def_bus_id2; - rx_h1ap_cfg, 0b000, def_IS_VBU && def_bus_id2; - rx_h1ap_cfg, 0b000, def_IS_VBU && def_bus_id0; - rx_h1ap_cfg, 0b011, def_IS_HW && def_bus_id1; - rx_h1ap_cfg, 0b000, def_IS_VBU && def_bus_id1; - rx_h1ap_cfg, 0b011, def_IS_HW && def_bus_id2; - rx_h1ap_cfg, 0b000, def_IS_VBU && def_bus_id2; + rx_h1_cfg, 0b01, def_IS_HW && def_bus_id0; + rx_h1_cfg, 0b01, def_IS_HW && def_bus_id1; + rx_h1_cfg, 0b00, def_IS_VBU && def_bus_id1; + rx_h1_cfg, 0b01, def_IS_HW && def_bus_id2; + rx_h1_cfg, 0b00, def_IS_VBU && def_bus_id2; + rx_h1_cfg, 0b00, def_IS_VBU && def_bus_id0; + rx_h1_cfg, 0b01, def_IS_HW && def_bus_id1; + rx_h1_cfg, 0b00, def_IS_VBU && def_bus_id1; + rx_h1_cfg, 0b01, def_IS_HW && def_bus_id2; + rx_h1_cfg, 0b00, def_IS_VBU && def_bus_id2; rx_peak_cfg, 0b10, def_IS_HW && def_bus_id0; rx_peak_cfg, 0b10, def_IS_HW && def_bus_id1; rx_peak_cfg, 0b00, def_IS_VBU && def_bus_id1; @@ -122,15 +151,45 @@ scom 0x800B780008010C3F { #RX0.RXCTL.RX_CTL_REGS.RX_DFE_TIMERS_PP scom 0x800B800008010C3F { bits, scom_data, expr; - rx_init_tmr_cfg, 0b100, def_IS_HW && def_bus_id0; - rx_init_tmr_cfg, 0b100, def_IS_HW && def_bus_id1; + rx_ber_cfg, 0b100, def_IS_HW && def_bus_id0; + rx_ber_cfg, 0b100, def_IS_HW && def_bus_id1; + rx_ber_cfg, 0b000, def_IS_VBU && def_bus_id1; + rx_ber_cfg, 0b100, def_IS_HW && def_bus_id2; + rx_ber_cfg, 0b000, def_IS_VBU && def_bus_id2; + rx_ber_cfg, 0b000, def_IS_VBU && def_bus_id0; + rx_ber_cfg, 0b100, def_IS_HW && def_bus_id1; + rx_ber_cfg, 0b000, def_IS_VBU && def_bus_id1; + rx_ber_cfg, 0b100, def_IS_HW && def_bus_id2; + rx_ber_cfg, 0b000, def_IS_VBU && def_bus_id2; + rx_dac_bo_cfg, 0b101, def_IS_HW && def_bus_id0; + rx_dac_bo_cfg, 0b101, def_IS_HW && def_bus_id1; + rx_dac_bo_cfg, 0b000, def_IS_VBU && def_bus_id1; + rx_dac_bo_cfg, 0b101, def_IS_HW && def_bus_id2; + rx_dac_bo_cfg, 0b000, def_IS_VBU && def_bus_id2; + rx_dac_bo_cfg, 0b000, def_IS_VBU && def_bus_id0; + rx_dac_bo_cfg, 0b101, def_IS_HW && def_bus_id1; + rx_dac_bo_cfg, 0b000, def_IS_VBU && def_bus_id1; + rx_dac_bo_cfg, 0b101, def_IS_HW && def_bus_id2; + rx_dac_bo_cfg, 0b000, def_IS_VBU && def_bus_id2; + rx_ddc_cfg, 0b10, def_IS_HW && def_bus_id0; + rx_ddc_cfg, 0b10, def_IS_HW && def_bus_id1; + rx_ddc_cfg, 0b00, def_IS_VBU && def_bus_id1; + rx_ddc_cfg, 0b10, def_IS_HW && def_bus_id2; + rx_ddc_cfg, 0b00, def_IS_VBU && def_bus_id2; + rx_ddc_cfg, 0b00, def_IS_VBU && def_bus_id0; + rx_ddc_cfg, 0b10, def_IS_HW && def_bus_id1; + rx_ddc_cfg, 0b00, def_IS_VBU && def_bus_id1; + rx_ddc_cfg, 0b10, def_IS_HW && def_bus_id2; + rx_ddc_cfg, 0b00, def_IS_VBU && def_bus_id2; + rx_init_tmr_cfg, 0b111, def_IS_HW && def_bus_id0; + rx_init_tmr_cfg, 0b111, def_IS_HW && def_bus_id1; rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id1; - rx_init_tmr_cfg, 0b100, def_IS_HW && def_bus_id2; + rx_init_tmr_cfg, 0b111, def_IS_HW && def_bus_id2; rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id2; rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id0; - rx_init_tmr_cfg, 0b100, def_IS_HW && def_bus_id1; + rx_init_tmr_cfg, 0b111, def_IS_HW && def_bus_id1; rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id1; - rx_init_tmr_cfg, 0b100, def_IS_HW && def_bus_id2; + rx_init_tmr_cfg, 0b111, def_IS_HW && def_bus_id2; rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id2; rx_prot_cfg, 0b10, def_IS_HW && def_bus_id0; rx_prot_cfg, 0b10, def_IS_HW && def_bus_id1; @@ -147,9 +206,17 @@ scom 0x800B800008010C3F { #RX0.RXCTL.RX_CTL_REGS.RX_DYN_RECAL_CONFIG_PG scom 0x800A180008010C3F { bits, scom_data, expr; - rx_dyn_recal_overall_timeout_sel, 0b001, def_bus_id0; - rx_dyn_recal_overall_timeout_sel, 0b001, def_bus_id1; - rx_dyn_recal_overall_timeout_sel, 0b001, def_bus_id2; + rx_dyn_recal_overall_timeout_sel, 0b100, def_bus_id0; + rx_dyn_recal_overall_timeout_sel, 0b100, def_bus_id1; + rx_dyn_recal_overall_timeout_sel, 0b100, def_bus_id2; +} + +#RX0.RXCTL.RX_CTL_REGS.RX_DYN_RECAL_TIMEOUTS_PP +scom 0x800B400008010C3F { + bits, scom_data, expr; + rx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id0; + rx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id1; + rx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id2; } #RX0.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING1_PG @@ -231,16 +298,9 @@ scom 0x800A380008010C3F { rx_eo_enable_final_l2u_adj, 0b1, def_bus_id0; rx_eo_enable_final_l2u_adj, 0b1, def_bus_id1; rx_eo_enable_final_l2u_adj, 0b1, def_bus_id2; - rx_eo_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id0; - rx_eo_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id1; - rx_eo_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id1; - rx_eo_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id2; - rx_eo_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id2; - rx_eo_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id0; - rx_eo_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id1; - rx_eo_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id1; - rx_eo_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id2; - rx_eo_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id2; + rx_eo_enable_h1ap_tweak, 0b0, def_bus_id0; + rx_eo_enable_h1ap_tweak, 0b0, def_bus_id1; + rx_eo_enable_h1ap_tweak, 0b0, def_bus_id2; rx_eo_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id0; rx_eo_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id1; rx_eo_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id1; @@ -352,21 +412,6 @@ scom 0x8009C00008010C3F { rx_prot_speed_slct, 0b1, def_IS_VBU && def_bus_id2; } -#RX0.RXCTL.RX_CTL_REGS.RX_MODE1_PP -scom 0x800B080008010C3F { - bits, scom_data, expr; - rx_bit_lock_timeout_sel, 0b110, def_IS_HW && def_bus_id0; - rx_bit_lock_timeout_sel, 0b110, def_IS_HW && def_bus_id1; - rx_bit_lock_timeout_sel, 0b101, def_IS_VBU && def_bus_id1; - rx_bit_lock_timeout_sel, 0b110, def_IS_HW && def_bus_id2; - rx_bit_lock_timeout_sel, 0b101, def_IS_VBU && def_bus_id2; - rx_bit_lock_timeout_sel, 0b101, def_IS_VBU && def_bus_id0; - rx_bit_lock_timeout_sel, 0b110, def_IS_HW && def_bus_id1; - rx_bit_lock_timeout_sel, 0b101, def_IS_VBU && def_bus_id1; - rx_bit_lock_timeout_sel, 0b110, def_IS_HW && def_bus_id2; - rx_bit_lock_timeout_sel, 0b101, def_IS_VBU && def_bus_id2; -} - #RX0.RXCTL.RX_CTL_REGS.RX_MODE_PG scom 0x8008180008010C3F { bits, scom_data, expr; @@ -411,16 +456,9 @@ scom 0x800AB80008010C3F { rx_rc_enable_dfe_h1_cal, 0b0, def_bus_id0; rx_rc_enable_dfe_h1_cal, 0b0, def_bus_id1; rx_rc_enable_dfe_h1_cal, 0b0, def_bus_id2; - rx_rc_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id0; - rx_rc_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id1; - rx_rc_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id1; - rx_rc_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id2; - rx_rc_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id2; - rx_rc_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id0; - rx_rc_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id1; - rx_rc_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id1; - rx_rc_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id2; - rx_rc_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id2; + rx_rc_enable_h1ap_tweak, 0b0, def_bus_id0; + rx_rc_enable_h1ap_tweak, 0b0, def_bus_id1; + rx_rc_enable_h1ap_tweak, 0b0, def_bus_id2; rx_rc_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id0; rx_rc_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id1; rx_rc_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id1; @@ -453,84 +491,109 @@ scom 0x800AB80008010C3F { rx_rc_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id2; } +#RX0.RXCTL.RX_CTL_REGS.RX_RECAL_TO1_PP +scom 0x800B900008010C3F { + bits, scom_data, expr; + rx_recal_timeout_sel_b, 0b0110, def_IS_HW && def_bus_id0; + rx_recal_timeout_sel_b, 0b0110, def_IS_HW && def_bus_id1; + rx_recal_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id1; + rx_recal_timeout_sel_b, 0b0110, def_IS_HW && def_bus_id2; + rx_recal_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id2; + rx_recal_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id0; + rx_recal_timeout_sel_b, 0b0110, def_IS_HW && def_bus_id1; + rx_recal_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id1; + rx_recal_timeout_sel_b, 0b0110, def_IS_HW && def_bus_id2; + rx_recal_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id2; +} + #RX0.RXCTL.RX_CTL_REGS.RX_RECAL_TO2_PP scom 0x800B980008010C3F { bits, scom_data, expr; rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id0; rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id1; - rx_recal_timeout_sel_g, 0b0110, def_IS_VBU && def_bus_id1; + rx_recal_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id1; rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id2; - rx_recal_timeout_sel_g, 0b0110, def_IS_VBU && def_bus_id2; - rx_recal_timeout_sel_g, 0b0110, def_IS_VBU && def_bus_id0; + rx_recal_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id2; + rx_recal_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id0; rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id1; - rx_recal_timeout_sel_g, 0b0110, def_IS_VBU && def_bus_id1; + rx_recal_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id1; rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id2; - rx_recal_timeout_sel_g, 0b0110, def_IS_VBU && def_bus_id2; - rx_recal_timeout_sel_h, 0b0110, def_IS_HW && def_bus_id0; - rx_recal_timeout_sel_h, 0b0110, def_IS_HW && def_bus_id1; + rx_recal_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id2; + rx_recal_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id0; + rx_recal_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id1; rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id1; - rx_recal_timeout_sel_h, 0b0110, def_IS_HW && def_bus_id2; + rx_recal_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id2; rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id2; rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id0; - rx_recal_timeout_sel_h, 0b0110, def_IS_HW && def_bus_id1; + rx_recal_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id1; rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id1; - rx_recal_timeout_sel_h, 0b0110, def_IS_HW && def_bus_id2; + rx_recal_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id2; rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id2; } #RX0.RXCTL.RX_CTL_REGS.RX_RECAL_TO3_PP scom 0x800BA00008010C3F { bits, scom_data, expr; - rx_recal_timeout_sel_i, 0b0111, def_IS_HW && def_bus_id0; - rx_recal_timeout_sel_i, 0b0111, def_IS_HW && def_bus_id1; + rx_recal_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id0; + rx_recal_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id1; rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id1; - rx_recal_timeout_sel_i, 0b0111, def_IS_HW && def_bus_id2; + rx_recal_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id2; rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id2; rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id0; - rx_recal_timeout_sel_i, 0b0111, def_IS_HW && def_bus_id1; + rx_recal_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id1; rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id1; - rx_recal_timeout_sel_i, 0b0111, def_IS_HW && def_bus_id2; + rx_recal_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id2; rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id2; - rx_recal_timeout_sel_l, 0b0100, def_IS_HW && def_bus_id0; - rx_recal_timeout_sel_l, 0b0100, def_IS_HW && def_bus_id1; - rx_recal_timeout_sel_l, 0b0110, def_IS_VBU && def_bus_id1; - rx_recal_timeout_sel_l, 0b0100, def_IS_HW && def_bus_id2; - rx_recal_timeout_sel_l, 0b0110, def_IS_VBU && def_bus_id2; - rx_recal_timeout_sel_l, 0b0110, def_IS_VBU && def_bus_id0; - rx_recal_timeout_sel_l, 0b0100, def_IS_HW && def_bus_id1; - rx_recal_timeout_sel_l, 0b0110, def_IS_VBU && def_bus_id1; - rx_recal_timeout_sel_l, 0b0100, def_IS_HW && def_bus_id2; - rx_recal_timeout_sel_l, 0b0110, def_IS_VBU && def_bus_id2; + rx_recal_timeout_sel_j, 0b1011, def_IS_HW && def_bus_id0; + rx_recal_timeout_sel_j, 0b1011, def_IS_HW && def_bus_id1; + rx_recal_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id1; + rx_recal_timeout_sel_j, 0b1011, def_IS_HW && def_bus_id2; + rx_recal_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id2; + rx_recal_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id0; + rx_recal_timeout_sel_j, 0b1011, def_IS_HW && def_bus_id1; + rx_recal_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id1; + rx_recal_timeout_sel_j, 0b1011, def_IS_HW && def_bus_id2; + rx_recal_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id2; + rx_recal_timeout_sel_k, 0b1011, def_IS_HW && def_bus_id0; + rx_recal_timeout_sel_k, 0b1011, def_IS_HW && def_bus_id1; + rx_recal_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id1; + rx_recal_timeout_sel_k, 0b1011, def_IS_HW && def_bus_id2; + rx_recal_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id2; + rx_recal_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id0; + rx_recal_timeout_sel_k, 0b1011, def_IS_HW && def_bus_id1; + rx_recal_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id1; + rx_recal_timeout_sel_k, 0b1011, def_IS_HW && def_bus_id2; + rx_recal_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id2; } #RX0.RXCTL.RX_CTL_REGS.RX_SERVO_TO1_PP scom 0x800B600008010C3F { bits, scom_data, expr; - rx_servo_timeout_sel_d, 0b1001, def_IS_HW && def_bus_id0; - rx_servo_timeout_sel_d, 0b1001, def_IS_HW && def_bus_id1; + rx_servo_timeout_sel_b, 0b1010, def_IS_HW && def_bus_id0; + rx_servo_timeout_sel_b, 0b1010, def_IS_HW && def_bus_id1; + rx_servo_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id1; + rx_servo_timeout_sel_b, 0b1010, def_IS_HW && def_bus_id2; + rx_servo_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id2; + rx_servo_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id0; + rx_servo_timeout_sel_b, 0b1010, def_IS_HW && def_bus_id1; + rx_servo_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id1; + rx_servo_timeout_sel_b, 0b1010, def_IS_HW && def_bus_id2; + rx_servo_timeout_sel_b, 0b1000, def_IS_VBU && def_bus_id2; + rx_servo_timeout_sel_d, 0b1010, def_IS_HW && def_bus_id0; + rx_servo_timeout_sel_d, 0b1010, def_IS_HW && def_bus_id1; rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_d, 0b1001, def_IS_HW && def_bus_id2; + rx_servo_timeout_sel_d, 0b1010, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id2; rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id0; - rx_servo_timeout_sel_d, 0b1001, def_IS_HW && def_bus_id1; + rx_servo_timeout_sel_d, 0b1010, def_IS_HW && def_bus_id1; rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_d, 0b1001, def_IS_HW && def_bus_id2; + rx_servo_timeout_sel_d, 0b1010, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id2; } #RX0.RXCTL.RX_CTL_REGS.RX_SERVO_TO2_PP scom 0x800B680008010C3F { bits, scom_data, expr; - rx_servo_timeout_sel_f, 0b0001, def_IS_HW && def_bus_id0; - rx_servo_timeout_sel_f, 0b0001, def_IS_HW && def_bus_id1; - rx_servo_timeout_sel_f, 0b0110, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_f, 0b0001, def_IS_HW && def_bus_id2; - rx_servo_timeout_sel_f, 0b0110, def_IS_VBU && def_bus_id2; - rx_servo_timeout_sel_f, 0b0110, def_IS_VBU && def_bus_id0; - rx_servo_timeout_sel_f, 0b0001, def_IS_HW && def_bus_id1; - rx_servo_timeout_sel_f, 0b0110, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_f, 0b0001, def_IS_HW && def_bus_id2; - rx_servo_timeout_sel_f, 0b0110, def_IS_VBU && def_bus_id2; rx_servo_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id0; rx_servo_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id1; rx_servo_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id1; @@ -541,15 +604,15 @@ scom 0x800B680008010C3F { rx_servo_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id1; rx_servo_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id2; - rx_servo_timeout_sel_h, 0b1110, def_IS_HW && def_bus_id0; - rx_servo_timeout_sel_h, 0b1110, def_IS_HW && def_bus_id1; + rx_servo_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id0; + rx_servo_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id1; rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_h, 0b1110, def_IS_HW && def_bus_id2; + rx_servo_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id2; rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id0; - rx_servo_timeout_sel_h, 0b1110, def_IS_HW && def_bus_id1; + rx_servo_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id1; rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_h, 0b1110, def_IS_HW && def_bus_id2; + rx_servo_timeout_sel_h, 0b1011, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id2; } @@ -566,15 +629,15 @@ scom 0x800B700008010C3F { rx_servo_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id1; rx_servo_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id2; - rx_servo_timeout_sel_j, 0b1100, def_IS_HW && def_bus_id0; - rx_servo_timeout_sel_j, 0b1100, def_IS_HW && def_bus_id1; + rx_servo_timeout_sel_j, 0b1101, def_IS_HW && def_bus_id0; + rx_servo_timeout_sel_j, 0b1101, def_IS_HW && def_bus_id1; rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_j, 0b1100, def_IS_HW && def_bus_id2; + rx_servo_timeout_sel_j, 0b1101, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id2; rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id0; - rx_servo_timeout_sel_j, 0b1100, def_IS_HW && def_bus_id1; + rx_servo_timeout_sel_j, 0b1101, def_IS_HW && def_bus_id1; rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id1; - rx_servo_timeout_sel_j, 0b1100, def_IS_HW && def_bus_id2; + rx_servo_timeout_sel_j, 0b1101, def_IS_HW && def_bus_id2; rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id2; rx_servo_timeout_sel_k, 0b1101, def_IS_HW && def_bus_id0; rx_servo_timeout_sel_k, 0b1101, def_IS_HW && def_bus_id1; @@ -666,9 +729,9 @@ scom 0x8008980008010C3F { rx_ds_timeout_sel, 0b010, def_IS_VBU && def_bus_id1; rx_ds_timeout_sel, 0b110, def_IS_HW && def_bus_id2; rx_ds_timeout_sel, 0b010, def_IS_VBU && def_bus_id2; - rx_sls_timeout_sel, 0b001, def_bus_id0; - rx_sls_timeout_sel, 0b001, def_bus_id1; - rx_sls_timeout_sel, 0b001, def_bus_id2; + rx_sls_timeout_sel, 0b110, def_bus_id0; + rx_sls_timeout_sel, 0b110, def_bus_id1; + rx_sls_timeout_sel, 0b110, def_bus_id2; rx_wt_timeout_sel, 0b111, def_IS_HW && def_bus_id0; rx_wt_timeout_sel, 0b111, def_IS_HW && def_bus_id1; rx_wt_timeout_sel, 0b011, def_IS_VBU && def_bus_id1; @@ -703,15 +766,15 @@ scom 0x8009580008010C3F { #RX0.RXCTL.RX_CTL_REGS.RX_WIRETEST_PLL_CNTL_PG scom 0x800A300008010C3F { bits, scom_data, expr; - rx_wt_cu_pll_pgooddly, 0b001, def_IS_HW && def_bus_id0; - rx_wt_cu_pll_pgooddly, 0b001, def_IS_HW && def_bus_id1; + rx_wt_cu_pll_pgooddly, 0b110, def_IS_HW && def_bus_id0; + rx_wt_cu_pll_pgooddly, 0b110, def_IS_HW && def_bus_id1; rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id1; - rx_wt_cu_pll_pgooddly, 0b001, def_IS_HW && def_bus_id2; + rx_wt_cu_pll_pgooddly, 0b110, def_IS_HW && def_bus_id2; rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id2; rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id0; - rx_wt_cu_pll_pgooddly, 0b001, def_IS_HW && def_bus_id1; + rx_wt_cu_pll_pgooddly, 0b110, def_IS_HW && def_bus_id1; rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id1; - rx_wt_cu_pll_pgooddly, 0b001, def_IS_HW && def_bus_id2; + rx_wt_cu_pll_pgooddly, 0b110, def_IS_HW && def_bus_id2; rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id2; rx_wt_cu_pll_reset, 0b0, def_IS_HW && def_bus_id0; rx_wt_cu_pll_reset, 0b0, def_IS_HW && def_bus_id1; @@ -725,6 +788,21 @@ scom 0x800A300008010C3F { rx_wt_cu_pll_reset, 0b1, def_IS_VBU && def_bus_id2; } +#RX0.RXPACKS#0.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_AMP_VAL_PL +scom 0x8000501508010C3F { + bits, scom_data, expr; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; +} + #RX0.RXPACKS#0.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B01508010C3F { bits, scom_data, expr; @@ -733,6 +811,21 @@ scom 0x8000B01508010C3F { rx_prbs_tap_id, 0b001, def_bus_id2; } +#RX0.RXPACKS#0.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_AMP_VAL_PL +scom 0x8000501408010C3F { + bits, scom_data, expr; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; +} + #RX0.RXPACKS#0.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B01408010C3F { bits, scom_data, expr; @@ -741,6 +834,21 @@ scom 0x8000B01408010C3F { rx_prbs_tap_id, 0b010, def_bus_id2; } +#RX0.RXPACKS#0.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_AMP_VAL_PL +scom 0x8000501608010C3F { + bits, scom_data, expr; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; +} + #RX0.RXPACKS#0.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B01608010C3F { bits, scom_data, expr; @@ -749,6 +857,21 @@ scom 0x8000B01608010C3F { rx_prbs_tap_id, 0b000, def_bus_id2; } +#RX0.RXPACKS#0.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_AMP_VAL_PL +scom 0x8000500A08010C3F { + bits, scom_data, expr; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; +} + #RX0.RXPACKS#0.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B00A08010C3F { bits, scom_data, expr; @@ -757,6 +880,21 @@ scom 0x8000B00A08010C3F { rx_prbs_tap_id, 0b010, def_bus_id2; } +#RX0.RXPACKS#0.RXPACK.RD.SLICE#4.RD.RX_BIT_REGS.RX_AMP_VAL_PL +scom 0x8000500B08010C3F { + bits, scom_data, expr; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; +} + #RX0.RXPACKS#0.RXPACK.RD.SLICE#4.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B00B08010C3F { bits, scom_data, expr; @@ -765,6 +903,21 @@ scom 0x8000B00B08010C3F { rx_prbs_tap_id, 0b011, def_bus_id2; } +#RX0.RXPACKS#0.RXPACK.RD.SLICE#5.RD.RX_BIT_REGS.RX_AMP_VAL_PL +scom 0x8000500908010C3F { + bits, scom_data, expr; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; +} + #RX0.RXPACKS#0.RXPACK.RD.SLICE#5.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B00908010C3F { bits, scom_data, expr; @@ -773,6 +926,21 @@ scom 0x8000B00908010C3F { rx_prbs_tap_id, 0b001, def_bus_id2; } +#RX0.RXPACKS#1.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_AMP_VAL_PL +scom 0x8000501208010C3F { + bits, scom_data, expr; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; +} + #RX0.RXPACKS#1.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B01208010C3F { bits, scom_data, expr; @@ -781,6 +949,21 @@ scom 0x8000B01208010C3F { rx_prbs_tap_id, 0b100, def_bus_id2; } +#RX0.RXPACKS#1.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_AMP_VAL_PL +scom 0x8000501708010C3F { + bits, scom_data, expr; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; +} + #RX0.RXPACKS#1.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B01708010C3F { bits, scom_data, expr; @@ -789,6 +972,21 @@ scom 0x8000B01708010C3F { rx_prbs_tap_id, 0b000, def_bus_id2; } +#RX0.RXPACKS#1.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_AMP_VAL_PL +scom 0x8000500708010C3F { + bits, scom_data, expr; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; +} + #RX0.RXPACKS#1.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B00708010C3F { bits, scom_data, expr; @@ -797,6 +995,21 @@ scom 0x8000B00708010C3F { rx_prbs_tap_id, 0b111, def_bus_id2; } +#RX0.RXPACKS#1.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_AMP_VAL_PL +scom 0x8000501308010C3F { + bits, scom_data, expr; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; +} + #RX0.RXPACKS#1.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B01308010C3F { bits, scom_data, expr; @@ -805,6 +1018,21 @@ scom 0x8000B01308010C3F { rx_prbs_tap_id, 0b011, def_bus_id2; } +#RX0.RXPACKS#1.RXPACK.RD.SLICE#4.RD.RX_BIT_REGS.RX_AMP_VAL_PL +scom 0x8000500608010C3F { + bits, scom_data, expr; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; +} + #RX0.RXPACKS#1.RXPACK.RD.SLICE#4.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B00608010C3F { bits, scom_data, expr; @@ -813,6 +1041,21 @@ scom 0x8000B00608010C3F { rx_prbs_tap_id, 0b110, def_bus_id2; } +#RX0.RXPACKS#1.RXPACK.RD.SLICE#5.RD.RX_BIT_REGS.RX_AMP_VAL_PL +scom 0x8000500808010C3F { + bits, scom_data, expr; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; +} + #RX0.RXPACKS#1.RXPACK.RD.SLICE#5.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B00808010C3F { bits, scom_data, expr; @@ -821,6 +1064,21 @@ scom 0x8000B00808010C3F { rx_prbs_tap_id, 0b000, def_bus_id2; } +#RX0.RXPACKS#2.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_AMP_VAL_PL +scom 0x8000500508010C3F { + bits, scom_data, expr; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; +} + #RX0.RXPACKS#2.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B00508010C3F { bits, scom_data, expr; @@ -829,6 +1087,21 @@ scom 0x8000B00508010C3F { rx_prbs_tap_id, 0b101, def_bus_id2; } +#RX0.RXPACKS#2.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_AMP_VAL_PL +scom 0x8000500308010C3F { + bits, scom_data, expr; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; +} + #RX0.RXPACKS#2.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B00308010C3F { bits, scom_data, expr; @@ -837,6 +1110,21 @@ scom 0x8000B00308010C3F { rx_prbs_tap_id, 0b011, def_bus_id2; } +#RX0.RXPACKS#2.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_AMP_VAL_PL +scom 0x8000501108010C3F { + bits, scom_data, expr; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; +} + #RX0.RXPACKS#2.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B01108010C3F { bits, scom_data, expr; @@ -845,6 +1133,21 @@ scom 0x8000B01108010C3F { rx_prbs_tap_id, 0b101, def_bus_id2; } +#RX0.RXPACKS#2.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_AMP_VAL_PL +scom 0x8000500408010C3F { + bits, scom_data, expr; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; +} + #RX0.RXPACKS#2.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B00408010C3F { bits, scom_data, expr; @@ -853,6 +1156,21 @@ scom 0x8000B00408010C3F { rx_prbs_tap_id, 0b100, def_bus_id2; } +#RX0.RXPACKS#2.RXPACK.RD.SLICE#4.RD.RX_BIT_REGS.RX_AMP_VAL_PL +scom 0x8000501008010C3F { + bits, scom_data, expr; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; +} + #RX0.RXPACKS#2.RXPACK.RD.SLICE#4.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B01008010C3F { bits, scom_data, expr; @@ -861,6 +1179,21 @@ scom 0x8000B01008010C3F { rx_prbs_tap_id, 0b110, def_bus_id2; } +#RX0.RXPACKS#2.RXPACK.RD.SLICE#5.RD.RX_BIT_REGS.RX_AMP_VAL_PL +scom 0x8000500F08010C3F { + bits, scom_data, expr; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; +} + #RX0.RXPACKS#2.RXPACK.RD.SLICE#5.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B00F08010C3F { bits, scom_data, expr; @@ -869,6 +1202,21 @@ scom 0x8000B00F08010C3F { rx_prbs_tap_id, 0b111, def_bus_id2; } +#RX0.RXPACKS#3.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_AMP_VAL_PL +scom 0x8000500008010C3F { + bits, scom_data, expr; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; +} + #RX0.RXPACKS#3.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B00008010C3F { bits, scom_data, expr; @@ -877,6 +1225,21 @@ scom 0x8000B00008010C3F { rx_prbs_tap_id, 0b000, def_bus_id2; } +#RX0.RXPACKS#3.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_AMP_VAL_PL +scom 0x8000500208010C3F { + bits, scom_data, expr; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; +} + #RX0.RXPACKS#3.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B00208010C3F { bits, scom_data, expr; @@ -885,6 +1248,21 @@ scom 0x8000B00208010C3F { rx_prbs_tap_id, 0b010, def_bus_id2; } +#RX0.RXPACKS#3.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_AMP_VAL_PL +scom 0x8000500108010C3F { + bits, scom_data, expr; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; +} + #RX0.RXPACKS#3.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B00108010C3F { bits, scom_data, expr; @@ -893,6 +1271,21 @@ scom 0x8000B00108010C3F { rx_prbs_tap_id, 0b001, def_bus_id2; } +#RX0.RXPACKS#3.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_AMP_VAL_PL +scom 0x8000500E08010C3F { + bits, scom_data, expr; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; +} + #RX0.RXPACKS#3.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B00E08010C3F { bits, scom_data, expr; @@ -901,6 +1294,21 @@ scom 0x8000B00E08010C3F { rx_prbs_tap_id, 0b000, def_bus_id2; } +#RX0.RXPACKS#3.RXPACK.RD.SLICE#4.RD.RX_BIT_REGS.RX_AMP_VAL_PL +scom 0x8000500C08010C3F { + bits, scom_data, expr; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; +} + #RX0.RXPACKS#3.RXPACK.RD.SLICE#4.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B00C08010C3F { bits, scom_data, expr; @@ -909,6 +1317,21 @@ scom 0x8000B00C08010C3F { rx_prbs_tap_id, 0b010, def_bus_id2; } +#RX0.RXPACKS#3.RXPACK.RD.SLICE#5.RD.RX_BIT_REGS.RX_AMP_VAL_PL +scom 0x8000500D08010C3F { + bits, scom_data, expr; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id0; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id0; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id1; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id1; + rx_amp_gain, 0b1001, def_IS_HW && def_bus_id2; + rx_amp_gain, 0b0000, def_IS_VBU && def_bus_id2; +} + #RX0.RXPACKS#3.RXPACK.RD.SLICE#5.RD.RX_BIT_REGS.RX_PRBS_MODE_PL scom 0x8000B00D08010C3F { bits, scom_data, expr; @@ -925,6 +1348,14 @@ scom 0x800CC40008010C3F { tx_drv_clk_pattern_gcrmsg, 0b00, def_bus_id2; } +#TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_DYN_RECAL_TIMEOUTS_PP +scom 0x800EAC0008010C3F { + bits, scom_data, expr; + tx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id0; + tx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id1; + tx_dyn_recal_interval_timeout_sel, 0b101, def_bus_id2; +} + #TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_ID1_PG scom 0x800C940008010C3F { bits, scom_data, expr; diff --git a/src/usr/hwpf/hwp/initfiles/p8.dmi.custom.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.dmi.custom.scom.initfile index 183ed1a35..1cfd3a003 100644 --- a/src/usr/hwpf/hwp/initfiles/p8.dmi.custom.scom.initfile +++ b/src/usr/hwpf/hwp/initfiles/p8.dmi.custom.scom.initfile @@ -1,4 +1,4 @@ -#-- $Id: p8.dmi.custom.scom.initfile,v 1.9 2013/05/01 20:31:29 jgrell Exp $ +#-- $Id: p8.dmi.custom.scom.initfile,v 1.12 2013/06/27 15:07:02 jgrell Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: @@ -256,41 +256,6 @@ scom 0x800.0b(tx_mode_pg)(tx_grp3)(lane_na).0x(dmi0_gcr_addr) { #--************************************************************************************************************** #---------------------------------------------------------------------------------------------------------------- -# ________________ ____ ________ ____ _ __ __ ___ __ -# / ____/ ____/ __ \ / __ )__ __/ __/ __/__ _____ / __ \____ ______(_) /___ __ / |/ /___ ______/ /__ -# / / __/ / / /_/ / / __ / / / / /_/ /_/ _ \/ ___/ / /_/ / __ `/ ___/ / __/ / / / / /|_/ / __ `/ ___/ //_/ -# / /_/ / /___/ _, _/ / /_/ / /_/ / __/ __/ __/ / / ____/ /_/ / / / / /_/ /_/ / / / / / /_/ (__ ) ,< -# \____/\____/_/ |_| /_____/\__,_/_/ /_/ \___/_/ /_/ \__,_/_/ /_/\__/\__, / /_/ /_/\__,_/____/_/|_| -# /____/ -#---------------------------------------------------------------------------------------------------------------- -#--************************************************************************************************************** -# HW242564: Temporarily mask the GCR Buffer Parity Checker until the source of the error can be found. This ungates the lab. -# 0x800???0002011E3F -# This is applied to all configured clkgrp's via chiplet targetting -scom 0x800.0b(rx_fir1_mask_pg)(rx_grp3)(lane_na).0x(dmi0_gcr_addr) { -bits, scom_data; -rx_pg_fir_err_mask_gcr_buff, 0b1; -} -scom 0x800.0b(tx_fir_mask_pg)(tx_grp3)(lane_na).0x(dmi0_gcr_addr) { -bits, scom_data; -tx_pg_fir_err_mask_gcr_buff, 0b1; -} -scom 0x800.0b(rx_fir_mask_pb)(rx_grp3)(lane_na).0x(dmi0_gcr_addr) { -bits, scom_data; -rx_pb_fir_err_mask_gcr_buff0, 0b1; -rx_pb_fir_err_mask_gcr_buff1, 0b1; -rx_pb_fir_err_mask_gcr_buff2, 0b1; -} - -# Mask off all rx and tx parity errors in the fir register -scom 0x02011A03 { -scom_data; -0xC000000000000000; -} - - -#--************************************************************************************************************** -#---------------------------------------------------------------------------------------------------------------- # Recal #---------------------------------------------------------------------------------------------------------------- #--************************************************************************************************************** diff --git a/src/usr/hwpf/hwp/initfiles/p8.mcs.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.mcs.scom.initfile index 6e50c4733..a194fcefe 100644 --- a/src/usr/hwpf/hwp/initfiles/p8.mcs.scom.initfile +++ b/src/usr/hwpf/hwp/initfiles/p8.mcs.scom.initfile @@ -1,4 +1,4 @@ -#-- $Id: p8.mcs.scom.initfile,v 1.10 2013/05/08 13:14:33 jmcgill Exp $ +#-- $Id: p8.mcs.scom.initfile,v 1.11 2013/07/18 13:56:05 jmcgill Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: @@ -161,6 +161,7 @@ define ecc_bypass_disable = ((TGT1.ATTR_CHIP_EC_FEATURE_MCS_ECC_BYPASS_DISABLE ! 1:3, 0b111 ; # DISABLE INTERFACE AND ARBITER BLOCKING DURING INTERNAL MCS CHECKSTOP 17:18, 0b01 ; # MCMODE4Q_SELECT_RPTHANG_DECODE 19 , 0b1 ; # MCMODE4Q_LOCAL_TIMEBASE_SELECT + 21 , 0b1 ; # MCMODE4Q_DISABLE_POWERBUS_READ_AND_WRITE_RAMPS_DURING_CHECKSTOP } #--****************************************************************************** diff --git a/src/usr/hwpf/hwp/p8_pmc_deconfig_setup_errors.xml b/src/usr/hwpf/hwp/p8_pmc_deconfig_setup_errors.xml index 0b5da9d25..c500fbf43 100644 --- a/src/usr/hwpf/hwp/p8_pmc_deconfig_setup_errors.xml +++ b/src/usr/hwpf/hwp/p8_pmc_deconfig_setup_errors.xml @@ -5,7 +5,7 @@ <!-- --> <!-- IBM CONFIDENTIAL --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2012 --> +<!-- COPYRIGHT International Business Machines Corp. 2012,2013 --> <!-- --> <!-- p1 --> <!-- --> @@ -20,6 +20,7 @@ <!-- Origin: 30 --> <!-- --> <!-- IBM_PROLOG_END_TAG --> +<!-- $Id: p8_pmc_deconfig_setup_errors.xml,v 1.2 2013/05/23 18:44:24 stillgs Exp $ --> <!-- Error definitions for p8_pmc_deconfig_setup procedure --> <hwpErrors> <!-- *********************************************************************** --> diff --git a/src/usr/hwpf/hwp/p8_poregpe_errors.xml b/src/usr/hwpf/hwp/p8_poregpe_errors.xml deleted file mode 100644 index 152cc34d9..000000000 --- a/src/usr/hwpf/hwp/p8_poregpe_errors.xml +++ /dev/null @@ -1,45 +0,0 @@ -<!-- IBM_PROLOG_BEGIN_TAG --> -<!-- This is an automatically generated prolog. --> -<!-- --> -<!-- $Source: src/usr/hwpf/hwp/p8_poregpe_errors.xml $ --> -<!-- --> -<!-- IBM CONFIDENTIAL --> -<!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2012 --> -<!-- --> -<!-- p1 --> -<!-- --> -<!-- Object Code Only (OCO) source materials --> -<!-- Licensed Internal Code Source Materials --> -<!-- IBM HostBoot Licensed Internal Code --> -<!-- --> -<!-- The source code for this program is not published or otherwise --> -<!-- divested of its trade secrets, irrespective of what has been --> -<!-- deposited with the U.S. Copyright Office. --> -<!-- --> -<!-- Origin: 30 --> -<!-- --> -<!-- IBM_PROLOG_END_TAG --> -<!-- Error definitions for proc_poregpe procedure --> -<hwpErrors> - <!-- *********************************************************************** --> - <hwpError> - <rc>RC_PROCPM_GPE0_RESET_TIMEOUT</rc> - <description>GPE0 reset failed in proc_poregpe_init.</description> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>RC_PROCPM_GPE1_RESET_TIMEOUT</rc> - <description>GPE1 reset failed in proc_poregpe_init.</description> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>RC_PROCPM_GPE_CODE_BAD_MODE</rc> - <description>Unknown mode passed to proc_poregpe_init.</description> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>RC_PROCPM_GPE_BAD_ENGINE</rc> - <description>Unknown engine passed to proc_poregpe_init. </description> - </hwpError> -</hwpErrors> diff --git a/src/usr/hwpf/hwp/p8_poreslw_errors.xml b/src/usr/hwpf/hwp/p8_poreslw_errors.xml deleted file mode 100644 index 6878351ec..000000000 --- a/src/usr/hwpf/hwp/p8_poreslw_errors.xml +++ /dev/null @@ -1,40 +0,0 @@ -<!-- IBM_PROLOG_BEGIN_TAG --> -<!-- This is an automatically generated prolog. --> -<!-- --> -<!-- $Source: src/usr/hwpf/hwp/p8_poreslw_errors.xml $ --> -<!-- --> -<!-- IBM CONFIDENTIAL --> -<!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2012 --> -<!-- --> -<!-- p1 --> -<!-- --> -<!-- Object Code Only (OCO) source materials --> -<!-- Licensed Internal Code Source Materials --> -<!-- IBM HostBoot Licensed Internal Code --> -<!-- --> -<!-- The source code for this program is not published or otherwise --> -<!-- divested of its trade secrets, irrespective of what has been --> -<!-- deposited with the U.S. Copyright Office. --> -<!-- --> -<!-- Origin: 30 --> -<!-- --> -<!-- IBM_PROLOG_END_TAG --> -<!-- Error definitions for p8_poreslw procedure --> -<hwpErrors> - <!-- *********************************************************************** --> - <hwpError> - <rc>RC_PROCPM_PORESLW_CODE_BAD_TBA</rc> - <description>Invalid Table Base Address value passed to p8_poreslw_init.</description> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>RC_PROCPM_SLW_RESET_TIMEOUT</rc> - <description>SLW reset failed in p8_poreslw_init.</description> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>RC_PROCPM_PORESLW_CODE_BAD_MODE</rc> - <description>Unknown mode passed to p8_poreslw_init.</description> - </hwpError> -</hwpErrors> diff --git a/src/usr/hwpf/hwp/runtime_errors/proc_force_vsafe_errors.xml b/src/usr/hwpf/hwp/runtime_errors/p8_force_vsafe_errors.xml index 243f745c0..908ff8c97 100644 --- a/src/usr/hwpf/hwp/runtime_errors/proc_force_vsafe_errors.xml +++ b/src/usr/hwpf/hwp/runtime_errors/p8_force_vsafe_errors.xml @@ -1,11 +1,11 @@ <!-- IBM_PROLOG_BEGIN_TAG --> <!-- This is an automatically generated prolog. --> <!-- --> -<!-- $Source: src/usr/hwpf/hwp/runtime_errors/proc_force_vsafe_errors.xml $ --> +<!-- $Source: src/usr/hwpf/hwp/runtime_errors/p8_force_vsafe_errors.xml $ --> <!-- --> <!-- IBM CONFIDENTIAL --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2012,2013 --> +<!-- COPYRIGHT International Business Machines Corp. 2013 --> <!-- --> <!-- p1 --> <!-- --> diff --git a/src/usr/hwpf/hwp/runtime_errors/p8_poregpe_errors.xml b/src/usr/hwpf/hwp/runtime_errors/p8_poregpe_errors.xml index 9725f2ffc..97c314aec 100644 --- a/src/usr/hwpf/hwp/runtime_errors/p8_poregpe_errors.xml +++ b/src/usr/hwpf/hwp/runtime_errors/p8_poregpe_errors.xml @@ -5,7 +5,7 @@ <!-- --> <!-- IBM CONFIDENTIAL --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2012 --> +<!-- COPYRIGHT International Business Machines Corp. 2012,2013 --> <!-- --> <!-- p1 --> <!-- --> @@ -20,6 +20,7 @@ <!-- Origin: 30 --> <!-- --> <!-- IBM_PROLOG_END_TAG --> +<!-- $Id: p8_poregpe_errors.xml,v 1.2 2013/05/23 18:44:30 stillgs Exp $ --> <!-- Error definitions for proc_poregpe procedure --> <hwpErrors> <!-- *********************************************************************** --> diff --git a/src/usr/hwpf/hwp/runtime_errors/proc_pss_errors.xml b/src/usr/hwpf/hwp/runtime_errors/p8_pss_errors.xml index 90e6ee0c0..b5bf0ecab 100644 --- a/src/usr/hwpf/hwp/runtime_errors/proc_pss_errors.xml +++ b/src/usr/hwpf/hwp/runtime_errors/p8_pss_errors.xml @@ -1,11 +1,11 @@ <!-- IBM_PROLOG_BEGIN_TAG --> <!-- This is an automatically generated prolog. --> <!-- --> -<!-- $Source: src/usr/hwpf/hwp/runtime_errors/proc_pss_errors.xml $ --> +<!-- $Source: src/usr/hwpf/hwp/runtime_errors/p8_pss_errors.xml $ --> <!-- --> <!-- IBM CONFIDENTIAL --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2012 --> +<!-- COPYRIGHT International Business Machines Corp. 2013 --> <!-- --> <!-- p1 --> <!-- --> @@ -20,6 +20,7 @@ <!-- Origin: 30 --> <!-- --> <!-- IBM_PROLOG_END_TAG --> +<!-- $Id: p8_pss_errors.xml,v 1.2 2013/05/23 18:44:33 stillgs Exp $ --> <!-- Error definitions for proc_pmc_init procedure --> <hwpErrors> <!-- *********************************************************************** --> diff --git a/src/usr/hwpf/hwp/thread_activate/proc_thread_control/proc_thread_control.xml b/src/usr/hwpf/hwp/thread_activate/proc_thread_control/proc_thread_control.xml index 98d252c7d..e6372c795 100644 --- a/src/usr/hwpf/hwp/thread_activate/proc_thread_control/proc_thread_control.xml +++ b/src/usr/hwpf/hwp/thread_activate/proc_thread_control/proc_thread_control.xml @@ -5,7 +5,7 @@ <!-- --> <!-- IBM CONFIDENTIAL --> <!-- --> -<!-- COPYRIGHT International Business Machines Corp. 2012 --> +<!-- COPYRIGHT International Business Machines Corp. 2012,2013 --> <!-- --> <!-- p1 --> <!-- --> @@ -40,15 +40,6 @@ </hwpError> <!-- ********************************************************************* --> <hwpError> - <rc>RC_PROC_PBA_ADDR_ALIGNMENT_ERROR</rc> - <description>pba BAR must be on a 1MB boundary</description> - </hwpError> - <!-- *********************************************************************** --> - <hwpError> - <rc>RC_PROC_PBA_BAR_SIZE_INVALID</rc> - <description>Non-zero PBA BAR defined with region size of 0. Size must be 1MB or greater</description> - </hwpError> - <hwpError> <rc>RC_PROC_THREAD_CONTROL_START_FAIL</rc> <description>Sreset command failed: RAS STAT instruction completed bit was not set after start command.</description> </hwpError> diff --git a/src/usr/hwpf/makefile b/src/usr/hwpf/makefile index f1352da1a..012c3f6c1 100644 --- a/src/usr/hwpf/makefile +++ b/src/usr/hwpf/makefile @@ -43,7 +43,7 @@ HWP_ERROR_XML_FILES = hwp/fapiHwpErrorInfo.xml \ hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit_errors.xml \ hwp/build_winkle_images/p8_slw_build/p8_slw_build_errors.xml \ hwp/build_winkle_images/p8_slw_build/p8_xip_customize_errors.xml \ - hwp/build_winkle_images/p8_slw_build/proc_pba_bar_config_errors.xml \ + hwp/build_winkle_images/p8_slw_build/p8_pba_bar_config_errors.xml \ hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup_errors.xml \ hwp/core_activate/proc_prep_master_winkle/proc_prep_master_winkle_errors.xml \ hwp/core_activate/proc_stop_deadman_timer/proc_stop_deadman_timer_errors.xml \ @@ -66,9 +66,9 @@ HWP_ERROR_XML_FILES = hwp/fapiHwpErrorInfo.xml \ hwp/runtime_errors/p8_oha_init_errors.xml \ hwp/runtime_errors/p8_pcbs_init_errors.xml \ hwp/runtime_errors/p8_pm_prep_for_reset_errors.xml \ - hwp/runtime_errors/proc_force_vsafe_errors.xml \ + hwp/runtime_errors/p8_force_vsafe_errors.xml \ hwp/runtime_errors/p8_pmc_errors.xml \ - hwp/runtime_errors/proc_pss_errors.xml \ + hwp/runtime_errors/p8_pss_errors.xml \ hwp/runtime_errors/proc_cpu_special_wakeup_errors.xml \ hwp/runtime_errors/p8_poregpe_errors.xml \ hwp/runtime_errors/p8_pba_init_errors.xml \ |
