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| author | Thi Tran <thi@us.ibm.com> | 2015-09-28 16:18:43 -0500 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2015-10-05 13:07:50 -0500 |
| commit | 597ebc37c6c4b16a62b0f693cc18d9f371e9bbb5 (patch) | |
| tree | 66e9388c9c78ed0d4a0198584fea2cea1ef3f77d /src/usr | |
| parent | eae12628f9d1c33505ebe6c41f57d7352f62ee0b (diff) | |
| download | talos-hostboot-597ebc37c6c4b16a62b0f693cc18d9f371e9bbb5.tar.gz talos-hostboot-597ebc37c6c4b16a62b0f693cc18d9f371e9bbb5.zip | |
SW323543: INITPROC: Workaround for IPL training fail
CQ:SW323543
Change-Id: Iac1be4ce141aaf56238be34dac16debd3fdb3897
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/20822
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/20823
Tested-by: Jenkins Server
Tested-by: Jenkins OP Build CI
Tested-by: Jenkins OP HW
Tested-by: FSP CI Jenkins
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr')
| -rw-r--r-- | src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C | 10982 |
1 files changed, 5572 insertions, 5410 deletions
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C index bf18b79f2..11905cba1 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C +++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C @@ -22,7 +22,7 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_draminit_training.C,v 1.101 2015/07/14 17:42:00 sglancy Exp $ +// $Id: mss_draminit_training.C,v 1.103 2015/09/22 19:13:20 kmack Exp $ //------------------------------------------------------------------------------ // Don't forget to create CVS comments when you check in your changes! //------------------------------------------------------------------------------ @@ -30,6 +30,8 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|------------------------------------------------ +// 1.103 | kmack |16-SEP-15| Replaced sleep with fapiDelay +// 1.102 | kmack |16-SEP-15| DQS Alignment Workaround // 1.101 | sglancy |14-JUL-15| Fixed compile issue // 1.100 | sglancy |13-JUL-15| Fixed compile issue // 1.99 | sglancy |13-JUL-15| Fixed LR DIMM order of operations and addressed FW comments @@ -39,11 +41,11 @@ // 1.95 | sglancy |12-MAY-15| Added DDR4 WR VREF set // 1.94 | jdsloat |27-JAN-14| Addressed FW concerns from gerrit. // 1.93 | jdsloat |22-JAN-14| Moved the initialization of rank_invalid within BYTE DISABLE WORKAROUND -// 1.92 | jdsloat |20-JAN-14| Added new workaround for BYTE DISABLE and for WR LVL DISABLE. This affects RAS/BBM work. -// 1.91 | jdsloat |24-SEP-14| Disabling spare CKE bit modify for SW275629. This bit will be modified via initfile. +// 1.92 | jdsloat |20-JAN-14| Added new workaround for BYTE DISABLE and for WR LVL DISABLE. This affects RAS/BBM work. +// 1.91 | jdsloat |24-SEP-14| Disabling spare CKE bit modify for SW275629. This bit will be modified via initfile. // 1.90 | jdsloat |29-JUL-14| disable for delay reset call moved to system level -// 1.89 | jdsloat |29-JUL-14| Added a disable for delay reset call -// 1.88 | jdsloat |14-JUL-14| Fixed delay reset call +// 1.89 | jdsloat |29-JUL-14| Added a disable for delay reset call +// 1.88 | jdsloat |14-JUL-14| Fixed delay reset call // 1.87 | jdsloat |09-JUN-14| Fixed log numbering... Added additonal error logs for more debug ability in a training error situation. // 1.85 | jdsloat |23-APL-14| Fixed attribute variable l_disable1_rdclk_fixed unitialized error in SW25701/v1.83 // 1.84 | jdsloat |23-APL-14| Fixed FAPI_ERR message within v1.83, mss_set_bbm_regs @@ -85,9 +87,9 @@ // 1.57 | jdsloat |27-FEB-13| Added second workaround adjustment to waterfall problem in order to use 2 rank pairs. // 1.56 | jdsloat |27-FEB-13| Fixed rtt_nom and rtt_wr swap bug during condition of rtt_nom = diabled and rtt_wr = non-disabled // | | | Added workaround on a per quad resolution -// | | | Added workaround as a seperate sub -// | | | Added framework of binning workaround based on timing reference -// | | | Added putscom to enable spare cke mirroring +// | | | Added workaround as a seperate sub +// | | | Added framework of binning workaround based on timing reference +// | | | Added putscom to enable spare cke mirroring // 1.55 | jdsloat |25-FEB-13| Added MBA/Port info to debug messages. // 1.54 | jdsloat |22-FEB-13| Edited WRITE_READ workaround to also edit DQSCLK PHASE // 1.53 | jdsloat |14-FEB-13| Fixed WRITE_READ workaround so it will execute in a partial substep case @@ -154,7 +156,7 @@ // 1.11 | jdsloat |21-Nov-11| Got rid of GOTO argument in CCS cmds. // 1.10 | divyakum |18-Nov-11| Fixed function calls to match procedure name. // 1.9 | divyakum |11-Oct-11| Fix to include mss_funcs instead of cen_funcs. -// | | | Changed usage of array attributes. +// | | | Changed usage of array attributes. // | | | NOTE: Needs to be compiled with mss_funcs v1.3. // 1.8 | divyakum |03-Oct-11| Removed primary_ranks_arrayvariable. Fixed rank loop for Socket1 // 1.7 | divyakum |30-Sep-11| First drop for Centaur. This code compiles @@ -173,6 +175,7 @@ //---------------------------------------------------------------------- #include <fapi.H> +#include <fapiUtil.H> //---------------------------------------------------------------------- // Centaur function Includes @@ -268,7 +271,7 @@ using namespace fapi; ReturnCode mss_draminit_training(Target& i_target); ReturnCode mss_draminit_training_cloned(Target& i_target); ReturnCode mss_check_cal_status(Target& i_target, uint8_t i_mbaPosition, uint8_t i_port, uint8_t i_group, mss_draminit_training_result& io_status); -ReturnCode mss_check_error_status(Target& i_target, uint8_t i_mbaPosition, uint8_t i_port, uint8_t i_group, uint8_t cur_cal_step, mss_draminit_training_result& io_status); +ReturnCode mss_check_error_status(Target& i_target, uint8_t i_mbaPosition, uint8_t i_port, uint8_t i_group, uint8_t cur_cal_step, mss_draminit_training_result& io_status, uint8_t i_max_cal_retry); ReturnCode mss_rtt_nom_rtt_wr_swap( Target& i_target, uint8_t i_mbaPosition, uint32_t i_port_number, uint8_t i_rank, uint32_t i_rank_pair_group, uint32_t& io_ccs_inst_cnt, uint8_t& io_dram_rtt_nom_original); ReturnCode mss_read_center_workaround(Target& i_target, uint8_t i_mbaPosition, uint32_t i_port, uint32_t i_rank_group); ReturnCode mss_read_center_second_workaround(Target& i_target); @@ -296,31 +299,31 @@ ReturnCode mss_draminit_training(Target& i_target) if (reset_disable != ENUM_ATTR_MSS_DRAMINIT_RESET_DISABLE_DISABLE) { - l_rc = mss_reset_delay_values(i_target); - if (l_rc) - { - return l_rc; - } + l_rc = mss_reset_delay_values(i_target); + if (l_rc) + { + return l_rc; + } } l_rc = mss_draminit_training_cloned(i_target); if (l_rc) { - return l_rc; + return l_rc; } - // If mss_unmask_draminit_training_errors gets it's own bad rc, - // it will commit the passed in rc (if non-zero), and return it's own bad rc. - // Else if mss_unmask_draminit_training_errors runs clean, - // it will just return the passed in rc. - l_rc = mss_unmask_draminit_training_errors(i_target, l_rc); + // If mss_unmask_draminit_training_errors gets it's own bad rc, + // it will commit the passed in rc (if non-zero), and return it's own bad rc. + // Else if mss_unmask_draminit_training_errors runs clean, + // it will just return the passed in rc. + l_rc = mss_unmask_draminit_training_errors(i_target, l_rc); if (l_rc) { - return l_rc; + return l_rc; } - return l_rc; + return l_rc; } @@ -336,7 +339,11 @@ ReturnCode mss_draminit_training_cloned(Target& i_target) MAX_NUM_DIMM = 2, MAX_NUM_GROUP = 4, MAX_CAL_STEPS = 7, //read course and write course will occur at the sametime - INVALID = 255 + MAX_DQS_RETRY = 10, //Used for the DQS Alignment workaround. Determines the number of DQS alignment retries. + INVALID = 255, + DELAY_0P5S = 500000000, + DELAY_LOOP = 6, + DELAY_SIM500 = 500 }; const uint32_t NUM_POLL = 10000; @@ -399,12 +406,16 @@ ReturnCode mss_draminit_training_cloned(Target& i_target) uint8_t group = 0; uint8_t primary_ranks_array[4][2]; //primary_ranks_array[group][port] uint8_t cal_steps = 0; + uint8_t delay_loop_cnt =0; + uint8_t dqs_try = 0; //part of DQS alignment workaround + uint8_t dqs_retry_num = 0; //part of DQS alignment workaround + uint8_t max_cal_retry = 0; //part of DQS alignment workaround added this to be a more generic var to pass into a proc. May be used if we need to add a retry to another cal step uint8_t cur_cal_step = 0; ecmdDataBufferBase cal_steps_8(8); uint8_t l_nwell_misplacement = 0; uint8_t dram_rtt_nom_original = 0; - uint8_t training_success = 0; + uint8_t training_success = 0; fapi::Target l_target_centaur; rc = fapiGetParentChip(i_target, l_target_centaur); @@ -459,7 +470,7 @@ ReturnCode mss_draminit_training_cloned(Target& i_target) rc_num = rc_num | cal_steps_8.insert(cal_steps, 0, 8, 0); /* - Disabling spare CKE bit modify for SW275629. This bit will be modified via initfile. + Disabling spare CKE bit modify for SW275629. This bit will be modified via initfile. //Setup SPARE CKE enable bit @@ -492,30 +503,30 @@ ReturnCode mss_draminit_training_cloned(Target& i_target) rc = mss_set_bbm_regs (i_target); if(rc) { - FAPI_ERR( "Error Moving bad bit information to the Phy regs. Exiting."); - return rc; + FAPI_ERR( "Error Moving bad bit information to the Phy regs. Exiting."); + return rc; } if ( ( cal_steps_8.isBitSet(0) ) || - ( (cal_steps_8.isBitClear(0)) && (cal_steps_8.isBitClear(1)) && - (cal_steps_8.isBitClear(2)) && (cal_steps_8.isBitClear(3)) && - (cal_steps_8.isBitClear(4)) && (cal_steps_8.isBitClear(5)) && - (cal_steps_8.isBitClear(6)) && (cal_steps_8.isBitClear(7)) )) + ( (cal_steps_8.isBitClear(0)) && (cal_steps_8.isBitClear(1)) && + (cal_steps_8.isBitClear(2)) && (cal_steps_8.isBitClear(3)) && + (cal_steps_8.isBitClear(4)) && (cal_steps_8.isBitClear(5)) && + (cal_steps_8.isBitClear(6)) && (cal_steps_8.isBitClear(7)) )) { - FAPI_INF( "Performing External ZQ Calibration on %s.", i_target.toEcmdString()); + FAPI_INF( "Performing External ZQ Calibration on %s.", i_target.toEcmdString()); //Execute ZQ_CAL - for(port = 0; port < MAX_NUM_PORT; port++) - { - rc = mss_execute_zq_cal(i_target, port); - if(rc) return rc; + for(port = 0; port < MAX_NUM_PORT; port++) + { + rc = mss_execute_zq_cal(i_target, port); + if(rc) return rc; - } + } - if ( (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3) && - (dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) ) + if ( (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3) && + (dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) ) { FAPI_INF("Performing LRDIMM MB-DRAM training"); @@ -523,273 +534,283 @@ ReturnCode mss_draminit_training_cloned(Target& i_target) rc = mss_execute_lrdimm_mb_dram_training(i_target); if (rc) return rc; } - //executes the following to ensure that DRAMS have a good intial WR VREF DQ - //1) enter training mode w/ old value (nominal VREF DQ) - //2) set value in training mode (nominal VREF DQ) - //3) exit training mode (nominal VREF DQ) - else if(dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) { - FAPI_INF("For DDR4, setting VREFDQ to have an initial value!!!!"); - uint8_t train_enable[2][2][4]; - uint8_t train_enable_override_on[2][2][4] ={{{ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE},{ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE}},{{ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE},{ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE}}}; - - rc = FAPI_ATTR_GET( ATTR_VREF_DQ_TRAIN_ENABLE, &i_target, train_enable); + //executes the following to ensure that DRAMS have a good intial WR VREF DQ + //1) enter training mode w/ old value (nominal VREF DQ) + //2) set value in training mode (nominal VREF DQ) + //3) exit training mode (nominal VREF DQ) + else if(dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) { + FAPI_INF("For DDR4, setting VREFDQ to have an initial value!!!!"); + uint8_t train_enable[2][2][4]; + uint8_t train_enable_override_on[2][2][4] ={{{ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE},{ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE}},{{ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE},{ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE}}}; + + rc = FAPI_ATTR_GET( ATTR_VREF_DQ_TRAIN_ENABLE, &i_target, train_enable); if(rc) return rc; - - rc = FAPI_ATTR_SET(ATTR_VREF_DQ_TRAIN_ENABLE, &i_target, train_enable_override_on); - if(rc) return rc; - - //runs new values w/ train enable forces on - FAPI_INF("RUN MRS6 1ST"); - rc = mss_mrs6_DDR4( i_target); - if(rc) return rc; - FAPI_INF("RUN MRS6 2ND"); - rc = mss_mrs6_DDR4( i_target); - if(rc) return rc; - - //set old train enable value - rc = FAPI_ATTR_SET(ATTR_VREF_DQ_TRAIN_ENABLE, &i_target, train_enable); - if(rc) return rc; - - FAPI_INF("RUN MRS6 3RD"); - rc = mss_mrs6_DDR4( i_target); - if(rc) return rc; - - //sets up the DQS offset to be 16 instead of 8 - rc = mss_setup_dqs_offset(i_target); - if(rc) return rc; - } - //have to do ZQ cal, then DDR4 training mode for initial VREF setup, then do LR training - for(port = 0; port < MAX_NUM_PORT; port++) - { + + rc = FAPI_ATTR_SET(ATTR_VREF_DQ_TRAIN_ENABLE, &i_target, train_enable_override_on); + if(rc) return rc; + + //runs new values w/ train enable forces on + FAPI_INF("RUN MRS6 1ST"); + rc = mss_mrs6_DDR4( i_target); + if(rc) return rc; + FAPI_INF("RUN MRS6 2ND"); + rc = mss_mrs6_DDR4( i_target); + if(rc) return rc; + + //set old train enable value + rc = FAPI_ATTR_SET(ATTR_VREF_DQ_TRAIN_ENABLE, &i_target, train_enable); + if(rc) return rc; + + FAPI_INF("RUN MRS6 3RD"); + rc = mss_mrs6_DDR4( i_target); + if(rc) return rc; + + //sets up the DQS offset to be 16 instead of 8 + rc = mss_setup_dqs_offset(i_target); + if(rc) return rc; + } + //have to do ZQ cal, then DDR4 training mode for initial VREF setup, then do LR training + for(port = 0; port < MAX_NUM_PORT; port++) + { // Should only be called for DDR4 LRDIMMs, training code is in development. Does not effect any other configs - if ( (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) && + if ( (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) && (dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) ) { rc = mss_mrep_training(i_target, port); - if(rc) return rc; - rc = mss_mxd_training(i_target,port,0); - if(rc) return rc; + if(rc) return rc; + rc = mss_mxd_training(i_target,port,0); + if(rc) return rc; } - } + } } for(port = 0; port < MAX_NUM_PORT; port++) { - for(group = 0; group < MAX_NUM_GROUP; group++) - { - - //Check if rank group exists - if(primary_ranks_array[group][port] != INVALID) - { - - //Set up for Init Cal - Done per port pair - rc_num = rc_num | test_buffer_4.setBit(0, 2); //Init Cal test = 11XX - rc_num = rc_num | wen_buffer_1.flushTo1(); //Init Cal ras/cas/we = 1/1/1 - rc_num = rc_num | casn_buffer_1.flushTo1(); - rc_num = rc_num | rasn_buffer_1.flushTo1(); - rc_num = rc_num | ddr_cal_enable_buffer_1.flushTo1(); //Init cal - - FAPI_INF( "+++ Setting up Init Cal on %s Port: %d rank group: %d cal_steps: 0x%02X +++", i_target.toEcmdString(), port, group, cal_steps); - - for(cur_cal_step = 1; cur_cal_step < MAX_CAL_STEPS; cur_cal_step++) //Cycle through all possible cal steps - { + for(group = 0; group < MAX_NUM_GROUP; group++) + { - //Clearing any status or errors bits that may have occured in previous training subtest. - if(port == 0) - { - //clear status reg - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P0_0x8000C0190301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.clearBit(48, 4); - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P0_0x8000C0190301143F, data_buffer_64); - if(rc) return rc; + //Check if rank group exists + if(primary_ranks_array[group][port] != INVALID) + { - //clear error reg - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P0_0x8000C0180301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.clearBit(48, 11); - rc_num = rc_num | data_buffer_64.clearBit(60, 4); - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P0_0x8000C0180301143F, data_buffer_64); - if(rc) return rc; + //Set up for Init Cal - Done per port pair + rc_num = rc_num | test_buffer_4.setBit(0, 2); //Init Cal test = 11XX + rc_num = rc_num | wen_buffer_1.flushTo1(); //Init Cal ras/cas/we = 1/1/1 + rc_num = rc_num | casn_buffer_1.flushTo1(); + rc_num = rc_num | rasn_buffer_1.flushTo1(); + rc_num = rc_num | ddr_cal_enable_buffer_1.flushTo1(); //Init cal + + FAPI_INF( "+++ Setting up Init Cal on %s Port: %d rank group: %d cal_steps: 0x%02X +++", i_target.toEcmdString(), port, group, cal_steps); + + for(cur_cal_step = 1; cur_cal_step < MAX_CAL_STEPS; cur_cal_step++) //Cycle through all possible cal steps + { + //DQS alignment workaround + max_cal_retry = 0; + + //Clearing any status or errors bits that may have occured in previous training subtest. + if(port == 0) + { + //clear status reg + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P0_0x8000C0190301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.clearBit(48, 4); + rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P0_0x8000C0190301143F, data_buffer_64); + if(rc) return rc; + + //clear error reg + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P0_0x8000C0180301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.clearBit(48, 11); + rc_num = rc_num | data_buffer_64.clearBit(60, 4); + rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P0_0x8000C0180301143F, data_buffer_64); + if(rc) return rc; //clear other port - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P1_0x8001C0160301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.clearBit(48); - rc_num = rc_num | data_buffer_64.clearBit(50); - rc_num = rc_num | data_buffer_64.clearBit(51); - rc_num = rc_num | data_buffer_64.clearBit(52); - rc_num = rc_num | data_buffer_64.clearBit(53); - rc_num = rc_num | data_buffer_64.clearBit(54); - rc_num = rc_num | data_buffer_64.clearBit(55); - rc_num = rc_num | data_buffer_64.clearBit(58); - rc_num = rc_num | data_buffer_64.clearBit(60); - rc_num = rc_num | data_buffer_64.clearBit(61); - rc_num = rc_num | data_buffer_64.clearBit(62); - rc_num = rc_num | data_buffer_64.clearBit(63); - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P1_0x8001C0160301143F, data_buffer_64); - if(rc) return rc; - - //Setup the Config Reg bit for the only cal step we want - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P0_0x8000C0160301143F, data_buffer_64); - if(rc) return rc; - - } - else - { - //clear status reg - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P1_0x8001C0190301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.clearBit(48, 4); - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P1_0x8001C0190301143F, data_buffer_64); - if(rc) return rc; - - //clear error reg - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P1_0x8001C0180301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.clearBit(48, 11); - rc_num = rc_num | data_buffer_64.clearBit(60, 4); - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P1_0x8001C0180301143F, data_buffer_64); - if(rc) return rc; + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P1_0x8001C0160301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.clearBit(48); + rc_num = rc_num | data_buffer_64.clearBit(50); + rc_num = rc_num | data_buffer_64.clearBit(51); + rc_num = rc_num | data_buffer_64.clearBit(52); + rc_num = rc_num | data_buffer_64.clearBit(53); + rc_num = rc_num | data_buffer_64.clearBit(54); + rc_num = rc_num | data_buffer_64.clearBit(55); + rc_num = rc_num | data_buffer_64.clearBit(58); + rc_num = rc_num | data_buffer_64.clearBit(60); + rc_num = rc_num | data_buffer_64.clearBit(61); + rc_num = rc_num | data_buffer_64.clearBit(62); + rc_num = rc_num | data_buffer_64.clearBit(63); + rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P1_0x8001C0160301143F, data_buffer_64); + if(rc) return rc; + + //Setup the Config Reg bit for the only cal step we want + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P0_0x8000C0160301143F, data_buffer_64); + if(rc) return rc; + + } + else + { + //clear status reg + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P1_0x8001C0190301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.clearBit(48, 4); + rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P1_0x8001C0190301143F, data_buffer_64); + if(rc) return rc; + + //clear error reg + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P1_0x8001C0180301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.clearBit(48, 11); + rc_num = rc_num | data_buffer_64.clearBit(60, 4); + rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P1_0x8001C0180301143F, data_buffer_64); + if(rc) return rc; //clear other port - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P0_0x8000C0160301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.clearBit(48); - rc_num = rc_num | data_buffer_64.clearBit(50); - rc_num = rc_num | data_buffer_64.clearBit(51); - rc_num = rc_num | data_buffer_64.clearBit(52); - rc_num = rc_num | data_buffer_64.clearBit(53); - rc_num = rc_num | data_buffer_64.clearBit(54); - rc_num = rc_num | data_buffer_64.clearBit(55); - rc_num = rc_num | data_buffer_64.clearBit(58); - rc_num = rc_num | data_buffer_64.clearBit(60); - rc_num = rc_num | data_buffer_64.clearBit(61); - rc_num = rc_num | data_buffer_64.clearBit(62); - rc_num = rc_num | data_buffer_64.clearBit(63); - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P0_0x8000C0160301143F, data_buffer_64); - if(rc) return rc; - - //Setup the Config Reg bit for the only cal step we want - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P1_0x8001C0160301143F, data_buffer_64); - if(rc) return rc; - - } - - //Clear training cnfg - rc_num = rc_num | data_buffer_64.clearBit(48); - rc_num = rc_num | data_buffer_64.clearBit(50); - rc_num = rc_num | data_buffer_64.clearBit(51); - rc_num = rc_num | data_buffer_64.clearBit(52); - rc_num = rc_num | data_buffer_64.clearBit(53); - rc_num = rc_num | data_buffer_64.clearBit(54); - rc_num = rc_num | data_buffer_64.clearBit(55); - rc_num = rc_num | data_buffer_64.clearBit(60); - rc_num = rc_num | data_buffer_64.clearBit(61); - rc_num = rc_num | data_buffer_64.clearBit(62); - rc_num = rc_num | data_buffer_64.clearBit(63); - - //Set stop on error - rc_num = rc_num | data_buffer_64.setBit(58); - - //cnfg rank groups - if(group == 0){ - rc_num = rc_num | data_buffer_64.setBit(60); - } - else if(group == 1){ - rc_num = rc_num | data_buffer_64.setBit(61); - } - else if(group == 2){ - rc_num = rc_num | data_buffer_64.setBit(62); - } - else if(group == 3){ - rc_num = rc_num | data_buffer_64.setBit(63); - } - - if ( (cur_cal_step == 1) && (cal_steps_8.isBitClear(0)) && (cal_steps_8.isBitClear(1)) && - (cal_steps_8.isBitClear(2)) && (cal_steps_8.isBitClear(3)) && - (cal_steps_8.isBitClear(4)) && (cal_steps_8.isBitClear(5)) && - (cal_steps_8.isBitClear(6)) && (cal_steps_8.isBitClear(7)) ) - { - FAPI_INF( "+++ Executing ALL Cal Steps at the same time on %s Port: %d rank group: %d +++", i_target.toEcmdString(), port, group); - rc_num = rc_num | data_buffer_64.setBit(48); - rc_num = rc_num | data_buffer_64.setBit(50); - rc_num = rc_num | data_buffer_64.setBit(51); - rc_num = rc_num | data_buffer_64.setBit(52); - rc_num = rc_num | data_buffer_64.setBit(53); - rc_num = rc_num | data_buffer_64.setBit(54); - rc_num = rc_num | data_buffer_64.setBit(55); - } - else if ( (cur_cal_step == 1) && (cal_steps_8.isBitSet(1)) ) - { - FAPI_INF( "+++ Write Leveling (WR_LVL) on %s Port %d rank group: %d +++", i_target.toEcmdString(), port, group); - rc_num = rc_num | data_buffer_64.setBit(48); - } - else if ( (cur_cal_step == 2) && (cal_steps_8.isBitSet(2)) ) - { - FAPI_INF( "+++ DQS Align (DQS_ALIGN) on %s Port: %d rank group: %d +++", i_target.toEcmdString(), port, group); - rc_num = rc_num | data_buffer_64.setBit(50); - } - else if ( (cur_cal_step == 3) && (cal_steps_8.isBitSet(3)) ) - { - FAPI_INF( "+++ RD CLK Align (RDCLK_ALIGN) on %s Port: %d rank group: %d +++", i_target.toEcmdString(), port, group); - rc_num = rc_num | data_buffer_64.setBit(51); - } - else if ( (cur_cal_step == 4) && (cal_steps_8.isBitSet(4)) ) - { - FAPI_INF( "+++ Read Centering (READ_CTR) on %s Port: %d rank group: %d +++", i_target.toEcmdString(), port, group); - rc_num = rc_num | data_buffer_64.setBit(52); - } - else if ( (cur_cal_step == 5) && (cal_steps_8.isBitSet(5)) ) - { - FAPI_INF( "+++ Write Centering (WRITE_CTR) on %s Port: %d rank group: %d +++", i_target.toEcmdString(), port, group); - rc_num = rc_num | data_buffer_64.setBit(53); - } - else if ( (cur_cal_step == 6) && (cal_steps_8.isBitSet(6)) && (cal_steps_8.isBitClear(7)) ) - { - FAPI_INF( "+++ Initial Course Write (COURSE_WR) on %s Port: %d rank group: %d +++", i_target.toEcmdString(), port, group); - rc_num = rc_num | data_buffer_64.setBit(54); - } - else if ( (cur_cal_step == 6) && (cal_steps_8.isBitClear(6)) && (cal_steps_8.isBitSet(7)) ) - { - FAPI_INF( "+++ Course Read (COURSE_RD) on %s Port: %d rank group: %d +++", i_target.toEcmdString(), port, group); - rc_num = rc_num | data_buffer_64.setBit(55); - } - else if ( (cur_cal_step == 6) && (cal_steps_8.isBitSet(6)) && (cal_steps_8.isBitSet(7)) ) - { - FAPI_INF( "+++ Initial Course Write (COURSE_WR) and Course Read (COURSE_RD) simultaneously on %s Port: %d rank group: %d +++", i_target.toEcmdString(), port, group); - rc_num = rc_num | data_buffer_64.setBit(54); - rc_num = rc_num | data_buffer_64.setBit(55); - } - - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - - if ( !( data_buffer_64.isBitClear(48, 8) ) ) // Only execute if we are doing a Cal Step - { - - // Before WR_LVL --- Change the RTT_NOM to RTT_WR pre-WR_LVL - if ( (cur_cal_step == 1) && (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3)) - { + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P0_0x8000C0160301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.clearBit(48); + rc_num = rc_num | data_buffer_64.clearBit(50); + rc_num = rc_num | data_buffer_64.clearBit(51); + rc_num = rc_num | data_buffer_64.clearBit(52); + rc_num = rc_num | data_buffer_64.clearBit(53); + rc_num = rc_num | data_buffer_64.clearBit(54); + rc_num = rc_num | data_buffer_64.clearBit(55); + rc_num = rc_num | data_buffer_64.clearBit(58); + rc_num = rc_num | data_buffer_64.clearBit(60); + rc_num = rc_num | data_buffer_64.clearBit(61); + rc_num = rc_num | data_buffer_64.clearBit(62); + rc_num = rc_num | data_buffer_64.clearBit(63); + rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P0_0x8000C0160301143F, data_buffer_64); + if(rc) return rc; + + //Setup the Config Reg bit for the only cal step we want + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P1_0x8001C0160301143F, data_buffer_64); + if(rc) return rc; + + } + + //Clear training cnfg + rc_num = rc_num | data_buffer_64.clearBit(48); + rc_num = rc_num | data_buffer_64.clearBit(50); + rc_num = rc_num | data_buffer_64.clearBit(51); + rc_num = rc_num | data_buffer_64.clearBit(52); + rc_num = rc_num | data_buffer_64.clearBit(53); + rc_num = rc_num | data_buffer_64.clearBit(54); + rc_num = rc_num | data_buffer_64.clearBit(55); + rc_num = rc_num | data_buffer_64.clearBit(60); + rc_num = rc_num | data_buffer_64.clearBit(61); + rc_num = rc_num | data_buffer_64.clearBit(62); + rc_num = rc_num | data_buffer_64.clearBit(63); + + //Set stop on error + rc_num = rc_num | data_buffer_64.setBit(58); + + //cnfg rank groups + if(group == 0){ + rc_num = rc_num | data_buffer_64.setBit(60); + } + else if(group == 1){ + rc_num = rc_num | data_buffer_64.setBit(61); + } + else if(group == 2){ + rc_num = rc_num | data_buffer_64.setBit(62); + } + else if(group == 3){ + rc_num = rc_num | data_buffer_64.setBit(63); + } + + if ( (cur_cal_step == 1) && (cal_steps_8.isBitClear(0)) && (cal_steps_8.isBitClear(1)) && + (cal_steps_8.isBitClear(2)) && (cal_steps_8.isBitClear(3)) && + (cal_steps_8.isBitClear(4)) && (cal_steps_8.isBitClear(5)) && + (cal_steps_8.isBitClear(6)) && (cal_steps_8.isBitClear(7)) ) + { + FAPI_INF( "+++ Executing ALL Cal Steps at the same time on %s Port: %d rank group: %d +++", i_target.toEcmdString(), port, group); + rc_num = rc_num | data_buffer_64.setBit(48); + rc_num = rc_num | data_buffer_64.setBit(50); + rc_num = rc_num | data_buffer_64.setBit(51); + rc_num = rc_num | data_buffer_64.setBit(52); + rc_num = rc_num | data_buffer_64.setBit(53); + rc_num = rc_num | data_buffer_64.setBit(54); + rc_num = rc_num | data_buffer_64.setBit(55); + } + else if ( (cur_cal_step == 1) && (cal_steps_8.isBitSet(1)) ) + { + FAPI_INF( "+++ Write Leveling (WR_LVL) on %s Port %d rank group: %d +++", i_target.toEcmdString(), port, group); + rc_num = rc_num | data_buffer_64.setBit(48); + } + else if ( (cur_cal_step == 2) && (cal_steps_8.isBitSet(2)) ) + { + max_cal_retry = 0; + dqs_try = dqs_retry_num + 1; + FAPI_INF( "+++ DQS Align (DQS_ALIGN) attempt %d on %s Port: %d rank group: %d +++", dqs_try,i_target.toEcmdString(), port, group); + if (dqs_try == MAX_DQS_RETRY) + { + max_cal_retry = 1; + FAPI_INF( "+++ DQS Align (DQS_ALIGN) final attempt!"); + + } + rc_num = rc_num | data_buffer_64.setBit(50); + } + else if ( (cur_cal_step == 3) && (cal_steps_8.isBitSet(3)) ) + { + FAPI_INF( "+++ RD CLK Align (RDCLK_ALIGN) on %s Port: %d rank group: %d +++", i_target.toEcmdString(), port, group); + rc_num = rc_num | data_buffer_64.setBit(51); + } + else if ( (cur_cal_step == 4) && (cal_steps_8.isBitSet(4)) ) + { + FAPI_INF( "+++ Read Centering (READ_CTR) on %s Port: %d rank group: %d +++", i_target.toEcmdString(), port, group); + rc_num = rc_num | data_buffer_64.setBit(52); + } + else if ( (cur_cal_step == 5) && (cal_steps_8.isBitSet(5)) ) + { + FAPI_INF( "+++ Write Centering (WRITE_CTR) on %s Port: %d rank group: %d +++", i_target.toEcmdString(), port, group); + rc_num = rc_num | data_buffer_64.setBit(53); + } + else if ( (cur_cal_step == 6) && (cal_steps_8.isBitSet(6)) && (cal_steps_8.isBitClear(7)) ) + { + FAPI_INF( "+++ Initial Course Write (COURSE_WR) on %s Port: %d rank group: %d +++", i_target.toEcmdString(), port, group); + rc_num = rc_num | data_buffer_64.setBit(54); + } + else if ( (cur_cal_step == 6) && (cal_steps_8.isBitClear(6)) && (cal_steps_8.isBitSet(7)) ) + { + FAPI_INF( "+++ Course Read (COURSE_RD) on %s Port: %d rank group: %d +++", i_target.toEcmdString(), port, group); + rc_num = rc_num | data_buffer_64.setBit(55); + } + else if ( (cur_cal_step == 6) && (cal_steps_8.isBitSet(6)) && (cal_steps_8.isBitSet(7)) ) + { + FAPI_INF( "+++ Initial Course Write (COURSE_WR) and Course Read (COURSE_RD) simultaneously on %s Port: %d rank group: %d +++", i_target.toEcmdString(), port, group); + rc_num = rc_num | data_buffer_64.setBit(54); + rc_num = rc_num | data_buffer_64.setBit(55); + } + + if(rc_num) + { + rc.setEcmdError(rc_num); + return rc; + } + + if ( !( data_buffer_64.isBitClear(48, 8) ) ) // Only execute if we are doing a Cal Step + { + + // Before WR_LVL --- Change the RTT_NOM to RTT_WR pre-WR_LVL + if ( (cur_cal_step == 1) && (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3)) + { if ( dimm_type != fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ) { - dram_rtt_nom_original = 0xFF; - rc = mss_rtt_nom_rtt_wr_swap(i_target, - mbaPosition, - port, - primary_ranks_array[group][port], - group, - instruction_number, - dram_rtt_nom_original); - if(rc) return rc; + dram_rtt_nom_original = 0xFF; + rc = mss_rtt_nom_rtt_wr_swap(i_target, + mbaPosition, + port, + primary_ranks_array[group][port], + group, + instruction_number, + dram_rtt_nom_original); + if(rc) return rc; } - } + } // Should only be called for DDR4 LRDIMMs, training code is in development. Does not effect any other configs else if ( (group == 0) && (cur_cal_step == 1) && (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) @@ -799,166 +820,206 @@ ReturnCode mss_draminit_training_cloned(Target& i_target) if(rc) return rc; } - //Set the config register - if(port == 0) - { - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P0_0x8000C0160301143F, data_buffer_64); - if(rc) return rc; - } - else - { - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P1_0x8001C0160301143F, data_buffer_64); - if(rc) return rc; - } - - rc = mss_ccs_inst_arry_0(i_target, - instruction_number, - address_buffer_16, - bank_buffer_8, - activate_buffer_1, - rasn_buffer_1, - casn_buffer_1, - wen_buffer_1, - cke_buffer_8, - csn_buffer_8, - odt_buffer_8, - test_buffer_4, - port); - - if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs - - FAPI_INF( "primary_ranks_array[%d][0]: %d [%d][1]: %d", group, primary_ranks_array[group][0], group, primary_ranks_array[group][1]); - - - rc_num = rc_num | rank_cal_buffer_4.insert(primary_ranks_array[group][port], 0, 4, 4); // 8 bit storage, need last 4 bits - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - - rc = mss_ccs_inst_arry_1(i_target, - instruction_number, - num_idles_buffer_16, - num_repeat_buffer_16, - data_buffer_20, - read_compare_buffer_1, - rank_cal_buffer_4, - ddr_cal_enable_buffer_1, - ccs_end_buffer_1); - - if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs - - - rc = mss_execute_ccs_inst_array( i_target, NUM_POLL, 60); - if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs - - //Check to see if the training completes - rc = mss_check_cal_status(i_target, mbaPosition, port, group, cur_complete_status); - if(rc) return rc; - - if (cur_complete_status == MSS_INIT_CAL_STALL) - { - complete_status = cur_complete_status; - } - - //Check to see if the training errored out - rc = mss_check_error_status(i_target, mbaPosition, port, group, cur_cal_step, cur_error_status); - if(rc) return rc; - - if (cur_error_status == MSS_INIT_CAL_FAIL) - { - error_status = cur_error_status; - } - - // Following WR_LVL -- Restore RTT_NOM to orignal value post-wr_lvl - if ((cur_cal_step == 1) && (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3)) - { + //Set the config register + if(port == 0) + { + rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P0_0x8000C0160301143F, data_buffer_64); + if(rc) return rc; + } + else + { + rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P1_0x8001C0160301143F, data_buffer_64); + if(rc) return rc; + } + + rc = mss_ccs_inst_arry_0(i_target, + instruction_number, + address_buffer_16, + bank_buffer_8, + activate_buffer_1, + rasn_buffer_1, + casn_buffer_1, + wen_buffer_1, + cke_buffer_8, + csn_buffer_8, + odt_buffer_8, + test_buffer_4, + port); + + if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs + + FAPI_INF( "primary_ranks_array[%d][0]: %d [%d][1]: %d", group, primary_ranks_array[group][0], group, primary_ranks_array[group][1]); + + + rc_num = rc_num | rank_cal_buffer_4.insert(primary_ranks_array[group][port], 0, 4, 4); // 8 bit storage, need last 4 bits + if(rc_num) + { + rc.setEcmdError(rc_num); + return rc; + } + + rc = mss_ccs_inst_arry_1(i_target, + instruction_number, + num_idles_buffer_16, + num_repeat_buffer_16, + data_buffer_20, + read_compare_buffer_1, + rank_cal_buffer_4, + ddr_cal_enable_buffer_1, + ccs_end_buffer_1); + + if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs + + + rc = mss_execute_ccs_inst_array( i_target, NUM_POLL, 60); + if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs + + //Check to see if the training completes + rc = mss_check_cal_status(i_target, mbaPosition, port, group, cur_complete_status); + if(rc) return rc; + + if (cur_complete_status == MSS_INIT_CAL_STALL) + { + complete_status = cur_complete_status; + } + + //Check to see if the training errored out + rc = mss_check_error_status(i_target, mbaPosition, port, group, cur_cal_step, cur_error_status, max_cal_retry); + if(rc) return rc; + + if (cur_error_status == MSS_INIT_CAL_FAIL) + { + error_status = cur_error_status; + + } + + // Following WR_LVL -- Restore RTT_NOM to orignal value post-wr_lvl + if ((cur_cal_step == 1) && (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3)) + { if ( dimm_type != fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ) { - rc = mss_rtt_nom_rtt_wr_swap(i_target, - mbaPosition, - port, - primary_ranks_array[group][port], - group, - instruction_number, - dram_rtt_nom_original); - if(rc) return rc; + rc = mss_rtt_nom_rtt_wr_swap(i_target, + mbaPosition, + port, + primary_ranks_array[group][port], + group, + instruction_number, + dram_rtt_nom_original); + if(rc) return rc; } - } - - // Following Read Centering -- Enter into READ CENTERING WORKAROUND - if ( (cur_cal_step == 4) && - ( waterfall_broken == fapi::ENUM_ATTR_MSS_BLUEWATERFALL_BROKEN_TRUE ) ) - { - rc = mss_read_center_workaround(i_target, mbaPosition, port, group); - if(rc) return rc; - } - - } - }//end of step loop - } - }//end of group loop + } + + // Following Read Centering -- Enter into READ CENTERING WORKAROUND + if ( (cur_cal_step == 4) && + ( waterfall_broken == fapi::ENUM_ATTR_MSS_BLUEWATERFALL_BROKEN_TRUE ) ) + { + rc = mss_read_center_workaround(i_target, mbaPosition, port, group); + if(rc) return rc; + } + + // DQS Alignment workaround + if (cur_cal_step == 2) + { + // Because the DQS cal step failed we need to rerun the step and clear out any bad bits + if (cur_error_status == MSS_INIT_CAL_FAIL) + { + + if (dqs_try < MAX_DQS_RETRY) + { + dqs_retry_num++; + cur_cal_step-- ; + for(delay_loop_cnt = 1; delay_loop_cnt <= DELAY_LOOP; delay_loop_cnt++) + { + rc = fapiDelay(DELAY_0P5S, DELAY_SIM500); + if(rc) return rc; + } + delay_loop_cnt = 0; + } + else if (dqs_try == MAX_DQS_RETRY) + { + dqs_retry_num = 0; + } + } + //If the DQS cal step passes on a retry, we need to reset the error status to a pass. + else if (cur_error_status == MSS_INIT_CAL_PASS) + { + if (dqs_try > 1) + { + error_status = MSS_INIT_CAL_PASS; + dqs_retry_num = 0; + } + + dqs_retry_num = 0; + + } + + } + + + } + }//end of step loop + } + }//end of group loop }//end of port loop // Make sure the DQS_CLK values of each byte have matching nibble values, using the lowest if ( waterfall_broken == fapi::ENUM_ATTR_MSS_BLUEWATERFALL_BROKEN_TRUE ) { - rc = mss_read_center_second_workaround(i_target); - if(rc) return rc; + rc = mss_read_center_second_workaround(i_target); + if(rc) return rc; } if ((error_status != MSS_INIT_CAL_FAIL) && (error_status != MSS_INIT_CAL_STALL)) { - training_success = 0xFF; + training_success = 0xFF; } rc = mss_get_bbm_regs(i_target, training_success); if(rc) { - FAPI_ERR( "Error Moving bad bit information from the Phy regs. Exiting."); - return rc; + FAPI_ERR( "Error Moving bad bit information from the Phy regs. Exiting."); + return rc; } //Executes if we do "all at once" or on the last cal steps //Must be a successful run. - if (error_status == MSS_INIT_CAL_PASS && - ((cal_steps_8.isBitSet(6) && cal_steps_8.isBitSet(7)) || - (cal_steps_8.isBitClear(0) && cal_steps_8.isBitClear(1) && - cal_steps_8.isBitClear(2) && cal_steps_8.isBitClear(3) && - cal_steps_8.isBitClear(4) && cal_steps_8.isBitClear(5) && - cal_steps_8.isBitClear(6) && cal_steps_8.isBitClear(7) ) ) ) + if (error_status == MSS_INIT_CAL_PASS && + ((cal_steps_8.isBitSet(6) && cal_steps_8.isBitSet(7)) || + (cal_steps_8.isBitClear(0) && cal_steps_8.isBitClear(1) && + cal_steps_8.isBitClear(2) && cal_steps_8.isBitClear(3) && + cal_steps_8.isBitClear(4) && cal_steps_8.isBitClear(5) && + cal_steps_8.isBitClear(6) && cal_steps_8.isBitClear(7) ) ) ) { - FAPI_INF( "WR LVL DISABLE WORKAROUND: Running wr_lvl workaround on %s", i_target.toEcmdString()); - rc = mss_wr_lvl_disable_workaround(i_target); - if(rc) return rc; + FAPI_INF( "WR LVL DISABLE WORKAROUND: Running wr_lvl workaround on %s", i_target.toEcmdString()); + rc = mss_wr_lvl_disable_workaround(i_target); + if(rc) return rc; } - // If we hit either of these States, the error callout originates from Mike Jones Bad Bit code. + // If we hit either of these States, the error callout originates from Mike Jones Bad Bit code. if (complete_status == MSS_INIT_CAL_STALL) { - FAPI_ERR( "+++ Partial/Full calibration stall. Check Debug trace. +++"); + FAPI_ERR( "+++ Partial/Full calibration stall. Check Debug trace. +++"); } else if (error_status == MSS_INIT_CAL_FAIL) { - FAPI_ERR( "+++ Partial/Full calibration fail. Check Debug trace. +++"); + FAPI_ERR( "+++ Partial/Full calibration fail. Check Debug trace. +++"); } else { - FAPI_INF( "+++ Full calibration successful. +++"); + FAPI_INF( "+++ Full calibration successful. +++"); } return rc; } ReturnCode mss_check_cal_status( Target& i_target, - uint8_t i_mbaPosition, + uint8_t i_mbaPosition, uint8_t i_port, uint8_t i_group, - mss_draminit_training_result& io_status + mss_draminit_training_result& io_status ) { ecmdDataBufferBase cal_status_buffer_64(64); @@ -1002,24 +1063,27 @@ ReturnCode mss_check_cal_status( Target& i_target, if(cal_status_buffer_64.isBitSet(cal_status_reg_offset)) { - FAPI_INF( "+++ Calibration on %s port: %d rank group: %d finished. +++", i_target.toEcmdString(), i_port, i_group); - io_status = MSS_INIT_CAL_COMPLETE; + FAPI_INF( "+++ Calibration on %s port: %d rank group: %d finished. +++", i_target.toEcmdString(), i_port, i_group); + io_status = MSS_INIT_CAL_COMPLETE; } else { - FAPI_ERR( "+++ Calibration on %s port: %d rank group: %d has stalled! +++", i_target.toEcmdString(), i_port, i_group); - io_status = MSS_INIT_CAL_STALL; + FAPI_ERR( "+++ Calibration on %s port: %d rank group: %d has stalled! +++", i_target.toEcmdString(), i_port, i_group); + io_status = MSS_INIT_CAL_STALL; } return rc; } + + ReturnCode mss_check_error_status( Target& i_target, - uint8_t i_mbaPosition, + uint8_t i_mbaPosition, uint8_t i_port, uint8_t i_group, - uint8_t cur_cal_step, - mss_draminit_training_result& io_status + uint8_t cur_cal_step, + mss_draminit_training_result& io_status, + uint8_t i_max_cal_retry ) { @@ -1043,146 +1107,244 @@ ReturnCode mss_check_error_status( Target& i_target, if((cal_error_buffer_64.isBitSet(60)) || (cal_error_buffer_64.isBitSet(61)) || (cal_error_buffer_64.isBitSet(62)) || (cal_error_buffer_64.isBitSet(63))) { - io_status = MSS_INIT_CAL_FAIL; + io_status = MSS_INIT_CAL_FAIL; if(cal_error_buffer_64.isBitSet(48)) { FAPI_ERR( "+++ Write leveling error occured on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group); - const fapi::Target & TARGET_MBA_ERROR = i_target; - MBA_POSITION = i_mbaPosition; - PORT_POSITION = i_port; - RANKGROUP_POSITION = i_group; - FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_WR_LVL_ERROR); - fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED); - rc = FAPI_RC_SUCCESS; + const fapi::Target & TARGET_MBA_ERROR = i_target; + MBA_POSITION = i_mbaPosition; + PORT_POSITION = i_port; + RANKGROUP_POSITION = i_group; + FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_WR_LVL_ERROR); + fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED); + rc = FAPI_RC_SUCCESS; } if(cal_error_buffer_64.isBitSet(50)) { FAPI_ERR( "+++ DQS Alignment error occured on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group); - const fapi::Target & TARGET_MBA_ERROR = i_target; - MBA_POSITION = i_mbaPosition; - PORT_POSITION = i_port; - RANKGROUP_POSITION = i_group; - FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_DQS_ALIGNMENT_ERROR); - fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED); - rc = FAPI_RC_SUCCESS; + const fapi::Target & TARGET_MBA_ERROR = i_target; + MBA_POSITION = i_mbaPosition; + PORT_POSITION = i_port; + RANKGROUP_POSITION = i_group; + + // Error Callout ByPass for Work Around: + //FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_DQS_ALIGNMENT_ERROR); + //fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED); + //rc = FAPI_RC_SUCCESS; + + // DQS Alignment Work Around: + if (i_max_cal_retry == 0) + { + FAPI_INF( "+++ DQS Alignment recovery attempt on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group); + uint64_t disable_bit_addr_for_dp18_0 = 0; + uint64_t disable_bit_addr_for_dp18_1 = 0; + uint64_t disable_bit_addr_for_dp18_2 = 0; + uint64_t disable_bit_addr_for_dp18_3 = 0; + uint64_t disable_bit_addr_for_dp18_4 = 0; + if (i_port == 0) { + if (i_group == 0) { + disable_bit_addr_for_dp18_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_0_0x8000007c0301143F; + disable_bit_addr_for_dp18_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_1_0x8000047c0301143F; + disable_bit_addr_for_dp18_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_2_0x8000087c0301143F; + disable_bit_addr_for_dp18_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_3_0x80000c7c0301143F; + disable_bit_addr_for_dp18_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_4_0x8000107c0301143F; + } else if (i_group == 1) { + disable_bit_addr_for_dp18_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_0_0x8000017c0301143F; + disable_bit_addr_for_dp18_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_1_0x8000057c0301143F; + disable_bit_addr_for_dp18_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_2_0x8000097c0301143F; + disable_bit_addr_for_dp18_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_3_0x80000d7c0301143F; + disable_bit_addr_for_dp18_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_4_0x8000117c0301143F; + } else if (i_group == 2) { + disable_bit_addr_for_dp18_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_0_0x8000027c0301143F; + disable_bit_addr_for_dp18_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_1_0x8000067c0301143F; + disable_bit_addr_for_dp18_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_2_0x80000a7c0301143F; + disable_bit_addr_for_dp18_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_3_0x80000e7c0301143F; + disable_bit_addr_for_dp18_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_4_0x8000127c0301143F; + } else if (i_group == 3) { + disable_bit_addr_for_dp18_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_0_0x8000037c0301143F; + disable_bit_addr_for_dp18_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_1_0x8000077c0301143F; + disable_bit_addr_for_dp18_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_2_0x80000b7c0301143F; + disable_bit_addr_for_dp18_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_3_0x80000f7c0301143F; + disable_bit_addr_for_dp18_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_4_0x8000137c0301143F; + } else { + FAPI_ERR( "+++ DQS Alignment Recovery error occured on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group); + FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_DQS_ALIGNMENT_ERROR); + fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED); + rc = FAPI_RC_SUCCESS; + } + } else if (i_port == 1) { + if (i_group == 0) { + disable_bit_addr_for_dp18_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_0_0x8001007c0301143F; disable_bit_addr_for_dp18_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_1_0x8001047c0301143F; + disable_bit_addr_for_dp18_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_2_0x8001087c0301143F; + disable_bit_addr_for_dp18_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_3_0x80010c7c0301143F; + disable_bit_addr_for_dp18_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_4_0x8001107c0301143F; + } else if (i_group == 1) { + disable_bit_addr_for_dp18_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_0_0x8001017c0301143F; + disable_bit_addr_for_dp18_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_1_0x8001057c0301143F; disable_bit_addr_for_dp18_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_2_0x8001097c0301143F; + disable_bit_addr_for_dp18_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_3_0x80010d7c0301143F; + disable_bit_addr_for_dp18_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_4_0x8001117c0301143F; + } else if (i_group == 2) { + disable_bit_addr_for_dp18_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_0_0x8001027c0301143F; + disable_bit_addr_for_dp18_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_1_0x8001067c0301143F; + disable_bit_addr_for_dp18_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_2_0x80010a7c0301143F; + disable_bit_addr_for_dp18_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_3_0x80010e7c0301143F; + disable_bit_addr_for_dp18_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_4_0x8001127c0301143F; + } else if (i_group == 3) { + disable_bit_addr_for_dp18_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_0_0x8001037c0301143F; + disable_bit_addr_for_dp18_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_1_0x8001077c0301143F; + disable_bit_addr_for_dp18_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_2_0x80010b7c0301143F; + disable_bit_addr_for_dp18_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_3_0x80010f7c0301143F; + disable_bit_addr_for_dp18_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_4_0x8001137c0301143F; + } else { + FAPI_ERR( "+++ DQS Alignment Recovery error occured on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group); + FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_DQS_ALIGNMENT_ERROR); + fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED); + rc = FAPI_RC_SUCCESS; + } + } else { + FAPI_ERR( "+++ DQS Alignment Recovery error occured on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group); + FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_DQS_ALIGNMENT_ERROR); + fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED); + rc = FAPI_RC_SUCCESS; + } + ecmdDataBufferBase disable_bit_data_for_dp18_buffer_64(64); + disable_bit_data_for_dp18_buffer_64.flushTo0(); + rc = fapiPutScom(i_target, disable_bit_addr_for_dp18_0, disable_bit_data_for_dp18_buffer_64); if(rc) return rc; + rc = fapiPutScom(i_target, disable_bit_addr_for_dp18_1, disable_bit_data_for_dp18_buffer_64); if(rc) return rc; + rc = fapiPutScom(i_target, disable_bit_addr_for_dp18_2, disable_bit_data_for_dp18_buffer_64); if(rc) return rc; + rc = fapiPutScom(i_target, disable_bit_addr_for_dp18_3, disable_bit_data_for_dp18_buffer_64); if(rc) return rc; + rc = fapiPutScom(i_target, disable_bit_addr_for_dp18_4, disable_bit_data_for_dp18_buffer_64); if(rc) return rc; + } else { + FAPI_ERR( "+++ DQS Alignment Recovery error occured on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group); + FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_DQS_ALIGNMENT_ERROR); + fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED); + rc = FAPI_RC_SUCCESS; + } + } if(cal_error_buffer_64.isBitSet(51)) { FAPI_ERR( "+++ RDCLK to SysClk alignment error occured on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group); - const fapi::Target & TARGET_MBA_ERROR = i_target; - MBA_POSITION = i_mbaPosition; - PORT_POSITION = i_port; - RANKGROUP_POSITION = i_group; - FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_RD_CLK_SYS_CLK_ALIGNMENT_ERROR); - fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED); - rc = FAPI_RC_SUCCESS; + const fapi::Target & TARGET_MBA_ERROR = i_target; + MBA_POSITION = i_mbaPosition; + PORT_POSITION = i_port; + RANKGROUP_POSITION = i_group; + FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_RD_CLK_SYS_CLK_ALIGNMENT_ERROR); + fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED); + rc = FAPI_RC_SUCCESS; } if(cal_error_buffer_64.isBitSet(52)) { FAPI_ERR( "+++ Read centering error occured on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group); - const fapi::Target & TARGET_MBA_ERROR = i_target; - MBA_POSITION = i_mbaPosition; - PORT_POSITION = i_port; - RANKGROUP_POSITION = i_group; - FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_RD_CENTERING_ERROR); - fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED); - rc = FAPI_RC_SUCCESS; + const fapi::Target & TARGET_MBA_ERROR = i_target; + MBA_POSITION = i_mbaPosition; + PORT_POSITION = i_port; + RANKGROUP_POSITION = i_group; + FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_RD_CENTERING_ERROR); + fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED); + rc = FAPI_RC_SUCCESS; } if(cal_error_buffer_64.isBitSet(53)) { FAPI_ERR( "+++ Write centering error occured on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group); - const fapi::Target & TARGET_MBA_ERROR = i_target; - MBA_POSITION = i_mbaPosition; - PORT_POSITION = i_port; - RANKGROUP_POSITION = i_group; - FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_WR_CENTERING_ERROR); - fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED); - rc = FAPI_RC_SUCCESS; + const fapi::Target & TARGET_MBA_ERROR = i_target; + MBA_POSITION = i_mbaPosition; + PORT_POSITION = i_port; + RANKGROUP_POSITION = i_group; + FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_WR_CENTERING_ERROR); + fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED); + rc = FAPI_RC_SUCCESS; } if(cal_error_buffer_64.isBitSet(55)) { FAPI_ERR( "+++ Coarse read centering error occured on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group); - const fapi::Target & TARGET_MBA_ERROR = i_target; - MBA_POSITION = i_mbaPosition; - PORT_POSITION = i_port; - RANKGROUP_POSITION = i_group; - FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_COURSE_RD_CENTERING_ERROR); - fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED); - rc = FAPI_RC_SUCCESS; + const fapi::Target & TARGET_MBA_ERROR = i_target; + MBA_POSITION = i_mbaPosition; + PORT_POSITION = i_port; + RANKGROUP_POSITION = i_group; + FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_COURSE_RD_CENTERING_ERROR); + fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED); + rc = FAPI_RC_SUCCESS; } if(cal_error_buffer_64.isBitSet(56)) { FAPI_ERR( "+++ Custom pattern read centering error occured on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group); - const fapi::Target & TARGET_MBA_ERROR = i_target; - MBA_POSITION = i_mbaPosition; - PORT_POSITION = i_port; - RANKGROUP_POSITION = i_group; - FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_CUSTOM_PATTERN_RD_CENTERING_ERROR); - fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED); - rc = FAPI_RC_SUCCESS; + const fapi::Target & TARGET_MBA_ERROR = i_target; + MBA_POSITION = i_mbaPosition; + PORT_POSITION = i_port; + RANKGROUP_POSITION = i_group; + FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_CUSTOM_PATTERN_RD_CENTERING_ERROR); + fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED); + rc = FAPI_RC_SUCCESS; } if(cal_error_buffer_64.isBitSet(57)) { FAPI_ERR( "+++ Custom pattern write centering error occured on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group); - const fapi::Target & TARGET_MBA_ERROR = i_target; - MBA_POSITION = i_mbaPosition; - PORT_POSITION = i_port; - RANKGROUP_POSITION = i_group; - FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_CUSTOM_PATTERN_WR_CENTERING_ERROR); - fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED); - rc = FAPI_RC_SUCCESS; + const fapi::Target & TARGET_MBA_ERROR = i_target; + MBA_POSITION = i_mbaPosition; + PORT_POSITION = i_port; + RANKGROUP_POSITION = i_group; + FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_CUSTOM_PATTERN_WR_CENTERING_ERROR); + fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED); + rc = FAPI_RC_SUCCESS; } if(cal_error_buffer_64.isBitSet(58)) { FAPI_ERR( "+++ Digital eye error occured on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group); - const fapi::Target & TARGET_MBA_ERROR = i_target; - MBA_POSITION = i_mbaPosition; - PORT_POSITION = i_port; - RANKGROUP_POSITION = i_group; - FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_DIGITAL_EYE_ERROR); - fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED); - rc = FAPI_RC_SUCCESS; + const fapi::Target & TARGET_MBA_ERROR = i_target; + MBA_POSITION = i_mbaPosition; + PORT_POSITION = i_port; + RANKGROUP_POSITION = i_group; + FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_DIGITAL_EYE_ERROR); + fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED); + rc = FAPI_RC_SUCCESS; } } else { - if (cur_cal_step == 1) - { - FAPI_INF( "+++ Write_leveling on %s port: %d rank group: %d was successful. +++", i_target.toEcmdString(), i_port, i_group); - } - else if (cur_cal_step == 2) - { - FAPI_INF( "+++ DQS Alignment on %s port: %d rank group: %d was successful. +++", i_target.toEcmdString(), i_port, i_group); - } - else if (cur_cal_step == 3) - { - FAPI_INF( "+++ RDCLK to SysClk alignment on %s port: %d rank group: %d was successful. +++", i_target.toEcmdString(), i_port, i_group); - } - else if (cur_cal_step == 4) - { - FAPI_INF( "+++ Read Centering on %s port: %d rank group: %d was successful. +++", i_target.toEcmdString(), i_port, i_group); - } - else if (cur_cal_step == 5) - { - FAPI_INF( "+++ Write Centering on %s port: %d rank group: %d was successful. +++", i_target.toEcmdString(), i_port, i_group); - } - else if (cur_cal_step == 6) - { - FAPI_INF( "+++ Course Read and/or Course Write on %s port: %d rank group: %d was successful. +++", i_target.toEcmdString(), i_port, i_group); - } - - io_status = MSS_INIT_CAL_PASS; + if (cur_cal_step == 1) + { + FAPI_INF( "+++ Write_leveling on %s port: %d rank group: %d was successful. +++", i_target.toEcmdString(), i_port, i_group); + } + else if (cur_cal_step == 2) + { + FAPI_INF( "+++ DQS Alignment on %s port: %d rank group: %d was successful. +++", i_target.toEcmdString(), i_port, i_group); + } + else if (cur_cal_step == 3) + { + FAPI_INF( "+++ RDCLK to SysClk alignment on %s port: %d rank group: %d was successful. +++", i_target.toEcmdString(), i_port, i_group); + } + else if (cur_cal_step == 4) + { + FAPI_INF( "+++ Read Centering on %s port: %d rank group: %d was successful. +++", i_target.toEcmdString(), i_port, i_group); + } + else if (cur_cal_step == 5) + { + FAPI_INF( "+++ Write Centering on %s port: %d rank group: %d was successful. +++", i_target.toEcmdString(), i_port, i_group); + } + else if (cur_cal_step == 6) + { + FAPI_INF( "+++ Course Read and/or Course Write on %s port: %d rank group: %d was successful. +++", i_target.toEcmdString(), i_port, i_group); + } + + io_status = MSS_INIT_CAL_PASS; } return rc; } + + + + + + ReturnCode mss_read_center_workaround( Target& i_target, uint8_t i_mbaPosition, uint32_t i_port, - uint32_t i_rank_group + uint32_t i_rank_group ) { @@ -1238,105 +1400,105 @@ ReturnCode mss_read_center_workaround( if ( i_port == 0 ) { - RD_TIMING_REF0_ADDR_0 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_0_0x800000700301143F; - RD_TIMING_REF0_ADDR_1 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_1_0x800004700301143F; - RD_TIMING_REF0_ADDR_2 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_2_0x800008700301143F; - RD_TIMING_REF0_ADDR_3 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_3_0x80000C700301143F; - RD_TIMING_REF0_ADDR_4 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_4_0x800010700301143F; - RD_TIMING_REF1_ADDR_0 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_0_0x800000710301143F; - RD_TIMING_REF1_ADDR_1 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_1_0x800004710301143F; - RD_TIMING_REF1_ADDR_2 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_2_0x800008710301143F; - RD_TIMING_REF1_ADDR_3 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_3_0x80000C710301143F; - RD_TIMING_REF1_ADDR_4 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_4_0x800010710301143F; - - if ( i_rank_group == 0 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_0x800000090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_0x800004090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_0x800008090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_0x80000C090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_0x800010090301143F; - - } - else if ( i_rank_group == 1 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_0x800001090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_0x800005090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_0x800009090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_0x80000D090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_0x800011090301143F; - - } - else if ( i_rank_group == 2 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_0x800002090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_0x800006090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_0x80000A090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_0x80000E090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_0x800012090301143F; - - } - else if ( i_rank_group == 3 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_0x800003090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_0x800007090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_0x80000B090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_0x80000F090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_0x800013090301143F; - - } + RD_TIMING_REF0_ADDR_0 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_0_0x800000700301143F; + RD_TIMING_REF0_ADDR_1 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_1_0x800004700301143F; + RD_TIMING_REF0_ADDR_2 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_2_0x800008700301143F; + RD_TIMING_REF0_ADDR_3 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_3_0x80000C700301143F; + RD_TIMING_REF0_ADDR_4 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_4_0x800010700301143F; + RD_TIMING_REF1_ADDR_0 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_0_0x800000710301143F; + RD_TIMING_REF1_ADDR_1 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_1_0x800004710301143F; + RD_TIMING_REF1_ADDR_2 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_2_0x800008710301143F; + RD_TIMING_REF1_ADDR_3 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_3_0x80000C710301143F; + RD_TIMING_REF1_ADDR_4 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_4_0x800010710301143F; + + if ( i_rank_group == 0 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_0x800000090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_0x800004090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_0x800008090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_0x80000C090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_0x800010090301143F; + + } + else if ( i_rank_group == 1 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_0x800001090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_0x800005090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_0x800009090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_0x80000D090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_0x800011090301143F; + + } + else if ( i_rank_group == 2 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_0x800002090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_0x800006090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_0x80000A090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_0x80000E090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_0x800012090301143F; + + } + else if ( i_rank_group == 3 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_0x800003090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_0x800007090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_0x80000B090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_0x80000F090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_0x800013090301143F; + + } } else if (i_port == 1 ) { - RD_TIMING_REF0_ADDR_0 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_0_0x800100700301143F; - RD_TIMING_REF0_ADDR_1 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_1_0x800104700301143F; - RD_TIMING_REF0_ADDR_2 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_2_0x800108700301143F; - RD_TIMING_REF0_ADDR_3 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_3_0x80010C700301143F; - RD_TIMING_REF0_ADDR_4 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_4_0x800110700301143F; - RD_TIMING_REF1_ADDR_0 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_0_0x800100710301143F; - RD_TIMING_REF1_ADDR_1 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_1_0x800104710301143F; - RD_TIMING_REF1_ADDR_2 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_2_0x800108710301143F; - RD_TIMING_REF1_ADDR_3 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_3_0x80010C710301143F; - RD_TIMING_REF1_ADDR_4 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_4_0x800110710301143F; - - if ( i_rank_group == 0 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_0x800100090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_0x800104090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_0x800108090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_0x80010C090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_0x800110090301143F; - - } - else if ( i_rank_group == 1 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_0x800101090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_0x800105090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_0x800109090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_0x80010D090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_0x800111090301143F; - - - } - else if ( i_rank_group == 2 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_0x800102090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_0x800106090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_0x80010A090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_0x80010E090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_0x800112090301143F; - - } - else if ( i_rank_group == 3 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_0x800103090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_0x800107090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_0x80010B090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_0x80010F090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_0x800113090301143F; - - } + RD_TIMING_REF0_ADDR_0 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_0_0x800100700301143F; + RD_TIMING_REF0_ADDR_1 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_1_0x800104700301143F; + RD_TIMING_REF0_ADDR_2 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_2_0x800108700301143F; + RD_TIMING_REF0_ADDR_3 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_3_0x80010C700301143F; + RD_TIMING_REF0_ADDR_4 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_4_0x800110700301143F; + RD_TIMING_REF1_ADDR_0 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_0_0x800100710301143F; + RD_TIMING_REF1_ADDR_1 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_1_0x800104710301143F; + RD_TIMING_REF1_ADDR_2 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_2_0x800108710301143F; + RD_TIMING_REF1_ADDR_3 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_3_0x80010C710301143F; + RD_TIMING_REF1_ADDR_4 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_4_0x800110710301143F; + + if ( i_rank_group == 0 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_0x800100090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_0x800104090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_0x800108090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_0x80010C090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_0x800110090301143F; + + } + else if ( i_rank_group == 1 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_0x800101090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_0x800105090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_0x800109090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_0x80010D090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_0x800111090301143F; + + + } + else if ( i_rank_group == 2 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_0x800102090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_0x800106090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_0x80010A090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_0x80010E090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_0x800112090301143F; + + } + else if ( i_rank_group == 3 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_0x800103090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_0x800107090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_0x80010B090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_0x80010F090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_0x800113090301143F; + + } } //Block 0 @@ -1349,75 +1511,75 @@ ReturnCode mss_read_center_workaround( rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad2, 49, 7); rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad3, 57, 7); - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } + if(rc_num) + { + rc.setEcmdError(rc_num); + return rc; + } if ( quad0_workaround_type == 0 ) { - dqs_clk_increment_quad0 = dqs_clk_increment_wa0; - read_phase_value_quad0 = read_phase_value_wa0; + dqs_clk_increment_quad0 = dqs_clk_increment_wa0; + read_phase_value_quad0 = read_phase_value_wa0; } else if ( quad0_workaround_type == 1 ) { - dqs_clk_increment_quad0 = dqs_clk_increment_wa1; - read_phase_value_quad0 = read_phase_value_wa1; + dqs_clk_increment_quad0 = dqs_clk_increment_wa1; + read_phase_value_quad0 = read_phase_value_wa1; } else if ( quad0_workaround_type == 2 ) { - dqs_clk_increment_quad0 = dqs_clk_increment_wa2; - read_phase_value_quad0 = read_phase_value_wa2; + dqs_clk_increment_quad0 = dqs_clk_increment_wa2; + read_phase_value_quad0 = read_phase_value_wa2; } FAPI_INF( "+++ ALL Blocks ALL Quads using workaround number %d with dqs_clk_increment: %d read_phase_value: %d +++", quad0_workaround_type, dqs_clk_increment_quad0, read_phase_value_quad0); if ( quad1_workaround_type == 0 ) { - dqs_clk_increment_quad1 = dqs_clk_increment_wa0; - read_phase_value_quad1 = read_phase_value_wa0; + dqs_clk_increment_quad1 = dqs_clk_increment_wa0; + read_phase_value_quad1 = read_phase_value_wa0; } else if ( quad1_workaround_type == 1 ) { - dqs_clk_increment_quad1 = dqs_clk_increment_wa1; - read_phase_value_quad1 = read_phase_value_wa1; + dqs_clk_increment_quad1 = dqs_clk_increment_wa1; + read_phase_value_quad1 = read_phase_value_wa1; } else if ( quad1_workaround_type == 2 ) { - dqs_clk_increment_quad1 = dqs_clk_increment_wa2; - read_phase_value_quad1 = read_phase_value_wa2; + dqs_clk_increment_quad1 = dqs_clk_increment_wa2; + read_phase_value_quad1 = read_phase_value_wa2; } if ( quad2_workaround_type == 0 ) { - dqs_clk_increment_quad2 = dqs_clk_increment_wa0; - read_phase_value_quad2 = read_phase_value_wa0; + dqs_clk_increment_quad2 = dqs_clk_increment_wa0; + read_phase_value_quad2 = read_phase_value_wa0; } else if ( quad2_workaround_type == 1 ) { - dqs_clk_increment_quad2 = dqs_clk_increment_wa1; - read_phase_value_quad2 = read_phase_value_wa1; + dqs_clk_increment_quad2 = dqs_clk_increment_wa1; + read_phase_value_quad2 = read_phase_value_wa1; } else if ( quad2_workaround_type == 2 ) { - dqs_clk_increment_quad2 = dqs_clk_increment_wa2; - read_phase_value_quad2 = read_phase_value_wa2; + dqs_clk_increment_quad2 = dqs_clk_increment_wa2; + read_phase_value_quad2 = read_phase_value_wa2; } if ( quad3_workaround_type == 0 ) { - dqs_clk_increment_quad3 = dqs_clk_increment_wa0; - read_phase_value_quad3 = read_phase_value_wa0; + dqs_clk_increment_quad3 = dqs_clk_increment_wa0; + read_phase_value_quad3 = read_phase_value_wa0; } else if ( quad3_workaround_type == 1 ) { - dqs_clk_increment_quad3 = dqs_clk_increment_wa1; - read_phase_value_quad3 = read_phase_value_wa1; + dqs_clk_increment_quad3 = dqs_clk_increment_wa1; + read_phase_value_quad3 = read_phase_value_wa1; } else if ( quad3_workaround_type == 2 ) { - dqs_clk_increment_quad3 = dqs_clk_increment_wa2; - read_phase_value_quad3 = read_phase_value_wa2; + dqs_clk_increment_quad3 = dqs_clk_increment_wa2; + read_phase_value_quad3 = read_phase_value_wa2; } rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64); @@ -1462,72 +1624,72 @@ ReturnCode mss_read_center_workaround( if(rc_num) { - rc.setEcmdError(rc_num); - return rc; + rc.setEcmdError(rc_num); + return rc; } if ( quad0_workaround_type == 0 ) { - dqs_clk_increment_quad0 = dqs_clk_increment_wa0; - read_phase_value_quad0 = read_phase_value_wa0; + dqs_clk_increment_quad0 = dqs_clk_increment_wa0; + read_phase_value_quad0 = read_phase_value_wa0; } else if ( quad0_workaround_type == 1 ) { - dqs_clk_increment_quad0 = dqs_clk_increment_wa1; - read_phase_value_quad0 = read_phase_value_wa1; + dqs_clk_increment_quad0 = dqs_clk_increment_wa1; + read_phase_value_quad0 = read_phase_value_wa1; } else if ( quad0_workaround_type == 2 ) { - dqs_clk_increment_quad0 = dqs_clk_increment_wa2; - read_phase_value_quad0 = read_phase_value_wa2; + dqs_clk_increment_quad0 = dqs_clk_increment_wa2; + read_phase_value_quad0 = read_phase_value_wa2; } if ( quad1_workaround_type == 0 ) { - dqs_clk_increment_quad1 = dqs_clk_increment_wa0; - read_phase_value_quad1 = read_phase_value_wa0; + dqs_clk_increment_quad1 = dqs_clk_increment_wa0; + read_phase_value_quad1 = read_phase_value_wa0; } else if ( quad1_workaround_type == 1 ) { - dqs_clk_increment_quad1 = dqs_clk_increment_wa1; - read_phase_value_quad1 = read_phase_value_wa1; + dqs_clk_increment_quad1 = dqs_clk_increment_wa1; + read_phase_value_quad1 = read_phase_value_wa1; } else if ( quad1_workaround_type == 2 ) { - dqs_clk_increment_quad1 = dqs_clk_increment_wa2; - read_phase_value_quad1 = read_phase_value_wa2; + dqs_clk_increment_quad1 = dqs_clk_increment_wa2; + read_phase_value_quad1 = read_phase_value_wa2; } if ( quad2_workaround_type == 0 ) { - dqs_clk_increment_quad2 = dqs_clk_increment_wa0; - read_phase_value_quad2 = read_phase_value_wa0; + dqs_clk_increment_quad2 = dqs_clk_increment_wa0; + read_phase_value_quad2 = read_phase_value_wa0; } else if ( quad2_workaround_type == 1 ) { - dqs_clk_increment_quad2 = dqs_clk_increment_wa1; - read_phase_value_quad2 = read_phase_value_wa1; + dqs_clk_increment_quad2 = dqs_clk_increment_wa1; + read_phase_value_quad2 = read_phase_value_wa1; } else if ( quad2_workaround_type == 2 ) { - dqs_clk_increment_quad2 = dqs_clk_increment_wa2; - read_phase_value_quad2 = read_phase_value_wa2; + dqs_clk_increment_quad2 = dqs_clk_increment_wa2; + read_phase_value_quad2 = read_phase_value_wa2; } if ( quad3_workaround_type == 0 ) { - dqs_clk_increment_quad3 = dqs_clk_increment_wa0; - read_phase_value_quad3 = read_phase_value_wa0; + dqs_clk_increment_quad3 = dqs_clk_increment_wa0; + read_phase_value_quad3 = read_phase_value_wa0; } else if ( quad3_workaround_type == 1 ) { - dqs_clk_increment_quad3 = dqs_clk_increment_wa1; - read_phase_value_quad3 = read_phase_value_wa1; + dqs_clk_increment_quad3 = dqs_clk_increment_wa1; + read_phase_value_quad3 = read_phase_value_wa1; } else if ( quad3_workaround_type == 2 ) { - dqs_clk_increment_quad3 = dqs_clk_increment_wa2; - read_phase_value_quad3 = read_phase_value_wa2; + dqs_clk_increment_quad3 = dqs_clk_increment_wa2; + read_phase_value_quad3 = read_phase_value_wa2; } @@ -1573,72 +1735,72 @@ ReturnCode mss_read_center_workaround( if(rc_num) { - rc.setEcmdError(rc_num); - return rc; + rc.setEcmdError(rc_num); + return rc; } if ( quad0_workaround_type == 0 ) { - dqs_clk_increment_quad0 = dqs_clk_increment_wa0; - read_phase_value_quad0 = read_phase_value_wa0; + dqs_clk_increment_quad0 = dqs_clk_increment_wa0; + read_phase_value_quad0 = read_phase_value_wa0; } else if ( quad0_workaround_type == 1 ) { - dqs_clk_increment_quad0 = dqs_clk_increment_wa1; - read_phase_value_quad0 = read_phase_value_wa1; + dqs_clk_increment_quad0 = dqs_clk_increment_wa1; + read_phase_value_quad0 = read_phase_value_wa1; } else if ( quad0_workaround_type == 2 ) { - dqs_clk_increment_quad0 = dqs_clk_increment_wa2; - read_phase_value_quad0 = read_phase_value_wa2; + dqs_clk_increment_quad0 = dqs_clk_increment_wa2; + read_phase_value_quad0 = read_phase_value_wa2; } if ( quad1_workaround_type == 0 ) { - dqs_clk_increment_quad1 = dqs_clk_increment_wa0; - read_phase_value_quad1 = read_phase_value_wa0; + dqs_clk_increment_quad1 = dqs_clk_increment_wa0; + read_phase_value_quad1 = read_phase_value_wa0; } else if ( quad1_workaround_type == 1 ) { - dqs_clk_increment_quad1 = dqs_clk_increment_wa1; - read_phase_value_quad1 = read_phase_value_wa1; + dqs_clk_increment_quad1 = dqs_clk_increment_wa1; + read_phase_value_quad1 = read_phase_value_wa1; } else if ( quad1_workaround_type == 2 ) { - dqs_clk_increment_quad1 = dqs_clk_increment_wa2; - read_phase_value_quad1 = read_phase_value_wa2; + dqs_clk_increment_quad1 = dqs_clk_increment_wa2; + read_phase_value_quad1 = read_phase_value_wa2; } if ( quad2_workaround_type == 0 ) { - dqs_clk_increment_quad2 = dqs_clk_increment_wa0; - read_phase_value_quad2 = read_phase_value_wa0; + dqs_clk_increment_quad2 = dqs_clk_increment_wa0; + read_phase_value_quad2 = read_phase_value_wa0; } else if ( quad2_workaround_type == 1 ) { - dqs_clk_increment_quad2 = dqs_clk_increment_wa1; - read_phase_value_quad2 = read_phase_value_wa1; + dqs_clk_increment_quad2 = dqs_clk_increment_wa1; + read_phase_value_quad2 = read_phase_value_wa1; } else if ( quad2_workaround_type == 2 ) { - dqs_clk_increment_quad2 = dqs_clk_increment_wa2; - read_phase_value_quad2 = read_phase_value_wa2; + dqs_clk_increment_quad2 = dqs_clk_increment_wa2; + read_phase_value_quad2 = read_phase_value_wa2; } if ( quad3_workaround_type == 0 ) { - dqs_clk_increment_quad3 = dqs_clk_increment_wa0; - read_phase_value_quad3 = read_phase_value_wa0; + dqs_clk_increment_quad3 = dqs_clk_increment_wa0; + read_phase_value_quad3 = read_phase_value_wa0; } else if ( quad3_workaround_type == 1 ) { - dqs_clk_increment_quad3 = dqs_clk_increment_wa1; - read_phase_value_quad3 = read_phase_value_wa1; + dqs_clk_increment_quad3 = dqs_clk_increment_wa1; + read_phase_value_quad3 = read_phase_value_wa1; } else if ( quad3_workaround_type == 2 ) { - dqs_clk_increment_quad3 = dqs_clk_increment_wa2; - read_phase_value_quad3 = read_phase_value_wa2; + dqs_clk_increment_quad3 = dqs_clk_increment_wa2; + read_phase_value_quad3 = read_phase_value_wa2; } @@ -1684,72 +1846,72 @@ ReturnCode mss_read_center_workaround( if(rc_num) { - rc.setEcmdError(rc_num); - return rc; + rc.setEcmdError(rc_num); + return rc; } if ( quad0_workaround_type == 0 ) { - dqs_clk_increment_quad0 = dqs_clk_increment_wa0; - read_phase_value_quad0 = read_phase_value_wa0; + dqs_clk_increment_quad0 = dqs_clk_increment_wa0; + read_phase_value_quad0 = read_phase_value_wa0; } else if ( quad0_workaround_type == 1 ) { - dqs_clk_increment_quad0 = dqs_clk_increment_wa1; - read_phase_value_quad0 = read_phase_value_wa1; + dqs_clk_increment_quad0 = dqs_clk_increment_wa1; + read_phase_value_quad0 = read_phase_value_wa1; } else if ( quad0_workaround_type == 2 ) { - dqs_clk_increment_quad0 = dqs_clk_increment_wa2; - read_phase_value_quad0 = read_phase_value_wa2; + dqs_clk_increment_quad0 = dqs_clk_increment_wa2; + read_phase_value_quad0 = read_phase_value_wa2; } if ( quad1_workaround_type == 0 ) { - dqs_clk_increment_quad1 = dqs_clk_increment_wa0; - read_phase_value_quad1 = read_phase_value_wa0; + dqs_clk_increment_quad1 = dqs_clk_increment_wa0; + read_phase_value_quad1 = read_phase_value_wa0; } else if ( quad1_workaround_type == 1 ) { - dqs_clk_increment_quad1 = dqs_clk_increment_wa1; - read_phase_value_quad1 = read_phase_value_wa1; + dqs_clk_increment_quad1 = dqs_clk_increment_wa1; + read_phase_value_quad1 = read_phase_value_wa1; } else if ( quad1_workaround_type == 2 ) { - dqs_clk_increment_quad1 = dqs_clk_increment_wa2; - read_phase_value_quad1 = read_phase_value_wa2; + dqs_clk_increment_quad1 = dqs_clk_increment_wa2; + read_phase_value_quad1 = read_phase_value_wa2; } if ( quad2_workaround_type == 0 ) { - dqs_clk_increment_quad2 = dqs_clk_increment_wa0; - read_phase_value_quad2 = read_phase_value_wa0; + dqs_clk_increment_quad2 = dqs_clk_increment_wa0; + read_phase_value_quad2 = read_phase_value_wa0; } else if ( quad2_workaround_type == 1 ) { - dqs_clk_increment_quad2 = dqs_clk_increment_wa1; - read_phase_value_quad2 = read_phase_value_wa1; + dqs_clk_increment_quad2 = dqs_clk_increment_wa1; + read_phase_value_quad2 = read_phase_value_wa1; } else if ( quad2_workaround_type == 2 ) { - dqs_clk_increment_quad2 = dqs_clk_increment_wa2; - read_phase_value_quad2 = read_phase_value_wa2; + dqs_clk_increment_quad2 = dqs_clk_increment_wa2; + read_phase_value_quad2 = read_phase_value_wa2; } if ( quad3_workaround_type == 0 ) { - dqs_clk_increment_quad3 = dqs_clk_increment_wa0; - read_phase_value_quad3 = read_phase_value_wa0; + dqs_clk_increment_quad3 = dqs_clk_increment_wa0; + read_phase_value_quad3 = read_phase_value_wa0; } else if ( quad3_workaround_type == 1 ) { - dqs_clk_increment_quad3 = dqs_clk_increment_wa1; - read_phase_value_quad3 = read_phase_value_wa1; + dqs_clk_increment_quad3 = dqs_clk_increment_wa1; + read_phase_value_quad3 = read_phase_value_wa1; } else if ( quad3_workaround_type == 2 ) { - dqs_clk_increment_quad3 = dqs_clk_increment_wa2; - read_phase_value_quad3 = read_phase_value_wa2; + dqs_clk_increment_quad3 = dqs_clk_increment_wa2; + read_phase_value_quad3 = read_phase_value_wa2; } @@ -1795,72 +1957,72 @@ ReturnCode mss_read_center_workaround( if(rc_num) { - rc.setEcmdError(rc_num); - return rc; + rc.setEcmdError(rc_num); + return rc; } if ( quad0_workaround_type == 0 ) { - dqs_clk_increment_quad0 = dqs_clk_increment_wa0; - read_phase_value_quad0 = read_phase_value_wa0; + dqs_clk_increment_quad0 = dqs_clk_increment_wa0; + read_phase_value_quad0 = read_phase_value_wa0; } else if ( quad0_workaround_type == 1 ) { - dqs_clk_increment_quad0 = dqs_clk_increment_wa1; - read_phase_value_quad0 = read_phase_value_wa1; + dqs_clk_increment_quad0 = dqs_clk_increment_wa1; + read_phase_value_quad0 = read_phase_value_wa1; } else if ( quad0_workaround_type == 2 ) { - dqs_clk_increment_quad0 = dqs_clk_increment_wa2; - read_phase_value_quad0 = read_phase_value_wa2; + dqs_clk_increment_quad0 = dqs_clk_increment_wa2; + read_phase_value_quad0 = read_phase_value_wa2; } if ( quad1_workaround_type == 0 ) { - dqs_clk_increment_quad1 = dqs_clk_increment_wa0; - read_phase_value_quad1 = read_phase_value_wa0; + dqs_clk_increment_quad1 = dqs_clk_increment_wa0; + read_phase_value_quad1 = read_phase_value_wa0; } else if ( quad1_workaround_type == 1 ) { - dqs_clk_increment_quad1 = dqs_clk_increment_wa1; - read_phase_value_quad1 = read_phase_value_wa1; + dqs_clk_increment_quad1 = dqs_clk_increment_wa1; + read_phase_value_quad1 = read_phase_value_wa1; } else if ( quad1_workaround_type == 2 ) { - dqs_clk_increment_quad1 = dqs_clk_increment_wa2; - read_phase_value_quad1 = read_phase_value_wa2; + dqs_clk_increment_quad1 = dqs_clk_increment_wa2; + read_phase_value_quad1 = read_phase_value_wa2; } if ( quad2_workaround_type == 0 ) { - dqs_clk_increment_quad2 = dqs_clk_increment_wa0; - read_phase_value_quad2 = read_phase_value_wa0; + dqs_clk_increment_quad2 = dqs_clk_increment_wa0; + read_phase_value_quad2 = read_phase_value_wa0; } else if ( quad2_workaround_type == 1 ) { - dqs_clk_increment_quad2 = dqs_clk_increment_wa1; - read_phase_value_quad2 = read_phase_value_wa1; + dqs_clk_increment_quad2 = dqs_clk_increment_wa1; + read_phase_value_quad2 = read_phase_value_wa1; } else if ( quad2_workaround_type == 2 ) { - dqs_clk_increment_quad2 = dqs_clk_increment_wa2; - read_phase_value_quad2 = read_phase_value_wa2; + dqs_clk_increment_quad2 = dqs_clk_increment_wa2; + read_phase_value_quad2 = read_phase_value_wa2; } if ( quad3_workaround_type == 0 ) { - dqs_clk_increment_quad3 = dqs_clk_increment_wa0; - read_phase_value_quad3 = read_phase_value_wa0; + dqs_clk_increment_quad3 = dqs_clk_increment_wa0; + read_phase_value_quad3 = read_phase_value_wa0; } else if ( quad3_workaround_type == 1 ) { - dqs_clk_increment_quad3 = dqs_clk_increment_wa1; - read_phase_value_quad3 = read_phase_value_wa1; + dqs_clk_increment_quad3 = dqs_clk_increment_wa1; + read_phase_value_quad3 = read_phase_value_wa1; } else if ( quad3_workaround_type == 2 ) { - dqs_clk_increment_quad3 = dqs_clk_increment_wa2; - read_phase_value_quad3 = read_phase_value_wa2; + dqs_clk_increment_quad3 = dqs_clk_increment_wa2; + read_phase_value_quad3 = read_phase_value_wa2; } @@ -1957,610 +2119,610 @@ ReturnCode mss_read_center_second_workaround( { - //FAPI_INF( "DQS_CLK Byte matching Workaround being applied on %s PORT: %d RP: %d", i_target.toEcmdString(), port, rank_group); + //FAPI_INF( "DQS_CLK Byte matching Workaround being applied on %s PORT: %d RP: %d", i_target.toEcmdString(), port, rank_group); - //Gather all the byte information + //Gather all the byte information for(rank_group = 0; rank_group < MAX_PRI_RANKS; rank_group++) - { - - //Initialize values - for(block = 0; block < maxblocks; block++) - { - for (byte = 0; byte < maxbytes; byte++) - { - for (nibble = 0; nibble < maxnibbles; nibble++) - { - l_lowest_value_u8[rank_group][block][byte][nibble] = 255; - l_gate_delay_value_u8[rank_group][block][byte][nibble] = 255; - } - } - } - - //Check if rank group exists - if(primary_ranks_array[rank_group][port] != 255) - { - FAPI_INF( "DQS_CLK Byte matching Workaround being applied on %s PORT: %d RP: %d", i_target.toEcmdString(), port, rank_group); - if ( port == 0 ) - { - - if ( rank_group == 0 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_0x800000090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_0x800004090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_0x800008090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_0x80000C090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_0x800010090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_0_0x800000130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_1_0x800004130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_2_0x800008130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_3_0x80000C130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_4_0x800010130301143F; - - } - else if ( rank_group == 1 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_0x800001090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_0x800005090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_0x800009090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_0x80000D090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_0x800011090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_0_0x800001130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_1_0x800005130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_2_0x800009130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_3_0x80000D130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_4_0x800011130301143F; - - } - else if ( rank_group == 2 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_0x800002090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_0x800006090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_0x80000A090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_0x80000E090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_0x800012090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_0_0x800002130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_1_0x800006130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_2_0x80000A130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_3_0x80000E130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_4_0x800012130301143F; - - } - else if ( rank_group == 3 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_0x800003090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_0x800007090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_0x80000B090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_0x80000F090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_0x800013090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_0_0x800003130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_1_0x800007130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_2_0x80000B130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_3_0x80000F130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_4_0x800013130301143F; - - } - } - else if (port == 1 ) - { - - if ( rank_group == 0 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_0x800100090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_0x800104090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_0x800108090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_0x80010C090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_0x800110090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_0_0x800100130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_1_0x800104130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_2_0x800108130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_3_0x80010C130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_4_0x800110130301143F; - - } - else if ( rank_group == 1 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_0x800101090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_0x800105090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_0x800109090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_0x80010D090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_0x800111090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_0_0x800101130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_1_0x800105130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_2_0x800109130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_3_0x80010D130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_4_0x800111130301143F; - - } - else if ( rank_group == 2 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_0x800102090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_0x800106090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_0x80010A090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_0x80010E090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_0x800112090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_0_0x800102130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_1_0x800106130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_2_0x80010A130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_3_0x80010E130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_4_0x800112130301143F; - - } - else if ( rank_group == 3 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_0x800103090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_0x800107090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_0x80010B090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_0x80010F090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_0x800113090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_0_0x800103130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_1_0x800107130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_2_0x80010B130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_3_0x80010F130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_4_0x800113130301143F; - - } - } - - - // PHY BLOCK 0 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64); - if (rc) return rc; - // Grabbing 2 nibbles of the same byte and making them equal to the same lowest value - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 2); - l_lowest_value_u8[rank_group][0][0][0] = l_value_n0_u8; - l_lowest_value_u8[rank_group][0][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 2); - l_lowest_value_u8[rank_group][0][1][0] = l_value_n0_u8; - l_lowest_value_u8[rank_group][0][1][1] = l_value_n1_u8; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_0, data_buffer_64); - if (rc) return rc; - // Grabbing 2 nibbles of the same byte and making them equal the same lowest value - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3); - l_gate_delay_value_u8[rank_group][0][0][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][0][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3); - l_gate_delay_value_u8[rank_group][0][1][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][0][1][1] = l_value_n1_u8; - - // PHY BLOCK 1 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64); - if (rc) return rc; - // Grabbing 2 nibbles of the same byte and making them equal to the same lowest value - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 2); - l_lowest_value_u8[rank_group][1][0][0] = l_value_n0_u8; - l_lowest_value_u8[rank_group][1][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 2); - l_lowest_value_u8[rank_group][1][1][0] = l_value_n0_u8; - l_lowest_value_u8[rank_group][1][1][1] = l_value_n1_u8; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_1, data_buffer_64); - if (rc) return rc; - // Grabbing 2 nibbles of the same byte and making them equal the same lowest value - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3); - l_gate_delay_value_u8[rank_group][1][0][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][1][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3); - l_gate_delay_value_u8[rank_group][1][1][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][1][1][1] = l_value_n1_u8; - - // PHY BLOCK 2 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64); - if (rc) return rc; - // Grabbing 2 nibbles of the same byte and making them equal to the same lowest value - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 2); - l_lowest_value_u8[rank_group][2][0][0] = l_value_n0_u8; - l_lowest_value_u8[rank_group][2][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 2); - l_lowest_value_u8[rank_group][2][1][0] = l_value_n0_u8; - l_lowest_value_u8[rank_group][2][1][1] = l_value_n1_u8; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_2, data_buffer_64); - if (rc) return rc; - // Grabbing 2 nibbles of the same byte and making them equal the same lowest value - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3); - l_gate_delay_value_u8[rank_group][2][0][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][2][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3); - l_gate_delay_value_u8[rank_group][2][1][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][2][1][1] = l_value_n1_u8; - - // PHY BLOCK 3 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64); - if (rc) return rc; - // Grabbing 2 nibbles of the same byte and making them equal to the same lowest value - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 2); - l_lowest_value_u8[rank_group][3][0][0] = l_value_n0_u8; - l_lowest_value_u8[rank_group][3][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 2); - l_lowest_value_u8[rank_group][3][1][0] = l_value_n0_u8; - l_lowest_value_u8[rank_group][3][1][1] = l_value_n1_u8; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_3, data_buffer_64); - if (rc) return rc; - // Grabbing 2 nibbles of the same byte and making them equal the same lowest value - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3); - l_gate_delay_value_u8[rank_group][3][0][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][3][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3); - l_gate_delay_value_u8[rank_group][3][1][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][3][1][1] = l_value_n1_u8; - - // PHY BLOCK 4 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64); - if (rc) return rc; - // Grabbing 2 nibbles of the same byte and making them equal to the same lowest value - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 2); - l_lowest_value_u8[rank_group][4][0][0] = l_value_n0_u8; - l_lowest_value_u8[rank_group][4][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 2); - l_lowest_value_u8[rank_group][4][1][0] = l_value_n0_u8; - l_lowest_value_u8[rank_group][4][1][1] = l_value_n1_u8; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_4, data_buffer_64); - if (rc) return rc; - // Grabbing 2 nibbles of the same byte and making them equal the same lowest value - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3); - l_gate_delay_value_u8[rank_group][4][0][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][4][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3); - l_gate_delay_value_u8[rank_group][4][1][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][4][1][1] = l_value_n1_u8; - - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - - } - } - - //Finding the lowest Value + { + + //Initialize values + for(block = 0; block < maxblocks; block++) + { + for (byte = 0; byte < maxbytes; byte++) + { + for (nibble = 0; nibble < maxnibbles; nibble++) + { + l_lowest_value_u8[rank_group][block][byte][nibble] = 255; + l_gate_delay_value_u8[rank_group][block][byte][nibble] = 255; + } + } + } + + //Check if rank group exists + if(primary_ranks_array[rank_group][port] != 255) + { + FAPI_INF( "DQS_CLK Byte matching Workaround being applied on %s PORT: %d RP: %d", i_target.toEcmdString(), port, rank_group); + if ( port == 0 ) + { + + if ( rank_group == 0 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_0x800000090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_0x800004090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_0x800008090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_0x80000C090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_0x800010090301143F; + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_0_0x800000130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_1_0x800004130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_2_0x800008130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_3_0x80000C130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_4_0x800010130301143F; + + } + else if ( rank_group == 1 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_0x800001090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_0x800005090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_0x800009090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_0x80000D090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_0x800011090301143F; + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_0_0x800001130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_1_0x800005130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_2_0x800009130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_3_0x80000D130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_4_0x800011130301143F; + + } + else if ( rank_group == 2 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_0x800002090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_0x800006090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_0x80000A090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_0x80000E090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_0x800012090301143F; + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_0_0x800002130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_1_0x800006130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_2_0x80000A130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_3_0x80000E130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_4_0x800012130301143F; + + } + else if ( rank_group == 3 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_0x800003090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_0x800007090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_0x80000B090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_0x80000F090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_0x800013090301143F; + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_0_0x800003130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_1_0x800007130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_2_0x80000B130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_3_0x80000F130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_4_0x800013130301143F; + + } + } + else if (port == 1 ) + { + + if ( rank_group == 0 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_0x800100090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_0x800104090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_0x800108090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_0x80010C090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_0x800110090301143F; + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_0_0x800100130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_1_0x800104130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_2_0x800108130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_3_0x80010C130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_4_0x800110130301143F; + + } + else if ( rank_group == 1 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_0x800101090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_0x800105090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_0x800109090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_0x80010D090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_0x800111090301143F; + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_0_0x800101130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_1_0x800105130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_2_0x800109130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_3_0x80010D130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_4_0x800111130301143F; + + } + else if ( rank_group == 2 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_0x800102090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_0x800106090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_0x80010A090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_0x80010E090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_0x800112090301143F; + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_0_0x800102130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_1_0x800106130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_2_0x80010A130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_3_0x80010E130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_4_0x800112130301143F; + + } + else if ( rank_group == 3 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_0x800103090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_0x800107090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_0x80010B090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_0x80010F090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_0x800113090301143F; + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_0_0x800103130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_1_0x800107130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_2_0x80010B130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_3_0x80010F130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_4_0x800113130301143F; + + } + } + + + // PHY BLOCK 0 + rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64); + if (rc) return rc; + // Grabbing 2 nibbles of the same byte and making them equal to the same lowest value + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 2); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 2); + l_lowest_value_u8[rank_group][0][0][0] = l_value_n0_u8; + l_lowest_value_u8[rank_group][0][0][1] = l_value_n1_u8; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 2); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 2); + l_lowest_value_u8[rank_group][0][1][0] = l_value_n0_u8; + l_lowest_value_u8[rank_group][0][1][1] = l_value_n1_u8; + + rc = fapiGetScom(i_target, GATE_DELAY_ADDR_0, data_buffer_64); + if (rc) return rc; + // Grabbing 2 nibbles of the same byte and making them equal the same lowest value + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3); + l_gate_delay_value_u8[rank_group][0][0][0] = l_value_n0_u8; + l_gate_delay_value_u8[rank_group][0][0][1] = l_value_n1_u8; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3); + l_gate_delay_value_u8[rank_group][0][1][0] = l_value_n0_u8; + l_gate_delay_value_u8[rank_group][0][1][1] = l_value_n1_u8; + + // PHY BLOCK 1 + rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64); + if (rc) return rc; + // Grabbing 2 nibbles of the same byte and making them equal to the same lowest value + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 2); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 2); + l_lowest_value_u8[rank_group][1][0][0] = l_value_n0_u8; + l_lowest_value_u8[rank_group][1][0][1] = l_value_n1_u8; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 2); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 2); + l_lowest_value_u8[rank_group][1][1][0] = l_value_n0_u8; + l_lowest_value_u8[rank_group][1][1][1] = l_value_n1_u8; + + rc = fapiGetScom(i_target, GATE_DELAY_ADDR_1, data_buffer_64); + if (rc) return rc; + // Grabbing 2 nibbles of the same byte and making them equal the same lowest value + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3); + l_gate_delay_value_u8[rank_group][1][0][0] = l_value_n0_u8; + l_gate_delay_value_u8[rank_group][1][0][1] = l_value_n1_u8; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3); + l_gate_delay_value_u8[rank_group][1][1][0] = l_value_n0_u8; + l_gate_delay_value_u8[rank_group][1][1][1] = l_value_n1_u8; + + // PHY BLOCK 2 + rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64); + if (rc) return rc; + // Grabbing 2 nibbles of the same byte and making them equal to the same lowest value + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 2); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 2); + l_lowest_value_u8[rank_group][2][0][0] = l_value_n0_u8; + l_lowest_value_u8[rank_group][2][0][1] = l_value_n1_u8; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 2); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 2); + l_lowest_value_u8[rank_group][2][1][0] = l_value_n0_u8; + l_lowest_value_u8[rank_group][2][1][1] = l_value_n1_u8; + + rc = fapiGetScom(i_target, GATE_DELAY_ADDR_2, data_buffer_64); + if (rc) return rc; + // Grabbing 2 nibbles of the same byte and making them equal the same lowest value + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3); + l_gate_delay_value_u8[rank_group][2][0][0] = l_value_n0_u8; + l_gate_delay_value_u8[rank_group][2][0][1] = l_value_n1_u8; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3); + l_gate_delay_value_u8[rank_group][2][1][0] = l_value_n0_u8; + l_gate_delay_value_u8[rank_group][2][1][1] = l_value_n1_u8; + + // PHY BLOCK 3 + rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64); + if (rc) return rc; + // Grabbing 2 nibbles of the same byte and making them equal to the same lowest value + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 2); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 2); + l_lowest_value_u8[rank_group][3][0][0] = l_value_n0_u8; + l_lowest_value_u8[rank_group][3][0][1] = l_value_n1_u8; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 2); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 2); + l_lowest_value_u8[rank_group][3][1][0] = l_value_n0_u8; + l_lowest_value_u8[rank_group][3][1][1] = l_value_n1_u8; + + rc = fapiGetScom(i_target, GATE_DELAY_ADDR_3, data_buffer_64); + if (rc) return rc; + // Grabbing 2 nibbles of the same byte and making them equal the same lowest value + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3); + l_gate_delay_value_u8[rank_group][3][0][0] = l_value_n0_u8; + l_gate_delay_value_u8[rank_group][3][0][1] = l_value_n1_u8; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3); + l_gate_delay_value_u8[rank_group][3][1][0] = l_value_n0_u8; + l_gate_delay_value_u8[rank_group][3][1][1] = l_value_n1_u8; + + // PHY BLOCK 4 + rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64); + if (rc) return rc; + // Grabbing 2 nibbles of the same byte and making them equal to the same lowest value + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 2); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 2); + l_lowest_value_u8[rank_group][4][0][0] = l_value_n0_u8; + l_lowest_value_u8[rank_group][4][0][1] = l_value_n1_u8; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 2); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 2); + l_lowest_value_u8[rank_group][4][1][0] = l_value_n0_u8; + l_lowest_value_u8[rank_group][4][1][1] = l_value_n1_u8; + + rc = fapiGetScom(i_target, GATE_DELAY_ADDR_4, data_buffer_64); + if (rc) return rc; + // Grabbing 2 nibbles of the same byte and making them equal the same lowest value + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3); + l_gate_delay_value_u8[rank_group][4][0][0] = l_value_n0_u8; + l_gate_delay_value_u8[rank_group][4][0][1] = l_value_n1_u8; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3); + l_gate_delay_value_u8[rank_group][4][1][0] = l_value_n0_u8; + l_gate_delay_value_u8[rank_group][4][1][1] = l_value_n1_u8; + + if(rc_num) + { + rc.setEcmdError(rc_num); + return rc; + } + + } + } + + //Finding the lowest Value for(block = 0; block < maxblocks; block++) - { - for (byte = 0; byte < maxbytes; byte++) - { - - for (nibble = 0; nibble < maxnibbles; nibble++) - { - - if ( (l_lowest_value_u8[0][block][byte][nibble] == 0) || - (l_lowest_value_u8[1][block][byte][nibble] == 0) || - (l_lowest_value_u8[2][block][byte][nibble] == 0) || - (l_lowest_value_u8[3][block][byte][nibble] == 0) ) - { - if ( (l_lowest_value_u8[0][block][byte][nibble] == 3) || - (l_lowest_value_u8[1][block][byte][nibble] == 3) || - (l_lowest_value_u8[2][block][byte][nibble] == 3) || - (l_lowest_value_u8[3][block][byte][nibble] == 3) ) - { - - //In this case alone we make all gate values equal the gate of the lowest DQSCLK - if (l_lowest_value_u8[0][block][byte][nibble] == 3) - { - l_gate_delay_value_u8[1][block][byte][nibble] = l_gate_delay_value_u8[0][block][byte][nibble]; - l_gate_delay_value_u8[2][block][byte][nibble] = l_gate_delay_value_u8[0][block][byte][nibble]; - l_gate_delay_value_u8[3][block][byte][nibble] = l_gate_delay_value_u8[0][block][byte][nibble]; - } - else if (l_lowest_value_u8[1][block][byte][nibble] == 3) - { - l_gate_delay_value_u8[0][block][byte][nibble] = l_gate_delay_value_u8[1][block][byte][nibble]; - l_gate_delay_value_u8[2][block][byte][nibble] = l_gate_delay_value_u8[1][block][byte][nibble]; - l_gate_delay_value_u8[3][block][byte][nibble] = l_gate_delay_value_u8[1][block][byte][nibble]; - } - else if (l_lowest_value_u8[2][block][byte][nibble] == 3) - { - l_gate_delay_value_u8[0][block][byte][nibble] = l_gate_delay_value_u8[2][block][byte][nibble]; - l_gate_delay_value_u8[1][block][byte][nibble] = l_gate_delay_value_u8[2][block][byte][nibble]; - l_gate_delay_value_u8[3][block][byte][nibble] = l_gate_delay_value_u8[2][block][byte][nibble]; - } - else if (l_lowest_value_u8[3][block][byte][nibble] == 3) - { - l_gate_delay_value_u8[0][block][byte][nibble] = l_gate_delay_value_u8[3][block][byte][nibble]; - l_gate_delay_value_u8[1][block][byte][nibble] = l_gate_delay_value_u8[3][block][byte][nibble]; - l_gate_delay_value_u8[2][block][byte][nibble] = l_gate_delay_value_u8[3][block][byte][nibble]; - } - - l_lowest_value_u8[0][block][byte][nibble] = 3; - l_lowest_value_u8[1][block][byte][nibble] = 3; - l_lowest_value_u8[2][block][byte][nibble] = 3; - l_lowest_value_u8[3][block][byte][nibble] = 3; - } - else - { - l_lowest_value_u8[0][block][byte][nibble] = 0; - l_lowest_value_u8[1][block][byte][nibble] = 0; - l_lowest_value_u8[2][block][byte][nibble] = 0; - l_lowest_value_u8[3][block][byte][nibble] = 0; - - } - } - else if ( (l_lowest_value_u8[0][block][byte][nibble] == 2) || - (l_lowest_value_u8[1][block][byte][nibble] == 2) || - (l_lowest_value_u8[2][block][byte][nibble] == 2) || - (l_lowest_value_u8[3][block][byte][nibble] == 2) ) - { - if ( (l_lowest_value_u8[0][block][byte][nibble] == 1) || - (l_lowest_value_u8[1][block][byte][nibble] == 1) || - (l_lowest_value_u8[2][block][byte][nibble] == 1) || - (l_lowest_value_u8[3][block][byte][nibble] == 1) ) - { - l_lowest_value_u8[0][block][byte][nibble] = 1; - l_lowest_value_u8[1][block][byte][nibble] = 1; - l_lowest_value_u8[2][block][byte][nibble] = 1; - l_lowest_value_u8[3][block][byte][nibble] = 1; - - } - else - { - l_lowest_value_u8[0][block][byte][nibble] = 2; - l_lowest_value_u8[1][block][byte][nibble] = 2; - l_lowest_value_u8[2][block][byte][nibble] = 2; - l_lowest_value_u8[3][block][byte][nibble] = 2; - - } - } - - } - } - - } - - - //Scoming in the New Values + { + for (byte = 0; byte < maxbytes; byte++) + { + + for (nibble = 0; nibble < maxnibbles; nibble++) + { + + if ( (l_lowest_value_u8[0][block][byte][nibble] == 0) || + (l_lowest_value_u8[1][block][byte][nibble] == 0) || + (l_lowest_value_u8[2][block][byte][nibble] == 0) || + (l_lowest_value_u8[3][block][byte][nibble] == 0) ) + { + if ( (l_lowest_value_u8[0][block][byte][nibble] == 3) || + (l_lowest_value_u8[1][block][byte][nibble] == 3) || + (l_lowest_value_u8[2][block][byte][nibble] == 3) || + (l_lowest_value_u8[3][block][byte][nibble] == 3) ) + { + + //In this case alone we make all gate values equal the gate of the lowest DQSCLK + if (l_lowest_value_u8[0][block][byte][nibble] == 3) + { + l_gate_delay_value_u8[1][block][byte][nibble] = l_gate_delay_value_u8[0][block][byte][nibble]; + l_gate_delay_value_u8[2][block][byte][nibble] = l_gate_delay_value_u8[0][block][byte][nibble]; + l_gate_delay_value_u8[3][block][byte][nibble] = l_gate_delay_value_u8[0][block][byte][nibble]; + } + else if (l_lowest_value_u8[1][block][byte][nibble] == 3) + { + l_gate_delay_value_u8[0][block][byte][nibble] = l_gate_delay_value_u8[1][block][byte][nibble]; + l_gate_delay_value_u8[2][block][byte][nibble] = l_gate_delay_value_u8[1][block][byte][nibble]; + l_gate_delay_value_u8[3][block][byte][nibble] = l_gate_delay_value_u8[1][block][byte][nibble]; + } + else if (l_lowest_value_u8[2][block][byte][nibble] == 3) + { + l_gate_delay_value_u8[0][block][byte][nibble] = l_gate_delay_value_u8[2][block][byte][nibble]; + l_gate_delay_value_u8[1][block][byte][nibble] = l_gate_delay_value_u8[2][block][byte][nibble]; + l_gate_delay_value_u8[3][block][byte][nibble] = l_gate_delay_value_u8[2][block][byte][nibble]; + } + else if (l_lowest_value_u8[3][block][byte][nibble] == 3) + { + l_gate_delay_value_u8[0][block][byte][nibble] = l_gate_delay_value_u8[3][block][byte][nibble]; + l_gate_delay_value_u8[1][block][byte][nibble] = l_gate_delay_value_u8[3][block][byte][nibble]; + l_gate_delay_value_u8[2][block][byte][nibble] = l_gate_delay_value_u8[3][block][byte][nibble]; + } + + l_lowest_value_u8[0][block][byte][nibble] = 3; + l_lowest_value_u8[1][block][byte][nibble] = 3; + l_lowest_value_u8[2][block][byte][nibble] = 3; + l_lowest_value_u8[3][block][byte][nibble] = 3; + } + else + { + l_lowest_value_u8[0][block][byte][nibble] = 0; + l_lowest_value_u8[1][block][byte][nibble] = 0; + l_lowest_value_u8[2][block][byte][nibble] = 0; + l_lowest_value_u8[3][block][byte][nibble] = 0; + + } + } + else if ( (l_lowest_value_u8[0][block][byte][nibble] == 2) || + (l_lowest_value_u8[1][block][byte][nibble] == 2) || + (l_lowest_value_u8[2][block][byte][nibble] == 2) || + (l_lowest_value_u8[3][block][byte][nibble] == 2) ) + { + if ( (l_lowest_value_u8[0][block][byte][nibble] == 1) || + (l_lowest_value_u8[1][block][byte][nibble] == 1) || + (l_lowest_value_u8[2][block][byte][nibble] == 1) || + (l_lowest_value_u8[3][block][byte][nibble] == 1) ) + { + l_lowest_value_u8[0][block][byte][nibble] = 1; + l_lowest_value_u8[1][block][byte][nibble] = 1; + l_lowest_value_u8[2][block][byte][nibble] = 1; + l_lowest_value_u8[3][block][byte][nibble] = 1; + + } + else + { + l_lowest_value_u8[0][block][byte][nibble] = 2; + l_lowest_value_u8[1][block][byte][nibble] = 2; + l_lowest_value_u8[2][block][byte][nibble] = 2; + l_lowest_value_u8[3][block][byte][nibble] = 2; + + } + } + + } + } + + } + + + //Scoming in the New Values for(rank_group = 0; rank_group < MAX_PRI_RANKS; rank_group++) - { - - //Check if rank group exists - if(primary_ranks_array[rank_group][port] != 255) - { - - if ( port == 0 ) - { - - if ( rank_group == 0 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_0x800000090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_0x800004090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_0x800008090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_0x80000C090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_0x800010090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_0_0x800000130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_1_0x800004130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_2_0x800008130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_3_0x80000C130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_4_0x800010130301143F; - - } - else if ( rank_group == 1 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_0x800001090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_0x800005090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_0x800009090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_0x80000D090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_0x800011090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_0_0x800001130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_1_0x800005130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_2_0x800009130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_3_0x80000D130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_4_0x800011130301143F; - - } - else if ( rank_group == 2 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_0x800002090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_0x800006090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_0x80000A090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_0x80000E090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_0x800012090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_0_0x800002130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_1_0x800006130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_2_0x80000A130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_3_0x80000E130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_4_0x800012130301143F; - - } - else if ( rank_group == 3 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_0x800003090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_0x800007090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_0x80000B090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_0x80000F090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_0x800013090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_0_0x800003130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_1_0x800007130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_2_0x80000B130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_3_0x80000F130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_4_0x800013130301143F; - - } - } - else if (port == 1 ) - { - - if ( rank_group == 0 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_0x800100090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_0x800104090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_0x800108090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_0x80010C090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_0x800110090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_0_0x800100130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_1_0x800104130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_2_0x800108130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_3_0x80010C130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_4_0x800110130301143F; - - } - else if ( rank_group == 1 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_0x800101090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_0x800105090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_0x800109090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_0x80010D090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_0x800111090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_0_0x800101130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_1_0x800105130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_2_0x800109130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_3_0x80010D130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_4_0x800111130301143F; - - } - else if ( rank_group == 2 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_0x800102090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_0x800106090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_0x80010A090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_0x80010E090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_0x800112090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_0_0x800102130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_1_0x800106130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_2_0x80010A130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_3_0x80010E130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_4_0x800112130301143F; - - } - else if ( rank_group == 3 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_0x800103090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_0x800107090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_0x80010B090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_0x80010F090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_0x800113090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_0_0x800103130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_1_0x800107130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_2_0x80010B130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_3_0x80010F130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_4_0x800113130301143F; - - } - } - - //BLOCK 0 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][0][0][0], 48, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][0][0][1], 52, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][0][1][0], 56, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][0][1][1], 60, 2); - rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64); - if (rc) return rc; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_0, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][0][0], 49, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][0][1], 53, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][1][0], 57, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][1][1], 61, 3); - rc = fapiPutScom(i_target, GATE_DELAY_ADDR_0, data_buffer_64); - if (rc) return rc; - - //BLOCK 1 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][1][0][0], 48, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][1][0][1], 52, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][1][1][0], 56, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][1][1][1], 60, 2); - rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64); - if (rc) return rc; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_1, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][0][0], 49, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][0][1], 53, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][1][0], 57, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][1][1], 61, 3); - rc = fapiPutScom(i_target, GATE_DELAY_ADDR_1, data_buffer_64); - if (rc) return rc; - - //BLOCK 2 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][2][0][0], 48, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][2][0][1], 52, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][2][1][0], 56, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][2][1][1], 60, 2); - rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64); - if (rc) return rc; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_2, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][0][0], 49, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][0][1], 53, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][1][0], 57, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][1][1], 61, 3); - rc = fapiPutScom(i_target, GATE_DELAY_ADDR_2, data_buffer_64); - if (rc) return rc; - - //BLOCK 3 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][3][0][0], 48, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][3][0][1], 52, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][3][1][0], 56, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][3][1][1], 60, 2); - rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64); - if (rc) return rc; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_3, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][0][0], 49, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][0][1], 53, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][1][0], 57, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][1][1], 61, 3); - rc = fapiPutScom(i_target, GATE_DELAY_ADDR_3, data_buffer_64); - if (rc) return rc; - - //Block 4 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][4][0][0], 48, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][4][0][1], 52, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][4][1][0], 56, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][4][1][1], 60, 2); - rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64); - if (rc) return rc; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_4, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][0][0], 49, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][0][1], 53, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][1][0], 57, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][1][1], 61, 3); - - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - - rc = fapiPutScom(i_target, GATE_DELAY_ADDR_4, data_buffer_64); - if (rc) return rc; - - } - } + { + + //Check if rank group exists + if(primary_ranks_array[rank_group][port] != 255) + { + + if ( port == 0 ) + { + + if ( rank_group == 0 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_0x800000090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_0x800004090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_0x800008090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_0x80000C090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_0x800010090301143F; + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_0_0x800000130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_1_0x800004130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_2_0x800008130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_3_0x80000C130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_4_0x800010130301143F; + + } + else if ( rank_group == 1 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_0x800001090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_0x800005090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_0x800009090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_0x80000D090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_0x800011090301143F; + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_0_0x800001130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_1_0x800005130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_2_0x800009130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_3_0x80000D130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_4_0x800011130301143F; + + } + else if ( rank_group == 2 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_0x800002090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_0x800006090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_0x80000A090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_0x80000E090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_0x800012090301143F; + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_0_0x800002130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_1_0x800006130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_2_0x80000A130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_3_0x80000E130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_4_0x800012130301143F; + + } + else if ( rank_group == 3 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_0x800003090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_0x800007090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_0x80000B090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_0x80000F090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_0x800013090301143F; + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_0_0x800003130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_1_0x800007130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_2_0x80000B130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_3_0x80000F130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_4_0x800013130301143F; + + } + } + else if (port == 1 ) + { + + if ( rank_group == 0 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_0x800100090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_0x800104090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_0x800108090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_0x80010C090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_0x800110090301143F; + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_0_0x800100130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_1_0x800104130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_2_0x800108130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_3_0x80010C130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_4_0x800110130301143F; + + } + else if ( rank_group == 1 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_0x800101090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_0x800105090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_0x800109090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_0x80010D090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_0x800111090301143F; + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_0_0x800101130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_1_0x800105130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_2_0x800109130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_3_0x80010D130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_4_0x800111130301143F; + + } + else if ( rank_group == 2 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_0x800102090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_0x800106090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_0x80010A090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_0x80010E090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_0x800112090301143F; + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_0_0x800102130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_1_0x800106130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_2_0x80010A130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_3_0x80010E130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_4_0x800112130301143F; + + } + else if ( rank_group == 3 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_0x800103090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_0x800107090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_0x80010B090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_0x80010F090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_0x800113090301143F; + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_0_0x800103130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_1_0x800107130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_2_0x80010B130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_3_0x80010F130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_4_0x800113130301143F; + + } + } + + //BLOCK 0 + rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][0][0][0], 48, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][0][0][1], 52, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][0][1][0], 56, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][0][1][1], 60, 2); + rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64); + if (rc) return rc; + + rc = fapiGetScom(i_target, GATE_DELAY_ADDR_0, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][0][0], 49, 3); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][0][1], 53, 3); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][1][0], 57, 3); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][1][1], 61, 3); + rc = fapiPutScom(i_target, GATE_DELAY_ADDR_0, data_buffer_64); + if (rc) return rc; + + //BLOCK 1 + rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][1][0][0], 48, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][1][0][1], 52, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][1][1][0], 56, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][1][1][1], 60, 2); + rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64); + if (rc) return rc; + + rc = fapiGetScom(i_target, GATE_DELAY_ADDR_1, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][0][0], 49, 3); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][0][1], 53, 3); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][1][0], 57, 3); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][1][1], 61, 3); + rc = fapiPutScom(i_target, GATE_DELAY_ADDR_1, data_buffer_64); + if (rc) return rc; + + //BLOCK 2 + rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][2][0][0], 48, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][2][0][1], 52, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][2][1][0], 56, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][2][1][1], 60, 2); + rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64); + if (rc) return rc; + + rc = fapiGetScom(i_target, GATE_DELAY_ADDR_2, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][0][0], 49, 3); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][0][1], 53, 3); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][1][0], 57, 3); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][1][1], 61, 3); + rc = fapiPutScom(i_target, GATE_DELAY_ADDR_2, data_buffer_64); + if (rc) return rc; + + //BLOCK 3 + rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][3][0][0], 48, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][3][0][1], 52, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][3][1][0], 56, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][3][1][1], 60, 2); + rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64); + if (rc) return rc; + + rc = fapiGetScom(i_target, GATE_DELAY_ADDR_3, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][0][0], 49, 3); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][0][1], 53, 3); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][1][0], 57, 3); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][1][1], 61, 3); + rc = fapiPutScom(i_target, GATE_DELAY_ADDR_3, data_buffer_64); + if (rc) return rc; + + //Block 4 + rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][4][0][0], 48, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][4][0][1], 52, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][4][1][0], 56, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][4][1][1], 60, 2); + rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64); + if (rc) return rc; + + rc = fapiGetScom(i_target, GATE_DELAY_ADDR_4, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][0][0], 49, 3); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][0][1], 53, 3); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][1][0], 57, 3); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][1][1], 61, 3); + + if(rc_num) + { + rc.setEcmdError(rc_num); + return rc; + } + + rc = fapiPutScom(i_target, GATE_DELAY_ADDR_4, data_buffer_64); + if (rc) return rc; + + } + } } return rc; @@ -2606,8 +2768,8 @@ ReturnCode mss_disable_workaround( uint32_t maxbytes = 2; uint32_t nibble; uint32_t maxnibbles = 2; - uint8_t l_min_gate_delay = 255; - uint8_t l_min_dqs_clk = 255; + uint8_t l_min_gate_delay = 255; + uint8_t l_min_dqs_clk = 255; uint8_t l_lowest_value_u8[4][5][2][2]; // l_lowest_value_u8[group][block][byte_of_reg][nibble_of_byte] uint8_t l_gate_delay_value_u8[4][5][2][2]; // l_lowest_value_u8[group][block][byte_of_reg][nibble_of_byte] @@ -2629,705 +2791,705 @@ ReturnCode mss_disable_workaround( { - //FAPI_INF( "DQS_CLK Byte matching Workaround being applied on %s PORT: %d RP: %d", i_target.toEcmdString(), port, rank_group); + //FAPI_INF( "DQS_CLK Byte matching Workaround being applied on %s PORT: %d RP: %d", i_target.toEcmdString(), port, rank_group); - //Gather all the byte information + //Gather all the byte information for(rank_group = 0; rank_group < MAX_PRI_RANKS; rank_group++) - { - - //Initialize values - for(block = 0; block < maxblocks; block++) - { - for (byte = 0; byte < maxbytes; byte++) - { - for (nibble = 0; nibble < maxnibbles; nibble++) - { - l_lowest_value_u8[rank_group][block][byte][nibble] = 255; - l_gate_delay_value_u8[rank_group][block][byte][nibble] = 255; - l_disable_value_u8[rank_group][block][byte][nibble] = 0; - } - } - } - - //Check if rank group exists - if(primary_ranks_array[rank_group][port] != 255) - { - FAPI_INF( "DISABLE Workaround being applied on %s PORT: %d RP: %d", i_target.toEcmdString(), port, rank_group); - if ( port == 0 ) - { - - if ( rank_group == 0 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_0x800000090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_0x800004090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_0x800008090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_0x80000C090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_0x800010090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_0_0x800000130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_1_0x800004130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_2_0x800008130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_3_0x80000C130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_4_0x800010130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_0_0x8000007c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_1_0x8000047c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_2_0x8000087c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_3_0x80000c7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_4_0x8000107c0301143F; - - - } - else if ( rank_group == 1 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_0x800001090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_0x800005090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_0x800009090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_0x80000D090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_0x800011090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_0_0x800001130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_1_0x800005130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_2_0x800009130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_3_0x80000D130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_4_0x800011130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_0_0x8000017c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_1_0x8000057c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_2_0x8000097c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_3_0x80000d7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_4_0x8000117c0301143F; - - } - else if ( rank_group == 2 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_0x800002090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_0x800006090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_0x80000A090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_0x80000E090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_0x800012090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_0_0x800002130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_1_0x800006130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_2_0x80000A130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_3_0x80000E130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_4_0x800012130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_0_0x8000027c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_1_0x8000067c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_2_0x80000a7c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_3_0x80000e7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_4_0x8000127c0301143F; - - } - else if ( rank_group == 3 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_0x800003090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_0x800007090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_0x80000B090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_0x80000F090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_0x800013090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_0_0x800003130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_1_0x800007130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_2_0x80000B130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_3_0x80000F130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_4_0x800013130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_0_0x8000037c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_1_0x8000077c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_2_0x80000b7c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_3_0x80000f7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_4_0x8000137c0301143F; - - } - } - else if (port == 1 ) - { - - if ( rank_group == 0 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_0x800100090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_0x800104090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_0x800108090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_0x80010C090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_0x800110090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_0_0x800100130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_1_0x800104130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_2_0x800108130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_3_0x80010C130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_4_0x800110130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_0_0x8001007c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_1_0x8001047c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_2_0x8001087c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_3_0x80010c7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_4_0x8001107c0301143F; - - } - else if ( rank_group == 1 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_0x800101090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_0x800105090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_0x800109090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_0x80010D090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_0x800111090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_0_0x800101130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_1_0x800105130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_2_0x800109130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_3_0x80010D130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_4_0x800111130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_0_0x8001017c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_1_0x8001057c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_2_0x8001097c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_3_0x80010d7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_4_0x8001117c0301143F; - - } - else if ( rank_group == 2 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_0x800102090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_0x800106090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_0x80010A090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_0x80010E090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_0x800112090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_0_0x800102130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_1_0x800106130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_2_0x80010A130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_3_0x80010E130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_4_0x800112130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_0_0x8001027c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_1_0x8001067c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_2_0x80010a7c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_3_0x80010e7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_4_0x8001127c0301143F; - - } - else if ( rank_group == 3 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_0x800103090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_0x800107090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_0x80010B090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_0x80010F090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_0x800113090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_0_0x800103130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_1_0x800107130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_2_0x80010B130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_3_0x80010F130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_4_0x800113130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_0_0x8001037c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_1_0x8001077c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_2_0x80010b7c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_3_0x80010f7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_4_0x8001137c0301143F; - - } - } - - - // PHY BLOCK 0 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 50, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 54, 2); - l_lowest_value_u8[rank_group][0][0][0] = l_value_n0_u8; - l_lowest_value_u8[rank_group][0][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 58, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 62, 2); - l_lowest_value_u8[rank_group][0][1][0] = l_value_n0_u8; - l_lowest_value_u8[rank_group][0][1][1] = l_value_n1_u8; - - rc = fapiGetScom(i_target, DISABLE_ADDR_0, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 4); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 4); - l_disable_value_u8[rank_group][0][0][0] = l_value_n0_u8; - l_disable_value_u8[rank_group][0][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 4); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 4); - l_disable_value_u8[rank_group][0][1][0] = l_value_n0_u8; - l_disable_value_u8[rank_group][0][1][1] = l_value_n1_u8; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_0, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3); - l_gate_delay_value_u8[rank_group][0][0][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][0][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3); - l_gate_delay_value_u8[rank_group][0][1][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][0][1][1] = l_value_n1_u8; - - // PHY BLOCK 1 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 50, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 54, 2); - l_lowest_value_u8[rank_group][1][0][0] = l_value_n0_u8; - l_lowest_value_u8[rank_group][1][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 58, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 62, 2); - l_lowest_value_u8[rank_group][1][1][0] = l_value_n0_u8; - l_lowest_value_u8[rank_group][1][1][1] = l_value_n1_u8; - - rc = fapiGetScom(i_target, DISABLE_ADDR_1, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 4); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 4); - l_disable_value_u8[rank_group][1][0][0] = l_value_n0_u8; - l_disable_value_u8[rank_group][1][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 4); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 4); - l_disable_value_u8[rank_group][1][1][0] = l_value_n0_u8; - l_disable_value_u8[rank_group][1][1][1] = l_value_n1_u8; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_1, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3); - l_gate_delay_value_u8[rank_group][1][0][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][1][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3); - l_gate_delay_value_u8[rank_group][1][1][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][1][1][1] = l_value_n1_u8; - - // PHY BLOCK 2 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 50, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 54, 2); - l_lowest_value_u8[rank_group][2][0][0] = l_value_n0_u8; - l_lowest_value_u8[rank_group][2][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 58, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 62, 2); - l_lowest_value_u8[rank_group][2][1][0] = l_value_n0_u8; - l_lowest_value_u8[rank_group][2][1][1] = l_value_n1_u8; - - rc = fapiGetScom(i_target, DISABLE_ADDR_2, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 4); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 4); - l_disable_value_u8[rank_group][2][0][0] = l_value_n0_u8; - l_disable_value_u8[rank_group][2][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 4); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 4); - l_disable_value_u8[rank_group][2][1][0] = l_value_n0_u8; - l_disable_value_u8[rank_group][2][1][1] = l_value_n1_u8; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_2, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3); - l_gate_delay_value_u8[rank_group][2][0][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][2][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3); - l_gate_delay_value_u8[rank_group][2][1][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][2][1][1] = l_value_n1_u8; - - // PHY BLOCK 3 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 50, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 54, 2); - l_lowest_value_u8[rank_group][3][0][0] = l_value_n0_u8; - l_lowest_value_u8[rank_group][3][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 58, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 62, 2); - l_lowest_value_u8[rank_group][3][1][0] = l_value_n0_u8; - l_lowest_value_u8[rank_group][3][1][1] = l_value_n1_u8; - - rc = fapiGetScom(i_target, DISABLE_ADDR_3, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 4); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 4); - l_disable_value_u8[rank_group][3][0][0] = l_value_n0_u8; - l_disable_value_u8[rank_group][3][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 4); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 4); - l_disable_value_u8[rank_group][3][1][0] = l_value_n0_u8; - l_disable_value_u8[rank_group][3][1][1] = l_value_n1_u8; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_3, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3); - l_gate_delay_value_u8[rank_group][3][0][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][3][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3); - l_gate_delay_value_u8[rank_group][3][1][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][3][1][1] = l_value_n1_u8; - - // PHY BLOCK 4 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 50, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 54, 2); - l_lowest_value_u8[rank_group][4][0][0] = l_value_n0_u8; - l_lowest_value_u8[rank_group][4][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 58, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 62, 2); - l_lowest_value_u8[rank_group][4][1][0] = l_value_n0_u8; - l_lowest_value_u8[rank_group][4][1][1] = l_value_n1_u8; - - rc = fapiGetScom(i_target, DISABLE_ADDR_4, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 4); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 4); - l_disable_value_u8[rank_group][4][0][0] = l_value_n0_u8; - l_disable_value_u8[rank_group][4][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 4); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 4); - l_disable_value_u8[rank_group][4][1][0] = l_value_n0_u8; - l_disable_value_u8[rank_group][4][1][1] = l_value_n1_u8; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_4, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3); - l_gate_delay_value_u8[rank_group][4][0][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][4][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3); - l_gate_delay_value_u8[rank_group][4][1][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][4][1][1] = l_value_n1_u8; - - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - - } - } - - - - - //Finding the lowest Values on disabled bytes, then resetting mask. - for(block = 0; block < maxblocks; block++) - { - for (byte = 0; byte < maxbytes; byte++) - { - - for (nibble = 0; nibble < maxnibbles; nibble++) - { - if ( (l_disable_value_u8[0][block][byte][nibble] != 0) || (l_disable_value_u8[1][block][byte][nibble] != 0) - || (l_disable_value_u8[2][block][byte][nibble] != 0) || (l_disable_value_u8[3][block][byte][nibble] != 0) ) - { - - FAPI_INF( "Located disabled block %d byte %d nibble %d", block, byte, nibble); - - l_min_gate_delay = 255; - for(rank_group = 0; rank_group < MAX_PRI_RANKS; rank_group++) - { - if ( (l_gate_delay_value_u8[rank_group][block][byte][nibble] < l_min_gate_delay) - && (l_disable_value_u8[rank_group][block][byte][nibble] == 0) ) - { - l_min_gate_delay = l_gate_delay_value_u8[rank_group][block][byte][nibble]; - } - } - - FAPI_INF( "Lowest gate_delay %d", l_min_gate_delay); - - l_min_dqs_clk = 255; - for(rank_group = 0; rank_group < MAX_PRI_RANKS; rank_group++) - { - if ( (l_lowest_value_u8[rank_group][block][byte][nibble] < l_min_dqs_clk) - && (l_disable_value_u8[rank_group][block][byte][nibble] == 0) ) - { - l_min_dqs_clk = l_lowest_value_u8[rank_group][block][byte][nibble]; - } - } - - - FAPI_INF( "Lowest rdclk phase %d", l_min_dqs_clk); - - for(rank_group = 0; rank_group < MAX_PRI_RANKS; rank_group++) - { - if (l_disable_value_u8[rank_group][block][byte][nibble] != 0) - { - l_gate_delay_value_u8[rank_group][block][byte][nibble] = l_min_gate_delay; - l_lowest_value_u8[rank_group][block][byte][nibble] = l_min_dqs_clk; - //l_disable_value_u8[rank_group][block][byte][nibble] = 0; - } - } - - } - } - } - - } - - - //Scoming in the New Values + { + + //Initialize values + for(block = 0; block < maxblocks; block++) + { + for (byte = 0; byte < maxbytes; byte++) + { + for (nibble = 0; nibble < maxnibbles; nibble++) + { + l_lowest_value_u8[rank_group][block][byte][nibble] = 255; + l_gate_delay_value_u8[rank_group][block][byte][nibble] = 255; + l_disable_value_u8[rank_group][block][byte][nibble] = 0; + } + } + } + + //Check if rank group exists + if(primary_ranks_array[rank_group][port] != 255) + { + FAPI_INF( "DISABLE Workaround being applied on %s PORT: %d RP: %d", i_target.toEcmdString(), port, rank_group); + if ( port == 0 ) + { + + if ( rank_group == 0 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_0x800000090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_0x800004090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_0x800008090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_0x80000C090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_0x800010090301143F; + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_0_0x800000130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_1_0x800004130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_2_0x800008130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_3_0x80000C130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_4_0x800010130301143F; + DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_0_0x8000007c0301143F; + DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_1_0x8000047c0301143F; + DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_2_0x8000087c0301143F; + DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_3_0x80000c7c0301143F; + DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_4_0x8000107c0301143F; + + + } + else if ( rank_group == 1 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_0x800001090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_0x800005090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_0x800009090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_0x80000D090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_0x800011090301143F; + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_0_0x800001130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_1_0x800005130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_2_0x800009130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_3_0x80000D130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_4_0x800011130301143F; + DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_0_0x8000017c0301143F; + DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_1_0x8000057c0301143F; + DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_2_0x8000097c0301143F; + DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_3_0x80000d7c0301143F; + DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_4_0x8000117c0301143F; + + } + else if ( rank_group == 2 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_0x800002090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_0x800006090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_0x80000A090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_0x80000E090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_0x800012090301143F; + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_0_0x800002130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_1_0x800006130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_2_0x80000A130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_3_0x80000E130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_4_0x800012130301143F; + DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_0_0x8000027c0301143F; + DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_1_0x8000067c0301143F; + DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_2_0x80000a7c0301143F; + DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_3_0x80000e7c0301143F; + DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_4_0x8000127c0301143F; + + } + else if ( rank_group == 3 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_0x800003090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_0x800007090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_0x80000B090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_0x80000F090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_0x800013090301143F; + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_0_0x800003130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_1_0x800007130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_2_0x80000B130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_3_0x80000F130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_4_0x800013130301143F; + DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_0_0x8000037c0301143F; + DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_1_0x8000077c0301143F; + DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_2_0x80000b7c0301143F; + DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_3_0x80000f7c0301143F; + DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_4_0x8000137c0301143F; + + } + } + else if (port == 1 ) + { + + if ( rank_group == 0 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_0x800100090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_0x800104090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_0x800108090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_0x80010C090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_0x800110090301143F; + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_0_0x800100130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_1_0x800104130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_2_0x800108130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_3_0x80010C130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_4_0x800110130301143F; + DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_0_0x8001007c0301143F; + DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_1_0x8001047c0301143F; + DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_2_0x8001087c0301143F; + DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_3_0x80010c7c0301143F; + DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_4_0x8001107c0301143F; + + } + else if ( rank_group == 1 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_0x800101090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_0x800105090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_0x800109090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_0x80010D090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_0x800111090301143F; + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_0_0x800101130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_1_0x800105130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_2_0x800109130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_3_0x80010D130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_4_0x800111130301143F; + DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_0_0x8001017c0301143F; + DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_1_0x8001057c0301143F; + DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_2_0x8001097c0301143F; + DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_3_0x80010d7c0301143F; + DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_4_0x8001117c0301143F; + + } + else if ( rank_group == 2 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_0x800102090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_0x800106090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_0x80010A090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_0x80010E090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_0x800112090301143F; + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_0_0x800102130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_1_0x800106130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_2_0x80010A130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_3_0x80010E130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_4_0x800112130301143F; + DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_0_0x8001027c0301143F; + DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_1_0x8001067c0301143F; + DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_2_0x80010a7c0301143F; + DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_3_0x80010e7c0301143F; + DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_4_0x8001127c0301143F; + + } + else if ( rank_group == 3 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_0x800103090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_0x800107090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_0x80010B090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_0x80010F090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_0x800113090301143F; + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_0_0x800103130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_1_0x800107130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_2_0x80010B130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_3_0x80010F130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_4_0x800113130301143F; + DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_0_0x8001037c0301143F; + DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_1_0x8001077c0301143F; + DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_2_0x80010b7c0301143F; + DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_3_0x80010f7c0301143F; + DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_4_0x8001137c0301143F; + + } + } + + + // PHY BLOCK 0 + rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 50, 2); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 54, 2); + l_lowest_value_u8[rank_group][0][0][0] = l_value_n0_u8; + l_lowest_value_u8[rank_group][0][0][1] = l_value_n1_u8; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 58, 2); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 62, 2); + l_lowest_value_u8[rank_group][0][1][0] = l_value_n0_u8; + l_lowest_value_u8[rank_group][0][1][1] = l_value_n1_u8; + + rc = fapiGetScom(i_target, DISABLE_ADDR_0, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 4); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 4); + l_disable_value_u8[rank_group][0][0][0] = l_value_n0_u8; + l_disable_value_u8[rank_group][0][0][1] = l_value_n1_u8; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 4); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 4); + l_disable_value_u8[rank_group][0][1][0] = l_value_n0_u8; + l_disable_value_u8[rank_group][0][1][1] = l_value_n1_u8; + + rc = fapiGetScom(i_target, GATE_DELAY_ADDR_0, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3); + l_gate_delay_value_u8[rank_group][0][0][0] = l_value_n0_u8; + l_gate_delay_value_u8[rank_group][0][0][1] = l_value_n1_u8; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3); + l_gate_delay_value_u8[rank_group][0][1][0] = l_value_n0_u8; + l_gate_delay_value_u8[rank_group][0][1][1] = l_value_n1_u8; + + // PHY BLOCK 1 + rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 50, 2); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 54, 2); + l_lowest_value_u8[rank_group][1][0][0] = l_value_n0_u8; + l_lowest_value_u8[rank_group][1][0][1] = l_value_n1_u8; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 58, 2); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 62, 2); + l_lowest_value_u8[rank_group][1][1][0] = l_value_n0_u8; + l_lowest_value_u8[rank_group][1][1][1] = l_value_n1_u8; + + rc = fapiGetScom(i_target, DISABLE_ADDR_1, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 4); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 4); + l_disable_value_u8[rank_group][1][0][0] = l_value_n0_u8; + l_disable_value_u8[rank_group][1][0][1] = l_value_n1_u8; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 4); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 4); + l_disable_value_u8[rank_group][1][1][0] = l_value_n0_u8; + l_disable_value_u8[rank_group][1][1][1] = l_value_n1_u8; + + rc = fapiGetScom(i_target, GATE_DELAY_ADDR_1, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3); + l_gate_delay_value_u8[rank_group][1][0][0] = l_value_n0_u8; + l_gate_delay_value_u8[rank_group][1][0][1] = l_value_n1_u8; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3); + l_gate_delay_value_u8[rank_group][1][1][0] = l_value_n0_u8; + l_gate_delay_value_u8[rank_group][1][1][1] = l_value_n1_u8; + + // PHY BLOCK 2 + rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 50, 2); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 54, 2); + l_lowest_value_u8[rank_group][2][0][0] = l_value_n0_u8; + l_lowest_value_u8[rank_group][2][0][1] = l_value_n1_u8; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 58, 2); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 62, 2); + l_lowest_value_u8[rank_group][2][1][0] = l_value_n0_u8; + l_lowest_value_u8[rank_group][2][1][1] = l_value_n1_u8; + + rc = fapiGetScom(i_target, DISABLE_ADDR_2, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 4); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 4); + l_disable_value_u8[rank_group][2][0][0] = l_value_n0_u8; + l_disable_value_u8[rank_group][2][0][1] = l_value_n1_u8; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 4); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 4); + l_disable_value_u8[rank_group][2][1][0] = l_value_n0_u8; + l_disable_value_u8[rank_group][2][1][1] = l_value_n1_u8; + + rc = fapiGetScom(i_target, GATE_DELAY_ADDR_2, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3); + l_gate_delay_value_u8[rank_group][2][0][0] = l_value_n0_u8; + l_gate_delay_value_u8[rank_group][2][0][1] = l_value_n1_u8; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3); + l_gate_delay_value_u8[rank_group][2][1][0] = l_value_n0_u8; + l_gate_delay_value_u8[rank_group][2][1][1] = l_value_n1_u8; + + // PHY BLOCK 3 + rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 50, 2); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 54, 2); + l_lowest_value_u8[rank_group][3][0][0] = l_value_n0_u8; + l_lowest_value_u8[rank_group][3][0][1] = l_value_n1_u8; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 58, 2); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 62, 2); + l_lowest_value_u8[rank_group][3][1][0] = l_value_n0_u8; + l_lowest_value_u8[rank_group][3][1][1] = l_value_n1_u8; + + rc = fapiGetScom(i_target, DISABLE_ADDR_3, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 4); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 4); + l_disable_value_u8[rank_group][3][0][0] = l_value_n0_u8; + l_disable_value_u8[rank_group][3][0][1] = l_value_n1_u8; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 4); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 4); + l_disable_value_u8[rank_group][3][1][0] = l_value_n0_u8; + l_disable_value_u8[rank_group][3][1][1] = l_value_n1_u8; + + rc = fapiGetScom(i_target, GATE_DELAY_ADDR_3, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3); + l_gate_delay_value_u8[rank_group][3][0][0] = l_value_n0_u8; + l_gate_delay_value_u8[rank_group][3][0][1] = l_value_n1_u8; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3); + l_gate_delay_value_u8[rank_group][3][1][0] = l_value_n0_u8; + l_gate_delay_value_u8[rank_group][3][1][1] = l_value_n1_u8; + + // PHY BLOCK 4 + rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 50, 2); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 54, 2); + l_lowest_value_u8[rank_group][4][0][0] = l_value_n0_u8; + l_lowest_value_u8[rank_group][4][0][1] = l_value_n1_u8; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 58, 2); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 62, 2); + l_lowest_value_u8[rank_group][4][1][0] = l_value_n0_u8; + l_lowest_value_u8[rank_group][4][1][1] = l_value_n1_u8; + + rc = fapiGetScom(i_target, DISABLE_ADDR_4, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 4); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 4); + l_disable_value_u8[rank_group][4][0][0] = l_value_n0_u8; + l_disable_value_u8[rank_group][4][0][1] = l_value_n1_u8; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 4); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 4); + l_disable_value_u8[rank_group][4][1][0] = l_value_n0_u8; + l_disable_value_u8[rank_group][4][1][1] = l_value_n1_u8; + + rc = fapiGetScom(i_target, GATE_DELAY_ADDR_4, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3); + l_gate_delay_value_u8[rank_group][4][0][0] = l_value_n0_u8; + l_gate_delay_value_u8[rank_group][4][0][1] = l_value_n1_u8; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3); + l_gate_delay_value_u8[rank_group][4][1][0] = l_value_n0_u8; + l_gate_delay_value_u8[rank_group][4][1][1] = l_value_n1_u8; + + if(rc_num) + { + rc.setEcmdError(rc_num); + return rc; + } + + } + } + + + + + //Finding the lowest Values on disabled bytes, then resetting mask. + for(block = 0; block < maxblocks; block++) + { + for (byte = 0; byte < maxbytes; byte++) + { + + for (nibble = 0; nibble < maxnibbles; nibble++) + { + if ( (l_disable_value_u8[0][block][byte][nibble] != 0) || (l_disable_value_u8[1][block][byte][nibble] != 0) + || (l_disable_value_u8[2][block][byte][nibble] != 0) || (l_disable_value_u8[3][block][byte][nibble] != 0) ) + { + + FAPI_INF( "Located disabled block %d byte %d nibble %d", block, byte, nibble); + + l_min_gate_delay = 255; + for(rank_group = 0; rank_group < MAX_PRI_RANKS; rank_group++) + { + if ( (l_gate_delay_value_u8[rank_group][block][byte][nibble] < l_min_gate_delay) + && (l_disable_value_u8[rank_group][block][byte][nibble] == 0) ) + { + l_min_gate_delay = l_gate_delay_value_u8[rank_group][block][byte][nibble]; + } + } + + FAPI_INF( "Lowest gate_delay %d", l_min_gate_delay); + + l_min_dqs_clk = 255; + for(rank_group = 0; rank_group < MAX_PRI_RANKS; rank_group++) + { + if ( (l_lowest_value_u8[rank_group][block][byte][nibble] < l_min_dqs_clk) + && (l_disable_value_u8[rank_group][block][byte][nibble] == 0) ) + { + l_min_dqs_clk = l_lowest_value_u8[rank_group][block][byte][nibble]; + } + } + + + FAPI_INF( "Lowest rdclk phase %d", l_min_dqs_clk); + + for(rank_group = 0; rank_group < MAX_PRI_RANKS; rank_group++) + { + if (l_disable_value_u8[rank_group][block][byte][nibble] != 0) + { + l_gate_delay_value_u8[rank_group][block][byte][nibble] = l_min_gate_delay; + l_lowest_value_u8[rank_group][block][byte][nibble] = l_min_dqs_clk; + //l_disable_value_u8[rank_group][block][byte][nibble] = 0; + } + } + + } + } + } + + } + + + //Scoming in the New Values for(rank_group = 0; rank_group < MAX_PRI_RANKS; rank_group++) - { - - //Check if rank group exists - if(primary_ranks_array[rank_group][port] != 255) - { - - if ( port == 0 ) - { - - if ( rank_group == 0 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_0x800000090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_0x800004090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_0x800008090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_0x80000C090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_0x800010090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_0_0x800000130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_1_0x800004130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_2_0x800008130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_3_0x80000C130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_4_0x800010130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_0_0x8000007c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_1_0x8000047c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_2_0x8000087c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_3_0x80000c7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_4_0x8000107c0301143F; - - - } - else if ( rank_group == 1 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_0x800001090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_0x800005090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_0x800009090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_0x80000D090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_0x800011090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_0_0x800001130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_1_0x800005130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_2_0x800009130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_3_0x80000D130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_4_0x800011130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_0_0x8000017c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_1_0x8000057c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_2_0x8000097c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_3_0x80000d7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_4_0x8000117c0301143F; - - } - else if ( rank_group == 2 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_0x800002090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_0x800006090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_0x80000A090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_0x80000E090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_0x800012090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_0_0x800002130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_1_0x800006130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_2_0x80000A130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_3_0x80000E130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_4_0x800012130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_0_0x8000027c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_1_0x8000067c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_2_0x80000a7c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_3_0x80000e7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_4_0x8000127c0301143F; - - } - else if ( rank_group == 3 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_0x800003090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_0x800007090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_0x80000B090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_0x80000F090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_0x800013090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_0_0x800003130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_1_0x800007130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_2_0x80000B130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_3_0x80000F130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_4_0x800013130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_0_0x8000037c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_1_0x8000077c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_2_0x80000b7c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_3_0x80000f7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_4_0x8000137c0301143F; - - } - } - else if (port == 1 ) - { - - if ( rank_group == 0 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_0x800100090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_0x800104090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_0x800108090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_0x80010C090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_0x800110090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_0_0x800100130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_1_0x800104130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_2_0x800108130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_3_0x80010C130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_4_0x800110130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_0_0x8001007c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_1_0x8001047c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_2_0x8001087c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_3_0x80010c7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_4_0x8001107c0301143F; - - } - else if ( rank_group == 1 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_0x800101090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_0x800105090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_0x800109090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_0x80010D090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_0x800111090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_0_0x800101130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_1_0x800105130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_2_0x800109130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_3_0x80010D130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_4_0x800111130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_0_0x8001017c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_1_0x8001057c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_2_0x8001097c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_3_0x80010d7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_4_0x8001117c0301143F; - - } - else if ( rank_group == 2 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_0x800102090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_0x800106090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_0x80010A090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_0x80010E090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_0x800112090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_0_0x800102130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_1_0x800106130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_2_0x80010A130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_3_0x80010E130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_4_0x800112130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_0_0x8001027c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_1_0x8001067c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_2_0x80010a7c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_3_0x80010e7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_4_0x8001127c0301143F; - - } - else if ( rank_group == 3 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_0x800103090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_0x800107090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_0x80010B090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_0x80010F090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_0x800113090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_0_0x800103130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_1_0x800107130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_2_0x80010B130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_3_0x80010F130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_4_0x800113130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_0_0x8001037c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_1_0x8001077c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_2_0x80010b7c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_3_0x80010f7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_4_0x8001137c0301143F; - - } - } - - //BLOCK 0 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][0][0][0], 50, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][0][0][1], 54, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][0][1][0], 58, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][0][1][1], 62, 2); - rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64); - if (rc) return rc; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_0, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][0][0], 49, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][0][1], 53, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][1][0], 57, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][1][1], 61, 3); - rc = fapiPutScom(i_target, GATE_DELAY_ADDR_0, data_buffer_64); - if (rc) return rc; - - //BLOCK 1 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][1][0][0], 50, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][1][0][1], 54, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][1][1][0], 58, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][1][1][1], 62, 2); - rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64); - if (rc) return rc; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_1, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][0][0], 49, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][0][1], 53, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][1][0], 57, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][1][1], 61, 3); - rc = fapiPutScom(i_target, GATE_DELAY_ADDR_1, data_buffer_64); - if (rc) return rc; - - //BLOCK 2 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][2][0][0], 50, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][2][0][1], 54, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][2][1][0], 58, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][2][1][1], 62, 2); - rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64); - if (rc) return rc; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_2, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][0][0], 49, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][0][1], 53, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][1][0], 57, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][1][1], 61, 3); - rc = fapiPutScom(i_target, GATE_DELAY_ADDR_2, data_buffer_64); - if (rc) return rc; - - //BLOCK 3 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][3][0][0], 50, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][3][0][1], 54, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][3][1][0], 58, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][3][1][1], 62, 2); - rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64); - if (rc) return rc; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_3, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][0][0], 49, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][0][1], 53, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][1][0], 57, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][1][1], 61, 3); - rc = fapiPutScom(i_target, GATE_DELAY_ADDR_3, data_buffer_64); - if (rc) return rc; - - //Block 4 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][4][0][0], 50, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][4][0][1], 54, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][4][1][0], 58, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][4][1][1], 62, 2); - rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64); - if (rc) return rc; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_4, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][0][0], 49, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][0][1], 53, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][1][0], 57, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][1][1], 61, 3); - rc = fapiPutScom(i_target, GATE_DELAY_ADDR_4, data_buffer_64); - if (rc) return rc; - - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - - - } - } + { + + //Check if rank group exists + if(primary_ranks_array[rank_group][port] != 255) + { + + if ( port == 0 ) + { + + if ( rank_group == 0 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_0x800000090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_0x800004090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_0x800008090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_0x80000C090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_0x800010090301143F; + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_0_0x800000130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_1_0x800004130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_2_0x800008130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_3_0x80000C130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_4_0x800010130301143F; + DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_0_0x8000007c0301143F; + DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_1_0x8000047c0301143F; + DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_2_0x8000087c0301143F; + DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_3_0x80000c7c0301143F; + DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_4_0x8000107c0301143F; + + + } + else if ( rank_group == 1 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_0x800001090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_0x800005090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_0x800009090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_0x80000D090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_0x800011090301143F; + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_0_0x800001130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_1_0x800005130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_2_0x800009130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_3_0x80000D130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_4_0x800011130301143F; + DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_0_0x8000017c0301143F; + DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_1_0x8000057c0301143F; + DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_2_0x8000097c0301143F; + DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_3_0x80000d7c0301143F; + DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_4_0x8000117c0301143F; + + } + else if ( rank_group == 2 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_0x800002090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_0x800006090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_0x80000A090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_0x80000E090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_0x800012090301143F; + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_0_0x800002130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_1_0x800006130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_2_0x80000A130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_3_0x80000E130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_4_0x800012130301143F; + DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_0_0x8000027c0301143F; + DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_1_0x8000067c0301143F; + DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_2_0x80000a7c0301143F; + DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_3_0x80000e7c0301143F; + DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_4_0x8000127c0301143F; + + } + else if ( rank_group == 3 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_0x800003090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_0x800007090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_0x80000B090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_0x80000F090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_0x800013090301143F; + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_0_0x800003130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_1_0x800007130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_2_0x80000B130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_3_0x80000F130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_4_0x800013130301143F; + DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_0_0x8000037c0301143F; + DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_1_0x8000077c0301143F; + DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_2_0x80000b7c0301143F; + DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_3_0x80000f7c0301143F; + DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_4_0x8000137c0301143F; + + } + } + else if (port == 1 ) + { + + if ( rank_group == 0 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_0x800100090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_0x800104090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_0x800108090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_0x80010C090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_0x800110090301143F; + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_0_0x800100130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_1_0x800104130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_2_0x800108130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_3_0x80010C130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_4_0x800110130301143F; + DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_0_0x8001007c0301143F; + DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_1_0x8001047c0301143F; + DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_2_0x8001087c0301143F; + DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_3_0x80010c7c0301143F; + DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_4_0x8001107c0301143F; + + } + else if ( rank_group == 1 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_0x800101090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_0x800105090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_0x800109090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_0x80010D090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_0x800111090301143F; + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_0_0x800101130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_1_0x800105130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_2_0x800109130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_3_0x80010D130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_4_0x800111130301143F; + DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_0_0x8001017c0301143F; + DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_1_0x8001057c0301143F; + DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_2_0x8001097c0301143F; + DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_3_0x80010d7c0301143F; + DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_4_0x8001117c0301143F; + + } + else if ( rank_group == 2 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_0x800102090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_0x800106090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_0x80010A090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_0x80010E090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_0x800112090301143F; + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_0_0x800102130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_1_0x800106130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_2_0x80010A130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_3_0x80010E130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_4_0x800112130301143F; + DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_0_0x8001027c0301143F; + DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_1_0x8001067c0301143F; + DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_2_0x80010a7c0301143F; + DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_3_0x80010e7c0301143F; + DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_4_0x8001127c0301143F; + + } + else if ( rank_group == 3 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_0x800103090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_0x800107090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_0x80010B090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_0x80010F090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_0x800113090301143F; + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_0_0x800103130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_1_0x800107130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_2_0x80010B130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_3_0x80010F130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_4_0x800113130301143F; + DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_0_0x8001037c0301143F; + DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_1_0x8001077c0301143F; + DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_2_0x80010b7c0301143F; + DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_3_0x80010f7c0301143F; + DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_4_0x8001137c0301143F; + + } + } + + //BLOCK 0 + rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][0][0][0], 50, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][0][0][1], 54, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][0][1][0], 58, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][0][1][1], 62, 2); + rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64); + if (rc) return rc; + + rc = fapiGetScom(i_target, GATE_DELAY_ADDR_0, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][0][0], 49, 3); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][0][1], 53, 3); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][1][0], 57, 3); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][1][1], 61, 3); + rc = fapiPutScom(i_target, GATE_DELAY_ADDR_0, data_buffer_64); + if (rc) return rc; + + //BLOCK 1 + rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][1][0][0], 50, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][1][0][1], 54, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][1][1][0], 58, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][1][1][1], 62, 2); + rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64); + if (rc) return rc; + + rc = fapiGetScom(i_target, GATE_DELAY_ADDR_1, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][0][0], 49, 3); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][0][1], 53, 3); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][1][0], 57, 3); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][1][1], 61, 3); + rc = fapiPutScom(i_target, GATE_DELAY_ADDR_1, data_buffer_64); + if (rc) return rc; + + //BLOCK 2 + rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][2][0][0], 50, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][2][0][1], 54, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][2][1][0], 58, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][2][1][1], 62, 2); + rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64); + if (rc) return rc; + + rc = fapiGetScom(i_target, GATE_DELAY_ADDR_2, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][0][0], 49, 3); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][0][1], 53, 3); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][1][0], 57, 3); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][1][1], 61, 3); + rc = fapiPutScom(i_target, GATE_DELAY_ADDR_2, data_buffer_64); + if (rc) return rc; + + //BLOCK 3 + rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][3][0][0], 50, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][3][0][1], 54, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][3][1][0], 58, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][3][1][1], 62, 2); + rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64); + if (rc) return rc; + + rc = fapiGetScom(i_target, GATE_DELAY_ADDR_3, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][0][0], 49, 3); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][0][1], 53, 3); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][1][0], 57, 3); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][1][1], 61, 3); + rc = fapiPutScom(i_target, GATE_DELAY_ADDR_3, data_buffer_64); + if (rc) return rc; + + //Block 4 + rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][4][0][0], 50, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][4][0][1], 54, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][4][1][0], 58, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][4][1][1], 62, 2); + rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64); + if (rc) return rc; + + rc = fapiGetScom(i_target, GATE_DELAY_ADDR_4, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][0][0], 49, 3); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][0][1], 53, 3); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][1][0], 57, 3); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][1][1], 61, 3); + rc = fapiPutScom(i_target, GATE_DELAY_ADDR_4, data_buffer_64); + if (rc) return rc; + + if(rc_num) + { + rc.setEcmdError(rc_num); + return rc; + } + + + } + } } return rc; @@ -3397,1423 +3559,1423 @@ ReturnCode mss_wr_lvl_disable_workaround( for(port = 0; port < MAX_PORTS; port++) { - //Gather all the byte information + //Gather all the byte information for(rank_group = 0; rank_group < MAX_PRI_RANKS; rank_group++) - { - - //Initialize values - for(block = 0; block < maxblocks; block++) - { - for (byte = 0; byte < maxbytes; byte++) - { - for (nibble = 0; nibble < maxnibbles; nibble++) - { - l_dqsclk_phase_value_u8[rank_group][block][byte][nibble] = 255; - l_gate_delay_value_u8[rank_group][block][byte][nibble] = 255; - l_rdclk_phase_value_u8[rank_group][block][byte][nibble] = 255; - l_disable_value_u8[rank_group][block][byte][nibble] = 0; - l_disable_old_value_u8[rank_group][block][byte][nibble] = 0; - - } - } - } - - //Check if rank group exists - if(primary_ranks_array[rank_group][port] != 255) - { - FAPI_DBG("WR LVL DISABLE WORKAROUND: DISABLE Workaround being applied on %s PORT: %d RP: %d", i_target.toEcmdString(), port, rank_group); - - if ( port == 0 ) - { - - if ( rank_group == 0 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_0x800000090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_0x800004090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_0x800008090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_0x80000C090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_0x800010090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_0_0x800000130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_1_0x800004130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_2_0x800008130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_3_0x80000C130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_4_0x800010130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_0_0x8000007c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_1_0x8000047c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_2_0x8000087c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_3_0x80000c7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_4_0x8000107c0301143F; - - - } - else if ( rank_group == 1 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_0x800001090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_0x800005090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_0x800009090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_0x80000D090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_0x800011090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_0_0x800001130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_1_0x800005130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_2_0x800009130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_3_0x80000D130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_4_0x800011130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_0_0x8000017c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_1_0x8000057c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_2_0x8000097c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_3_0x80000d7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_4_0x8000117c0301143F; - - } - else if ( rank_group == 2 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_0x800002090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_0x800006090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_0x80000A090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_0x80000E090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_0x800012090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_0_0x800002130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_1_0x800006130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_2_0x80000A130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_3_0x80000E130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_4_0x800012130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_0_0x8000027c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_1_0x8000067c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_2_0x80000a7c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_3_0x80000e7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_4_0x8000127c0301143F; - - } - else if ( rank_group == 3 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_0x800003090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_0x800007090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_0x80000B090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_0x80000F090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_0x800013090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_0_0x800003130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_1_0x800007130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_2_0x80000B130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_3_0x80000F130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_4_0x800013130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_0_0x8000037c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_1_0x8000077c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_2_0x80000b7c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_3_0x80000f7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_4_0x8000137c0301143F; - - } - } - else if (port == 1 ) - { - - if ( rank_group == 0 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_0x800100090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_0x800104090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_0x800108090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_0x80010C090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_0x800110090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_0_0x800100130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_1_0x800104130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_2_0x800108130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_3_0x80010C130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_4_0x800110130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_0_0x8001007c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_1_0x8001047c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_2_0x8001087c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_3_0x80010c7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_4_0x8001107c0301143F; - - } - else if ( rank_group == 1 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_0x800101090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_0x800105090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_0x800109090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_0x80010D090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_0x800111090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_0_0x800101130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_1_0x800105130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_2_0x800109130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_3_0x80010D130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_4_0x800111130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_0_0x8001017c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_1_0x8001057c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_2_0x8001097c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_3_0x80010d7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_4_0x8001117c0301143F; - - } - else if ( rank_group == 2 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_0x800102090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_0x800106090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_0x80010A090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_0x80010E090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_0x800112090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_0_0x800102130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_1_0x800106130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_2_0x80010A130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_3_0x80010E130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_4_0x800112130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_0_0x8001027c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_1_0x8001067c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_2_0x80010a7c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_3_0x80010e7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_4_0x8001127c0301143F; - - } - else if ( rank_group == 3 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_0x800103090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_0x800107090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_0x80010B090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_0x80010F090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_0x800113090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_0_0x800103130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_1_0x800107130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_2_0x80010B130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_3_0x80010F130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_4_0x800113130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_0_0x8001037c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_1_0x8001077c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_2_0x80010b7c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_3_0x80010f7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_4_0x8001137c0301143F; - - } - } - - - // PHY BLOCK 0 - - rc = fapiGetScom(i_target, DISABLE_ADDR_0, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 4); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 4); - l_disable_value_u8[rank_group][0][0][0] = l_value_n0_u8; - l_disable_value_u8[rank_group][0][0][1] = l_value_n1_u8; - l_disable_old_value_u8[rank_group][0][0][0] = l_value_n0_u8; - l_disable_old_value_u8[rank_group][0][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 4); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 4); - l_disable_value_u8[rank_group][0][1][0] = l_value_n0_u8; - l_disable_value_u8[rank_group][0][1][1] = l_value_n1_u8; - l_disable_old_value_u8[rank_group][0][1][0] = l_value_n0_u8; - l_disable_old_value_u8[rank_group][0][1][1] = l_value_n1_u8; - - - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64); - if (rc) return rc; - // Grabbing 2 nibbles of the same byte and making them equal the same lowest value - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 2); - l_dqsclk_phase_value_u8[rank_group][0][0][0] = l_value_n0_u8; - l_dqsclk_phase_value_u8[rank_group][0][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 2); - l_dqsclk_phase_value_u8[rank_group][0][1][0] = l_value_n0_u8; - l_dqsclk_phase_value_u8[rank_group][0][1][1] = l_value_n1_u8; - - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 50, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 54, 2); - l_rdclk_phase_value_u8[rank_group][0][0][0] = l_value_n0_u8; - l_rdclk_phase_value_u8[rank_group][0][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 58, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 62, 2); - l_rdclk_phase_value_u8[rank_group][0][1][0] = l_value_n0_u8; - l_rdclk_phase_value_u8[rank_group][0][1][1] = l_value_n1_u8; - - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_0, data_buffer_64); - if (rc) return rc; - // Grabbing 2 nibbles of the same byte and making them equal the same lowest value - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3); - l_gate_delay_value_u8[rank_group][0][0][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][0][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3); - l_gate_delay_value_u8[rank_group][0][1][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][0][1][1] = l_value_n1_u8; - - - // PHY BLOCK 1 - - rc = fapiGetScom(i_target, DISABLE_ADDR_1, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 4); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 4); - l_disable_value_u8[rank_group][1][0][0] = l_value_n0_u8; - l_disable_value_u8[rank_group][1][0][1] = l_value_n1_u8; - l_disable_old_value_u8[rank_group][1][0][0] = l_value_n0_u8; - l_disable_old_value_u8[rank_group][1][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 4); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 4); - l_disable_value_u8[rank_group][1][1][0] = l_value_n0_u8; - l_disable_value_u8[rank_group][1][1][1] = l_value_n1_u8; - l_disable_old_value_u8[rank_group][1][1][0] = l_value_n0_u8; - l_disable_old_value_u8[rank_group][1][1][1] = l_value_n1_u8; - - - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64); - if (rc) return rc; - // Grabbing 2 nibbles of the same byte and making them equal the same lowest value - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 2); - l_dqsclk_phase_value_u8[rank_group][1][0][0] = l_value_n0_u8; - l_dqsclk_phase_value_u8[rank_group][1][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 2); - l_dqsclk_phase_value_u8[rank_group][1][1][0] = l_value_n0_u8; - l_dqsclk_phase_value_u8[rank_group][1][1][1] = l_value_n1_u8; - - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 50, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 54, 2); - l_rdclk_phase_value_u8[rank_group][1][0][0] = l_value_n0_u8; - l_rdclk_phase_value_u8[rank_group][1][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 58, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 62, 2); - l_rdclk_phase_value_u8[rank_group][1][1][0] = l_value_n0_u8; - l_rdclk_phase_value_u8[rank_group][1][1][1] = l_value_n1_u8; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_1, data_buffer_64); - if (rc) return rc; - // Grabbing 2 nibbles of the same byte and making them equal the same lowest value - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3); - l_gate_delay_value_u8[rank_group][1][0][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][1][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3); - l_gate_delay_value_u8[rank_group][1][1][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][1][1][1] = l_value_n1_u8; - - // PHY BLOCK 2 - - rc = fapiGetScom(i_target, DISABLE_ADDR_2, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 4); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 4); - l_disable_value_u8[rank_group][2][0][0] = l_value_n0_u8; - l_disable_value_u8[rank_group][2][0][1] = l_value_n1_u8; - l_disable_old_value_u8[rank_group][2][0][0] = l_value_n0_u8; - l_disable_old_value_u8[rank_group][2][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 4); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 4); - l_disable_value_u8[rank_group][2][1][0] = l_value_n0_u8; - l_disable_value_u8[rank_group][2][1][1] = l_value_n1_u8; - l_disable_old_value_u8[rank_group][2][1][0] = l_value_n0_u8; - l_disable_old_value_u8[rank_group][2][1][1] = l_value_n1_u8; - - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64); - if (rc) return rc; - // Grabbing 2 nibbles of the same byte and making them equal the same lowest value - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 2); - l_dqsclk_phase_value_u8[rank_group][2][0][0] = l_value_n0_u8; - l_dqsclk_phase_value_u8[rank_group][2][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 2); - l_dqsclk_phase_value_u8[rank_group][2][1][0] = l_value_n0_u8; - l_dqsclk_phase_value_u8[rank_group][2][1][1] = l_value_n1_u8; - - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 50, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 54, 2); - l_rdclk_phase_value_u8[rank_group][2][0][0] = l_value_n0_u8; - l_rdclk_phase_value_u8[rank_group][2][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 58, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 62, 2); - l_rdclk_phase_value_u8[rank_group][2][1][0] = l_value_n0_u8; - l_rdclk_phase_value_u8[rank_group][2][1][1] = l_value_n1_u8; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_2, data_buffer_64); - if (rc) return rc; - // Grabbing 2 nibbles of the same byte and making them equal the same lowest value - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3); - l_gate_delay_value_u8[rank_group][2][0][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][2][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3); - l_gate_delay_value_u8[rank_group][2][1][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][2][1][1] = l_value_n1_u8; - - // PHY BLOCK 3 - - rc = fapiGetScom(i_target, DISABLE_ADDR_3, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 4); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 4); - l_disable_value_u8[rank_group][3][0][0] = l_value_n0_u8; - l_disable_value_u8[rank_group][3][0][1] = l_value_n1_u8; - l_disable_old_value_u8[rank_group][3][0][0] = l_value_n0_u8; - l_disable_old_value_u8[rank_group][3][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 4); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 4); - l_disable_value_u8[rank_group][3][1][0] = l_value_n0_u8; - l_disable_value_u8[rank_group][3][1][1] = l_value_n1_u8; - l_disable_old_value_u8[rank_group][3][1][0] = l_value_n0_u8; - l_disable_old_value_u8[rank_group][3][1][1] = l_value_n1_u8; - - - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64); - if (rc) return rc; - // Grabbing 2 nibbles of the same byte and making them equal the same lowest value - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 2); - l_dqsclk_phase_value_u8[rank_group][3][0][0] = l_value_n0_u8; - l_dqsclk_phase_value_u8[rank_group][3][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 2); - l_dqsclk_phase_value_u8[rank_group][3][1][0] = l_value_n0_u8; - l_dqsclk_phase_value_u8[rank_group][3][1][1] = l_value_n1_u8; - - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 50, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 54, 2); - l_rdclk_phase_value_u8[rank_group][3][0][0] = l_value_n0_u8; - l_rdclk_phase_value_u8[rank_group][3][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 58, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 62, 2); - l_rdclk_phase_value_u8[rank_group][3][1][0] = l_value_n0_u8; - l_rdclk_phase_value_u8[rank_group][3][1][1] = l_value_n1_u8; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_3, data_buffer_64); - if (rc) return rc; - // Grabbing 2 nibbles of the same byte and making them equal the same lowest value - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3); - l_gate_delay_value_u8[rank_group][3][0][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][3][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3); - l_gate_delay_value_u8[rank_group][3][1][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][3][1][1] = l_value_n1_u8; - - // PHY BLOCK 4 - - rc = fapiGetScom(i_target, DISABLE_ADDR_4, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 4); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 4); - l_disable_value_u8[rank_group][4][0][0] = l_value_n0_u8; - l_disable_value_u8[rank_group][4][0][1] = l_value_n1_u8; - l_disable_old_value_u8[rank_group][4][0][0] = l_value_n0_u8; - l_disable_old_value_u8[rank_group][4][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 4); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 4); - l_disable_value_u8[rank_group][4][1][0] = l_value_n0_u8; - l_disable_value_u8[rank_group][4][1][1] = l_value_n1_u8; - l_disable_old_value_u8[rank_group][4][1][0] = l_value_n0_u8; - l_disable_old_value_u8[rank_group][4][1][1] = l_value_n1_u8; - - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64); - if (rc) return rc; - // Grabbing 2 nibbles of the same byte and making them equal the same lowest value - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 2); - l_dqsclk_phase_value_u8[rank_group][4][0][0] = l_value_n0_u8; - l_dqsclk_phase_value_u8[rank_group][4][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 2); - l_dqsclk_phase_value_u8[rank_group][4][1][0] = l_value_n0_u8; - l_dqsclk_phase_value_u8[rank_group][4][1][1] = l_value_n1_u8; - - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 50, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 54, 2); - l_rdclk_phase_value_u8[rank_group][4][0][0] = l_value_n0_u8; - l_rdclk_phase_value_u8[rank_group][4][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 58, 2); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 62, 2); - l_rdclk_phase_value_u8[rank_group][4][1][0] = l_value_n0_u8; - l_rdclk_phase_value_u8[rank_group][4][1][1] = l_value_n1_u8; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_4, data_buffer_64); - if (rc) return rc; - // Grabbing 2 nibbles of the same byte and making them equal the same lowest value - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3); - l_gate_delay_value_u8[rank_group][4][0][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][4][0][1] = l_value_n1_u8; - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3); - rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3); - l_gate_delay_value_u8[rank_group][4][1][0] = l_value_n0_u8; - l_gate_delay_value_u8[rank_group][4][1][1] = l_value_n1_u8; - - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - - } - } - - uint8_t ranks_array[4][4][2]; //[group][rank_group position][port] + { + + //Initialize values + for(block = 0; block < maxblocks; block++) + { + for (byte = 0; byte < maxbytes; byte++) + { + for (nibble = 0; nibble < maxnibbles; nibble++) + { + l_dqsclk_phase_value_u8[rank_group][block][byte][nibble] = 255; + l_gate_delay_value_u8[rank_group][block][byte][nibble] = 255; + l_rdclk_phase_value_u8[rank_group][block][byte][nibble] = 255; + l_disable_value_u8[rank_group][block][byte][nibble] = 0; + l_disable_old_value_u8[rank_group][block][byte][nibble] = 0; + + } + } + } + + //Check if rank group exists + if(primary_ranks_array[rank_group][port] != 255) + { + FAPI_DBG("WR LVL DISABLE WORKAROUND: DISABLE Workaround being applied on %s PORT: %d RP: %d", i_target.toEcmdString(), port, rank_group); + + if ( port == 0 ) + { + + if ( rank_group == 0 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_0x800000090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_0x800004090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_0x800008090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_0x80000C090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_0x800010090301143F; + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_0_0x800000130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_1_0x800004130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_2_0x800008130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_3_0x80000C130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_4_0x800010130301143F; + DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_0_0x8000007c0301143F; + DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_1_0x8000047c0301143F; + DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_2_0x8000087c0301143F; + DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_3_0x80000c7c0301143F; + DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_4_0x8000107c0301143F; + + + } + else if ( rank_group == 1 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_0x800001090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_0x800005090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_0x800009090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_0x80000D090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_0x800011090301143F; + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_0_0x800001130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_1_0x800005130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_2_0x800009130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_3_0x80000D130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_4_0x800011130301143F; + DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_0_0x8000017c0301143F; + DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_1_0x8000057c0301143F; + DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_2_0x8000097c0301143F; + DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_3_0x80000d7c0301143F; + DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_4_0x8000117c0301143F; + + } + else if ( rank_group == 2 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_0x800002090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_0x800006090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_0x80000A090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_0x80000E090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_0x800012090301143F; + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_0_0x800002130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_1_0x800006130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_2_0x80000A130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_3_0x80000E130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_4_0x800012130301143F; + DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_0_0x8000027c0301143F; + DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_1_0x8000067c0301143F; + DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_2_0x80000a7c0301143F; + DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_3_0x80000e7c0301143F; + DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_4_0x8000127c0301143F; + + } + else if ( rank_group == 3 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_0x800003090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_0x800007090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_0x80000B090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_0x80000F090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_0x800013090301143F; + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_0_0x800003130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_1_0x800007130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_2_0x80000B130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_3_0x80000F130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_4_0x800013130301143F; + DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_0_0x8000037c0301143F; + DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_1_0x8000077c0301143F; + DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_2_0x80000b7c0301143F; + DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_3_0x80000f7c0301143F; + DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_4_0x8000137c0301143F; + + } + } + else if (port == 1 ) + { + + if ( rank_group == 0 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_0x800100090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_0x800104090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_0x800108090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_0x80010C090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_0x800110090301143F; + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_0_0x800100130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_1_0x800104130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_2_0x800108130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_3_0x80010C130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_4_0x800110130301143F; + DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_0_0x8001007c0301143F; + DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_1_0x8001047c0301143F; + DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_2_0x8001087c0301143F; + DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_3_0x80010c7c0301143F; + DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_4_0x8001107c0301143F; + + } + else if ( rank_group == 1 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_0x800101090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_0x800105090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_0x800109090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_0x80010D090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_0x800111090301143F; + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_0_0x800101130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_1_0x800105130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_2_0x800109130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_3_0x80010D130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_4_0x800111130301143F; + DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_0_0x8001017c0301143F; + DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_1_0x8001057c0301143F; + DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_2_0x8001097c0301143F; + DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_3_0x80010d7c0301143F; + DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_4_0x8001117c0301143F; + + } + else if ( rank_group == 2 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_0x800102090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_0x800106090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_0x80010A090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_0x80010E090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_0x800112090301143F; + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_0_0x800102130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_1_0x800106130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_2_0x80010A130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_3_0x80010E130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_4_0x800112130301143F; + DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_0_0x8001027c0301143F; + DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_1_0x8001067c0301143F; + DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_2_0x80010a7c0301143F; + DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_3_0x80010e7c0301143F; + DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_4_0x8001127c0301143F; + + } + else if ( rank_group == 3 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_0x800103090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_0x800107090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_0x80010B090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_0x80010F090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_0x800113090301143F; + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_0_0x800103130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_1_0x800107130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_2_0x80010B130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_3_0x80010F130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_4_0x800113130301143F; + DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_0_0x8001037c0301143F; + DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_1_0x8001077c0301143F; + DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_2_0x80010b7c0301143F; + DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_3_0x80010f7c0301143F; + DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_4_0x8001137c0301143F; + + } + } + + + // PHY BLOCK 0 + + rc = fapiGetScom(i_target, DISABLE_ADDR_0, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 4); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 4); + l_disable_value_u8[rank_group][0][0][0] = l_value_n0_u8; + l_disable_value_u8[rank_group][0][0][1] = l_value_n1_u8; + l_disable_old_value_u8[rank_group][0][0][0] = l_value_n0_u8; + l_disable_old_value_u8[rank_group][0][0][1] = l_value_n1_u8; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 4); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 4); + l_disable_value_u8[rank_group][0][1][0] = l_value_n0_u8; + l_disable_value_u8[rank_group][0][1][1] = l_value_n1_u8; + l_disable_old_value_u8[rank_group][0][1][0] = l_value_n0_u8; + l_disable_old_value_u8[rank_group][0][1][1] = l_value_n1_u8; + + + rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64); + if (rc) return rc; + // Grabbing 2 nibbles of the same byte and making them equal the same lowest value + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 2); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 2); + l_dqsclk_phase_value_u8[rank_group][0][0][0] = l_value_n0_u8; + l_dqsclk_phase_value_u8[rank_group][0][0][1] = l_value_n1_u8; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 2); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 2); + l_dqsclk_phase_value_u8[rank_group][0][1][0] = l_value_n0_u8; + l_dqsclk_phase_value_u8[rank_group][0][1][1] = l_value_n1_u8; + + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 50, 2); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 54, 2); + l_rdclk_phase_value_u8[rank_group][0][0][0] = l_value_n0_u8; + l_rdclk_phase_value_u8[rank_group][0][0][1] = l_value_n1_u8; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 58, 2); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 62, 2); + l_rdclk_phase_value_u8[rank_group][0][1][0] = l_value_n0_u8; + l_rdclk_phase_value_u8[rank_group][0][1][1] = l_value_n1_u8; + + + rc = fapiGetScom(i_target, GATE_DELAY_ADDR_0, data_buffer_64); + if (rc) return rc; + // Grabbing 2 nibbles of the same byte and making them equal the same lowest value + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3); + l_gate_delay_value_u8[rank_group][0][0][0] = l_value_n0_u8; + l_gate_delay_value_u8[rank_group][0][0][1] = l_value_n1_u8; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3); + l_gate_delay_value_u8[rank_group][0][1][0] = l_value_n0_u8; + l_gate_delay_value_u8[rank_group][0][1][1] = l_value_n1_u8; + + + // PHY BLOCK 1 + + rc = fapiGetScom(i_target, DISABLE_ADDR_1, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 4); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 4); + l_disable_value_u8[rank_group][1][0][0] = l_value_n0_u8; + l_disable_value_u8[rank_group][1][0][1] = l_value_n1_u8; + l_disable_old_value_u8[rank_group][1][0][0] = l_value_n0_u8; + l_disable_old_value_u8[rank_group][1][0][1] = l_value_n1_u8; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 4); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 4); + l_disable_value_u8[rank_group][1][1][0] = l_value_n0_u8; + l_disable_value_u8[rank_group][1][1][1] = l_value_n1_u8; + l_disable_old_value_u8[rank_group][1][1][0] = l_value_n0_u8; + l_disable_old_value_u8[rank_group][1][1][1] = l_value_n1_u8; + + + rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64); + if (rc) return rc; + // Grabbing 2 nibbles of the same byte and making them equal the same lowest value + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 2); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 2); + l_dqsclk_phase_value_u8[rank_group][1][0][0] = l_value_n0_u8; + l_dqsclk_phase_value_u8[rank_group][1][0][1] = l_value_n1_u8; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 2); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 2); + l_dqsclk_phase_value_u8[rank_group][1][1][0] = l_value_n0_u8; + l_dqsclk_phase_value_u8[rank_group][1][1][1] = l_value_n1_u8; + + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 50, 2); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 54, 2); + l_rdclk_phase_value_u8[rank_group][1][0][0] = l_value_n0_u8; + l_rdclk_phase_value_u8[rank_group][1][0][1] = l_value_n1_u8; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 58, 2); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 62, 2); + l_rdclk_phase_value_u8[rank_group][1][1][0] = l_value_n0_u8; + l_rdclk_phase_value_u8[rank_group][1][1][1] = l_value_n1_u8; + + rc = fapiGetScom(i_target, GATE_DELAY_ADDR_1, data_buffer_64); + if (rc) return rc; + // Grabbing 2 nibbles of the same byte and making them equal the same lowest value + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3); + l_gate_delay_value_u8[rank_group][1][0][0] = l_value_n0_u8; + l_gate_delay_value_u8[rank_group][1][0][1] = l_value_n1_u8; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3); + l_gate_delay_value_u8[rank_group][1][1][0] = l_value_n0_u8; + l_gate_delay_value_u8[rank_group][1][1][1] = l_value_n1_u8; + + // PHY BLOCK 2 + + rc = fapiGetScom(i_target, DISABLE_ADDR_2, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 4); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 4); + l_disable_value_u8[rank_group][2][0][0] = l_value_n0_u8; + l_disable_value_u8[rank_group][2][0][1] = l_value_n1_u8; + l_disable_old_value_u8[rank_group][2][0][0] = l_value_n0_u8; + l_disable_old_value_u8[rank_group][2][0][1] = l_value_n1_u8; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 4); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 4); + l_disable_value_u8[rank_group][2][1][0] = l_value_n0_u8; + l_disable_value_u8[rank_group][2][1][1] = l_value_n1_u8; + l_disable_old_value_u8[rank_group][2][1][0] = l_value_n0_u8; + l_disable_old_value_u8[rank_group][2][1][1] = l_value_n1_u8; + + rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64); + if (rc) return rc; + // Grabbing 2 nibbles of the same byte and making them equal the same lowest value + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 2); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 2); + l_dqsclk_phase_value_u8[rank_group][2][0][0] = l_value_n0_u8; + l_dqsclk_phase_value_u8[rank_group][2][0][1] = l_value_n1_u8; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 2); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 2); + l_dqsclk_phase_value_u8[rank_group][2][1][0] = l_value_n0_u8; + l_dqsclk_phase_value_u8[rank_group][2][1][1] = l_value_n1_u8; + + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 50, 2); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 54, 2); + l_rdclk_phase_value_u8[rank_group][2][0][0] = l_value_n0_u8; + l_rdclk_phase_value_u8[rank_group][2][0][1] = l_value_n1_u8; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 58, 2); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 62, 2); + l_rdclk_phase_value_u8[rank_group][2][1][0] = l_value_n0_u8; + l_rdclk_phase_value_u8[rank_group][2][1][1] = l_value_n1_u8; + + rc = fapiGetScom(i_target, GATE_DELAY_ADDR_2, data_buffer_64); + if (rc) return rc; + // Grabbing 2 nibbles of the same byte and making them equal the same lowest value + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3); + l_gate_delay_value_u8[rank_group][2][0][0] = l_value_n0_u8; + l_gate_delay_value_u8[rank_group][2][0][1] = l_value_n1_u8; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3); + l_gate_delay_value_u8[rank_group][2][1][0] = l_value_n0_u8; + l_gate_delay_value_u8[rank_group][2][1][1] = l_value_n1_u8; + + // PHY BLOCK 3 + + rc = fapiGetScom(i_target, DISABLE_ADDR_3, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 4); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 4); + l_disable_value_u8[rank_group][3][0][0] = l_value_n0_u8; + l_disable_value_u8[rank_group][3][0][1] = l_value_n1_u8; + l_disable_old_value_u8[rank_group][3][0][0] = l_value_n0_u8; + l_disable_old_value_u8[rank_group][3][0][1] = l_value_n1_u8; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 4); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 4); + l_disable_value_u8[rank_group][3][1][0] = l_value_n0_u8; + l_disable_value_u8[rank_group][3][1][1] = l_value_n1_u8; + l_disable_old_value_u8[rank_group][3][1][0] = l_value_n0_u8; + l_disable_old_value_u8[rank_group][3][1][1] = l_value_n1_u8; + + + rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64); + if (rc) return rc; + // Grabbing 2 nibbles of the same byte and making them equal the same lowest value + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 2); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 2); + l_dqsclk_phase_value_u8[rank_group][3][0][0] = l_value_n0_u8; + l_dqsclk_phase_value_u8[rank_group][3][0][1] = l_value_n1_u8; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 2); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 2); + l_dqsclk_phase_value_u8[rank_group][3][1][0] = l_value_n0_u8; + l_dqsclk_phase_value_u8[rank_group][3][1][1] = l_value_n1_u8; + + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 50, 2); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 54, 2); + l_rdclk_phase_value_u8[rank_group][3][0][0] = l_value_n0_u8; + l_rdclk_phase_value_u8[rank_group][3][0][1] = l_value_n1_u8; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 58, 2); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 62, 2); + l_rdclk_phase_value_u8[rank_group][3][1][0] = l_value_n0_u8; + l_rdclk_phase_value_u8[rank_group][3][1][1] = l_value_n1_u8; + + rc = fapiGetScom(i_target, GATE_DELAY_ADDR_3, data_buffer_64); + if (rc) return rc; + // Grabbing 2 nibbles of the same byte and making them equal the same lowest value + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3); + l_gate_delay_value_u8[rank_group][3][0][0] = l_value_n0_u8; + l_gate_delay_value_u8[rank_group][3][0][1] = l_value_n1_u8; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3); + l_gate_delay_value_u8[rank_group][3][1][0] = l_value_n0_u8; + l_gate_delay_value_u8[rank_group][3][1][1] = l_value_n1_u8; + + // PHY BLOCK 4 + + rc = fapiGetScom(i_target, DISABLE_ADDR_4, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 4); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 4); + l_disable_value_u8[rank_group][4][0][0] = l_value_n0_u8; + l_disable_value_u8[rank_group][4][0][1] = l_value_n1_u8; + l_disable_old_value_u8[rank_group][4][0][0] = l_value_n0_u8; + l_disable_old_value_u8[rank_group][4][0][1] = l_value_n1_u8; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 4); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 4); + l_disable_value_u8[rank_group][4][1][0] = l_value_n0_u8; + l_disable_value_u8[rank_group][4][1][1] = l_value_n1_u8; + l_disable_old_value_u8[rank_group][4][1][0] = l_value_n0_u8; + l_disable_old_value_u8[rank_group][4][1][1] = l_value_n1_u8; + + rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64); + if (rc) return rc; + // Grabbing 2 nibbles of the same byte and making them equal the same lowest value + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 2); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 2); + l_dqsclk_phase_value_u8[rank_group][4][0][0] = l_value_n0_u8; + l_dqsclk_phase_value_u8[rank_group][4][0][1] = l_value_n1_u8; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 2); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 2); + l_dqsclk_phase_value_u8[rank_group][4][1][0] = l_value_n0_u8; + l_dqsclk_phase_value_u8[rank_group][4][1][1] = l_value_n1_u8; + + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 50, 2); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 54, 2); + l_rdclk_phase_value_u8[rank_group][4][0][0] = l_value_n0_u8; + l_rdclk_phase_value_u8[rank_group][4][0][1] = l_value_n1_u8; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 58, 2); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 62, 2); + l_rdclk_phase_value_u8[rank_group][4][1][0] = l_value_n0_u8; + l_rdclk_phase_value_u8[rank_group][4][1][1] = l_value_n1_u8; + + rc = fapiGetScom(i_target, GATE_DELAY_ADDR_4, data_buffer_64); + if (rc) return rc; + // Grabbing 2 nibbles of the same byte and making them equal the same lowest value + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3); + l_gate_delay_value_u8[rank_group][4][0][0] = l_value_n0_u8; + l_gate_delay_value_u8[rank_group][4][0][1] = l_value_n1_u8; + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3); + rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3); + l_gate_delay_value_u8[rank_group][4][1][0] = l_value_n0_u8; + l_gate_delay_value_u8[rank_group][4][1][1] = l_value_n1_u8; + + if(rc_num) + { + rc.setEcmdError(rc_num); + return rc; + } + + } + } + + uint8_t ranks_array[4][4][2]; //[group][rank_group position][port] // Determine rank and rank group matching rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP0, &i_target, ranks_array[0][0]); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP1, &i_target, ranks_array[1][0]); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP2, &i_target, ranks_array[2][0]); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP3, &i_target, ranks_array[3][0]); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_SECONDARY_RANK_GROUP0, &i_target, ranks_array[0][1]); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_SECONDARY_RANK_GROUP1, &i_target, ranks_array[1][1]); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_SECONDARY_RANK_GROUP2, &i_target, ranks_array[2][1]); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_SECONDARY_RANK_GROUP3, &i_target, ranks_array[3][1]); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_TERTIARY_RANK_GROUP0, &i_target, ranks_array[0][2]); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_TERTIARY_RANK_GROUP1, &i_target, ranks_array[1][2]); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_TERTIARY_RANK_GROUP2, &i_target, ranks_array[2][2]); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_TERTIARY_RANK_GROUP3, &i_target, ranks_array[3][2]); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_QUATERNARY_RANK_GROUP0, &i_target, ranks_array[0][3]); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_QUATERNARY_RANK_GROUP1, &i_target, ranks_array[1][3]); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_QUATERNARY_RANK_GROUP2, &i_target, ranks_array[2][3]); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_QUATERNARY_RANK_GROUP3, &i_target, ranks_array[3][3]); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP1, &i_target, ranks_array[1][0]); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP2, &i_target, ranks_array[2][0]); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP3, &i_target, ranks_array[3][0]); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_EFF_SECONDARY_RANK_GROUP0, &i_target, ranks_array[0][1]); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_EFF_SECONDARY_RANK_GROUP1, &i_target, ranks_array[1][1]); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_EFF_SECONDARY_RANK_GROUP2, &i_target, ranks_array[2][1]); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_EFF_SECONDARY_RANK_GROUP3, &i_target, ranks_array[3][1]); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_EFF_TERTIARY_RANK_GROUP0, &i_target, ranks_array[0][2]); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_EFF_TERTIARY_RANK_GROUP1, &i_target, ranks_array[1][2]); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_EFF_TERTIARY_RANK_GROUP2, &i_target, ranks_array[2][2]); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_EFF_TERTIARY_RANK_GROUP3, &i_target, ranks_array[3][2]); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_EFF_QUATERNARY_RANK_GROUP0, &i_target, ranks_array[0][3]); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_EFF_QUATERNARY_RANK_GROUP1, &i_target, ranks_array[1][3]); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_EFF_QUATERNARY_RANK_GROUP2, &i_target, ranks_array[2][3]); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_EFF_QUATERNARY_RANK_GROUP3, &i_target, ranks_array[3][3]); if(rc) return rc; access_type_t l_access_type_e = READ; - //READ - //WRITE + //READ + //WRITE input_type_t l_input_type_e = WR_DQS; //WR_DQ_t, //RAW_WR_DQ, //WR_DQS_t, //RAW_WR_DQS, - uint8_t l_flag = 0; - uint8_t l_verbose = 0; - uint8_t l_rank_u8; - uint32_t l_old_delay_value_u32 = 0; - uint32_t l_old_DQS_delay_value_u32 = 0; - uint32_t l_delay_value_u32 = 0; - uint32_t l_DQS_delay_value_u32 = 0; - uint8_t l_index_u8 = 0; - uint8_t mask; - uint8_t nibble_dq; + uint8_t l_flag = 0; + uint8_t l_verbose = 0; + uint8_t l_rank_u8; + uint32_t l_old_delay_value_u32 = 0; + uint32_t l_old_DQS_delay_value_u32 = 0; + uint32_t l_delay_value_u32 = 0; + uint32_t l_DQS_delay_value_u32 = 0; + uint8_t l_index_u8 = 0; + uint8_t mask; + uint8_t nibble_dq; uint8_t lane; - uint8_t rg; + uint8_t rg; uint8_t rank_2; - uint8_t width; - uint8_t dqs_index; - - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target, width); - - uint32_t instruction_number = 0; - ecmdDataBufferBase address_buffer_16(16); - rc_num = rc_num | address_buffer_16.flushTo0(); - ecmdDataBufferBase bank_buffer_8(8); - rc_num = rc_num | bank_buffer_8.flushTo0(); - ecmdDataBufferBase activate_buffer_1(1); - rc_num = rc_num | activate_buffer_1.flushTo0(); - ecmdDataBufferBase rasn_buffer_1(1); - ecmdDataBufferBase casn_buffer_1(1); - ecmdDataBufferBase wen_buffer_1(1); - ecmdDataBufferBase cke_buffer_8(8); - rc_num = rc_num | cke_buffer_8.flushTo1(); - ecmdDataBufferBase csn_buffer_8(8); - rc_num = rc_num | csn_buffer_8.flushTo1(); - ecmdDataBufferBase odt_buffer_8(8); - rc_num = rc_num | odt_buffer_8.flushTo0(); - ecmdDataBufferBase test_buffer_4(4); - rc_num = rc_num | test_buffer_4.setBit(0,4); - - ecmdDataBufferBase num_idles_buffer_16(16); - rc_num = rc_num | num_idles_buffer_16.flushTo1(); - ecmdDataBufferBase num_repeat_buffer_16(16); - rc_num = rc_num | num_repeat_buffer_16.flushTo0(); - ecmdDataBufferBase data_buffer_20(20); - rc_num = rc_num | data_buffer_20.flushTo0(); - ecmdDataBufferBase read_compare_buffer_1(1); - rc_num = rc_num | read_compare_buffer_1.flushTo0(); - ecmdDataBufferBase rank_cal_buffer_4(4); - rc_num = rc_num | rank_cal_buffer_4.flushTo0(); - ecmdDataBufferBase ddr_cal_enable_buffer_1(1); - rc_num = rc_num | ddr_cal_enable_buffer_1.flushTo1(); - ecmdDataBufferBase ccs_end_buffer_1(1); - rc_num = rc_num | ccs_end_buffer_1.flushTo1(); - uint8_t group = 255; - const uint32_t NUM_POLL = 10000; - - - uint8_t cur_cal_step = 2; - enum mss_draminit_training_result cur_error_status = MSS_INIT_CAL_PASS; - uint8_t mbaPosition; - // Get MBA position: 0 = mba01, 1 = mba23 - rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target, mbaPosition); - if(rc) - { - FAPI_ERR("Error getting MBA position"); - return rc; - } - - - - //Resetting Disable mask. Avoid spares. - for(block = 0; block < maxblocks; block++) - { - for (byte = 0; byte < 2; byte++) - { - - for (nibble = 0; nibble < maxnibbles; nibble++) - { - - for(rank_group = 0; rank_group < MAX_PRI_RANKS; rank_group++) - { - - //Check if rank group exists - if(primary_ranks_array[rank_group][port] != 255) - { - - - if ( port == 0 ) - { - - if ( rank_group == 0 ) - { - - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_0_0x8000007c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_1_0x8000047c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_2_0x8000087c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_3_0x80000c7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_4_0x8000107c0301143F; - - } - else if ( rank_group == 1 ) - { - - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_0_0x8000017c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_1_0x8000057c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_2_0x8000097c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_3_0x80000d7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_4_0x8000117c0301143F; - - } - else if ( rank_group == 2 ) - { - - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_0_0x8000027c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_1_0x8000067c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_2_0x80000a7c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_3_0x80000e7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_4_0x8000127c0301143F; - - } - else if ( rank_group == 3 ) - { - - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_0_0x8000037c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_1_0x8000077c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_2_0x80000b7c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_3_0x80000f7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_4_0x8000137c0301143F; - - } - } - else if (port == 1 ) - { - - if ( rank_group == 0 ) - { - - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_0_0x8001007c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_1_0x8001047c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_2_0x8001087c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_3_0x80010c7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_4_0x8001107c0301143F; - - } - else if ( rank_group == 1 ) - { - - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_0_0x8001017c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_1_0x8001057c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_2_0x8001097c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_3_0x80010d7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_4_0x8001117c0301143F; - - - } - else if ( rank_group == 2 ) - { - - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_0_0x8001027c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_1_0x8001067c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_2_0x80010a7c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_3_0x80010e7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_4_0x8001127c0301143F; - - - } - else if ( rank_group == 3 ) - { - - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_0_0x8001037c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_1_0x8001077c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_2_0x80010b7c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_3_0x80010f7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_4_0x8001137c0301143F; - - } - } - - lane = byte * 8 + nibble*4; - l_input_type_e = WR_DQ; - l_flag = 1; - // C4 DQ to lane/block (flag = 0) in PHY or lane/block to C4 DQ (flag = 1) - // In this case moving from lane/block to C4 DQ to determine spare - rc = mss_c4_phy(i_target, port, rank_group, l_input_type_e, l_index_u8, l_verbose, lane, block, l_flag); - if (rc) return rc; - - dqs_index = l_index_u8 / 8; - - - if ( ((dqs_index % 9 == 0)&&(dqs_index/9 > 0)) && (l_disable_value_u8[rank_group][block][byte][nibble] != 0x0)) - { - //This is a spare. Unmark it in the old map for the rest of the workaround to not operate on a spare - FAPI_DBG("WR LVL DISABLE WORKAROUND: Denoting Spare that is disabled for block: %d byte: %d nibble: %d Previous Value: 0x%02X", block, byte, nibble, l_disable_value_u8[rank_group][block][byte][nibble]); - l_disable_old_value_u8[rank_group][block][byte][nibble] = 0x00; - - } - else if (l_disable_value_u8[rank_group][block][byte][nibble] != 0x00) - { - //This is not a spare. Unmark into what will be scommed back in; to be able to reset the disable mask. - FAPI_DBG("WR LVL DISABLE WORKAROUND: Unmasking disable for block: %d byte: %d nibble: %d Previous Value: 0x%02X", block, byte, nibble, l_disable_value_u8[rank_group][block][byte][nibble]); - l_disable_value_u8[rank_group][block][byte][nibble] = 0x00; - - } - - - //BLOCK 0 - rc = fapiGetScom(i_target, DISABLE_ADDR_0, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][0][0][0], 48, 4); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][0][0][1], 52, 4); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][0][1][0], 56, 4); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][0][1][1], 60, 4); - rc = fapiPutScom(i_target, DISABLE_ADDR_0, data_buffer_64); - if (rc) return rc; - - //BLOCK 1 - - rc = fapiGetScom(i_target, DISABLE_ADDR_1, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][1][0][0], 48, 4); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][1][0][1], 52, 4); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][1][1][0], 56, 4); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][1][1][1], 60, 4); - rc = fapiPutScom(i_target, DISABLE_ADDR_1, data_buffer_64); - if (rc) return rc; - - //BLOCK 2 - - rc = fapiGetScom(i_target, DISABLE_ADDR_2, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][2][0][0], 48, 4); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][2][0][1], 52, 4); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][2][1][0], 56, 4); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][2][1][1], 60, 4); - rc = fapiPutScom(i_target, DISABLE_ADDR_2, data_buffer_64); - if (rc) return rc; - - - //BLOCK 3 - - rc = fapiGetScom(i_target, DISABLE_ADDR_3, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][3][0][0], 48, 4); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][3][0][1], 52, 4); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][3][1][0], 56, 4); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][3][1][1], 60, 4); - rc = fapiPutScom(i_target, DISABLE_ADDR_3, data_buffer_64); - if (rc) return rc; - - - //Block 4 - rc = fapiGetScom(i_target, DISABLE_ADDR_4, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][4][0][0], 48, 4); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][4][0][1], 52, 4); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][4][1][0], 56, 4); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][4][1][1], 60, 4); - rc = fapiPutScom(i_target, DISABLE_ADDR_4, data_buffer_64); - if (rc) return rc; - - - } - } - } - } - } - - - //Re-run DQS ALIGN for only rank_group/ports that had a disable. - - for(rank_group = 0; rank_group < MAX_PRI_RANKS; rank_group++) - { - group = 255; - for(block = 0; block < maxblocks; block++) - { - for (byte = 0; byte < maxbytes; byte++) - { - - for (nibble = 0; nibble < maxnibbles; nibble++) - { - //Check if rank group exists - if(primary_ranks_array[rank_group][port] != 255) - { - if (l_disable_old_value_u8[rank_group][block][byte][nibble] != 0x0) - { - group = rank_group; - } - } - - } - } - } - FAPI_DBG("WR LVL DISABLE WORKAROUND: DQS ALIGN LOOP on group: %d rank_group: %d port: %d", group, rank_group, port); - if (group != 255) - { - - FAPI_DBG("WR LVL DISABLE WORKAROUND: Re-Running DQS ALIGN on rank_group: %d port: %d", group, port); - //Clearing any status or errors bits that may have occured in previous training subtest. - if(port == 0) - { - //clear status reg - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P0_0x8000C0190301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.clearBit(48, 4); - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P0_0x8000C0190301143F, data_buffer_64); - if(rc) return rc; - - //clear error reg - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P0_0x8000C0180301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.clearBit(48, 11); - rc_num = rc_num | data_buffer_64.clearBit(60, 4); - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P0_0x8000C0180301143F, data_buffer_64); - if(rc) return rc; + uint8_t width; + uint8_t dqs_index; + + rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target, width); + + uint32_t instruction_number = 0; + ecmdDataBufferBase address_buffer_16(16); + rc_num = rc_num | address_buffer_16.flushTo0(); + ecmdDataBufferBase bank_buffer_8(8); + rc_num = rc_num | bank_buffer_8.flushTo0(); + ecmdDataBufferBase activate_buffer_1(1); + rc_num = rc_num | activate_buffer_1.flushTo0(); + ecmdDataBufferBase rasn_buffer_1(1); + ecmdDataBufferBase casn_buffer_1(1); + ecmdDataBufferBase wen_buffer_1(1); + ecmdDataBufferBase cke_buffer_8(8); + rc_num = rc_num | cke_buffer_8.flushTo1(); + ecmdDataBufferBase csn_buffer_8(8); + rc_num = rc_num | csn_buffer_8.flushTo1(); + ecmdDataBufferBase odt_buffer_8(8); + rc_num = rc_num | odt_buffer_8.flushTo0(); + ecmdDataBufferBase test_buffer_4(4); + rc_num = rc_num | test_buffer_4.setBit(0,4); + + ecmdDataBufferBase num_idles_buffer_16(16); + rc_num = rc_num | num_idles_buffer_16.flushTo1(); + ecmdDataBufferBase num_repeat_buffer_16(16); + rc_num = rc_num | num_repeat_buffer_16.flushTo0(); + ecmdDataBufferBase data_buffer_20(20); + rc_num = rc_num | data_buffer_20.flushTo0(); + ecmdDataBufferBase read_compare_buffer_1(1); + rc_num = rc_num | read_compare_buffer_1.flushTo0(); + ecmdDataBufferBase rank_cal_buffer_4(4); + rc_num = rc_num | rank_cal_buffer_4.flushTo0(); + ecmdDataBufferBase ddr_cal_enable_buffer_1(1); + rc_num = rc_num | ddr_cal_enable_buffer_1.flushTo1(); + ecmdDataBufferBase ccs_end_buffer_1(1); + rc_num = rc_num | ccs_end_buffer_1.flushTo1(); + uint8_t group = 255; + const uint32_t NUM_POLL = 10000; + + + uint8_t cur_cal_step = 2; + enum mss_draminit_training_result cur_error_status = MSS_INIT_CAL_PASS; + uint8_t mbaPosition; + // Get MBA position: 0 = mba01, 1 = mba23 + rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target, mbaPosition); + if(rc) + { + FAPI_ERR("Error getting MBA position"); + return rc; + } + + + + //Resetting Disable mask. Avoid spares. + for(block = 0; block < maxblocks; block++) + { + for (byte = 0; byte < 2; byte++) + { + + for (nibble = 0; nibble < maxnibbles; nibble++) + { + + for(rank_group = 0; rank_group < MAX_PRI_RANKS; rank_group++) + { + + //Check if rank group exists + if(primary_ranks_array[rank_group][port] != 255) + { + + + if ( port == 0 ) + { + + if ( rank_group == 0 ) + { + + DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_0_0x8000007c0301143F; + DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_1_0x8000047c0301143F; + DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_2_0x8000087c0301143F; + DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_3_0x80000c7c0301143F; + DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_4_0x8000107c0301143F; + + } + else if ( rank_group == 1 ) + { + + DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_0_0x8000017c0301143F; + DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_1_0x8000057c0301143F; + DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_2_0x8000097c0301143F; + DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_3_0x80000d7c0301143F; + DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_4_0x8000117c0301143F; + + } + else if ( rank_group == 2 ) + { + + DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_0_0x8000027c0301143F; + DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_1_0x8000067c0301143F; + DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_2_0x80000a7c0301143F; + DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_3_0x80000e7c0301143F; + DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_4_0x8000127c0301143F; + + } + else if ( rank_group == 3 ) + { + + DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_0_0x8000037c0301143F; + DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_1_0x8000077c0301143F; + DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_2_0x80000b7c0301143F; + DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_3_0x80000f7c0301143F; + DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_4_0x8000137c0301143F; + + } + } + else if (port == 1 ) + { + + if ( rank_group == 0 ) + { + + DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_0_0x8001007c0301143F; + DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_1_0x8001047c0301143F; + DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_2_0x8001087c0301143F; + DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_3_0x80010c7c0301143F; + DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_4_0x8001107c0301143F; + + } + else if ( rank_group == 1 ) + { + + DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_0_0x8001017c0301143F; + DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_1_0x8001057c0301143F; + DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_2_0x8001097c0301143F; + DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_3_0x80010d7c0301143F; + DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_4_0x8001117c0301143F; + + + } + else if ( rank_group == 2 ) + { + + DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_0_0x8001027c0301143F; + DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_1_0x8001067c0301143F; + DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_2_0x80010a7c0301143F; + DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_3_0x80010e7c0301143F; + DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_4_0x8001127c0301143F; + + + } + else if ( rank_group == 3 ) + { + + DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_0_0x8001037c0301143F; + DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_1_0x8001077c0301143F; + DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_2_0x80010b7c0301143F; + DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_3_0x80010f7c0301143F; + DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_4_0x8001137c0301143F; + + } + } + + lane = byte * 8 + nibble*4; + l_input_type_e = WR_DQ; + l_flag = 1; + // C4 DQ to lane/block (flag = 0) in PHY or lane/block to C4 DQ (flag = 1) + // In this case moving from lane/block to C4 DQ to determine spare + rc = mss_c4_phy(i_target, port, rank_group, l_input_type_e, l_index_u8, l_verbose, lane, block, l_flag); + if (rc) return rc; + + dqs_index = l_index_u8 / 8; + + + if ( ((dqs_index % 9 == 0)&&(dqs_index/9 > 0)) && (l_disable_value_u8[rank_group][block][byte][nibble] != 0x0)) + { + //This is a spare. Unmark it in the old map for the rest of the workaround to not operate on a spare + FAPI_DBG("WR LVL DISABLE WORKAROUND: Denoting Spare that is disabled for block: %d byte: %d nibble: %d Previous Value: 0x%02X", block, byte, nibble, l_disable_value_u8[rank_group][block][byte][nibble]); + l_disable_old_value_u8[rank_group][block][byte][nibble] = 0x00; + + } + else if (l_disable_value_u8[rank_group][block][byte][nibble] != 0x00) + { + //This is not a spare. Unmark into what will be scommed back in; to be able to reset the disable mask. + FAPI_DBG("WR LVL DISABLE WORKAROUND: Unmasking disable for block: %d byte: %d nibble: %d Previous Value: 0x%02X", block, byte, nibble, l_disable_value_u8[rank_group][block][byte][nibble]); + l_disable_value_u8[rank_group][block][byte][nibble] = 0x00; + + } + + + //BLOCK 0 + rc = fapiGetScom(i_target, DISABLE_ADDR_0, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][0][0][0], 48, 4); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][0][0][1], 52, 4); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][0][1][0], 56, 4); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][0][1][1], 60, 4); + rc = fapiPutScom(i_target, DISABLE_ADDR_0, data_buffer_64); + if (rc) return rc; + + //BLOCK 1 + + rc = fapiGetScom(i_target, DISABLE_ADDR_1, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][1][0][0], 48, 4); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][1][0][1], 52, 4); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][1][1][0], 56, 4); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][1][1][1], 60, 4); + rc = fapiPutScom(i_target, DISABLE_ADDR_1, data_buffer_64); + if (rc) return rc; + + //BLOCK 2 + + rc = fapiGetScom(i_target, DISABLE_ADDR_2, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][2][0][0], 48, 4); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][2][0][1], 52, 4); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][2][1][0], 56, 4); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][2][1][1], 60, 4); + rc = fapiPutScom(i_target, DISABLE_ADDR_2, data_buffer_64); + if (rc) return rc; + + + //BLOCK 3 + + rc = fapiGetScom(i_target, DISABLE_ADDR_3, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][3][0][0], 48, 4); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][3][0][1], 52, 4); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][3][1][0], 56, 4); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][3][1][1], 60, 4); + rc = fapiPutScom(i_target, DISABLE_ADDR_3, data_buffer_64); + if (rc) return rc; + + + //Block 4 + rc = fapiGetScom(i_target, DISABLE_ADDR_4, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][4][0][0], 48, 4); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][4][0][1], 52, 4); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][4][1][0], 56, 4); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][4][1][1], 60, 4); + rc = fapiPutScom(i_target, DISABLE_ADDR_4, data_buffer_64); + if (rc) return rc; + + + } + } + } + } + } + + + //Re-run DQS ALIGN for only rank_group/ports that had a disable. + + for(rank_group = 0; rank_group < MAX_PRI_RANKS; rank_group++) + { + group = 255; + for(block = 0; block < maxblocks; block++) + { + for (byte = 0; byte < maxbytes; byte++) + { + + for (nibble = 0; nibble < maxnibbles; nibble++) + { + //Check if rank group exists + if(primary_ranks_array[rank_group][port] != 255) + { + if (l_disable_old_value_u8[rank_group][block][byte][nibble] != 0x0) + { + group = rank_group; + } + } + + } + } + } + FAPI_DBG("WR LVL DISABLE WORKAROUND: DQS ALIGN LOOP on group: %d rank_group: %d port: %d", group, rank_group, port); + if (group != 255) + { + + FAPI_DBG("WR LVL DISABLE WORKAROUND: Re-Running DQS ALIGN on rank_group: %d port: %d", group, port); + //Clearing any status or errors bits that may have occured in previous training subtest. + if(port == 0) + { + //clear status reg + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P0_0x8000C0190301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.clearBit(48, 4); + rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P0_0x8000C0190301143F, data_buffer_64); + if(rc) return rc; + + //clear error reg + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P0_0x8000C0180301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.clearBit(48, 11); + rc_num = rc_num | data_buffer_64.clearBit(60, 4); + rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P0_0x8000C0180301143F, data_buffer_64); + if(rc) return rc; //clear other port - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P1_0x8001C0160301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.clearBit(48); - rc_num = rc_num | data_buffer_64.clearBit(50); - rc_num = rc_num | data_buffer_64.clearBit(51); - rc_num = rc_num | data_buffer_64.clearBit(52); - rc_num = rc_num | data_buffer_64.clearBit(53); - rc_num = rc_num | data_buffer_64.clearBit(54); - rc_num = rc_num | data_buffer_64.clearBit(55); - rc_num = rc_num | data_buffer_64.clearBit(58); - rc_num = rc_num | data_buffer_64.clearBit(60); - rc_num = rc_num | data_buffer_64.clearBit(61); - rc_num = rc_num | data_buffer_64.clearBit(62); - rc_num = rc_num | data_buffer_64.clearBit(63); - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P1_0x8001C0160301143F, data_buffer_64); - if(rc) return rc; - - //Setup the Config Reg bit for the only cal step we want - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P0_0x8000C0160301143F, data_buffer_64); - if(rc) return rc; - - } - else - { - //clear status reg - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P1_0x8001C0190301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.clearBit(48, 4); - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P1_0x8001C0190301143F, data_buffer_64); - if(rc) return rc; - - //clear error reg - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P1_0x8001C0180301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.clearBit(48, 11); - rc_num = rc_num | data_buffer_64.clearBit(60, 4); - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P1_0x8001C0180301143F, data_buffer_64); - if(rc) return rc; + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P1_0x8001C0160301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.clearBit(48); + rc_num = rc_num | data_buffer_64.clearBit(50); + rc_num = rc_num | data_buffer_64.clearBit(51); + rc_num = rc_num | data_buffer_64.clearBit(52); + rc_num = rc_num | data_buffer_64.clearBit(53); + rc_num = rc_num | data_buffer_64.clearBit(54); + rc_num = rc_num | data_buffer_64.clearBit(55); + rc_num = rc_num | data_buffer_64.clearBit(58); + rc_num = rc_num | data_buffer_64.clearBit(60); + rc_num = rc_num | data_buffer_64.clearBit(61); + rc_num = rc_num | data_buffer_64.clearBit(62); + rc_num = rc_num | data_buffer_64.clearBit(63); + rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P1_0x8001C0160301143F, data_buffer_64); + if(rc) return rc; + + //Setup the Config Reg bit for the only cal step we want + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P0_0x8000C0160301143F, data_buffer_64); + if(rc) return rc; + + } + else + { + //clear status reg + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P1_0x8001C0190301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.clearBit(48, 4); + rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P1_0x8001C0190301143F, data_buffer_64); + if(rc) return rc; + + //clear error reg + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P1_0x8001C0180301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.clearBit(48, 11); + rc_num = rc_num | data_buffer_64.clearBit(60, 4); + rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P1_0x8001C0180301143F, data_buffer_64); + if(rc) return rc; //clear other port - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P0_0x8000C0160301143F, data_buffer_64); - if(rc) return rc; - rc_num = rc_num | data_buffer_64.clearBit(48); - rc_num = rc_num | data_buffer_64.clearBit(50); - rc_num = rc_num | data_buffer_64.clearBit(51); - rc_num = rc_num | data_buffer_64.clearBit(52); - rc_num = rc_num | data_buffer_64.clearBit(53); - rc_num = rc_num | data_buffer_64.clearBit(54); - rc_num = rc_num | data_buffer_64.clearBit(55); - rc_num = rc_num | data_buffer_64.clearBit(58); - rc_num = rc_num | data_buffer_64.clearBit(60); - rc_num = rc_num | data_buffer_64.clearBit(61); - rc_num = rc_num | data_buffer_64.clearBit(62); - rc_num = rc_num | data_buffer_64.clearBit(63); - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P0_0x8000C0160301143F, data_buffer_64); - if(rc) return rc; - - //Setup the Config Reg bit for the only cal step we want - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P1_0x8001C0160301143F, data_buffer_64); - if(rc) return rc; - - } - - //Clear training cnfg - rc_num = rc_num | data_buffer_64.clearBit(48); - rc_num = rc_num | data_buffer_64.setBit(50); - rc_num = rc_num | data_buffer_64.clearBit(51); - rc_num = rc_num | data_buffer_64.clearBit(52); - rc_num = rc_num | data_buffer_64.clearBit(53); - rc_num = rc_num | data_buffer_64.clearBit(54); - rc_num = rc_num | data_buffer_64.clearBit(55); - rc_num = rc_num | data_buffer_64.clearBit(60); - rc_num = rc_num | data_buffer_64.clearBit(61); - rc_num = rc_num | data_buffer_64.clearBit(62); - rc_num = rc_num | data_buffer_64.clearBit(63); - - if(group == 0){ - rc_num = rc_num | data_buffer_64.setBit(60); - } - else if(group == 1){ - rc_num = rc_num | data_buffer_64.setBit(61); - } - else if(group == 2){ - rc_num = rc_num | data_buffer_64.setBit(62); - } - else if(group == 3){ - rc_num = rc_num | data_buffer_64.setBit(63); - } - - //Set the config register - if(port == 0) - { - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P0_0x8000C0160301143F, data_buffer_64); - if(rc) return rc; - } - else - { - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P1_0x8001C0160301143F, data_buffer_64); - if(rc) return rc; - } - - rc = mss_ccs_inst_arry_0(i_target, - instruction_number, - address_buffer_16, - bank_buffer_8, - activate_buffer_1, - rasn_buffer_1, - casn_buffer_1, - wen_buffer_1, - cke_buffer_8, - csn_buffer_8, - odt_buffer_8, - test_buffer_4, - port); - - if(rc) return rc; - rc_num = rc_num | rank_cal_buffer_4.insert(primary_ranks_array[rank_group][port], 0, 4, 4); // 8 bit storage, need last 4 bits - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - - rc = mss_ccs_inst_arry_1(i_target, - instruction_number, - num_idles_buffer_16, - num_repeat_buffer_16, - data_buffer_20, - read_compare_buffer_1, - rank_cal_buffer_4, - ddr_cal_enable_buffer_1, - ccs_end_buffer_1); - if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs - - rc = mss_execute_ccs_inst_array( i_target, NUM_POLL, 60); - if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs - - //Check to see if the training errored out - rc = mss_check_error_status(i_target, mbaPosition, port, group, cur_cal_step, cur_error_status); - if(rc) return rc; - - if (cur_error_status == MSS_INIT_CAL_FAIL) - { - //RC/Log is generated in mss_check_error_status - FAPI_ERR("Error returned on workaround Re-run of DQS_ALIGN on %s PORT: %d RP: %d", i_target.toEcmdString(), port, group); - } - - } - } - - uint8_t curr_bit; - - //Finding the lowest Values on disabled bytes, then resetting mask. - for(block = 0; block < maxblocks; block++) - { - for (byte = 0; byte < maxbytes; byte++) - { - - for (nibble = 0; nibble < maxnibbles; nibble++) - { - - for(rank_group = 0; rank_group < MAX_PRI_RANKS; rank_group++) - { - for (nibble_dq = 0; nibble_dq < 4; nibble_dq++) - { - - - if (l_disable_old_value_u8[rank_group][block][byte][nibble] != 0x00) - { - - FAPI_DBG("WR LVL DISABLE WORKAROUND: DISABLED block: %d byte: %d nibble: %d disable value: 0x%02X", block, byte, nibble, l_disable_old_value_u8[rank_group][block][byte][nibble]); - FAPI_DBG("WR LVL DISABLE WORKAROUND: DQSCLK replacement: block: %d byte: %d nibble: %d current value: %d", block, byte, nibble, l_dqsclk_phase_value_u8[rank_group][block][byte][nibble]); - //SWAPPING DQSCLK PHASE SELECT - for (rg = 0; rg < MAX_PRI_RANKS; rg++) - { - FAPI_DBG("WR LVL DISABLE WORKAROUND: DQSCLK possible replacement value: %d", l_dqsclk_phase_value_u8[rg][block][byte][nibble]); - - if ( (l_disable_old_value_u8[rg][block][byte][nibble] == 0) && (l_dqsclk_phase_value_u8[rg][block][byte][nibble] < l_dqsclk_phase_value_u8[rank_group][block][byte][nibble]) ) - { - FAPI_DBG("WR LVL DISABLE WORKAROUND: DQSCLK replacement: block: %d byte: %d nibble: %d", block, byte, nibble); - FAPI_DBG("WR LVL DISABLE WORKAROUND: DQSCLK replacement value: %d", l_dqsclk_phase_value_u8[rg][block][byte][nibble]); - l_dqsclk_phase_value_u8[rank_group][block][byte][nibble] = l_dqsclk_phase_value_u8[rg][block][byte][nibble]; - } - } - - FAPI_DBG("WR LVL DISABLE WORKAROUND: RDCLK replacement: block: %d byte: %d nibble: %d current value: %d", block, byte, nibble, l_dqsclk_phase_value_u8[rank_group][block][byte][nibble]); - //SWAPPING RDCLK PHASE SELECT - for (rg = 0; rg < MAX_PRI_RANKS; rg++) - { - FAPI_DBG("WR LVL DISABLE WORKAROUND: RDCLK possible replacement value: %d", l_rdclk_phase_value_u8[rg][block][byte][nibble]); - - if ( (l_disable_old_value_u8[rg][block][byte][nibble] == 0) && (l_rdclk_phase_value_u8[rg][block][byte][nibble] < l_rdclk_phase_value_u8[rank_group][block][byte][nibble]) ) - { - FAPI_DBG("WR LVL DISABLE WORKAROUND: RDCLK replacement: block: %d byte: %d nibble: %d", block, byte, nibble); - FAPI_DBG("WR LVL DISABLE WORKAROUND: RDCLK replacement value: %d", l_rdclk_phase_value_u8[rg][block][byte][nibble]); - l_rdclk_phase_value_u8[rank_group][block][byte][nibble] = l_rdclk_phase_value_u8[rg][block][byte][nibble]; - } - } - - FAPI_DBG("WR LVL DISABLE WORKAROUND: GATE DELAY replacement: block: %d byte: %d nibble: %d current value: %d", block, byte, nibble, l_dqsclk_phase_value_u8[rank_group][block][byte][nibble]); - //SWAPPING RDCLK PHASE SELECT - for (rg = 0; rg < MAX_PRI_RANKS; rg++) - { - FAPI_DBG("WR LVL DISABLE WORKAROUND: GATE DELAY possible replacement value: %d", l_gate_delay_value_u8[rg][block][byte][nibble]); - - if ( (l_disable_old_value_u8[rg][block][byte][nibble] == 0) && (l_gate_delay_value_u8[rg][block][byte][nibble] < l_gate_delay_value_u8[rank_group][block][byte][nibble]) ) - { - FAPI_DBG("WR LVL DISABLE WORKAROUND: GATE DELAY replacement: block: %d byte: %d nibble: %d", block, byte, nibble); - FAPI_DBG("WR LVL DISABLE WORKAROUND: GATE DELAY replacement value: %d", l_gate_delay_value_u8[rg][block][byte][nibble]); - l_gate_delay_value_u8[rank_group][block][byte][nibble] = l_gate_delay_value_u8[rg][block][byte][nibble]; - } - } - - //SWAPPING DQ AND DQS - mask = 0x8 >> nibble_dq; - curr_bit = l_disable_old_value_u8[rank_group][block][byte][nibble] & mask; - FAPI_DBG("WR LVL DISABLE WORKAROUND: DQ/DQS SWAP MASK: 0x%02X DISABLE BIT: 0x%02X CURR BIT: 0x%02X", mask, l_disable_old_value_u8[rank_group][block][byte][nibble] & mask, curr_bit); - - if (curr_bit) - { - - FAPI_DBG("WR LVL DISABLE WORKAROUND: DQ/DQS SWAP RANK_GROUP: %d BLOCK: %d BYTE: %d NIBBLE: %d DISABLE VALUE: 0x%02X", rank_group, block, byte, nibble, l_disable_old_value_u8[rank_group][block][byte][nibble]); - - //Figure out which lane to investigate - l_index_u8 = nibble_dq + 4 * nibble + 8 * byte; - lane = l_index_u8; - - l_input_type_e = WR_DQ; - l_flag = 1; - // C4 DQ to lane/block (flag = 0) in PHY or lane/block to C4 DQ (flag = 1) - // In this case moving from lane/block to C4 DQ to use access_delay_reg - rc = mss_c4_phy(i_target, port, rank_group, l_input_type_e, l_index_u8, l_verbose, lane, block, l_flag); - - - l_access_type_e = READ; - l_rank_u8 = ranks_array[rank_group][0][0]; - if (l_rank_u8 == 255) - continue; - - // Getting old DQ Value - l_input_type_e = WR_DQ; - rc = mss_access_delay_reg(i_target, l_access_type_e, port, ranks_array[rank_group][0][0], l_input_type_e, l_index_u8, l_verbose, l_old_delay_value_u32); - if(rc) return rc; - - - if (width == fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X8) - { - dqs_index = l_index_u8 / 8; - } - else - { - dqs_index = l_index_u8 / 4; - } - - // Getting old DQS Value - l_input_type_e = WR_DQS; - rc = mss_access_delay_reg(i_target, l_access_type_e, port, ranks_array[rank_group][0][0], l_input_type_e, dqs_index, l_verbose, l_old_DQS_delay_value_u32); - if(rc) return rc; - - FAPI_DBG("WR LVL DISABLE WORKAROUND: Value being replaced C4: %d C4 DQS: %d Rank:%d DQ DELAY VALUE: 0x%03X DQS DELAY VALUE: 0x%03X ", l_index_u8, dqs_index, ranks_array[rank_group][0][0], l_old_delay_value_u32, l_old_DQS_delay_value_u32); - - for (rg = 0; rg < MAX_PRI_RANKS; rg++) - { - l_access_type_e = READ; - rank_2 = ranks_array[rg][0][0]; - FAPI_DBG("WR LVL DISABLE WORKAROUND: RANK: %d DISABLE VALUE: 0x%02X MASKED: 0x%02X", rank_2, l_disable_old_value_u8[rg][block][byte][nibble], l_disable_old_value_u8[rg][block][byte][nibble] & mask); - if ( (rank_2 != 255) && (l_disable_old_value_u8[rg][block][byte][nibble] == 0 ) ) - { - // Getting New DQ Value - l_input_type_e = WR_DQ; - rc = mss_access_delay_reg(i_target, l_access_type_e, port, rank_2, l_input_type_e, l_index_u8, l_verbose, l_delay_value_u32); - if(rc) return rc; - - // Getting New DQS Value - l_input_type_e = WR_DQS; - rc = mss_access_delay_reg(i_target, l_access_type_e, port, rank_2, l_input_type_e, dqs_index, l_verbose, l_DQS_delay_value_u32); - if(rc) return rc; - - FAPI_DBG("WR LVL DISABLE WORKAROUND: Possible Replacement Value C4: %d C4 DQS: %d Rank:%d DQ DELAY VALUE: 0x%03X DQS DELAY VALUE: 0x%03X", l_index_u8, dqs_index, rank_2, l_delay_value_u32, l_DQS_delay_value_u32); - - if ( l_delay_value_u32 < l_old_delay_value_u32) - { - l_old_delay_value_u32 = l_delay_value_u32; - // Writing DQ Value - l_access_type_e = WRITE; - l_rank_u8 = ranks_array[rank_group][0][0]; - l_input_type_e = WR_DQ; - rc = mss_access_delay_reg(i_target, l_access_type_e, port, ranks_array[rank_group][0][0], l_input_type_e, l_index_u8, l_verbose, l_delay_value_u32); - if(rc) return rc; - - FAPI_DBG("WR LVL DISABLE WORKAROUND: Replacing DQ: Value C4: %d C4 DQS: %d Rank:%d DELAY VALUE: 0x%03X", l_index_u8, dqs_index, ranks_array[rank_group][0][0], l_delay_value_u32); - } - if ( l_DQS_delay_value_u32 < l_old_DQS_delay_value_u32) - { - l_old_DQS_delay_value_u32 = l_DQS_delay_value_u32; - // Writing DQS Value - l_access_type_e = WRITE; - l_rank_u8 = ranks_array[rank_group][0][0]; - l_input_type_e = WR_DQS; - rc = mss_access_delay_reg(i_target, l_access_type_e, port, ranks_array[rank_group][0][0], l_input_type_e, dqs_index, l_verbose, l_DQS_delay_value_u32); - if(rc) return rc; - - FAPI_DBG("WR LVL DISABLE WORKAROUND: Replacing DQS: Value C4: %d C4 DQS: %d Rank:%d DQS DELAY VALUE: 0x%03X", l_index_u8, dqs_index, ranks_array[rank_group][0][0], l_DQS_delay_value_u32); - } - - } - - } - - - } - } - } - - } - } - - } - } - - - //Scoming in the New Values + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P0_0x8000C0160301143F, data_buffer_64); + if(rc) return rc; + rc_num = rc_num | data_buffer_64.clearBit(48); + rc_num = rc_num | data_buffer_64.clearBit(50); + rc_num = rc_num | data_buffer_64.clearBit(51); + rc_num = rc_num | data_buffer_64.clearBit(52); + rc_num = rc_num | data_buffer_64.clearBit(53); + rc_num = rc_num | data_buffer_64.clearBit(54); + rc_num = rc_num | data_buffer_64.clearBit(55); + rc_num = rc_num | data_buffer_64.clearBit(58); + rc_num = rc_num | data_buffer_64.clearBit(60); + rc_num = rc_num | data_buffer_64.clearBit(61); + rc_num = rc_num | data_buffer_64.clearBit(62); + rc_num = rc_num | data_buffer_64.clearBit(63); + rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P0_0x8000C0160301143F, data_buffer_64); + if(rc) return rc; + + //Setup the Config Reg bit for the only cal step we want + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P1_0x8001C0160301143F, data_buffer_64); + if(rc) return rc; + + } + + //Clear training cnfg + rc_num = rc_num | data_buffer_64.clearBit(48); + rc_num = rc_num | data_buffer_64.setBit(50); + rc_num = rc_num | data_buffer_64.clearBit(51); + rc_num = rc_num | data_buffer_64.clearBit(52); + rc_num = rc_num | data_buffer_64.clearBit(53); + rc_num = rc_num | data_buffer_64.clearBit(54); + rc_num = rc_num | data_buffer_64.clearBit(55); + rc_num = rc_num | data_buffer_64.clearBit(60); + rc_num = rc_num | data_buffer_64.clearBit(61); + rc_num = rc_num | data_buffer_64.clearBit(62); + rc_num = rc_num | data_buffer_64.clearBit(63); + + if(group == 0){ + rc_num = rc_num | data_buffer_64.setBit(60); + } + else if(group == 1){ + rc_num = rc_num | data_buffer_64.setBit(61); + } + else if(group == 2){ + rc_num = rc_num | data_buffer_64.setBit(62); + } + else if(group == 3){ + rc_num = rc_num | data_buffer_64.setBit(63); + } + + //Set the config register + if(port == 0) + { + rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P0_0x8000C0160301143F, data_buffer_64); + if(rc) return rc; + } + else + { + rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P1_0x8001C0160301143F, data_buffer_64); + if(rc) return rc; + } + + rc = mss_ccs_inst_arry_0(i_target, + instruction_number, + address_buffer_16, + bank_buffer_8, + activate_buffer_1, + rasn_buffer_1, + casn_buffer_1, + wen_buffer_1, + cke_buffer_8, + csn_buffer_8, + odt_buffer_8, + test_buffer_4, + port); + + if(rc) return rc; + rc_num = rc_num | rank_cal_buffer_4.insert(primary_ranks_array[rank_group][port], 0, 4, 4); // 8 bit storage, need last 4 bits + if(rc_num) + { + rc.setEcmdError(rc_num); + return rc; + } + + rc = mss_ccs_inst_arry_1(i_target, + instruction_number, + num_idles_buffer_16, + num_repeat_buffer_16, + data_buffer_20, + read_compare_buffer_1, + rank_cal_buffer_4, + ddr_cal_enable_buffer_1, + ccs_end_buffer_1); + if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs + + rc = mss_execute_ccs_inst_array( i_target, NUM_POLL, 60); + if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs + + //Check to see if the training errored out + rc = mss_check_error_status(i_target, mbaPosition, port, group, cur_cal_step, cur_error_status, 1); + if(rc) return rc; + + if (cur_error_status == MSS_INIT_CAL_FAIL) + { + //RC/Log is generated in mss_check_error_status + FAPI_ERR("Error returned on workaround Re-run of DQS_ALIGN on %s PORT: %d RP: %d", i_target.toEcmdString(), port, group); + } + + } + } + + uint8_t curr_bit; + + //Finding the lowest Values on disabled bytes, then resetting mask. + for(block = 0; block < maxblocks; block++) + { + for (byte = 0; byte < maxbytes; byte++) + { + + for (nibble = 0; nibble < maxnibbles; nibble++) + { + + for(rank_group = 0; rank_group < MAX_PRI_RANKS; rank_group++) + { + for (nibble_dq = 0; nibble_dq < 4; nibble_dq++) + { + + + if (l_disable_old_value_u8[rank_group][block][byte][nibble] != 0x00) + { + + FAPI_DBG("WR LVL DISABLE WORKAROUND: DISABLED block: %d byte: %d nibble: %d disable value: 0x%02X", block, byte, nibble, l_disable_old_value_u8[rank_group][block][byte][nibble]); + FAPI_DBG("WR LVL DISABLE WORKAROUND: DQSCLK replacement: block: %d byte: %d nibble: %d current value: %d", block, byte, nibble, l_dqsclk_phase_value_u8[rank_group][block][byte][nibble]); + //SWAPPING DQSCLK PHASE SELECT + for (rg = 0; rg < MAX_PRI_RANKS; rg++) + { + FAPI_DBG("WR LVL DISABLE WORKAROUND: DQSCLK possible replacement value: %d", l_dqsclk_phase_value_u8[rg][block][byte][nibble]); + + if ( (l_disable_old_value_u8[rg][block][byte][nibble] == 0) && (l_dqsclk_phase_value_u8[rg][block][byte][nibble] < l_dqsclk_phase_value_u8[rank_group][block][byte][nibble]) ) + { + FAPI_DBG("WR LVL DISABLE WORKAROUND: DQSCLK replacement: block: %d byte: %d nibble: %d", block, byte, nibble); + FAPI_DBG("WR LVL DISABLE WORKAROUND: DQSCLK replacement value: %d", l_dqsclk_phase_value_u8[rg][block][byte][nibble]); + l_dqsclk_phase_value_u8[rank_group][block][byte][nibble] = l_dqsclk_phase_value_u8[rg][block][byte][nibble]; + } + } + + FAPI_DBG("WR LVL DISABLE WORKAROUND: RDCLK replacement: block: %d byte: %d nibble: %d current value: %d", block, byte, nibble, l_dqsclk_phase_value_u8[rank_group][block][byte][nibble]); + //SWAPPING RDCLK PHASE SELECT + for (rg = 0; rg < MAX_PRI_RANKS; rg++) + { + FAPI_DBG("WR LVL DISABLE WORKAROUND: RDCLK possible replacement value: %d", l_rdclk_phase_value_u8[rg][block][byte][nibble]); + + if ( (l_disable_old_value_u8[rg][block][byte][nibble] == 0) && (l_rdclk_phase_value_u8[rg][block][byte][nibble] < l_rdclk_phase_value_u8[rank_group][block][byte][nibble]) ) + { + FAPI_DBG("WR LVL DISABLE WORKAROUND: RDCLK replacement: block: %d byte: %d nibble: %d", block, byte, nibble); + FAPI_DBG("WR LVL DISABLE WORKAROUND: RDCLK replacement value: %d", l_rdclk_phase_value_u8[rg][block][byte][nibble]); + l_rdclk_phase_value_u8[rank_group][block][byte][nibble] = l_rdclk_phase_value_u8[rg][block][byte][nibble]; + } + } + + FAPI_DBG("WR LVL DISABLE WORKAROUND: GATE DELAY replacement: block: %d byte: %d nibble: %d current value: %d", block, byte, nibble, l_dqsclk_phase_value_u8[rank_group][block][byte][nibble]); + //SWAPPING RDCLK PHASE SELECT + for (rg = 0; rg < MAX_PRI_RANKS; rg++) + { + FAPI_DBG("WR LVL DISABLE WORKAROUND: GATE DELAY possible replacement value: %d", l_gate_delay_value_u8[rg][block][byte][nibble]); + + if ( (l_disable_old_value_u8[rg][block][byte][nibble] == 0) && (l_gate_delay_value_u8[rg][block][byte][nibble] < l_gate_delay_value_u8[rank_group][block][byte][nibble]) ) + { + FAPI_DBG("WR LVL DISABLE WORKAROUND: GATE DELAY replacement: block: %d byte: %d nibble: %d", block, byte, nibble); + FAPI_DBG("WR LVL DISABLE WORKAROUND: GATE DELAY replacement value: %d", l_gate_delay_value_u8[rg][block][byte][nibble]); + l_gate_delay_value_u8[rank_group][block][byte][nibble] = l_gate_delay_value_u8[rg][block][byte][nibble]; + } + } + + //SWAPPING DQ AND DQS + mask = 0x8 >> nibble_dq; + curr_bit = l_disable_old_value_u8[rank_group][block][byte][nibble] & mask; + FAPI_DBG("WR LVL DISABLE WORKAROUND: DQ/DQS SWAP MASK: 0x%02X DISABLE BIT: 0x%02X CURR BIT: 0x%02X", mask, l_disable_old_value_u8[rank_group][block][byte][nibble] & mask, curr_bit); + + if (curr_bit) + { + + FAPI_DBG("WR LVL DISABLE WORKAROUND: DQ/DQS SWAP RANK_GROUP: %d BLOCK: %d BYTE: %d NIBBLE: %d DISABLE VALUE: 0x%02X", rank_group, block, byte, nibble, l_disable_old_value_u8[rank_group][block][byte][nibble]); + + //Figure out which lane to investigate + l_index_u8 = nibble_dq + 4 * nibble + 8 * byte; + lane = l_index_u8; + + l_input_type_e = WR_DQ; + l_flag = 1; + // C4 DQ to lane/block (flag = 0) in PHY or lane/block to C4 DQ (flag = 1) + // In this case moving from lane/block to C4 DQ to use access_delay_reg + rc = mss_c4_phy(i_target, port, rank_group, l_input_type_e, l_index_u8, l_verbose, lane, block, l_flag); + + + l_access_type_e = READ; + l_rank_u8 = ranks_array[rank_group][0][0]; + if (l_rank_u8 == 255) + continue; + + // Getting old DQ Value + l_input_type_e = WR_DQ; + rc = mss_access_delay_reg(i_target, l_access_type_e, port, ranks_array[rank_group][0][0], l_input_type_e, l_index_u8, l_verbose, l_old_delay_value_u32); + if(rc) return rc; + + + if (width == fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X8) + { + dqs_index = l_index_u8 / 8; + } + else + { + dqs_index = l_index_u8 / 4; + } + + // Getting old DQS Value + l_input_type_e = WR_DQS; + rc = mss_access_delay_reg(i_target, l_access_type_e, port, ranks_array[rank_group][0][0], l_input_type_e, dqs_index, l_verbose, l_old_DQS_delay_value_u32); + if(rc) return rc; + + FAPI_DBG("WR LVL DISABLE WORKAROUND: Value being replaced C4: %d C4 DQS: %d Rank:%d DQ DELAY VALUE: 0x%03X DQS DELAY VALUE: 0x%03X ", l_index_u8, dqs_index, ranks_array[rank_group][0][0], l_old_delay_value_u32, l_old_DQS_delay_value_u32); + + for (rg = 0; rg < MAX_PRI_RANKS; rg++) + { + l_access_type_e = READ; + rank_2 = ranks_array[rg][0][0]; + FAPI_DBG("WR LVL DISABLE WORKAROUND: RANK: %d DISABLE VALUE: 0x%02X MASKED: 0x%02X", rank_2, l_disable_old_value_u8[rg][block][byte][nibble], l_disable_old_value_u8[rg][block][byte][nibble] & mask); + if ( (rank_2 != 255) && (l_disable_old_value_u8[rg][block][byte][nibble] == 0 ) ) + { + // Getting New DQ Value + l_input_type_e = WR_DQ; + rc = mss_access_delay_reg(i_target, l_access_type_e, port, rank_2, l_input_type_e, l_index_u8, l_verbose, l_delay_value_u32); + if(rc) return rc; + + // Getting New DQS Value + l_input_type_e = WR_DQS; + rc = mss_access_delay_reg(i_target, l_access_type_e, port, rank_2, l_input_type_e, dqs_index, l_verbose, l_DQS_delay_value_u32); + if(rc) return rc; + + FAPI_DBG("WR LVL DISABLE WORKAROUND: Possible Replacement Value C4: %d C4 DQS: %d Rank:%d DQ DELAY VALUE: 0x%03X DQS DELAY VALUE: 0x%03X", l_index_u8, dqs_index, rank_2, l_delay_value_u32, l_DQS_delay_value_u32); + + if ( l_delay_value_u32 < l_old_delay_value_u32) + { + l_old_delay_value_u32 = l_delay_value_u32; + // Writing DQ Value + l_access_type_e = WRITE; + l_rank_u8 = ranks_array[rank_group][0][0]; + l_input_type_e = WR_DQ; + rc = mss_access_delay_reg(i_target, l_access_type_e, port, ranks_array[rank_group][0][0], l_input_type_e, l_index_u8, l_verbose, l_delay_value_u32); + if(rc) return rc; + + FAPI_DBG("WR LVL DISABLE WORKAROUND: Replacing DQ: Value C4: %d C4 DQS: %d Rank:%d DELAY VALUE: 0x%03X", l_index_u8, dqs_index, ranks_array[rank_group][0][0], l_delay_value_u32); + } + if ( l_DQS_delay_value_u32 < l_old_DQS_delay_value_u32) + { + l_old_DQS_delay_value_u32 = l_DQS_delay_value_u32; + // Writing DQS Value + l_access_type_e = WRITE; + l_rank_u8 = ranks_array[rank_group][0][0]; + l_input_type_e = WR_DQS; + rc = mss_access_delay_reg(i_target, l_access_type_e, port, ranks_array[rank_group][0][0], l_input_type_e, dqs_index, l_verbose, l_DQS_delay_value_u32); + if(rc) return rc; + + FAPI_DBG("WR LVL DISABLE WORKAROUND: Replacing DQS: Value C4: %d C4 DQS: %d Rank:%d DQS DELAY VALUE: 0x%03X", l_index_u8, dqs_index, ranks_array[rank_group][0][0], l_DQS_delay_value_u32); + } + + } + + } + + + } + } + } + + } + } + + } + } + + + //Scoming in the New Values for(rank_group = 0; rank_group < MAX_PRI_RANKS; rank_group++) - { - - //Check if rank group exists - if(primary_ranks_array[rank_group][port] != 255) - { - - - if ( port == 0 ) - { - - if ( rank_group == 0 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_0x800000090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_0x800004090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_0x800008090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_0x80000C090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_0x800010090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_0_0x800000130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_1_0x800004130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_2_0x800008130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_3_0x80000C130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_4_0x800010130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_0_0x8000007c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_1_0x8000047c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_2_0x8000087c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_3_0x80000c7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_4_0x8000107c0301143F; - - - } - else if ( rank_group == 1 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_0x800001090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_0x800005090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_0x800009090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_0x80000D090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_0x800011090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_0_0x800001130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_1_0x800005130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_2_0x800009130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_3_0x80000D130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_4_0x800011130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_0_0x8000017c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_1_0x8000057c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_2_0x8000097c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_3_0x80000d7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_4_0x8000117c0301143F; - - } - else if ( rank_group == 2 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_0x800002090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_0x800006090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_0x80000A090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_0x80000E090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_0x800012090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_0_0x800002130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_1_0x800006130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_2_0x80000A130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_3_0x80000E130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_4_0x800012130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_0_0x8000027c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_1_0x8000067c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_2_0x80000a7c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_3_0x80000e7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_4_0x8000127c0301143F; - - } - else if ( rank_group == 3 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_0x800003090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_0x800007090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_0x80000B090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_0x80000F090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_0x800013090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_0_0x800003130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_1_0x800007130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_2_0x80000B130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_3_0x80000F130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_4_0x800013130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_0_0x8000037c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_1_0x8000077c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_2_0x80000b7c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_3_0x80000f7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_4_0x8000137c0301143F; - - } - } - else if (port == 1 ) - { - - if ( rank_group == 0 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_0x800100090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_0x800104090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_0x800108090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_0x80010C090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_0x800110090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_0_0x800100130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_1_0x800104130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_2_0x800108130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_3_0x80010C130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_4_0x800110130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_0_0x8001007c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_1_0x8001047c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_2_0x8001087c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_3_0x80010c7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_4_0x8001107c0301143F; - - } - else if ( rank_group == 1 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_0x800101090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_0x800105090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_0x800109090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_0x80010D090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_0x800111090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_0_0x800101130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_1_0x800105130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_2_0x800109130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_3_0x80010D130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_4_0x800111130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_0_0x8001017c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_1_0x8001057c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_2_0x8001097c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_3_0x80010d7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_4_0x8001117c0301143F; - - } - else if ( rank_group == 2 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_0x800102090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_0x800106090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_0x80010A090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_0x80010E090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_0x800112090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_0_0x800102130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_1_0x800106130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_2_0x80010A130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_3_0x80010E130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_4_0x800112130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_0_0x8001027c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_1_0x8001067c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_2_0x80010a7c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_3_0x80010e7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_4_0x8001127c0301143F; - - } - else if ( rank_group == 3 ) - { - DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_0x800103090301143F; - DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_0x800107090301143F; - DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_0x80010B090301143F; - DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_0x80010F090301143F; - DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_0x800113090301143F; - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_0_0x800103130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_1_0x800107130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_2_0x80010B130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_3_0x80010F130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_4_0x800113130301143F; - DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_0_0x8001037c0301143F; - DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_1_0x8001077c0301143F; - DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_2_0x80010b7c0301143F; - DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_3_0x80010f7c0301143F; - DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_4_0x8001137c0301143F; - - } - } - - //Block 0 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][0][0][0], 48, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][0][0][1], 52, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][0][1][0], 56, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][0][1][1], 60, 2); - - rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][0][0][0], 50, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][0][0][1], 54, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][0][1][0], 58, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][0][1][1], 62, 2); - rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64); - if (rc) return rc; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_0, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][0][0], 49, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][0][1], 53, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][1][0], 57, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][1][1], 61, 3); - rc = fapiPutScom(i_target, GATE_DELAY_ADDR_0, data_buffer_64); - if (rc) return rc; - - //Block 1 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][1][0][0], 48, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][1][0][1], 52, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][1][1][0], 56, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][1][1][1], 60, 2); - - rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][1][0][0], 50, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][1][0][1], 54, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][1][1][0], 58, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][1][1][1], 62, 2); - rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64); - if (rc) return rc; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_1, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][0][0], 49, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][0][1], 53, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][1][0], 57, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][1][1], 61, 3); - rc = fapiPutScom(i_target, GATE_DELAY_ADDR_1, data_buffer_64); - if (rc) return rc; - - //Block 2 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][2][0][0], 48, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][2][0][1], 52, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][2][1][0], 56, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][2][1][1], 60, 2); - - rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][2][0][0], 50, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][2][0][1], 54, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][2][1][0], 58, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][2][1][1], 62, 2); - rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64); - if (rc) return rc; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_2, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][0][0], 49, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][0][1], 53, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][1][0], 57, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][1][1], 61, 3); - rc = fapiPutScom(i_target, GATE_DELAY_ADDR_2, data_buffer_64); - if (rc) return rc; - - //Block 3 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][3][0][0], 48, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][3][0][1], 52, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][3][1][0], 56, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][3][1][1], 60, 2); - - rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][3][0][0], 50, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][3][0][1], 54, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][3][1][0], 58, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][3][1][1], 62, 2); - rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64); - if (rc) return rc; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_3, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][0][0], 49, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][0][1], 53, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][1][0], 57, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][1][1], 61, 3); - rc = fapiPutScom(i_target, GATE_DELAY_ADDR_3, data_buffer_64); - if (rc) return rc; - - - //Block 4 - rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][4][0][0], 48, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][4][0][1], 52, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][4][1][0], 56, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][4][1][1], 60, 2); - - rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][4][0][0], 50, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][4][0][1], 54, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][4][1][0], 58, 2); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][4][1][1], 62, 2); - rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64); - if (rc) return rc; - - rc = fapiGetScom(i_target, GATE_DELAY_ADDR_4, data_buffer_64); - if (rc) return rc; - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][0][0], 49, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][0][1], 53, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][1][0], 57, 3); - rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][1][1], 61, 3); - rc = fapiPutScom(i_target, GATE_DELAY_ADDR_4, data_buffer_64); - if (rc) return rc; - - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - - - } - } + { + + //Check if rank group exists + if(primary_ranks_array[rank_group][port] != 255) + { + + + if ( port == 0 ) + { + + if ( rank_group == 0 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_0x800000090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_0x800004090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_0x800008090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_0x80000C090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_0x800010090301143F; + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_0_0x800000130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_1_0x800004130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_2_0x800008130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_3_0x80000C130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_4_0x800010130301143F; + DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_0_0x8000007c0301143F; + DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_1_0x8000047c0301143F; + DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_2_0x8000087c0301143F; + DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_3_0x80000c7c0301143F; + DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_4_0x8000107c0301143F; + + + } + else if ( rank_group == 1 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_0x800001090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_0x800005090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_0x800009090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_0x80000D090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_0x800011090301143F; + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_0_0x800001130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_1_0x800005130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_2_0x800009130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_3_0x80000D130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_4_0x800011130301143F; + DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_0_0x8000017c0301143F; + DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_1_0x8000057c0301143F; + DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_2_0x8000097c0301143F; + DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_3_0x80000d7c0301143F; + DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_4_0x8000117c0301143F; + + } + else if ( rank_group == 2 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_0x800002090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_0x800006090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_0x80000A090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_0x80000E090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_0x800012090301143F; + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_0_0x800002130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_1_0x800006130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_2_0x80000A130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_3_0x80000E130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_4_0x800012130301143F; + DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_0_0x8000027c0301143F; + DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_1_0x8000067c0301143F; + DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_2_0x80000a7c0301143F; + DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_3_0x80000e7c0301143F; + DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_4_0x8000127c0301143F; + + } + else if ( rank_group == 3 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_0x800003090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_0x800007090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_0x80000B090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_0x80000F090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_0x800013090301143F; + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_0_0x800003130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_1_0x800007130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_2_0x80000B130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_3_0x80000F130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_4_0x800013130301143F; + DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_0_0x8000037c0301143F; + DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_1_0x8000077c0301143F; + DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_2_0x80000b7c0301143F; + DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_3_0x80000f7c0301143F; + DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_4_0x8000137c0301143F; + + } + } + else if (port == 1 ) + { + + if ( rank_group == 0 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_0x800100090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_0x800104090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_0x800108090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_0x80010C090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_0x800110090301143F; + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_0_0x800100130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_1_0x800104130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_2_0x800108130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_3_0x80010C130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_4_0x800110130301143F; + DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_0_0x8001007c0301143F; + DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_1_0x8001047c0301143F; + DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_2_0x8001087c0301143F; + DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_3_0x80010c7c0301143F; + DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_4_0x8001107c0301143F; + + } + else if ( rank_group == 1 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_0x800101090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_0x800105090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_0x800109090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_0x80010D090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_0x800111090301143F; + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_0_0x800101130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_1_0x800105130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_2_0x800109130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_3_0x80010D130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_4_0x800111130301143F; + DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_0_0x8001017c0301143F; + DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_1_0x8001057c0301143F; + DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_2_0x8001097c0301143F; + DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_3_0x80010d7c0301143F; + DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_4_0x8001117c0301143F; + + } + else if ( rank_group == 2 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_0x800102090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_0x800106090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_0x80010A090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_0x80010E090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_0x800112090301143F; + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_0_0x800102130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_1_0x800106130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_2_0x80010A130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_3_0x80010E130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_4_0x800112130301143F; + DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_0_0x8001027c0301143F; + DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_1_0x8001067c0301143F; + DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_2_0x80010a7c0301143F; + DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_3_0x80010e7c0301143F; + DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_4_0x8001127c0301143F; + + } + else if ( rank_group == 3 ) + { + DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_0x800103090301143F; + DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_0x800107090301143F; + DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_0x80010B090301143F; + DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_0x80010F090301143F; + DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_0x800113090301143F; + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_0_0x800103130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_1_0x800107130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_2_0x80010B130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_3_0x80010F130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_4_0x800113130301143F; + DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_0_0x8001037c0301143F; + DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_1_0x8001077c0301143F; + DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_2_0x80010b7c0301143F; + DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_3_0x80010f7c0301143F; + DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_4_0x8001137c0301143F; + + } + } + + //Block 0 + rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][0][0][0], 48, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][0][0][1], 52, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][0][1][0], 56, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][0][1][1], 60, 2); + + rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][0][0][0], 50, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][0][0][1], 54, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][0][1][0], 58, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][0][1][1], 62, 2); + rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64); + if (rc) return rc; + + rc = fapiGetScom(i_target, GATE_DELAY_ADDR_0, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][0][0], 49, 3); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][0][1], 53, 3); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][1][0], 57, 3); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][1][1], 61, 3); + rc = fapiPutScom(i_target, GATE_DELAY_ADDR_0, data_buffer_64); + if (rc) return rc; + + //Block 1 + rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][1][0][0], 48, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][1][0][1], 52, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][1][1][0], 56, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][1][1][1], 60, 2); + + rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][1][0][0], 50, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][1][0][1], 54, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][1][1][0], 58, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][1][1][1], 62, 2); + rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64); + if (rc) return rc; + + rc = fapiGetScom(i_target, GATE_DELAY_ADDR_1, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][0][0], 49, 3); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][0][1], 53, 3); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][1][0], 57, 3); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][1][1], 61, 3); + rc = fapiPutScom(i_target, GATE_DELAY_ADDR_1, data_buffer_64); + if (rc) return rc; + + //Block 2 + rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][2][0][0], 48, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][2][0][1], 52, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][2][1][0], 56, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][2][1][1], 60, 2); + + rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][2][0][0], 50, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][2][0][1], 54, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][2][1][0], 58, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][2][1][1], 62, 2); + rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64); + if (rc) return rc; + + rc = fapiGetScom(i_target, GATE_DELAY_ADDR_2, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][0][0], 49, 3); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][0][1], 53, 3); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][1][0], 57, 3); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][1][1], 61, 3); + rc = fapiPutScom(i_target, GATE_DELAY_ADDR_2, data_buffer_64); + if (rc) return rc; + + //Block 3 + rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][3][0][0], 48, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][3][0][1], 52, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][3][1][0], 56, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][3][1][1], 60, 2); + + rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][3][0][0], 50, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][3][0][1], 54, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][3][1][0], 58, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][3][1][1], 62, 2); + rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64); + if (rc) return rc; + + rc = fapiGetScom(i_target, GATE_DELAY_ADDR_3, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][0][0], 49, 3); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][0][1], 53, 3); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][1][0], 57, 3); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][1][1], 61, 3); + rc = fapiPutScom(i_target, GATE_DELAY_ADDR_3, data_buffer_64); + if (rc) return rc; + + + //Block 4 + rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][4][0][0], 48, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][4][0][1], 52, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][4][1][0], 56, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][4][1][1], 60, 2); + + rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][4][0][0], 50, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][4][0][1], 54, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][4][1][0], 58, 2); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][4][1][1], 62, 2); + rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64); + if (rc) return rc; + + rc = fapiGetScom(i_target, GATE_DELAY_ADDR_4, data_buffer_64); + if (rc) return rc; + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][0][0], 49, 3); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][0][1], 53, 3); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][1][0], 57, 3); + rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][1][1], 61, 3); + rc = fapiPutScom(i_target, GATE_DELAY_ADDR_4, data_buffer_64); + if (rc) return rc; + + if(rc_num) + { + rc.setEcmdError(rc_num); + return rc; + } + + + } + } } return rc; @@ -4869,138 +5031,138 @@ ReturnCode mss_reset_delay_values( if(rc_num) { - rc.setEcmdError(rc_num); - return rc; + rc.setEcmdError(rc_num); + return rc; } //Scoming in zeros into the Gate delay registers. for(port = 0; port < MAX_PORTS; port++) { - for(rank_group = 0; rank_group < MAX_PRI_RANKS; rank_group++) - { - - //Check if rank group exists - if(primary_ranks_array[rank_group][port] != 255) - { - - if ( port == 0 ) - { - - if ( rank_group == 0 ) - { - - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_0_0x800000130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_1_0x800004130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_2_0x800008130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_3_0x80000C130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_4_0x800010130301143F; - - } - else if ( rank_group == 1 ) - { - - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_0_0x800001130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_1_0x800005130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_2_0x800009130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_3_0x80000D130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_4_0x800011130301143F; - - } - else if ( rank_group == 2 ) - { - - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_0_0x800002130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_1_0x800006130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_2_0x80000A130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_3_0x80000E130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_4_0x800012130301143F; - - } - else if ( rank_group == 3 ) - { - - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_0_0x800003130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_1_0x800007130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_2_0x80000B130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_3_0x80000F130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_4_0x800013130301143F; - - } - } - else if (port == 1 ) - { - - if ( rank_group == 0 ) - { - - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_0_0x800100130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_1_0x800104130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_2_0x800108130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_3_0x80010C130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_4_0x800110130301143F; - - } - else if ( rank_group == 1 ) - { - - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_0_0x800101130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_1_0x800105130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_2_0x800109130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_3_0x80010D130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_4_0x800111130301143F; - - } - else if ( rank_group == 2 ) - { - - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_0_0x800102130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_1_0x800106130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_2_0x80010A130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_3_0x80010E130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_4_0x800112130301143F; - - } - else if ( rank_group == 3 ) - { - - GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_0_0x800103130301143F; - GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_1_0x800107130301143F; - GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_2_0x80010B130301143F; - GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_3_0x80010F130301143F; - GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_4_0x800113130301143F; - - } - } - - rc_num = rc_num | data_buffer_64.flushTo0(); - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - - //BLOCK 0 - rc = fapiPutScom(i_target, GATE_DELAY_ADDR_0, data_buffer_64); - if (rc) return rc; - //BLOCK 1 - rc = fapiPutScom(i_target, GATE_DELAY_ADDR_1, data_buffer_64); - if (rc) return rc; - //BLOCK 2 - rc = fapiPutScom(i_target, GATE_DELAY_ADDR_2, data_buffer_64); - if (rc) return rc; - //BLOCK 3 - rc = fapiPutScom(i_target, GATE_DELAY_ADDR_3, data_buffer_64); - if (rc) return rc; - //BLOCK 4 - rc = fapiPutScom(i_target, GATE_DELAY_ADDR_4, data_buffer_64); - if (rc) return rc; - - - } - } - - } + for(rank_group = 0; rank_group < MAX_PRI_RANKS; rank_group++) + { + + //Check if rank group exists + if(primary_ranks_array[rank_group][port] != 255) + { + + if ( port == 0 ) + { + + if ( rank_group == 0 ) + { + + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_0_0x800000130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_1_0x800004130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_2_0x800008130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_3_0x80000C130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_4_0x800010130301143F; + + } + else if ( rank_group == 1 ) + { + + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_0_0x800001130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_1_0x800005130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_2_0x800009130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_3_0x80000D130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_4_0x800011130301143F; + + } + else if ( rank_group == 2 ) + { + + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_0_0x800002130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_1_0x800006130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_2_0x80000A130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_3_0x80000E130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_4_0x800012130301143F; + + } + else if ( rank_group == 3 ) + { + + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_0_0x800003130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_1_0x800007130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_2_0x80000B130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_3_0x80000F130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_4_0x800013130301143F; + + } + } + else if (port == 1 ) + { + + if ( rank_group == 0 ) + { + + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_0_0x800100130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_1_0x800104130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_2_0x800108130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_3_0x80010C130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_4_0x800110130301143F; + + } + else if ( rank_group == 1 ) + { + + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_0_0x800101130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_1_0x800105130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_2_0x800109130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_3_0x80010D130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_4_0x800111130301143F; + + } + else if ( rank_group == 2 ) + { + + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_0_0x800102130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_1_0x800106130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_2_0x80010A130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_3_0x80010E130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_4_0x800112130301143F; + + } + else if ( rank_group == 3 ) + { + + GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_0_0x800103130301143F; + GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_1_0x800107130301143F; + GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_2_0x80010B130301143F; + GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_3_0x80010F130301143F; + GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_4_0x800113130301143F; + + } + } + + rc_num = rc_num | data_buffer_64.flushTo0(); + if(rc_num) + { + rc.setEcmdError(rc_num); + return rc; + } + + //BLOCK 0 + rc = fapiPutScom(i_target, GATE_DELAY_ADDR_0, data_buffer_64); + if (rc) return rc; + //BLOCK 1 + rc = fapiPutScom(i_target, GATE_DELAY_ADDR_1, data_buffer_64); + if (rc) return rc; + //BLOCK 2 + rc = fapiPutScom(i_target, GATE_DELAY_ADDR_2, data_buffer_64); + if (rc) return rc; + //BLOCK 3 + rc = fapiPutScom(i_target, GATE_DELAY_ADDR_3, data_buffer_64); + if (rc) return rc; + //BLOCK 4 + rc = fapiPutScom(i_target, GATE_DELAY_ADDR_4, data_buffer_64); + if (rc) return rc; + + + } + } + + } return rc; @@ -5011,9 +5173,9 @@ ReturnCode mss_rtt_nom_rtt_wr_swap( uint8_t i_mbaPosition, uint32_t i_port_number, uint8_t i_rank, - uint32_t i_rank_pair_group, + uint32_t i_rank_pair_group, uint32_t& io_ccs_inst_cnt, - uint8_t& io_dram_rtt_nom_original + uint8_t& io_dram_rtt_nom_original ) { // Target MBA level @@ -5087,8 +5249,8 @@ ReturnCode mss_rtt_nom_rtt_wr_swap( rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 400, 0, 16); if(rc_num) { - rc.setEcmdError(rc_num); - return rc; + rc.setEcmdError(rc_num); + return rc; } rc = mss_ccs_inst_arry_0( i_target, io_ccs_inst_cnt, @@ -5119,43 +5281,43 @@ ReturnCode mss_rtt_nom_rtt_wr_swap( rc_num = rc_num | csn_8.setBit(0,8); if (i_rank == 0) { - rc_num = rc_num | csn_8.clearBit(0); + rc_num = rc_num | csn_8.clearBit(0); } else if (i_rank == 1) { - rc_num = rc_num | csn_8.clearBit(1); + rc_num = rc_num | csn_8.clearBit(1); } else if (i_rank == 2) { - rc_num = rc_num | csn_8.clearBit(2); + rc_num = rc_num | csn_8.clearBit(2); } else if (i_rank == 3) { - rc_num = rc_num | csn_8.clearBit(3); + rc_num = rc_num | csn_8.clearBit(3); } else if (i_rank == 4) { - rc_num = rc_num | csn_8.clearBit(4); + rc_num = rc_num | csn_8.clearBit(4); } else if (i_rank == 5) { - rc_num = rc_num | csn_8.clearBit(5); + rc_num = rc_num | csn_8.clearBit(5); } else if (i_rank == 6) { - rc_num = rc_num | csn_8.clearBit(6); + rc_num = rc_num | csn_8.clearBit(6); } else if (i_rank == 7) { - rc_num = rc_num | csn_8.clearBit(7); + rc_num = rc_num | csn_8.clearBit(7); } // MRS CMD to CMD spacing = 12 cycles rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 12, 0, 16); if(rc_num) { - rc.setEcmdError(rc_num); - return rc; + rc.setEcmdError(rc_num); + return rc; } FAPI_INF( "Editing RTT_NOM during wr_lvl for %s PORT: %d RP: %d", i_target.toEcmdString(), i_port_number, i_rank_pair_group); @@ -5164,48 +5326,48 @@ ReturnCode mss_rtt_nom_rtt_wr_swap( // Get contents of MRS 1 Shadow Reg if (i_port_number == 0){ - if (i_rank_pair_group == 0) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP0_P0_0x8000C01D0301143F, data_buffer_64); - if(rc) return rc; - } - else if (i_rank_pair_group == 1) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP1_P0_0x8000C11D0301143F, data_buffer_64); - if(rc) return rc; - } - else if (i_rank_pair_group == 2) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP2_P0_0x8000C21D0301143F, data_buffer_64); - if(rc) return rc; - } - else if (i_rank_pair_group == 3) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP3_P0_0x8000C31D0301143F, data_buffer_64); - if(rc) return rc; - } + if (i_rank_pair_group == 0) + { + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP0_P0_0x8000C01D0301143F, data_buffer_64); + if(rc) return rc; + } + else if (i_rank_pair_group == 1) + { + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP1_P0_0x8000C11D0301143F, data_buffer_64); + if(rc) return rc; + } + else if (i_rank_pair_group == 2) + { + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP2_P0_0x8000C21D0301143F, data_buffer_64); + if(rc) return rc; + } + else if (i_rank_pair_group == 3) + { + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP3_P0_0x8000C31D0301143F, data_buffer_64); + if(rc) return rc; + } } else if (i_port_number == 1){ - if (i_rank_pair_group == 0) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP0_P1_0x8001C01D0301143F, data_buffer_64); - if(rc) return rc; - } - else if (i_rank_pair_group == 1) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP1_P1_0x8001C11D0301143F, data_buffer_64); - if(rc) return rc; - } - else if (i_rank_pair_group == 2) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP2_P1_0x8001C21D0301143F, data_buffer_64); - if(rc) return rc; - } - else if (i_rank_pair_group == 3) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP3_P1_0x8001C31D0301143F, data_buffer_64); - if(rc) return rc; - } + if (i_rank_pair_group == 0) + { + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP0_P1_0x8001C01D0301143F, data_buffer_64); + if(rc) return rc; + } + else if (i_rank_pair_group == 1) + { + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP1_P1_0x8001C11D0301143F, data_buffer_64); + if(rc) return rc; + } + else if (i_rank_pair_group == 2) + { + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP2_P1_0x8001C21D0301143F, data_buffer_64); + if(rc) return rc; + } + else if (i_rank_pair_group == 3) + { + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP3_P1_0x8001C31D0301143F, data_buffer_64); + if(rc) return rc; + } } rc_num = rc_num | data_buffer_64.reverse(); @@ -5213,171 +5375,171 @@ ReturnCode mss_rtt_nom_rtt_wr_swap( rc_num = rc_num | mrs1_16.extractPreserve(&MRS1, 0, 16, 0); if(rc_num) { - rc.setEcmdError(rc_num); - return rc; + rc.setEcmdError(rc_num); + return rc; } FAPI_INF( "CURRENT MRS 1: 0x%04X", MRS1); uint8_t dll_enable = 0x00; //DLL Enable if (mrs1_16.isBitSet(0)) { - // DLL disabled - dll_enable = 0xFF; + // DLL disabled + dll_enable = 0xFF; } else if (mrs1_16.isBitClear(0)) { - // DLL enabled - dll_enable = 0x00; + // DLL enabled + dll_enable = 0x00; } uint8_t out_drv_imp_cntl = 0x00; if ( (mrs1_16.isBitClear(1)) && (mrs1_16.isBitClear(5)) ) { - // out_drv_imp_ctrl set to 40 (Rzq/6) - out_drv_imp_cntl = 0x00; + // out_drv_imp_ctrl set to 40 (Rzq/6) + out_drv_imp_cntl = 0x00; } else if ( (mrs1_16.isBitSet(1)) && (mrs1_16.isBitClear(5)) ) { - // out_drv_imp_ctrl set to 34 (Rzq/7) - out_drv_imp_cntl = 0x80; + // out_drv_imp_ctrl set to 34 (Rzq/7) + out_drv_imp_cntl = 0x80; } uint8_t dram_rtt_nom = 0x00; if ( (mrs1_16.isBitClear(2)) && (mrs1_16.isBitClear(6)) && (mrs1_16.isBitClear(9)) ) { - // RTT_NOM set to disabled - FAPI_INF( "DRAM_RTT_NOM orignally set to Disabled."); - dram_rtt_nom = 0x00; + // RTT_NOM set to disabled + FAPI_INF( "DRAM_RTT_NOM orignally set to Disabled."); + dram_rtt_nom = 0x00; } else if ( (mrs1_16.isBitClear(2)) && (mrs1_16.isBitClear(6)) && (mrs1_16.isBitSet(9)) ) { - // RTT_NOM set to 20 - FAPI_INF( "DRAM_RTT_NOM orignally set to 20 Ohm."); - dram_rtt_nom = 0x20; + // RTT_NOM set to 20 + FAPI_INF( "DRAM_RTT_NOM orignally set to 20 Ohm."); + dram_rtt_nom = 0x20; } else if ( (mrs1_16.isBitSet(2)) && (mrs1_16.isBitClear(6)) && (mrs1_16.isBitSet(9)) ) { - // RTT_NOM set to 30 - FAPI_INF( "DRAM_RTT_NOM orignally set to 30 Ohm."); - dram_rtt_nom = 0xA0; + // RTT_NOM set to 30 + FAPI_INF( "DRAM_RTT_NOM orignally set to 30 Ohm."); + dram_rtt_nom = 0xA0; } else if ( (mrs1_16.isBitSet(2)) && (mrs1_16.isBitSet(6)) && (mrs1_16.isBitClear(9)) ) { - // RTT_NOM set to 40 - FAPI_INF( "DRAM_RTT_NOM orignally set to 40 Ohm."); - dram_rtt_nom = 0xC0; + // RTT_NOM set to 40 + FAPI_INF( "DRAM_RTT_NOM orignally set to 40 Ohm."); + dram_rtt_nom = 0xC0; } else if ( (mrs1_16.isBitSet(2)) && (mrs1_16.isBitSet(6)) && (mrs1_16.isBitClear(9)) ) { // RTT_NOM set to 60 - FAPI_INF( "DRAM_RTT_NOM orignally set to 60 Ohm."); - dram_rtt_nom = 0x80; + FAPI_INF( "DRAM_RTT_NOM orignally set to 60 Ohm."); + dram_rtt_nom = 0x80; } else if ( (mrs1_16.isBitClear(2)) && (mrs1_16.isBitSet(6)) && (mrs1_16.isBitClear(9)) ) { - // RTT_NOM set to 120 - FAPI_INF( "DRAM_RTT_NOM orignally set to 120 Ohm."); - dram_rtt_nom = 0x40; + // RTT_NOM set to 120 + FAPI_INF( "DRAM_RTT_NOM orignally set to 120 Ohm."); + dram_rtt_nom = 0x40; } uint8_t dram_al = 0x00; if ( (mrs1_16.isBitClear(3)) && (mrs1_16.isBitClear(4)) ) { - //AL DISABLED + //AL DISABLED dram_al = 0x00; } else if ( (mrs1_16.isBitSet(3)) && (mrs1_16.isBitClear(4)) ) { - // AL = CL -1 + // AL = CL -1 dram_al = 0x80; } else if ( (mrs1_16.isBitClear(3)) && (mrs1_16.isBitSet(4)) ) { - // AL = CL -2 + // AL = CL -2 dram_al = 0x40; } uint8_t wr_lvl = 0x00; //write leveling enable if (mrs1_16.isBitClear(7)) { - // WR_LVL DISABLED + // WR_LVL DISABLED wr_lvl = 0x00; } else if (mrs1_16.isBitSet(7)) { - // WR_LVL ENABLED + // WR_LVL ENABLED wr_lvl = 0xFF; } uint8_t tdqs_enable = 0x00; //TDQS Enable if (mrs1_16.isBitClear(11)) { - //TDQS DISABLED + //TDQS DISABLED tdqs_enable = 0x00; } else if (mrs1_16.isBitSet(11)) { - //TDQS ENABLED + //TDQS ENABLED tdqs_enable = 0xFF; } uint8_t q_off = 0x00; //Qoff - Output buffer Enable if (mrs1_16.isBitSet(12)) { - //Output Buffer Disabled + //Output Buffer Disabled q_off = 0xFF; } else if (mrs1_16.isBitClear(12)) { - //Output Buffer Enabled + //Output Buffer Enabled q_off = 0x00; } // Get contents of MRS 2 Shadow Reg if (i_port_number == 0){ - if (i_rank_pair_group == 0) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP0_P0_0x8000C01E0301143F, data_buffer_64); - if(rc) return rc; - } - else if (i_rank_pair_group == 1) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP1_P0_0x8000C11E0301143F, data_buffer_64); - if(rc) return rc; + if (i_rank_pair_group == 0) + { + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP0_P0_0x8000C01E0301143F, data_buffer_64); + if(rc) return rc; + } + else if (i_rank_pair_group == 1) + { + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP1_P0_0x8000C11E0301143F, data_buffer_64); + if(rc) return rc; } else if (i_rank_pair_group == 2) { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP2_P0_0x8000C21E0301143F, data_buffer_64); - if(rc) return rc; + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP2_P0_0x8000C21E0301143F, data_buffer_64); + if(rc) return rc; } else if (i_rank_pair_group == 3) { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP3_P0_0x8000C31E0301143F, data_buffer_64); - if(rc) return rc; + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP3_P0_0x8000C31E0301143F, data_buffer_64); + if(rc) return rc; } } else if (i_port_number == 1){ - if (i_rank_pair_group == 0) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP0_P1_0x8001C01E0301143F, data_buffer_64); - if(rc) return rc; - } - else if (i_rank_pair_group == 1) - { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP1_P1_0x8001C11E0301143F, data_buffer_64); - if(rc) return rc; + if (i_rank_pair_group == 0) + { + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP0_P1_0x8001C01E0301143F, data_buffer_64); + if(rc) return rc; + } + else if (i_rank_pair_group == 1) + { + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP1_P1_0x8001C11E0301143F, data_buffer_64); + if(rc) return rc; } else if (i_rank_pair_group == 2) { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP2_P1_0x8001C21E0301143F, data_buffer_64); - if(rc) return rc; + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP2_P1_0x8001C21E0301143F, data_buffer_64); + if(rc) return rc; } else if (i_rank_pair_group == 3) { - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP3_P1_0x8001C31E0301143F, data_buffer_64); - if(rc) return rc; + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP3_P1_0x8001C31E0301143F, data_buffer_64); + if(rc) return rc; } } @@ -5386,40 +5548,40 @@ ReturnCode mss_rtt_nom_rtt_wr_swap( rc_num = rc_num | mrs2_16.extractPreserve(&MRS2, 0, 16, 0); if(rc_num) { - rc.setEcmdError(rc_num); - return rc; + rc.setEcmdError(rc_num); + return rc; } FAPI_INF( "MRS 2: 0x%04X", MRS2); uint8_t dram_rtt_wr = 0x00; if ( (mrs2_16.isBitClear(9)) && (mrs2_16.isBitClear(10)) ) { - //RTT WR DISABLE - FAPI_INF( "DRAM_RTT_WR currently set to Disable."); - dram_rtt_wr = 0x00; + //RTT WR DISABLE + FAPI_INF( "DRAM_RTT_WR currently set to Disable."); + dram_rtt_wr = 0x00; - //RTT NOM CODE FOR THIS VALUE IS - // dram_rtt_nom = 0x00 + //RTT NOM CODE FOR THIS VALUE IS + // dram_rtt_nom = 0x00 } else if ( (mrs2_16.isBitSet(9)) && (mrs2_16.isBitClear(10)) ) { - //RTT WR 60 OHM - FAPI_INF( "DRAM_RTT_WR currently set to 60 Ohm."); - dram_rtt_wr = 0x80; + //RTT WR 60 OHM + FAPI_INF( "DRAM_RTT_WR currently set to 60 Ohm."); + dram_rtt_wr = 0x80; //RTT NOM CODE FOR THIS VALUE IS - // dram_rtt_nom = 0x80 + // dram_rtt_nom = 0x80 } else if ( (mrs2_16.isBitClear(9)) && (mrs2_16.isBitSet(10)) ) { - //RTT WR 120 OHM - FAPI_INF( "DRAM_RTT_WR currently set to 120 Ohm."); - dram_rtt_wr = 0x40; + //RTT WR 120 OHM + FAPI_INF( "DRAM_RTT_WR currently set to 120 Ohm."); + dram_rtt_wr = 0x40; //RTT NOM CODE FOR THIS VALUE IS - // dram_rtt_nom = 0x40 + // dram_rtt_nom = 0x40 } @@ -5428,62 +5590,62 @@ ReturnCode mss_rtt_nom_rtt_wr_swap( // you will use dram_rtt_nom_original to save the original value if (io_dram_rtt_nom_original == 0xFF) { - io_dram_rtt_nom_original = dram_rtt_nom; - dram_rtt_nom = dram_rtt_wr; - - if (dram_rtt_wr == 0x00) - { - FAPI_INF( "DRAM_RTT_NOM to be set to DRAM_RTT_WR which is Disable."); - } - else if (dram_rtt_wr == 0x80) - { - FAPI_INF( "DRAM_RTT_NOM to be set to DRAM_RTT_WR which is 60 Ohm."); - } - else if (dram_rtt_wr == 0x40) - { - FAPI_INF( "DRAM_RTT_NOM to be set to DRAM_RTT_WR which is 120 Ohm."); - } + io_dram_rtt_nom_original = dram_rtt_nom; + dram_rtt_nom = dram_rtt_wr; + + if (dram_rtt_wr == 0x00) + { + FAPI_INF( "DRAM_RTT_NOM to be set to DRAM_RTT_WR which is Disable."); + } + else if (dram_rtt_wr == 0x80) + { + FAPI_INF( "DRAM_RTT_NOM to be set to DRAM_RTT_WR which is 60 Ohm."); + } + else if (dram_rtt_wr == 0x40) + { + FAPI_INF( "DRAM_RTT_NOM to be set to DRAM_RTT_WR which is 120 Ohm."); + } } else if (io_dram_rtt_nom_original != 0xFF) { - dram_rtt_nom = io_dram_rtt_nom_original; - - if ( dram_rtt_nom == 0x00 ) - { - // RTT_NOM set to disabled - FAPI_INF( "DRAM_RTT_NOM being set back to Disabled."); - - } - else if ( dram_rtt_nom == 0x20 ) - { - // RTT_NOM set to 20 - FAPI_INF( "DRAM_RTT_NOM being set back to 20 Ohm."); - } - else if ( dram_rtt_nom == 0xA0 ) - { - // RTT_NOM set to 30 - FAPI_INF( "DRAM_RTT_NOM being set back to 30 Ohm."); - } - else if ( dram_rtt_nom == 0xC0 ) - { - // RTT_NOM set to 40 - FAPI_INF( "DRAM_RTT_NOM being set back to 40 Ohm."); - } - else if ( dram_rtt_nom == 0x80 ) - { - // RTT_NOM set to 60 - FAPI_INF( "DRAM_RTT_NOM being set back to 60 Ohm."); - } - else if ( dram_rtt_nom == 0x40 ) - { - // RTT_NOM set to 120 - FAPI_INF( "DRAM_RTT_NOM being set back to 120 Ohm."); - } - else - { - FAPI_INF( "Proposed DRAM_RTT_NOM value is a non-supported. Using Disabled."); - dram_rtt_nom = 0x00; - } + dram_rtt_nom = io_dram_rtt_nom_original; + + if ( dram_rtt_nom == 0x00 ) + { + // RTT_NOM set to disabled + FAPI_INF( "DRAM_RTT_NOM being set back to Disabled."); + + } + else if ( dram_rtt_nom == 0x20 ) + { + // RTT_NOM set to 20 + FAPI_INF( "DRAM_RTT_NOM being set back to 20 Ohm."); + } + else if ( dram_rtt_nom == 0xA0 ) + { + // RTT_NOM set to 30 + FAPI_INF( "DRAM_RTT_NOM being set back to 30 Ohm."); + } + else if ( dram_rtt_nom == 0xC0 ) + { + // RTT_NOM set to 40 + FAPI_INF( "DRAM_RTT_NOM being set back to 40 Ohm."); + } + else if ( dram_rtt_nom == 0x80 ) + { + // RTT_NOM set to 60 + FAPI_INF( "DRAM_RTT_NOM being set back to 60 Ohm."); + } + else if ( dram_rtt_nom == 0x40 ) + { + // RTT_NOM set to 120 + FAPI_INF( "DRAM_RTT_NOM being set back to 120 Ohm."); + } + else + { + FAPI_INF( "Proposed DRAM_RTT_NOM value is a non-supported. Using Disabled."); + dram_rtt_nom = 0x00; + } } @@ -5516,45 +5678,45 @@ ReturnCode mss_rtt_nom_rtt_wr_swap( if ( ( address_mirror_map[i_port_number][dimm] & (0x08 >> dimm_rank) ) && (is_sim == 0)) { - //dimm and rank are only for print trace only, functionally not needed - rc = mss_address_mirror_swizzle(i_target, i_port_number, dimm, dimm_rank, address_16, bank_3); - if(rc) return rc; + //dimm and rank are only for print trace only, functionally not needed + rc = mss_address_mirror_swizzle(i_target, i_port_number, dimm, dimm_rank, address_16, bank_3); + if(rc) return rc; } if (rc_num) { - FAPI_ERR( "mss_mrs_load: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; + FAPI_ERR( "mss_mrs_load: Error setting up buffers"); + rc_buff.setEcmdError(rc_num); + return rc_buff; } ccs_end_1.setBit(0); // Send out to the CCS array rc = mss_ccs_inst_arry_0( i_target, - io_ccs_inst_cnt, - address_16, - bank_3, - activate_1, - rasn_1, - casn_1, - wen_1, - cke_4, - csn_8, - odt_4, - ddr_cal_type_4, - i_port_number); + io_ccs_inst_cnt, + address_16, + bank_3, + activate_1, + rasn_1, + casn_1, + wen_1, + cke_4, + csn_8, + odt_4, + ddr_cal_type_4, + i_port_number); if(rc) return rc; rc = mss_ccs_inst_arry_1( i_target, - io_ccs_inst_cnt, - num_idles_16, - num_repeat_16, - data_20, - read_compare_1, - rank_cal_4, - ddr_cal_enable_1, - ccs_end_1); + io_ccs_inst_cnt, + num_idles_16, + num_repeat_16, + data_20, + read_compare_1, + rank_cal_4, + ddr_cal_enable_1, + ccs_end_1); if(rc) return rc; uint32_t NUM_POLL = 100; @@ -5572,83 +5734,83 @@ ReturnCode mss_rtt_nom_rtt_wr_swap( fapi::ReturnCode mss_set_bbm_regs (const fapi::Target & mba_target) { // Flash to registers. - // disable0=dq bits, disable1=dqs(+,-) - // wrclk_en=dqs follows quad, same as disable0 - - const uint64_t disable_reg[MAX_PORTS][MAX_PRI_RANKS][DP18_INSTANCES] = { - /* port 0 */ - { // primary rank pair 0 - {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_0_0x8000007c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_1_0x8000047c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_2_0x8000087c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_3_0x80000c7c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_4_0x8000107c0301143F}, - // primary rank pair 1 - {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_0_0x8000017c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_1_0x8000057c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_2_0x8000097c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_3_0x80000d7c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_4_0x8000117c0301143F}, - // primary rank pair 2 - {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_0_0x8000027c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_1_0x8000067c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_2_0x80000a7c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_3_0x80000e7c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_4_0x8000127c0301143F}, - // primary rank pair 3 - {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_0_0x8000037c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_1_0x8000077c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_2_0x80000b7c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_3_0x80000f7c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_4_0x8000137c0301143F} - }, - /* port 1 */ - { - // primary rank pair 0 - {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_0_0x8001007c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_1_0x8001047c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_2_0x8001087c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_3_0x80010c7c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_4_0x8001107c0301143F}, + // disable0=dq bits, disable1=dqs(+,-) + // wrclk_en=dqs follows quad, same as disable0 + + const uint64_t disable_reg[MAX_PORTS][MAX_PRI_RANKS][DP18_INSTANCES] = { + /* port 0 */ + { // primary rank pair 0 + {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_0_0x8000007c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_1_0x8000047c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_2_0x8000087c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_3_0x80000c7c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_4_0x8000107c0301143F}, + // primary rank pair 1 + {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_0_0x8000017c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_1_0x8000057c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_2_0x8000097c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_3_0x80000d7c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_4_0x8000117c0301143F}, + // primary rank pair 2 + {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_0_0x8000027c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_1_0x8000067c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_2_0x80000a7c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_3_0x80000e7c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_4_0x8000127c0301143F}, + // primary rank pair 3 + {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_0_0x8000037c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_1_0x8000077c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_2_0x80000b7c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_3_0x80000f7c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_4_0x8000137c0301143F} + }, + /* port 1 */ + { + // primary rank pair 0 + {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_0_0x8001007c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_1_0x8001047c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_2_0x8001087c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_3_0x80010c7c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_4_0x8001107c0301143F}, // primary rank p1 - {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_0_0x8001017c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_1_0x8001057c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_2_0x8001097c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_3_0x80010d7c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_4_0x8001117c0301143F}, + {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_0_0x8001017c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_1_0x8001057c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_2_0x8001097c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_3_0x80010d7c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_4_0x8001117c0301143F}, // primary rank pair 2 - {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_0_0x8001027c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_1_0x8001067c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_2_0x80010a7c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_3_0x80010e7c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_4_0x8001127c0301143F}, + {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_0_0x8001027c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_1_0x8001067c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_2_0x80010a7c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_3_0x80010e7c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_4_0x8001127c0301143F}, // primary rank pair 3 - {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_0_0x8001037c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_1_0x8001077c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_2_0x80010b7c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_3_0x80010f7c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_4_0x8001137c0301143F} - }}; - const uint8_t rg_invalid[] = { - ENUM_ATTR_EFF_PRIMARY_RANK_GROUP0_INVALID, - ENUM_ATTR_EFF_PRIMARY_RANK_GROUP1_INVALID, - ENUM_ATTR_EFF_PRIMARY_RANK_GROUP2_INVALID, - ENUM_ATTR_EFF_PRIMARY_RANK_GROUP3_INVALID, - }; - - const uint16_t wrclk_disable_mask[] = { // by quads - 0x8800, 0x4400, 0x2280, 0x1140 - }; - - uint8_t l_dram_width, l_disable1_fixed, l_disable1_rdclk_fixed; - uint64_t l_addr; - // 0x8000007d0301143f from disable0 register - const uint64_t l_disable1_addr_offset = 0x0000000100000000ull; - // 0x800000050301143f from disable1 register - const uint64_t l_wrclk_en_addr_mask = 0xFFFFFF07FFFFFFFFull; - - ReturnCode rc; - ecmdDataBufferBase data_buffer(64); + {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_0_0x8001037c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_1_0x8001077c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_2_0x80010b7c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_3_0x80010f7c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_4_0x8001137c0301143F} + }}; + const uint8_t rg_invalid[] = { + ENUM_ATTR_EFF_PRIMARY_RANK_GROUP0_INVALID, + ENUM_ATTR_EFF_PRIMARY_RANK_GROUP1_INVALID, + ENUM_ATTR_EFF_PRIMARY_RANK_GROUP2_INVALID, + ENUM_ATTR_EFF_PRIMARY_RANK_GROUP3_INVALID, + }; + + const uint16_t wrclk_disable_mask[] = { // by quads + 0x8800, 0x4400, 0x2280, 0x1140 + }; + + uint8_t l_dram_width, l_disable1_fixed, l_disable1_rdclk_fixed; + uint64_t l_addr; + // 0x8000007d0301143f from disable0 register + const uint64_t l_disable1_addr_offset = 0x0000000100000000ull; + // 0x800000050301143f from disable1 register + const uint64_t l_wrclk_en_addr_mask = 0xFFFFFF07FFFFFFFFull; + + ReturnCode rc; + ecmdDataBufferBase data_buffer(64); ecmdDataBufferBase db_reg(BITS_PER_PORT); ecmdDataBufferBase db_reg_rank0(BITS_PER_PORT); ecmdDataBufferBase db_reg_rank1(BITS_PER_PORT); @@ -5658,691 +5820,691 @@ fapi::ReturnCode mss_set_bbm_regs (const fapi::Target & mba_target) ecmdDataBufferBase db_reg_rank5(BITS_PER_PORT); ecmdDataBufferBase db_reg_rank6(BITS_PER_PORT); ecmdDataBufferBase db_reg_rank7(BITS_PER_PORT); - uint32_t l_ecmdRc = ECMD_DBUF_SUCCESS; - uint8_t prg[MAX_PRI_RANKS][MAX_PORTS]; // primary rank group values + uint32_t l_ecmdRc = ECMD_DBUF_SUCCESS; + uint8_t prg[MAX_PRI_RANKS][MAX_PORTS]; // primary rank group values - FAPI_INF("Running flash->registers(set)"); + FAPI_INF("Running flash->registers(set)"); - std::vector<Target> mba_dimms; - rc = fapiGetAssociatedDimms(mba_target, mba_dimms); // functional dimms - if(rc) return rc; + std::vector<Target> mba_dimms; + rc = fapiGetAssociatedDimms(mba_target, mba_dimms); // functional dimms + if(rc) return rc; + + // ATTR_EFF_PRIMARY_RANK_GROUP0[port], GROUP1[port], + // GROUP2[port], GROUP3[port] + rc=FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP0, &mba_target, prg[0]); + if(rc) return rc; + rc=FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP1, &mba_target, prg[1]); + if(rc) return rc; + rc=FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP2, &mba_target, prg[2]); + if(rc) return rc; + rc=FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP3, &mba_target, prg[3]); + if(rc) return rc; - // ATTR_EFF_PRIMARY_RANK_GROUP0[port], GROUP1[port], - // GROUP2[port], GROUP3[port] - rc=FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP0, &mba_target, prg[0]); - if(rc) return rc; - rc=FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP1, &mba_target, prg[1]); - if(rc) return rc; - rc=FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP2, &mba_target, prg[2]); - if(rc) return rc; - rc=FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP3, &mba_target, prg[3]); - if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &mba_target, l_dram_width); + if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &mba_target, l_dram_width); - if(rc) return rc; - fapi::Target l_target_centaur; rc = fapiGetParentChip(mba_target, l_target_centaur); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_MSS_DISABLE1_REG_FIXED, &l_target_centaur, l_disable1_fixed); + rc = FAPI_ATTR_GET(ATTR_MSS_DISABLE1_REG_FIXED, &l_target_centaur, l_disable1_fixed); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_MSS_DISABLE1_RDCLK_REG_FIXED, &l_target_centaur, l_disable1_rdclk_fixed); + rc = FAPI_ATTR_GET(ATTR_MSS_DISABLE1_RDCLK_REG_FIXED, &l_target_centaur, l_disable1_rdclk_fixed); if(rc) return rc; - switch (l_dram_width) - { - case ENUM_ATTR_EFF_DRAM_WIDTH_X4: - l_dram_width = 4; - break; - case ENUM_ATTR_EFF_DRAM_WIDTH_X8: - l_dram_width = 8; - break; - case ENUM_ATTR_EFF_DRAM_WIDTH_X16: - l_dram_width = 16; - break; - case ENUM_ATTR_EFF_DRAM_WIDTH_X32: - l_dram_width = 32; - break; - default: - //DECONFIG and FFDC INFO - const fapi::Target & TARGET_MBA_ERROR = mba_target; + switch (l_dram_width) + { + case ENUM_ATTR_EFF_DRAM_WIDTH_X4: + l_dram_width = 4; + break; + case ENUM_ATTR_EFF_DRAM_WIDTH_X8: + l_dram_width = 8; + break; + case ENUM_ATTR_EFF_DRAM_WIDTH_X16: + l_dram_width = 16; + break; + case ENUM_ATTR_EFF_DRAM_WIDTH_X32: + l_dram_width = 32; + break; + default: + //DECONFIG and FFDC INFO + const fapi::Target & TARGET_MBA_ERROR = mba_target; const uint8_t & WIDTH = l_dram_width; - FAPI_ERR("ATTR_EFF_DRAM_WIDTH is invalid %u", l_dram_width); - FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_DRAM_WIDTH_INPUT_ERROR_SETBBM); - return rc; - } - - l_ecmdRc = data_buffer.flushTo0(); - if (l_ecmdRc != ECMD_DBUF_SUCCESS) - { - FAPI_ERR("Error from ecmdDataBuffer flushTo0() " - "- rc 0x%.8X", l_ecmdRc); - rc.setEcmdError(l_ecmdRc); - return rc; - } - for (uint8_t port = 0; port < MAX_PORTS; port++ ) // [0:1] - { - db_reg_rank0.flushTo0(); - db_reg_rank1.flushTo0(); - db_reg_rank2.flushTo0(); - db_reg_rank3.flushTo0(); - db_reg_rank4.flushTo0(); - db_reg_rank5.flushTo0(); - db_reg_rank6.flushTo0(); - db_reg_rank7.flushTo0(); - uint8_t is_clean = 1; - - uint8_t l_rank0_invalid = 1; //0 = valid, 1 = invalid - uint8_t l_rank1_invalid = 1; - uint8_t l_rank2_invalid = 1; - uint8_t l_rank3_invalid = 1; - uint8_t l_rank4_invalid = 1; - uint8_t l_rank5_invalid = 1; - uint8_t l_rank6_invalid = 1; - uint8_t l_rank7_invalid = 1; - - // Gather all ranks first - // loop through primary ranks [0:3] - for (uint8_t prank = 0; prank < MAX_PRI_RANKS; prank++ ) - { - - is_clean = 1; - if (prg[prank][port] == rg_invalid[prank]) // invalid rank - { - FAPI_DBG("BYTE DISABLE WORKAROUND Primary rank group (prank) %i port %d rank value: %d INVALID, Marking and continuing...", - prank, port, prg[prank][port]); - - continue; - } - - if ( prg[prank][port] == 0) - { - FAPI_DBG("BYTE DISABLE WORKAROUND Primary rank group (prank) %i port %d rank value: %d Not INVALID, Marking and continuing...", - prank, port, prg[prank][port]); - rc = getC4dq2reg(mba_target, port, 0, 0, db_reg_rank0, is_clean); - if (rc) - { - FAPI_ERR("Error from getting register bitmap port=%i: " - "dimm=%i, rank=%i rc=%i", port, 0, 0, - static_cast<uint32_t>(rc)); - return rc; - } - l_rank0_invalid = 0; - } - - if ( prg[prank][port] == 1) - { - FAPI_DBG("BYTE DISABLE WORKAROUND Primary rank group (prank) %i port %d rank value: %d Not INVALID, Marking and continuing...", - prank, port, prg[prank][port]); - rc = getC4dq2reg(mba_target, port, 0, 1, db_reg_rank1, is_clean); - if (rc) - { - FAPI_ERR("Error from getting register bitmap port=%i: " - "dimm=%i, rank=%i rc=%i", port, 0, 1, - static_cast<uint32_t>(rc)); - return rc; - } - l_rank1_invalid = 0; - } - - if ( prg[prank][port] == 2) - { - FAPI_DBG("BYTE DISABLE WORKAROUND Primary rank group (prank) %i port %d rank value: %d Not INVALID, Marking and continuing...", - prank, port, prg[prank][port]); - rc = getC4dq2reg(mba_target, port, 0, 2, db_reg_rank2, is_clean); - if (rc) - { - FAPI_ERR("Error from getting register bitmap port=%i: " - "dimm=%i, rank=%i rc=%i", port, 0, 2, - static_cast<uint32_t>(rc)); - return rc; - } - l_rank2_invalid = 0; - } - - - if ( prg[prank][port] == 3) - { - FAPI_DBG("BYTE DISABLE WORKAROUND Primary rank group (prank) %i port %d rank value: %d Not INVALID, Marking and continuing...", - prank, port, prg[prank][port]); - rc = getC4dq2reg(mba_target, port, 0, 3, db_reg_rank3, is_clean); - if (rc) - { - FAPI_ERR("Error from getting register bitmap port=%i: " - "dimm=%i, rank=%i rc=%i", port, 0, 3, - static_cast<uint32_t>(rc)); - return rc; - } - l_rank3_invalid = 0; - } - - - - if ( prg[prank][port] == 4) - { - FAPI_DBG("BYTE DISABLE WORKAROUND Primary rank group (prank) %i port %d rank value: %d Not INVALID, Marking and continuing...", - prank, port, prg[prank][port]); - rc = getC4dq2reg(mba_target, port, 1, 0, db_reg_rank4, is_clean); - if (rc) - { - FAPI_ERR("Error from getting register bitmap port=%i: " - "dimm=%i, rank=%i rc=%i", port, 1, 0, - static_cast<uint32_t>(rc)); - return rc; - } - l_rank4_invalid = 0; - } - - - if ( prg[prank][port] == 5) - { - FAPI_DBG("BYTE DISABLE WORKAROUND Primary rank group (prank) %i port %d rank value: %d Not INVALID, Marking and continuing...", - prank, port, prg[prank][port]); - rc = getC4dq2reg(mba_target, port, 1, 1, db_reg_rank5, is_clean); - if (rc) - { - FAPI_ERR("Error from getting register bitmap port=%i: " - "dimm=%i, rank=%i rc=%i", port, 1, 1, - static_cast<uint32_t>(rc)); - return rc; - } - l_rank5_invalid = 0; - } - - - if ( prg[prank][port] == 6) - { - FAPI_DBG("BYTE DISABLE WORKAROUND Primary rank group (prank) %i port %d rank value: %d Not INVALID, Marking and continuing...", - prank, port, prg[prank][port]); - rc = getC4dq2reg(mba_target, port, 1, 2, db_reg_rank6, is_clean); - if (rc) - { - FAPI_ERR("Error from getting register bitmap port=%i: " - "dimm=%i, rank=%i rc=%i", port, 1, 2, - static_cast<uint32_t>(rc)); - return rc; - } - l_rank6_invalid = 0; - } - - - if ( prg[prank][port] == 7) - { - FAPI_DBG("BYTE DISABLE WORKAROUND Primary rank group (prank) %i port %d rank value: %d Not INVALID, Marking and continuing...", - prank, port, prg[prank][port]); - rc = getC4dq2reg(mba_target, port, 1, 3, db_reg_rank7, is_clean); - if (rc) - { - FAPI_ERR("Error from getting register bitmap port=%i: " - "dimm=%i, rank=%i rc=%i", port, 1, 3, - static_cast<uint32_t>(rc)); - return rc; - } - l_rank7_invalid = 0; - } - - } - - // loop through primary ranks [0:3] - for (uint8_t prank = 0; prank < MAX_PRI_RANKS; prank++ ) - { - uint8_t dimm = prg[prank][port] >> 2; - uint8_t rank = prg[prank][port] & 0x03; - uint16_t l_data = 0; - uint16_t l_data_rank0 = 0; - uint16_t l_data_rank1 = 0; - uint16_t l_data_rank2 = 0; - uint16_t l_data_rank3 = 0; - uint16_t l_data_rank4 = 0; - uint16_t l_data_rank5 = 0; - uint16_t l_data_rank6 = 0; - uint16_t l_data_rank7 = 0; - is_clean = 1; - - if (prg[prank][port] == rg_invalid[prank]) // invalid rank - { - FAPI_DBG("Primary rank group %i: INVALID, continuing...", - prank); - continue; - } - - rc = getC4dq2reg(mba_target, port, dimm, rank, db_reg, is_clean); - if (rc) - { - FAPI_ERR("Error from getting register bitmap port=%i: " - "dimm=%i, rank=%i rc=%i", port, dimm, rank, - static_cast<uint32_t>(rc)); - return rc; - } - - - - // quick test to move on to next rank if no bits need to be set - if (is_clean == 1) // Note ignores spares that match attribute - { - FAPI_INF("Primary rank group %i: No bad bits found for " - "p%i:d%i:r%i:cs%i", prank, port, dimm, rank, - prg[prank][port]); - continue; - } - for ( uint8_t i=0; i < DP18_INSTANCES; i++ ) // dp18 [0:4] - { - uint8_t disable1_data = 0; - uint16_t wrclk_mask = 0; - - // check or not to check(always set register)? - l_data = db_reg.getHalfWord(i); - l_data_rank0 = db_reg_rank0.getHalfWord(i); - l_data_rank1 = db_reg_rank1.getHalfWord(i); - l_data_rank2 = db_reg_rank2.getHalfWord(i); - l_data_rank3 = db_reg_rank3.getHalfWord(i); - l_data_rank4 = db_reg_rank4.getHalfWord(i); - l_data_rank5 = db_reg_rank5.getHalfWord(i); - l_data_rank6 = db_reg_rank6.getHalfWord(i); - l_data_rank7 = db_reg_rank7.getHalfWord(i); - - if (l_data == 0) - { - FAPI_DBG("\tDP18_%i has no bad bits set, continuing...", i); - continue; - } - // clear bits 48:63 - l_ecmdRc = data_buffer.flushTo0(); - if (l_ecmdRc != ECMD_DBUF_SUCCESS) - { - FAPI_ERR("Error from ecmdDataBuffer flushTo0() " - "- rc 0x%.8X", l_ecmdRc); - - rc.setEcmdError(l_ecmdRc); - return rc; - } - - uint16_t mask = 0xF000; - // Temp 0xE removed. - //uint16_t emask = 0xE000; - uint8_t all_F_mask = 0; - for (uint8_t n=0; n < 4; n++) { // check each nibble - uint16_t nmask = mask >> (4*n); - // Temp 0xE removed. - //uint16_t e_nmask = emask >> (4*n); - - - if ((nmask & l_data) == nmask) { - FAPI_DBG("BYTE DISABLE WORKAROUND Found a 0XF on nibble=%i Port%i, dimm=%i, prg%i rank=%i data=0x%04X", n, port, dimm, prank, rank, l_data); - if ( ( ((nmask & l_data_rank0) == nmask) || (l_rank0_invalid) ) && - ( ((nmask & l_data_rank1) == nmask) || (l_rank1_invalid) ) && - ( ((nmask & l_data_rank2) == nmask) || (l_rank2_invalid) ) && - ( ((nmask & l_data_rank3) == nmask) || (l_rank3_invalid) ) && - ( ((nmask & l_data_rank4) == nmask) || (l_rank4_invalid) ) && - ( ((nmask & l_data_rank5) == nmask) || (l_rank5_invalid) ) && - ( ((nmask & l_data_rank6) == nmask) || (l_rank6_invalid) ) && - ( ((nmask & l_data_rank7) == nmask) || (l_rank7_invalid) ) ) - { - //Leave it an F. - FAPI_DBG("BYTE DISABLE WORKAROUND All ranks are a F so writing an 0xF to disable regs."); - FAPI_DBG("BYTE DISABLE WORKAROUND data rank 0 =0x%04X rank 1 =0x%04X rank 2 =0x%04X rank 3 =0x%04X rank 4 =0x%04X rank 5 =0x%04X rank 6 =0x%04X rank 7 =0x%04X", l_data_rank0,l_data_rank1,l_data_rank2,l_data_rank3,l_data_rank4,l_data_rank5,l_data_rank6,l_data_rank7 ); - all_F_mask = 1; - } - else - { - //Replacing F nibble with E nibble - FAPI_DBG("BYTE DISABLE WORKAROUND Single rank is a 0xF so writing an 0x0 to disable regs. PRE DATA: 0x%04X", l_data); - l_data = l_data & ~(nmask); - FAPI_DBG("BYTE DISABLE WORKAROUND POST DATA: 0x%04X", l_data); - } - } - - // Temporarily removing the 0xE case - /* - if ((nmask & l_data) == e_nmask) { - FAPI_DBG("BYTE DISABLE WORKAROUND Found a 0XE on nibble=%i Port%i, dimm=%i, prg%i rank=%i data=0x%04X", n, port, dimm, prank, rank, l_data); - - //Leave it an E. - FAPI_DBG("BYTE DISABLE WORKAROUND Found a 0xE so writing an 0xE to disable regs."); - - } - */ - - uint16_t wrclk_nmask = 0xF000 >> (4*n); - if (l_dram_width != 4) // x8 only disable the wrclk - { - - if (((wrclk_nmask & l_data)>>(4*(3-n))) == 0x0F) - { - wrclk_mask |= wrclk_disable_mask[n]; - } - } - - } - - - if (all_F_mask ==1) { - FAPI_INF("Entering into all F across all ranks case. Need to Disable WRCLK Enable as well."); - for (uint8_t n=0; n < 4; n++) // check each nibble - { - uint16_t nmask = 0xF000 >> (4*n); - if (l_dram_width == 4) - { - if ((nmask & l_data) == nmask) // bad bit(s) in nibble - { - // For Marc Gollub, since repair for x4 DRAM is in nibble - // granularity. Also due to higher chance of hitting dq0 of - // Micron causing write leveling to fail for entire x4 DRAM. - // Will also save a re-training loop. Complement in get_bbm_regs. - - - FAPI_INF("Disabling entire nibble %i",n); - rc = mss_get_dqs_lane(mba_target, port, i, n, - disable1_data); - if (rc) return rc; - wrclk_mask |= wrclk_disable_mask[n]; - } - } // end x4 - else // width == 8+? - { - if ((n % 2) == 0) - { - nmask = 0xFF00 >> (4*n); - if ((nmask & l_data) == nmask) // entire byte bad - { - disable1_data |= (0xF0 >> (n*2)); - } - } - if (((nmask & l_data)>>(4*(3-n))) == 0x0F) - { - wrclk_mask |= wrclk_disable_mask[n]; - } - } - } - - } - - - FAPI_DBG("\t\tdisable1_data=0x%04X", disable1_data); - - // set disable0(dq) reg - l_ecmdRc |= data_buffer.setHalfWord(3, l_data); - - if (l_ecmdRc != ECMD_DBUF_SUCCESS) - { - FAPI_ERR("Error from ecmdDataBuffer setHalfWord() " - "- rc 0x%.8X", l_ecmdRc); - - rc.setEcmdError(l_ecmdRc); - return rc; - } - - l_addr = disable_reg[port][prank][i]; - - FAPI_INF("+++ Setting Disable0 Bad Bit Mask p%i: DIMM%i PRG%i " - "Rank%i dp18_%i addr=0x%llx, data=0x%04X", port, - dimm, prank, prg[prank][port], i, l_addr , l_data); - - rc = fapiPutScomUnderMask(mba_target, l_addr, data_buffer, - data_buffer); - - if (rc) - { - FAPI_ERR("Error from fapiPutScom writing disable0 reg"); - return rc; - } - - if (all_F_mask ==1) { - FAPI_INF("Entering into all F across ranks case. Need to Disable DQS as well."); - // set address for disable1(dqs) register - l_addr += l_disable1_addr_offset; - if (disable1_data != 0) - { - l_ecmdRc = data_buffer.flushTo0(); // clear buffer - if (l_ecmdRc != ECMD_DBUF_SUCCESS) - { - FAPI_ERR("Error from ecmdDataBuffer flushTo0() " - "- rc 0x%.8X", l_ecmdRc); - - rc.setEcmdError(l_ecmdRc); - return rc; - } - - l_ecmdRc = data_buffer.setByte(6, disable1_data); - if (l_ecmdRc != ECMD_DBUF_SUCCESS) - { - FAPI_ERR("Error from ecmdDataBuffer setByte() " - "- rc 0x%.8X", l_ecmdRc); - - rc.setEcmdError(l_ecmdRc); - return rc; - } - - // write disable1(dqs) register - rc = fapiPutScomUnderMask(mba_target, l_addr, - data_buffer, data_buffer); - if (rc) - { - FAPI_ERR("Error from PutScom writing disable1 reg"); - return rc; - } - } // end disable1_data != 0 - - - // set address for wrclk_en register - l_addr &= l_wrclk_en_addr_mask; - - if (wrclk_mask != 0) - { - l_ecmdRc = data_buffer.flushTo0(); // clear buffer - if (l_ecmdRc != ECMD_DBUF_SUCCESS) - { - FAPI_ERR("Error from ecmdDataBuffer flushTo0() " - "- rc 0x%.8X", l_ecmdRc); - - rc.setEcmdError(l_ecmdRc); - return rc; - } - ecmdDataBufferBase put_mask(64); - l_ecmdRc = put_mask.setHalfWord(3, wrclk_mask); - if (l_ecmdRc != ECMD_DBUF_SUCCESS) - { - FAPI_ERR("Error from ecmdDataBuffer setHalfWord()" - " for wrclk_mask - rc 0x%.8X", l_ecmdRc); - - rc.setEcmdError(l_ecmdRc); - return rc; - } - - if (!l_disable1_fixed) - { - // clear(0) out the unused quads for wrclkdb_reg - rc = fapiPutScomUnderMask(mba_target, l_addr, - data_buffer, put_mask); - if (rc) - { - FAPI_ERR("Error from fapiPutScomUnderMask writing " - "wrclk_en reg"); - return rc; - } - } - // does disabling read clocks for unused bytes cause problems? - // SW25701 Workaround - x4s will not mask out RDCLKs on Bad Bits to avoid translation issues - else if ( (!l_disable1_rdclk_fixed) && (l_dram_width != 4) ) - { - uint64_t rdclk_addr = - disable_reg[port][prank][i] & 0xFFFFFF040FFFFFFFull; - // clear(0) out the unused quads for rdclk - rc = fapiPutScomUnderMask(mba_target, rdclk_addr, - data_buffer, put_mask); - if (rc) - { - FAPI_ERR("Error from fapiPutScomUnderMask writing " - "rdclk_en reg"); - return rc; - } - - FAPI_DBG("rdclk_addr=0x%llx, wrclk_addr=0x%llx, " - "wrclk_mask=0x%04X", rdclk_addr, l_addr, wrclk_mask); - } - } // end wrclk_mask != 0 - } - - - } // end DP18 instance loop - } // end primary rank loop - } // end port loop + FAPI_ERR("ATTR_EFF_DRAM_WIDTH is invalid %u", l_dram_width); + FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_DRAM_WIDTH_INPUT_ERROR_SETBBM); + return rc; + } + + l_ecmdRc = data_buffer.flushTo0(); + if (l_ecmdRc != ECMD_DBUF_SUCCESS) + { + FAPI_ERR("Error from ecmdDataBuffer flushTo0() " + "- rc 0x%.8X", l_ecmdRc); + rc.setEcmdError(l_ecmdRc); + return rc; + } + for (uint8_t port = 0; port < MAX_PORTS; port++ ) // [0:1] + { + db_reg_rank0.flushTo0(); + db_reg_rank1.flushTo0(); + db_reg_rank2.flushTo0(); + db_reg_rank3.flushTo0(); + db_reg_rank4.flushTo0(); + db_reg_rank5.flushTo0(); + db_reg_rank6.flushTo0(); + db_reg_rank7.flushTo0(); + uint8_t is_clean = 1; + + uint8_t l_rank0_invalid = 1; //0 = valid, 1 = invalid + uint8_t l_rank1_invalid = 1; + uint8_t l_rank2_invalid = 1; + uint8_t l_rank3_invalid = 1; + uint8_t l_rank4_invalid = 1; + uint8_t l_rank5_invalid = 1; + uint8_t l_rank6_invalid = 1; + uint8_t l_rank7_invalid = 1; + + // Gather all ranks first + // loop through primary ranks [0:3] + for (uint8_t prank = 0; prank < MAX_PRI_RANKS; prank++ ) + { + + is_clean = 1; + if (prg[prank][port] == rg_invalid[prank]) // invalid rank + { + FAPI_DBG("BYTE DISABLE WORKAROUND Primary rank group (prank) %i port %d rank value: %d INVALID, Marking and continuing...", + prank, port, prg[prank][port]); + + continue; + } + + if ( prg[prank][port] == 0) + { + FAPI_DBG("BYTE DISABLE WORKAROUND Primary rank group (prank) %i port %d rank value: %d Not INVALID, Marking and continuing...", + prank, port, prg[prank][port]); + rc = getC4dq2reg(mba_target, port, 0, 0, db_reg_rank0, is_clean); + if (rc) + { + FAPI_ERR("Error from getting register bitmap port=%i: " + "dimm=%i, rank=%i rc=%i", port, 0, 0, + static_cast<uint32_t>(rc)); + return rc; + } + l_rank0_invalid = 0; + } + + if ( prg[prank][port] == 1) + { + FAPI_DBG("BYTE DISABLE WORKAROUND Primary rank group (prank) %i port %d rank value: %d Not INVALID, Marking and continuing...", + prank, port, prg[prank][port]); + rc = getC4dq2reg(mba_target, port, 0, 1, db_reg_rank1, is_clean); + if (rc) + { + FAPI_ERR("Error from getting register bitmap port=%i: " + "dimm=%i, rank=%i rc=%i", port, 0, 1, + static_cast<uint32_t>(rc)); + return rc; + } + l_rank1_invalid = 0; + } + + if ( prg[prank][port] == 2) + { + FAPI_DBG("BYTE DISABLE WORKAROUND Primary rank group (prank) %i port %d rank value: %d Not INVALID, Marking and continuing...", + prank, port, prg[prank][port]); + rc = getC4dq2reg(mba_target, port, 0, 2, db_reg_rank2, is_clean); + if (rc) + { + FAPI_ERR("Error from getting register bitmap port=%i: " + "dimm=%i, rank=%i rc=%i", port, 0, 2, + static_cast<uint32_t>(rc)); + return rc; + } + l_rank2_invalid = 0; + } + + + if ( prg[prank][port] == 3) + { + FAPI_DBG("BYTE DISABLE WORKAROUND Primary rank group (prank) %i port %d rank value: %d Not INVALID, Marking and continuing...", + prank, port, prg[prank][port]); + rc = getC4dq2reg(mba_target, port, 0, 3, db_reg_rank3, is_clean); + if (rc) + { + FAPI_ERR("Error from getting register bitmap port=%i: " + "dimm=%i, rank=%i rc=%i", port, 0, 3, + static_cast<uint32_t>(rc)); + return rc; + } + l_rank3_invalid = 0; + } + + + + if ( prg[prank][port] == 4) + { + FAPI_DBG("BYTE DISABLE WORKAROUND Primary rank group (prank) %i port %d rank value: %d Not INVALID, Marking and continuing...", + prank, port, prg[prank][port]); + rc = getC4dq2reg(mba_target, port, 1, 0, db_reg_rank4, is_clean); + if (rc) + { + FAPI_ERR("Error from getting register bitmap port=%i: " + "dimm=%i, rank=%i rc=%i", port, 1, 0, + static_cast<uint32_t>(rc)); + return rc; + } + l_rank4_invalid = 0; + } + + + if ( prg[prank][port] == 5) + { + FAPI_DBG("BYTE DISABLE WORKAROUND Primary rank group (prank) %i port %d rank value: %d Not INVALID, Marking and continuing...", + prank, port, prg[prank][port]); + rc = getC4dq2reg(mba_target, port, 1, 1, db_reg_rank5, is_clean); + if (rc) + { + FAPI_ERR("Error from getting register bitmap port=%i: " + "dimm=%i, rank=%i rc=%i", port, 1, 1, + static_cast<uint32_t>(rc)); + return rc; + } + l_rank5_invalid = 0; + } + + + if ( prg[prank][port] == 6) + { + FAPI_DBG("BYTE DISABLE WORKAROUND Primary rank group (prank) %i port %d rank value: %d Not INVALID, Marking and continuing...", + prank, port, prg[prank][port]); + rc = getC4dq2reg(mba_target, port, 1, 2, db_reg_rank6, is_clean); + if (rc) + { + FAPI_ERR("Error from getting register bitmap port=%i: " + "dimm=%i, rank=%i rc=%i", port, 1, 2, + static_cast<uint32_t>(rc)); + return rc; + } + l_rank6_invalid = 0; + } + + + if ( prg[prank][port] == 7) + { + FAPI_DBG("BYTE DISABLE WORKAROUND Primary rank group (prank) %i port %d rank value: %d Not INVALID, Marking and continuing...", + prank, port, prg[prank][port]); + rc = getC4dq2reg(mba_target, port, 1, 3, db_reg_rank7, is_clean); + if (rc) + { + FAPI_ERR("Error from getting register bitmap port=%i: " + "dimm=%i, rank=%i rc=%i", port, 1, 3, + static_cast<uint32_t>(rc)); + return rc; + } + l_rank7_invalid = 0; + } + + } + + // loop through primary ranks [0:3] + for (uint8_t prank = 0; prank < MAX_PRI_RANKS; prank++ ) + { + uint8_t dimm = prg[prank][port] >> 2; + uint8_t rank = prg[prank][port] & 0x03; + uint16_t l_data = 0; + uint16_t l_data_rank0 = 0; + uint16_t l_data_rank1 = 0; + uint16_t l_data_rank2 = 0; + uint16_t l_data_rank3 = 0; + uint16_t l_data_rank4 = 0; + uint16_t l_data_rank5 = 0; + uint16_t l_data_rank6 = 0; + uint16_t l_data_rank7 = 0; + is_clean = 1; + + if (prg[prank][port] == rg_invalid[prank]) // invalid rank + { + FAPI_DBG("Primary rank group %i: INVALID, continuing...", + prank); + continue; + } + + rc = getC4dq2reg(mba_target, port, dimm, rank, db_reg, is_clean); + if (rc) + { + FAPI_ERR("Error from getting register bitmap port=%i: " + "dimm=%i, rank=%i rc=%i", port, dimm, rank, + static_cast<uint32_t>(rc)); + return rc; + } + + + + // quick test to move on to next rank if no bits need to be set + if (is_clean == 1) // Note ignores spares that match attribute + { + FAPI_INF("Primary rank group %i: No bad bits found for " + "p%i:d%i:r%i:cs%i", prank, port, dimm, rank, + prg[prank][port]); + continue; + } + for ( uint8_t i=0; i < DP18_INSTANCES; i++ ) // dp18 [0:4] + { + uint8_t disable1_data = 0; + uint16_t wrclk_mask = 0; + + // check or not to check(always set register)? + l_data = db_reg.getHalfWord(i); + l_data_rank0 = db_reg_rank0.getHalfWord(i); + l_data_rank1 = db_reg_rank1.getHalfWord(i); + l_data_rank2 = db_reg_rank2.getHalfWord(i); + l_data_rank3 = db_reg_rank3.getHalfWord(i); + l_data_rank4 = db_reg_rank4.getHalfWord(i); + l_data_rank5 = db_reg_rank5.getHalfWord(i); + l_data_rank6 = db_reg_rank6.getHalfWord(i); + l_data_rank7 = db_reg_rank7.getHalfWord(i); + + if (l_data == 0) + { + FAPI_DBG("\tDP18_%i has no bad bits set, continuing...", i); + continue; + } + // clear bits 48:63 + l_ecmdRc = data_buffer.flushTo0(); + if (l_ecmdRc != ECMD_DBUF_SUCCESS) + { + FAPI_ERR("Error from ecmdDataBuffer flushTo0() " + "- rc 0x%.8X", l_ecmdRc); + + rc.setEcmdError(l_ecmdRc); + return rc; + } + + uint16_t mask = 0xF000; + // Temp 0xE removed. + //uint16_t emask = 0xE000; + uint8_t all_F_mask = 0; + for (uint8_t n=0; n < 4; n++) { // check each nibble + uint16_t nmask = mask >> (4*n); + // Temp 0xE removed. + //uint16_t e_nmask = emask >> (4*n); + + + if ((nmask & l_data) == nmask) { + FAPI_DBG("BYTE DISABLE WORKAROUND Found a 0XF on nibble=%i Port%i, dimm=%i, prg%i rank=%i data=0x%04X", n, port, dimm, prank, rank, l_data); + if ( ( ((nmask & l_data_rank0) == nmask) || (l_rank0_invalid) ) && + ( ((nmask & l_data_rank1) == nmask) || (l_rank1_invalid) ) && + ( ((nmask & l_data_rank2) == nmask) || (l_rank2_invalid) ) && + ( ((nmask & l_data_rank3) == nmask) || (l_rank3_invalid) ) && + ( ((nmask & l_data_rank4) == nmask) || (l_rank4_invalid) ) && + ( ((nmask & l_data_rank5) == nmask) || (l_rank5_invalid) ) && + ( ((nmask & l_data_rank6) == nmask) || (l_rank6_invalid) ) && + ( ((nmask & l_data_rank7) == nmask) || (l_rank7_invalid) ) ) + { + //Leave it an F. + FAPI_DBG("BYTE DISABLE WORKAROUND All ranks are a F so writing an 0xF to disable regs."); + FAPI_DBG("BYTE DISABLE WORKAROUND data rank 0 =0x%04X rank 1 =0x%04X rank 2 =0x%04X rank 3 =0x%04X rank 4 =0x%04X rank 5 =0x%04X rank 6 =0x%04X rank 7 =0x%04X", l_data_rank0,l_data_rank1,l_data_rank2,l_data_rank3,l_data_rank4,l_data_rank5,l_data_rank6,l_data_rank7 ); + all_F_mask = 1; + } + else + { + //Replacing F nibble with E nibble + FAPI_DBG("BYTE DISABLE WORKAROUND Single rank is a 0xF so writing an 0x0 to disable regs. PRE DATA: 0x%04X", l_data); + l_data = l_data & ~(nmask); + FAPI_DBG("BYTE DISABLE WORKAROUND POST DATA: 0x%04X", l_data); + } + } + + // Temporarily removing the 0xE case + /* + if ((nmask & l_data) == e_nmask) { + FAPI_DBG("BYTE DISABLE WORKAROUND Found a 0XE on nibble=%i Port%i, dimm=%i, prg%i rank=%i data=0x%04X", n, port, dimm, prank, rank, l_data); + + //Leave it an E. + FAPI_DBG("BYTE DISABLE WORKAROUND Found a 0xE so writing an 0xE to disable regs."); + + } + */ + + uint16_t wrclk_nmask = 0xF000 >> (4*n); + if (l_dram_width != 4) // x8 only disable the wrclk + { + + if (((wrclk_nmask & l_data)>>(4*(3-n))) == 0x0F) + { + wrclk_mask |= wrclk_disable_mask[n]; + } + } + + } + + + if (all_F_mask ==1) { + FAPI_INF("Entering into all F across all ranks case. Need to Disable WRCLK Enable as well."); + for (uint8_t n=0; n < 4; n++) // check each nibble + { + uint16_t nmask = 0xF000 >> (4*n); + if (l_dram_width == 4) + { + if ((nmask & l_data) == nmask) // bad bit(s) in nibble + { + // For Marc Gollub, since repair for x4 DRAM is in nibble + // granularity. Also due to higher chance of hitting dq0 of + // Micron causing write leveling to fail for entire x4 DRAM. + // Will also save a re-training loop. Complement in get_bbm_regs. + + + FAPI_INF("Disabling entire nibble %i",n); + rc = mss_get_dqs_lane(mba_target, port, i, n, + disable1_data); + if (rc) return rc; + wrclk_mask |= wrclk_disable_mask[n]; + } + } // end x4 + else // width == 8+? + { + if ((n % 2) == 0) + { + nmask = 0xFF00 >> (4*n); + if ((nmask & l_data) == nmask) // entire byte bad + { + disable1_data |= (0xF0 >> (n*2)); + } + } + if (((nmask & l_data)>>(4*(3-n))) == 0x0F) + { + wrclk_mask |= wrclk_disable_mask[n]; + } + } + } + + } + + + FAPI_DBG("\t\tdisable1_data=0x%04X", disable1_data); + + // set disable0(dq) reg + l_ecmdRc |= data_buffer.setHalfWord(3, l_data); + + if (l_ecmdRc != ECMD_DBUF_SUCCESS) + { + FAPI_ERR("Error from ecmdDataBuffer setHalfWord() " + "- rc 0x%.8X", l_ecmdRc); + + rc.setEcmdError(l_ecmdRc); + return rc; + } + + l_addr = disable_reg[port][prank][i]; + + FAPI_INF("+++ Setting Disable0 Bad Bit Mask p%i: DIMM%i PRG%i " + "Rank%i dp18_%i addr=0x%llx, data=0x%04X", port, + dimm, prank, prg[prank][port], i, l_addr , l_data); + + rc = fapiPutScomUnderMask(mba_target, l_addr, data_buffer, + data_buffer); + + if (rc) + { + FAPI_ERR("Error from fapiPutScom writing disable0 reg"); + return rc; + } + + if (all_F_mask ==1) { + FAPI_INF("Entering into all F across ranks case. Need to Disable DQS as well."); + // set address for disable1(dqs) register + l_addr += l_disable1_addr_offset; + if (disable1_data != 0) + { + l_ecmdRc = data_buffer.flushTo0(); // clear buffer + if (l_ecmdRc != ECMD_DBUF_SUCCESS) + { + FAPI_ERR("Error from ecmdDataBuffer flushTo0() " + "- rc 0x%.8X", l_ecmdRc); + + rc.setEcmdError(l_ecmdRc); + return rc; + } + + l_ecmdRc = data_buffer.setByte(6, disable1_data); + if (l_ecmdRc != ECMD_DBUF_SUCCESS) + { + FAPI_ERR("Error from ecmdDataBuffer setByte() " + "- rc 0x%.8X", l_ecmdRc); + + rc.setEcmdError(l_ecmdRc); + return rc; + } + + // write disable1(dqs) register + rc = fapiPutScomUnderMask(mba_target, l_addr, + data_buffer, data_buffer); + if (rc) + { + FAPI_ERR("Error from PutScom writing disable1 reg"); + return rc; + } + } // end disable1_data != 0 + + + // set address for wrclk_en register + l_addr &= l_wrclk_en_addr_mask; + + if (wrclk_mask != 0) + { + l_ecmdRc = data_buffer.flushTo0(); // clear buffer + if (l_ecmdRc != ECMD_DBUF_SUCCESS) + { + FAPI_ERR("Error from ecmdDataBuffer flushTo0() " + "- rc 0x%.8X", l_ecmdRc); + + rc.setEcmdError(l_ecmdRc); + return rc; + } + ecmdDataBufferBase put_mask(64); + l_ecmdRc = put_mask.setHalfWord(3, wrclk_mask); + if (l_ecmdRc != ECMD_DBUF_SUCCESS) + { + FAPI_ERR("Error from ecmdDataBuffer setHalfWord()" + " for wrclk_mask - rc 0x%.8X", l_ecmdRc); + + rc.setEcmdError(l_ecmdRc); + return rc; + } + + if (!l_disable1_fixed) + { + // clear(0) out the unused quads for wrclkdb_reg + rc = fapiPutScomUnderMask(mba_target, l_addr, + data_buffer, put_mask); + if (rc) + { + FAPI_ERR("Error from fapiPutScomUnderMask writing " + "wrclk_en reg"); + return rc; + } + } + // does disabling read clocks for unused bytes cause problems? + // SW25701 Workaround - x4s will not mask out RDCLKs on Bad Bits to avoid translation issues + else if ( (!l_disable1_rdclk_fixed) && (l_dram_width != 4) ) + { + uint64_t rdclk_addr = + disable_reg[port][prank][i] & 0xFFFFFF040FFFFFFFull; + // clear(0) out the unused quads for rdclk + rc = fapiPutScomUnderMask(mba_target, rdclk_addr, + data_buffer, put_mask); + if (rc) + { + FAPI_ERR("Error from fapiPutScomUnderMask writing " + "rdclk_en reg"); + return rc; + } + + FAPI_DBG("rdclk_addr=0x%llx, wrclk_addr=0x%llx, " + "wrclk_mask=0x%04X", rdclk_addr, l_addr, wrclk_mask); + } + } // end wrclk_mask != 0 + } + + + } // end DP18 instance loop + } // end primary rank loop + } // end port loop return rc; } // end mss_set_bbm_regs fapi::ReturnCode mss_get_dqs_lane (const fapi::Target & i_mba, - const uint8_t i_port, const uint8_t i_block, const uint8_t i_quad, - uint8_t &o_lane) + const uint8_t i_port, const uint8_t i_block, const uint8_t i_quad, + uint8_t &o_lane) { // input = mba, port, dp18 block, quad // output = OR'd in lane of the dqs for the specified input - ReturnCode rc; - uint8_t dq, dqs; - uint8_t phy_lane = i_quad * 4; - uint8_t l_block = i_block; - // returns dq - rc=mss_c4_phy(i_mba,i_port,0,RD_DQ,dq,1,phy_lane,l_block,1); - if (rc) return rc; - FAPI_INF("DQ returning mss_c4_phy inputs port: %d input index: %d phy_lane: %d block: %d",i_port,dq,phy_lane,l_block); - - dqs = dq / 4; - // returns phy_lane - rc=mss_c4_phy(i_mba,i_port,0,WR_DQS,dqs,1,phy_lane,l_block,0); - if (rc) return rc; - FAPI_INF("phy_lane returning mss_c4_phy inputs port: %d input index: %d phy_lane: %d block: %d",i_port,dqs,phy_lane,l_block); - - if (l_block != i_block) - { - FAPI_ERR("\t !!! blocks don't match from c4 to phy i_block=%i," - " o_block=%i", i_block, l_block); - } - - switch (phy_lane) - { - case 16: - case 17: - o_lane |= 0xC0; - break; - case 18: - case 19: - o_lane |= 0x30; - break; - case 20: - case 21: - o_lane |= 0x0C; - break; - case 22: - case 23: - o_lane |= 0x03; - break; - default: - //DECONFIG and FFDC INFO - const fapi::Target & TARGET_MBA_ERROR = i_mba; - const uint8_t & PORT = i_port; - const uint8_t & BLOCK = i_block; - const uint8_t & QUAD = i_quad; - const uint8_t & PHYLANE = phy_lane; - - FAPI_ERR("\t!!! (Port%i, dp18_%i, q=%i) phy_lane(%i)" - "returned from mss_c4_phy is invalid", - i_port, i_block, i_quad, phy_lane); - FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_C4_PHY_TRANSLATION_ERROR); - } - return rc; + ReturnCode rc; + uint8_t dq, dqs; + uint8_t phy_lane = i_quad * 4; + uint8_t l_block = i_block; + // returns dq + rc=mss_c4_phy(i_mba,i_port,0,RD_DQ,dq,1,phy_lane,l_block,1); + if (rc) return rc; + FAPI_INF("DQ returning mss_c4_phy inputs port: %d input index: %d phy_lane: %d block: %d",i_port,dq,phy_lane,l_block); + + dqs = dq / 4; + // returns phy_lane + rc=mss_c4_phy(i_mba,i_port,0,WR_DQS,dqs,1,phy_lane,l_block,0); + if (rc) return rc; + FAPI_INF("phy_lane returning mss_c4_phy inputs port: %d input index: %d phy_lane: %d block: %d",i_port,dqs,phy_lane,l_block); + + if (l_block != i_block) + { + FAPI_ERR("\t !!! blocks don't match from c4 to phy i_block=%i," + " o_block=%i", i_block, l_block); + } + + switch (phy_lane) + { + case 16: + case 17: + o_lane |= 0xC0; + break; + case 18: + case 19: + o_lane |= 0x30; + break; + case 20: + case 21: + o_lane |= 0x0C; + break; + case 22: + case 23: + o_lane |= 0x03; + break; + default: + //DECONFIG and FFDC INFO + const fapi::Target & TARGET_MBA_ERROR = i_mba; + const uint8_t & PORT = i_port; + const uint8_t & BLOCK = i_block; + const uint8_t & QUAD = i_quad; + const uint8_t & PHYLANE = phy_lane; + + FAPI_ERR("\t!!! (Port%i, dp18_%i, q=%i) phy_lane(%i)" + "returned from mss_c4_phy is invalid", + i_port, i_block, i_quad, phy_lane); + FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_C4_PHY_TRANSLATION_ERROR); + } + return rc; } //end mss_get_dqs_lane fapi::ReturnCode mss_get_bbm_regs (const fapi::Target & mba_target, uint8_t i_training_success) { // Registers to Flash. - const uint64_t disable_reg[MAX_PORTS][MAX_PRI_RANKS][DP18_INSTANCES] = { - /* port 0 */ - { // primary rank pair 0 - {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_0_0x8000007c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_1_0x8000047c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_2_0x8000087c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_3_0x80000c7c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_4_0x8000107c0301143F}, - // primary rank pair 1 - {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_0_0x8000017c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_1_0x8000057c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_2_0x8000097c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_3_0x80000d7c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_4_0x8000117c0301143F}, - // primary rank pair 2 - {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_0_0x8000027c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_1_0x8000067c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_2_0x80000a7c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_3_0x80000e7c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_4_0x8000127c0301143F}, - // primary rank pair 3 - {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_0_0x8000037c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_1_0x8000077c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_2_0x80000b7c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_3_0x80000f7c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_4_0x8000137c0301143F} - }, - /* port 1 */ - { - // primary rank pair 0 - {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_0_0x8001007c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_1_0x8001047c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_2_0x8001087c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_3_0x80010c7c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_4_0x8001107c0301143F}, + const uint64_t disable_reg[MAX_PORTS][MAX_PRI_RANKS][DP18_INSTANCES] = { + /* port 0 */ + { // primary rank pair 0 + {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_0_0x8000007c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_1_0x8000047c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_2_0x8000087c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_3_0x80000c7c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_4_0x8000107c0301143F}, + // primary rank pair 1 + {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_0_0x8000017c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_1_0x8000057c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_2_0x8000097c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_3_0x80000d7c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_4_0x8000117c0301143F}, + // primary rank pair 2 + {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_0_0x8000027c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_1_0x8000067c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_2_0x80000a7c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_3_0x80000e7c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_4_0x8000127c0301143F}, + // primary rank pair 3 + {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_0_0x8000037c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_1_0x8000077c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_2_0x80000b7c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_3_0x80000f7c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_4_0x8000137c0301143F} + }, + /* port 1 */ + { + // primary rank pair 0 + {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_0_0x8001007c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_1_0x8001047c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_2_0x8001087c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_3_0x80010c7c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_4_0x8001107c0301143F}, // primary rank pair 1 - {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_0_0x8001017c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_1_0x8001057c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_2_0x8001097c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_3_0x80010d7c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_4_0x8001117c0301143F}, + {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_0_0x8001017c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_1_0x8001057c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_2_0x8001097c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_3_0x80010d7c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_4_0x8001117c0301143F}, // primary rank pair 2 - {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_0_0x8001027c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_1_0x8001067c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_2_0x80010a7c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_3_0x80010e7c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_4_0x8001127c0301143F}, + {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_0_0x8001027c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_1_0x8001067c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_2_0x80010a7c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_3_0x80010e7c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_4_0x8001127c0301143F}, // primary rank pair 3 - {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_0_0x8001037c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_1_0x8001077c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_2_0x80010b7c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_3_0x80010f7c0301143F, - DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_4_0x8001137c0301143F} + {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_0_0x8001037c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_1_0x8001077c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_2_0x80010b7c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_3_0x80010f7c0301143F, + DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_4_0x8001137c0301143F} - }}; + }}; - const uint8_t rg_invalid[] = { - ENUM_ATTR_EFF_PRIMARY_RANK_GROUP0_INVALID, - ENUM_ATTR_EFF_PRIMARY_RANK_GROUP1_INVALID, - ENUM_ATTR_EFF_PRIMARY_RANK_GROUP2_INVALID, - ENUM_ATTR_EFF_PRIMARY_RANK_GROUP3_INVALID, - }; + const uint8_t rg_invalid[] = { + ENUM_ATTR_EFF_PRIMARY_RANK_GROUP0_INVALID, + ENUM_ATTR_EFF_PRIMARY_RANK_GROUP1_INVALID, + ENUM_ATTR_EFF_PRIMARY_RANK_GROUP2_INVALID, + ENUM_ATTR_EFF_PRIMARY_RANK_GROUP3_INVALID, + }; ReturnCode rc; ecmdDataBufferBase data_buffer(64); ecmdDataBufferBase db_reg(BITS_PER_PORT); ecmdDataBufferBase db_reg_vpd(BITS_PER_PORT); - uint32_t l_ecmdRc = ECMD_DBUF_SUCCESS; - uint8_t prg[MAX_PRI_RANKS][MAX_PORTS]; // primary rank group values - uint8_t l_dram_width; - uint8_t dimm; - uint8_t l_rank0_invalid = 1; //0 = valid, 1 = invalid - uint8_t l_rank1_invalid = 1; - uint8_t l_rank2_invalid = 1; - uint8_t l_rank3_invalid = 1; - uint8_t l_rank4_invalid = 1; - uint8_t l_rank5_invalid = 1; - uint8_t l_rank6_invalid = 1; - uint8_t l_rank7_invalid = 1; - - //Storing all the errors across rank/eff dimm + uint32_t l_ecmdRc = ECMD_DBUF_SUCCESS; + uint8_t prg[MAX_PRI_RANKS][MAX_PORTS]; // primary rank group values + uint8_t l_dram_width; + uint8_t dimm; + uint8_t l_rank0_invalid = 1; //0 = valid, 1 = invalid + uint8_t l_rank1_invalid = 1; + uint8_t l_rank2_invalid = 1; + uint8_t l_rank3_invalid = 1; + uint8_t l_rank4_invalid = 1; + uint8_t l_rank5_invalid = 1; + uint8_t l_rank6_invalid = 1; + uint8_t l_rank7_invalid = 1; + + //Storing all the errors across rank/eff dimm ecmdDataBufferBase db_reg_dimm0_rank0(BITS_PER_PORT); ecmdDataBufferBase db_reg_dimm0_rank1(BITS_PER_PORT); ecmdDataBufferBase db_reg_dimm0_rank2(BITS_PER_PORT); @@ -6353,843 +6515,843 @@ fapi::ReturnCode mss_get_bbm_regs (const fapi::Target & mba_target, uint8_t i_tr ecmdDataBufferBase db_reg_dimm1_rank3(BITS_PER_PORT); - FAPI_INF("Running (get)registers->flash"); - - std::vector<Target> mba_dimms; - rc = fapiGetAssociatedDimms(mba_target, mba_dimms); // functional dimms - if(rc) return rc; - - // 4 dimms per MBA, 2 per port - // ATTR_EFF_PRIMARY_RANK_GROUP0[port], GROUP1[port], - // GROUP2[port], GROUP3[port] - rc=FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP0, &mba_target, prg[0]); - if(rc) return rc; - rc=FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP1, &mba_target, prg[1]); - if(rc) return rc; - rc=FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP2, &mba_target, prg[2]); - if(rc) return rc; - rc=FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP3, &mba_target, prg[3]); - if(rc) return rc; - - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &mba_target, l_dram_width); - if(rc) return rc; - - switch (l_dram_width) - { - case ENUM_ATTR_EFF_DRAM_WIDTH_X4: - l_dram_width = 4; - break; - case ENUM_ATTR_EFF_DRAM_WIDTH_X8: - l_dram_width = 8; - break; - case ENUM_ATTR_EFF_DRAM_WIDTH_X16: - l_dram_width = 16; - break; - case ENUM_ATTR_EFF_DRAM_WIDTH_X32: - l_dram_width = 32; - break; - default: - //DECONFIG and FFDC INFO - const fapi::Target & TARGET_MBA_ERROR = mba_target; + FAPI_INF("Running (get)registers->flash"); + + std::vector<Target> mba_dimms; + rc = fapiGetAssociatedDimms(mba_target, mba_dimms); // functional dimms + if(rc) return rc; + + // 4 dimms per MBA, 2 per port + // ATTR_EFF_PRIMARY_RANK_GROUP0[port], GROUP1[port], + // GROUP2[port], GROUP3[port] + rc=FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP0, &mba_target, prg[0]); + if(rc) return rc; + rc=FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP1, &mba_target, prg[1]); + if(rc) return rc; + rc=FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP2, &mba_target, prg[2]); + if(rc) return rc; + rc=FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP3, &mba_target, prg[3]); + if(rc) return rc; + + rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &mba_target, l_dram_width); + if(rc) return rc; + + switch (l_dram_width) + { + case ENUM_ATTR_EFF_DRAM_WIDTH_X4: + l_dram_width = 4; + break; + case ENUM_ATTR_EFF_DRAM_WIDTH_X8: + l_dram_width = 8; + break; + case ENUM_ATTR_EFF_DRAM_WIDTH_X16: + l_dram_width = 16; + break; + case ENUM_ATTR_EFF_DRAM_WIDTH_X32: + l_dram_width = 32; + break; + default: + //DECONFIG and FFDC INFO + const fapi::Target & TARGET_MBA_ERROR = mba_target; const uint8_t & WIDTH = l_dram_width; - FAPI_ERR("ATTR_EFF_DRAM_WIDTH is invalid %u", l_dram_width); - FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_DRAM_WIDTH_INPUT_ERROR_GETBBM); - return rc; - } - - l_ecmdRc = data_buffer.flushTo0(); - if (l_ecmdRc != ECMD_DBUF_SUCCESS) - { - FAPI_ERR("Error from ecmdDataBuffer flushTo0() " - "- rc 0x%.8X", l_ecmdRc); - - rc.setEcmdError(l_ecmdRc); - return rc; - } - for (uint8_t port = 0; port < MAX_PORTS; port++ ) // [0:1] - { - // Initialize all the stored errors to 0. - l_ecmdRc |= db_reg_dimm0_rank0.flushTo0(); - l_ecmdRc |= db_reg_dimm0_rank1.flushTo0(); - l_ecmdRc |= db_reg_dimm0_rank2.flushTo0(); - l_ecmdRc |= db_reg_dimm0_rank3.flushTo0(); - l_ecmdRc |= db_reg_dimm1_rank0.flushTo0(); - l_ecmdRc |= db_reg_dimm1_rank1.flushTo0(); - l_ecmdRc |= db_reg_dimm1_rank2.flushTo0(); - l_ecmdRc |= db_reg_dimm1_rank3.flushTo0(); - l_rank0_invalid = 1; //0 = valid, 1 = invalid - l_rank1_invalid = 1; - l_rank2_invalid = 1; - l_rank3_invalid = 1; - l_rank4_invalid = 1; - l_rank5_invalid = 1; - l_rank6_invalid = 1; - l_rank7_invalid = 1; - - if (l_ecmdRc != ECMD_DBUF_SUCCESS) - { - FAPI_ERR("Error from ecmdDataBuffer setHalfWord()" - " for wrclk_mask - rc 0x%.8X", l_ecmdRc); - - rc.setEcmdError(l_ecmdRc); - return rc; - } - - // loop through primary ranks [0:3] - for (uint8_t prank = 0; prank < MAX_PRI_RANKS; prank++ ) - { - dimm = prg[prank][port] >> 2; - uint8_t rank = prg[prank][port] & 0x03; - uint16_t l_data = 0; - - if (prg[prank][port] == rg_invalid[prank]) // invalid rank - { - FAPI_DBG("Primary rank group %i is INVALID, continuing...", - prank); - if ( prg[prank][port] == 0) - { - l_ecmdRc |= db_reg_dimm0_rank0.flushTo1(); - if (l_ecmdRc != ECMD_DBUF_SUCCESS) - { - FAPI_ERR("Error from ecmdDataBuffer setHalfWord() " - "- rc 0x%.8X", l_ecmdRc); - - rc.setEcmdError(l_ecmdRc); - return rc; - } - } - - if ( prg[prank][port] == 1) - { - l_ecmdRc |= db_reg_dimm0_rank1.flushTo1(); - if (l_ecmdRc != ECMD_DBUF_SUCCESS) - { - FAPI_ERR("Error from ecmdDataBuffer setHalfWord() " - "- rc 0x%.8X", l_ecmdRc); - - rc.setEcmdError(l_ecmdRc); - return rc; - } - } - - if ( prg[prank][port] == 2) - { - l_ecmdRc |= db_reg_dimm0_rank2.flushTo1(); - if (l_ecmdRc != ECMD_DBUF_SUCCESS) - { - FAPI_ERR("Error from ecmdDataBuffer setHalfWord() " - "- rc 0x%.8X", l_ecmdRc); - - rc.setEcmdError(l_ecmdRc); - return rc; - } - } - - - if ( prg[prank][port] == 3) - { - l_ecmdRc |= db_reg_dimm0_rank3.flushTo1(); - if (l_ecmdRc != ECMD_DBUF_SUCCESS) - { - FAPI_ERR("Error from ecmdDataBuffer setHalfWord() " - "- rc 0x%.8X", l_ecmdRc); - - rc.setEcmdError(l_ecmdRc); - return rc; - } - } - - - - if ( prg[prank][port] == 4) - { - l_ecmdRc |= db_reg_dimm1_rank0.flushTo1(); - if (l_ecmdRc != ECMD_DBUF_SUCCESS) - { - FAPI_ERR("Error from ecmdDataBuffer setHalfWord() " - "- rc 0x%.8X", l_ecmdRc); - - rc.setEcmdError(l_ecmdRc); - return rc; - } - } - - - if ( prg[prank][port] == 5) - { - l_ecmdRc |= db_reg_dimm1_rank1.flushTo1(); - if (l_ecmdRc != ECMD_DBUF_SUCCESS) - { - FAPI_ERR("Error from ecmdDataBuffer setHalfWord() " - "- rc 0x%.8X", l_ecmdRc); - - rc.setEcmdError(l_ecmdRc); - return rc; - } - } - - - if ( prg[prank][port] == 6) - { - l_ecmdRc |= db_reg_dimm1_rank2.flushTo1(); - if (l_ecmdRc != ECMD_DBUF_SUCCESS) - { - FAPI_ERR("Error from ecmdDataBuffer setHalfWord() " - "- rc 0x%.8X", l_ecmdRc); - - rc.setEcmdError(l_ecmdRc); - return rc; - } - } - - - if ( prg[prank][port] == 7) - { - l_ecmdRc |= db_reg_dimm1_rank3.flushTo1(); - if (l_ecmdRc != ECMD_DBUF_SUCCESS) - { - FAPI_ERR("Error from ecmdDataBuffer setHalfWord() " - "- rc 0x%.8X", l_ecmdRc); - - rc.setEcmdError(l_ecmdRc); - return rc; - } - } - - continue; - } - - // create the db_reg (all the failed bits of the port) - l_ecmdRc = db_reg.flushTo0(); - if (l_ecmdRc != ECMD_DBUF_SUCCESS) - { - FAPI_ERR("Error from ecmdDataBuffer flushTo0() " - "- rc 0x%.8X", l_ecmdRc); - - rc.setEcmdError(l_ecmdRc); - return rc; - } - - FAPI_DBG("Port%i, dimm=%i, prg%i rank=%i", port, dimm, prank, rank); - for ( uint8_t i=0; i < DP18_INSTANCES; i++ ) // dp18 [0:4] - { - // clear bits 48:63 - l_ecmdRc = data_buffer.clearBit(48, BITS_PER_REG); - if (l_ecmdRc != ECMD_DBUF_SUCCESS) - { - FAPI_ERR("Error from ecmdDataBuffer setHalfWord() " - "- rc 0x%.8X", l_ecmdRc); - - rc.setEcmdError(l_ecmdRc); - return rc; - } - - rc = fapiGetScom(mba_target, disable_reg[port][prank][i], - data_buffer); - if (rc) - { - FAPI_ERR("Error from fapiPutScom writing disable reg"); - return rc; - } - - l_data = data_buffer.getHalfWord(3); - - FAPI_DBG("dp18_%i 0x%llx = 0x%x", i, - disable_reg[port][prank][i], l_data); - - if (l_data != 0) - { - - l_ecmdRc = db_reg.setHalfWord(i, l_data); - if (l_ecmdRc != ECMD_DBUF_SUCCESS) - { - FAPI_ERR("Error from ecmdDataBuffer setHalfWord() " - "- rc 0x%.8X", l_ecmdRc); - - rc.setEcmdError(l_ecmdRc); - return rc; - } - - FAPI_INF("+++ Setting Bad Bit Mask p%i: DIMM%i PRG%i " - "Rank%i \tdp18_%i addr=0x%llx, data=0x%04X", port, - dimm, prank, prg[prank][port], i, - disable_reg[port][prank][i], l_data); - } - } // end DP18 instance loop - - if (prg[prank][port] == rg_invalid[prank]) // invalid rank - { - FAPI_DBG("Primary rank group %i: INVALID, continuing...", - prank); - - continue; - } - - - if (dimm == 0) - { - if (rank == 0) - { - l_ecmdRc |= db_reg.copy(db_reg_dimm0_rank0); - l_rank0_invalid = 0; //0 = valid, 1 = invalid - } - else if (rank == 1) - { - l_ecmdRc |= db_reg.copy(db_reg_dimm0_rank1); - l_rank1_invalid = 0; //0 = valid, 1 = invalid - } - else if (rank == 2) - { - l_ecmdRc |= db_reg.copy(db_reg_dimm0_rank2); - l_rank2_invalid = 0; //0 = valid, 1 = invalid - } - else if (rank == 3) - { - l_ecmdRc |= db_reg.copy(db_reg_dimm0_rank3); - l_rank3_invalid = 0; //0 = valid, 1 = invalid - } - } - else if (dimm == 1) - { - if (rank == 0) - { - l_ecmdRc |= db_reg.copy(db_reg_dimm1_rank0); - l_rank4_invalid = 0; //0 = valid, 1 = invalid - } - else if (rank == 1) - { - l_ecmdRc |= db_reg.copy(db_reg_dimm1_rank1); - l_rank5_invalid = 0; //0 = valid, 1 = invalid - } - else if (rank == 2) - { - l_ecmdRc |= db_reg.copy(db_reg_dimm1_rank2); - l_rank6_invalid = 0; //0 = valid, 1 = invalid - } - else if (rank == 3) - { - l_ecmdRc |= db_reg.copy(db_reg_dimm1_rank3); - l_rank7_invalid = 0; //0 = valid, 1 = invalid - } - } - - if (l_ecmdRc != ECMD_DBUF_SUCCESS) - { - FAPI_ERR("Error from ecmdDataBuffer copy() " - "- rc 0x%.8X", l_ecmdRc); - - rc.setEcmdError(l_ecmdRc); - return rc; - } - - } // end primary rank loop - - - // loop through primary ranks [0:3] - for (uint8_t prank = 0; prank < MAX_PRI_RANKS; prank++ ) - { - - dimm = prg[prank][port] >> 2; - uint8_t rank = prg[prank][port] & 0x03; - uint16_t l_data = 0; - uint16_t l_data_rank0 = 0; - uint16_t l_data_rank1 = 0; - uint16_t l_data_rank2 = 0; - uint16_t l_data_rank3 = 0; - uint16_t l_data_rank4 = 0; - uint16_t l_data_rank5 = 0; - uint16_t l_data_rank6 = 0; - uint16_t l_data_rank7 = 0; - uint16_t l_data_curr_vpd = 0; - - if (prg[prank][port] == rg_invalid[prank]) // invalid rank - { - FAPI_DBG("Primary rank group %i is INVALID, continuing...", - prank); - continue; - } - - FAPI_DBG("Port%i, dimm=%i, prg%i rank=%i", port, dimm, prank, rank); - for ( uint8_t i=0; i < DP18_INSTANCES; i++ ) // dp18 [0:4] - { - - - l_data_rank0 = db_reg_dimm0_rank0.getHalfWord(i); - l_data_rank1 = db_reg_dimm0_rank1.getHalfWord(i); - l_data_rank2 = db_reg_dimm0_rank2.getHalfWord(i); - l_data_rank3 = db_reg_dimm0_rank3.getHalfWord(i); - l_data_rank4 = db_reg_dimm1_rank0.getHalfWord(i); - l_data_rank5 = db_reg_dimm1_rank1.getHalfWord(i); - l_data_rank6 = db_reg_dimm1_rank2.getHalfWord(i); - l_data_rank7 = db_reg_dimm1_rank3.getHalfWord(i); - - - - if (dimm == 0) - { - if (rank == 0) - { - l_data = l_data_rank0; - } - else if (rank == 1) - { - l_data = l_data_rank1; - } - else if (rank == 2) - { - l_data = l_data_rank2; - } - else if (rank == 3) - { - l_data = l_data_rank3; - } - } - else if (dimm == 1) - { - if (rank == 0) - { - l_data = l_data_rank4; - } - else if (rank == 1) - { - l_data = l_data_rank5; - } - else if (rank == 2) - { - l_data = l_data_rank6; - } - else if (rank == 3) - { - l_data = l_data_rank7; - } - } - - - uint8_t is_clean = 1; - rc = getC4dq2reg(mba_target, port, dimm, rank, db_reg_vpd, is_clean); - l_data_curr_vpd = db_reg_vpd.getHalfWord(i); - - uint16_t mask = 0xF000; - // Temp remove of 0xE case - //uint16_t emask = 0xE000; - for (uint8_t n=0; n < 4; n++) { // check each nibble - uint16_t nmask = mask >> (4*n); - // Temp remove of 0xE case - //uint16_t e_nmask = emask >> (4*n); - - - if ((nmask & l_data_curr_vpd) == nmask) { - FAPI_DBG("BYTE DISABLE WORKAROUND: Found a 0XF on nibble=%i Port%i, dimm=%i, prg%i rank=%i data= 0x%04X", n, port, dimm, prank, rank, l_data); - FAPI_DBG("BYTE DISABLE WORKAROUND: data rank 0 =0x%04X rank 1 =0x%04X rank 2 =0x%04X rank 3 =0x%04X rank 4 =0x%04X rank 5 =0x%04X rank 6 =0x%04X rank 7 =0x%04X", l_data_rank0,l_data_rank1,l_data_rank2,l_data_rank3,l_data_rank4,l_data_rank5,l_data_rank6,l_data_rank7 ); - if (i_training_success) - { //Leave it an F. - FAPI_DBG("BYTE DISABLE WORKAROUND: Training was successful so writing an 0xF to VPD. PRE data: 0x%04X", l_data); - l_data = l_data | nmask; - FAPI_DBG("BYTE DISABLE WORKAROUND: POST DATA: 0x%04X", l_data); - } - else - { - if ( ( ((nmask & l_data_rank0) == nmask) || (l_rank0_invalid) ) && - ( ((nmask & l_data_rank1) == nmask) || (l_rank1_invalid) ) && - ( ((nmask & l_data_rank2) == nmask) || (l_rank2_invalid) ) && - ( ((nmask & l_data_rank3) == nmask) || (l_rank3_invalid) ) && - ( ((nmask & l_data_rank4) == nmask) || (l_rank4_invalid) ) && - ( ((nmask & l_data_rank5) == nmask) || (l_rank5_invalid) ) && - ( ((nmask & l_data_rank6) == nmask) || (l_rank6_invalid) ) && - ( ((nmask & l_data_rank7) == nmask) || (l_rank7_invalid) ) ) - { - FAPI_DBG("BYTE DISABLE WORKAROUND: All ranks were F's and training was not successful. Uncool."); - continue; - } - else - { - - //Temprorarily removing 0xE version. Skipping Straight to 0xFs to all ranks. - /* - //Replacing F nibble with E nibble - FAPI_DBG("BYTE DISABLE WORKAROUND: Training was not successful so writing an 0xE to VPD. PRE DATA: 0x%04X", l_data); - l_data = (l_data & ~(nmask)) | e_nmask; - FAPI_DBG("BYTE DISABLE WORKAROUND: POST DATA: 0x%04X", l_data); - */ - - //Replacing E nibble with F nibble - FAPI_DBG("BYTE DISABLE WORKAROUND: Training failed so writing an 0xF to VPD for all ranks."); - l_data = l_data | nmask; - l_data_rank0 = l_data_rank0 | nmask; - l_data_rank1 = l_data_rank1 | nmask; - l_data_rank2 = l_data_rank2 | nmask; - l_data_rank3 = l_data_rank3 | nmask; - l_data_rank4 = l_data_rank4 | nmask; - l_data_rank5 = l_data_rank5 | nmask; - l_data_rank6 = l_data_rank6 | nmask; - l_data_rank7 = l_data_rank7 | nmask; - - } - } - } - else if ( ((nmask & l_data_curr_vpd) != nmask) && ((nmask & l_data_curr_vpd) > 0)) { - FAPI_DBG("BYTE DISABLE WORKAROUND: Found a non-zero, non-F nibble. Applying to all ranks."); - - if (l_dram_width == 4) - { - FAPI_DBG("BYTE DISABLE WORKAROUND: Its a x4 so turning it to a 0xF. PRE DATA: 0x%04X", l_data); - l_data = l_data | nmask; - FAPI_DBG("BYTE DISABLE WORKAROUND: POST DATA: 0x%04X", l_data); - - FAPI_DBG("BYTE DISABLE WORKAROUND: PRE data rank 0 =0x%04X rank 1 =0x%04X rank 2 =0x%04X rank 3 =0x%04X rank 4 =0x%04X rank 5 =0x%04X rank 6 =0x%04X rank 7 =0x%04X", l_data_rank0,l_data_rank1,l_data_rank2,l_data_rank3,l_data_rank4,l_data_rank5,l_data_rank6,l_data_rank7 ); - l_data_rank0 = l_data_rank0 | nmask; - l_data_rank1 = l_data_rank1 | nmask; - l_data_rank2 = l_data_rank2 | nmask; - l_data_rank3 = l_data_rank3 | nmask; - l_data_rank4 = l_data_rank4 | nmask; - l_data_rank5 = l_data_rank5 | nmask; - l_data_rank6 = l_data_rank6 | nmask; - l_data_rank7 = l_data_rank7 | nmask; - FAPI_DBG("BYTE DISABLE WORKAROUND: POST data rank 0 =0x%04X rank 1 =0x%04X rank 2 =0x%04X rank 3 =0x%04X rank 4 =0x%04X rank 5 =0x%04X rank 6 =0x%04X rank 7 =0x%04X", l_data_rank0,l_data_rank1,l_data_rank2,l_data_rank3,l_data_rank4,l_data_rank5,l_data_rank6,l_data_rank7 ); - - } - else if (l_dram_width == 8) - { - FAPI_DBG("BYTE DISABLE WORKAROUND: Its a x8 so leaving it the same."); - - FAPI_DBG("BYTE DISABLE WORKAROUND: PRE data rank 0 =0x%04X rank 1 =0x%04X rank 2 =0x%04X rank 3 =0x%04X rank 4 =0x%04X rank 5 =0x%04X rank 6 =0x%04X rank 7 =0x%04X", l_data_rank0,l_data_rank1,l_data_rank2,l_data_rank3,l_data_rank4,l_data_rank5,l_data_rank6,l_data_rank7 ); - l_data_rank0 = (l_data_rank0) | ( l_data & nmask); - l_data_rank1 = (l_data_rank1) | ( l_data & nmask); - l_data_rank2 = (l_data_rank2) | ( l_data & nmask); - l_data_rank3 = (l_data_rank3) | ( l_data & nmask); - l_data_rank4 = (l_data_rank4) | ( l_data & nmask); - l_data_rank5 = (l_data_rank5) | ( l_data & nmask); - l_data_rank6 = (l_data_rank6) | ( l_data & nmask); - l_data_rank7 = (l_data_rank7) | ( l_data & nmask); - - FAPI_DBG("BYTE DISABLE WORKAROUND: POST data rank 0 =0x%04X rank 1 =0x%04X rank 2 =0x%04X rank 3 =0x%04X rank 4 =0x%04X rank 5 =0x%04X rank 6 =0x%04X rank 7 =0x%04X", l_data_rank0,l_data_rank1,l_data_rank2,l_data_rank3,l_data_rank4,l_data_rank5,l_data_rank6,l_data_rank7 ); - } - - - - - } - // Temporarily Removing the 0xE case with this workaround. - /* - else if ((nmask & l_data_curr_vpd) == e_nmask) { - FAPI_DBG("BYTE DISABLE WORKAROUND: Found a 0XE on nibble=%i Port%i, dimm=%i, prg%i rank=%i data= 0x%04X", n, port, dimm, prank, rank, l_data); - if (i_training_success) - { - //Leave it an E. - FAPI_DBG("BYTE DISABLE WORKAROUND: Training was successful so writing an 0xE to VPD."); - } - else - { - //Replacing E nibble with F nibble - FAPI_DBG("BYTE DISABLE WORKAROUND: Training failed so writing an 0xF to VPD for all ranks."); - l_data = l_data | nmask; - l_data_rank0 = l_data_rank0 | nmask; - l_data_rank1 = l_data_rank1 | nmask; - l_data_rank2 = l_data_rank2 | nmask; - l_data_rank3 = l_data_rank3 | nmask; - l_data_rank4 = l_data_rank4 | nmask; - l_data_rank5 = l_data_rank5 | nmask; - l_data_rank6 = l_data_rank6 | nmask; - l_data_rank7 = l_data_rank7 | nmask; - } - } - */ - } - - if (dimm == 0) - { - if (rank == 0) - { - l_data_rank0 = l_data; - } - else if (rank == 1) - { - l_data_rank1 = l_data; - } - else if (rank == 2) - { - l_data_rank2 = l_data; - } - else if (rank == 3) - { - l_data_rank3 = l_data; - } - } - else if (dimm == 1) - { - if (rank == 0) - { - l_data_rank4 = l_data; - } - else if (rank == 1) - { - l_data_rank5 = l_data; - } - else if (rank == 2) - { - l_data_rank6 = l_data; - } - else if (rank == 3) - { - l_data_rank7 = l_data; - } - } - - - l_ecmdRc |= db_reg_dimm0_rank0.setHalfWord(i, l_data_rank0); - l_ecmdRc |= db_reg_dimm0_rank1.setHalfWord(i, l_data_rank1); - l_ecmdRc |= db_reg_dimm0_rank2.setHalfWord(i, l_data_rank2); - l_ecmdRc |= db_reg_dimm0_rank3.setHalfWord(i, l_data_rank3); - - l_ecmdRc |= db_reg_dimm1_rank0.setHalfWord(i, l_data_rank4); - l_ecmdRc |= db_reg_dimm1_rank1.setHalfWord(i, l_data_rank5); - l_ecmdRc |= db_reg_dimm1_rank2.setHalfWord(i, l_data_rank6); - l_ecmdRc |= db_reg_dimm1_rank3.setHalfWord(i, l_data_rank7); - - if (l_ecmdRc != ECMD_DBUF_SUCCESS) - { - FAPI_ERR("Error from ecmdDataBuffer flushTo0() " - "- rc 0x%.8X", l_ecmdRc); - rc.setEcmdError(l_ecmdRc); - return rc; - } - - - } - - - }// end of primary rank loop - - - // loop through primary ranks [0:3] - for (uint8_t prank = 0; prank < MAX_PRI_RANKS; prank++ ) - { - dimm = prg[prank][port] >> 2; - uint8_t rank = prg[prank][port] & 0x03; - FAPI_DBG("BYTE DISABLE WORKAROUND: Looping through dimm: %d rank: %d ", dimm, rank); - - if (prg[prank][port] == rg_invalid[prank]) // invalid rank - { - FAPI_DBG("Primary rank group %i is INVALID, continuing...", - prank); - continue; - } - - if (dimm == 0) - { - if (rank == 0) - { - l_ecmdRc |= db_reg_dimm0_rank0.copy(db_reg); - } - else if (rank == 1) - { - l_ecmdRc |= db_reg_dimm0_rank1.copy(db_reg); - } - else if (rank == 2) - { - l_ecmdRc |= db_reg_dimm0_rank2.copy(db_reg); - } - else if (rank == 3) - { - - l_ecmdRc |= db_reg_dimm0_rank3.copy(db_reg); - } - } - else if (dimm == 1) - { - if (rank == 0) - { - l_ecmdRc |= db_reg_dimm1_rank0.copy(db_reg); - } - else if (rank == 1) - { - l_ecmdRc |= db_reg_dimm1_rank1.copy(db_reg); - } - else if (rank == 2) - { - l_ecmdRc |= db_reg_dimm1_rank2.copy(db_reg); - } - else if (rank == 3) - { - l_ecmdRc |= db_reg_dimm1_rank3.copy(db_reg); - } - } - - if (l_ecmdRc != ECMD_DBUF_SUCCESS) - { - FAPI_ERR("Error from ecmdDataBuffer flushTo0() " - "- rc 0x%.8X", l_ecmdRc); - rc.setEcmdError(l_ecmdRc); - return rc; - } - - FAPI_INF("Setting BBM across dimm: %d rank: %d", dimm, rank); - rc = setC4dq2reg(mba_target, port, dimm, rank, db_reg); - if (rc) - { - FAPI_ERR("Error from setting register bitmap p%i: " - "dimm=%i, rank=%i rc=%i", port, dimm, rank, - static_cast<uint32_t>(rc)); - return rc; - } - - }// end of primary rank loop - - - - } // end port loop + FAPI_ERR("ATTR_EFF_DRAM_WIDTH is invalid %u", l_dram_width); + FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_DRAM_WIDTH_INPUT_ERROR_GETBBM); + return rc; + } + + l_ecmdRc = data_buffer.flushTo0(); + if (l_ecmdRc != ECMD_DBUF_SUCCESS) + { + FAPI_ERR("Error from ecmdDataBuffer flushTo0() " + "- rc 0x%.8X", l_ecmdRc); + + rc.setEcmdError(l_ecmdRc); + return rc; + } + for (uint8_t port = 0; port < MAX_PORTS; port++ ) // [0:1] + { + // Initialize all the stored errors to 0. + l_ecmdRc |= db_reg_dimm0_rank0.flushTo0(); + l_ecmdRc |= db_reg_dimm0_rank1.flushTo0(); + l_ecmdRc |= db_reg_dimm0_rank2.flushTo0(); + l_ecmdRc |= db_reg_dimm0_rank3.flushTo0(); + l_ecmdRc |= db_reg_dimm1_rank0.flushTo0(); + l_ecmdRc |= db_reg_dimm1_rank1.flushTo0(); + l_ecmdRc |= db_reg_dimm1_rank2.flushTo0(); + l_ecmdRc |= db_reg_dimm1_rank3.flushTo0(); + l_rank0_invalid = 1; //0 = valid, 1 = invalid + l_rank1_invalid = 1; + l_rank2_invalid = 1; + l_rank3_invalid = 1; + l_rank4_invalid = 1; + l_rank5_invalid = 1; + l_rank6_invalid = 1; + l_rank7_invalid = 1; + + if (l_ecmdRc != ECMD_DBUF_SUCCESS) + { + FAPI_ERR("Error from ecmdDataBuffer setHalfWord()" + " for wrclk_mask - rc 0x%.8X", l_ecmdRc); + + rc.setEcmdError(l_ecmdRc); + return rc; + } + + // loop through primary ranks [0:3] + for (uint8_t prank = 0; prank < MAX_PRI_RANKS; prank++ ) + { + dimm = prg[prank][port] >> 2; + uint8_t rank = prg[prank][port] & 0x03; + uint16_t l_data = 0; + + if (prg[prank][port] == rg_invalid[prank]) // invalid rank + { + FAPI_DBG("Primary rank group %i is INVALID, continuing...", + prank); + if ( prg[prank][port] == 0) + { + l_ecmdRc |= db_reg_dimm0_rank0.flushTo1(); + if (l_ecmdRc != ECMD_DBUF_SUCCESS) + { + FAPI_ERR("Error from ecmdDataBuffer setHalfWord() " + "- rc 0x%.8X", l_ecmdRc); + + rc.setEcmdError(l_ecmdRc); + return rc; + } + } + + if ( prg[prank][port] == 1) + { + l_ecmdRc |= db_reg_dimm0_rank1.flushTo1(); + if (l_ecmdRc != ECMD_DBUF_SUCCESS) + { + FAPI_ERR("Error from ecmdDataBuffer setHalfWord() " + "- rc 0x%.8X", l_ecmdRc); + + rc.setEcmdError(l_ecmdRc); + return rc; + } + } + + if ( prg[prank][port] == 2) + { + l_ecmdRc |= db_reg_dimm0_rank2.flushTo1(); + if (l_ecmdRc != ECMD_DBUF_SUCCESS) + { + FAPI_ERR("Error from ecmdDataBuffer setHalfWord() " + "- rc 0x%.8X", l_ecmdRc); + + rc.setEcmdError(l_ecmdRc); + return rc; + } + } + + + if ( prg[prank][port] == 3) + { + l_ecmdRc |= db_reg_dimm0_rank3.flushTo1(); + if (l_ecmdRc != ECMD_DBUF_SUCCESS) + { + FAPI_ERR("Error from ecmdDataBuffer setHalfWord() " + "- rc 0x%.8X", l_ecmdRc); + + rc.setEcmdError(l_ecmdRc); + return rc; + } + } + + + + if ( prg[prank][port] == 4) + { + l_ecmdRc |= db_reg_dimm1_rank0.flushTo1(); + if (l_ecmdRc != ECMD_DBUF_SUCCESS) + { + FAPI_ERR("Error from ecmdDataBuffer setHalfWord() " + "- rc 0x%.8X", l_ecmdRc); + + rc.setEcmdError(l_ecmdRc); + return rc; + } + } + + + if ( prg[prank][port] == 5) + { + l_ecmdRc |= db_reg_dimm1_rank1.flushTo1(); + if (l_ecmdRc != ECMD_DBUF_SUCCESS) + { + FAPI_ERR("Error from ecmdDataBuffer setHalfWord() " + "- rc 0x%.8X", l_ecmdRc); + + rc.setEcmdError(l_ecmdRc); + return rc; + } + } + + + if ( prg[prank][port] == 6) + { + l_ecmdRc |= db_reg_dimm1_rank2.flushTo1(); + if (l_ecmdRc != ECMD_DBUF_SUCCESS) + { + FAPI_ERR("Error from ecmdDataBuffer setHalfWord() " + "- rc 0x%.8X", l_ecmdRc); + + rc.setEcmdError(l_ecmdRc); + return rc; + } + } + + + if ( prg[prank][port] == 7) + { + l_ecmdRc |= db_reg_dimm1_rank3.flushTo1(); + if (l_ecmdRc != ECMD_DBUF_SUCCESS) + { + FAPI_ERR("Error from ecmdDataBuffer setHalfWord() " + "- rc 0x%.8X", l_ecmdRc); + + rc.setEcmdError(l_ecmdRc); + return rc; + } + } + + continue; + } + + // create the db_reg (all the failed bits of the port) + l_ecmdRc = db_reg.flushTo0(); + if (l_ecmdRc != ECMD_DBUF_SUCCESS) + { + FAPI_ERR("Error from ecmdDataBuffer flushTo0() " + "- rc 0x%.8X", l_ecmdRc); + + rc.setEcmdError(l_ecmdRc); + return rc; + } + + FAPI_DBG("Port%i, dimm=%i, prg%i rank=%i", port, dimm, prank, rank); + for ( uint8_t i=0; i < DP18_INSTANCES; i++ ) // dp18 [0:4] + { + // clear bits 48:63 + l_ecmdRc = data_buffer.clearBit(48, BITS_PER_REG); + if (l_ecmdRc != ECMD_DBUF_SUCCESS) + { + FAPI_ERR("Error from ecmdDataBuffer setHalfWord() " + "- rc 0x%.8X", l_ecmdRc); + + rc.setEcmdError(l_ecmdRc); + return rc; + } + + rc = fapiGetScom(mba_target, disable_reg[port][prank][i], + data_buffer); + if (rc) + { + FAPI_ERR("Error from fapiPutScom writing disable reg"); + return rc; + } + + l_data = data_buffer.getHalfWord(3); + + FAPI_DBG("dp18_%i 0x%llx = 0x%x", i, + disable_reg[port][prank][i], l_data); + + if (l_data != 0) + { + + l_ecmdRc = db_reg.setHalfWord(i, l_data); + if (l_ecmdRc != ECMD_DBUF_SUCCESS) + { + FAPI_ERR("Error from ecmdDataBuffer setHalfWord() " + "- rc 0x%.8X", l_ecmdRc); + + rc.setEcmdError(l_ecmdRc); + return rc; + } + + FAPI_INF("+++ Setting Bad Bit Mask p%i: DIMM%i PRG%i " + "Rank%i \tdp18_%i addr=0x%llx, data=0x%04X", port, + dimm, prank, prg[prank][port], i, + disable_reg[port][prank][i], l_data); + } + } // end DP18 instance loop + + if (prg[prank][port] == rg_invalid[prank]) // invalid rank + { + FAPI_DBG("Primary rank group %i: INVALID, continuing...", + prank); + + continue; + } + + + if (dimm == 0) + { + if (rank == 0) + { + l_ecmdRc |= db_reg.copy(db_reg_dimm0_rank0); + l_rank0_invalid = 0; //0 = valid, 1 = invalid + } + else if (rank == 1) + { + l_ecmdRc |= db_reg.copy(db_reg_dimm0_rank1); + l_rank1_invalid = 0; //0 = valid, 1 = invalid + } + else if (rank == 2) + { + l_ecmdRc |= db_reg.copy(db_reg_dimm0_rank2); + l_rank2_invalid = 0; //0 = valid, 1 = invalid + } + else if (rank == 3) + { + l_ecmdRc |= db_reg.copy(db_reg_dimm0_rank3); + l_rank3_invalid = 0; //0 = valid, 1 = invalid + } + } + else if (dimm == 1) + { + if (rank == 0) + { + l_ecmdRc |= db_reg.copy(db_reg_dimm1_rank0); + l_rank4_invalid = 0; //0 = valid, 1 = invalid + } + else if (rank == 1) + { + l_ecmdRc |= db_reg.copy(db_reg_dimm1_rank1); + l_rank5_invalid = 0; //0 = valid, 1 = invalid + } + else if (rank == 2) + { + l_ecmdRc |= db_reg.copy(db_reg_dimm1_rank2); + l_rank6_invalid = 0; //0 = valid, 1 = invalid + } + else if (rank == 3) + { + l_ecmdRc |= db_reg.copy(db_reg_dimm1_rank3); + l_rank7_invalid = 0; //0 = valid, 1 = invalid + } + } + + if (l_ecmdRc != ECMD_DBUF_SUCCESS) + { + FAPI_ERR("Error from ecmdDataBuffer copy() " + "- rc 0x%.8X", l_ecmdRc); + + rc.setEcmdError(l_ecmdRc); + return rc; + } + + } // end primary rank loop + + + // loop through primary ranks [0:3] + for (uint8_t prank = 0; prank < MAX_PRI_RANKS; prank++ ) + { + + dimm = prg[prank][port] >> 2; + uint8_t rank = prg[prank][port] & 0x03; + uint16_t l_data = 0; + uint16_t l_data_rank0 = 0; + uint16_t l_data_rank1 = 0; + uint16_t l_data_rank2 = 0; + uint16_t l_data_rank3 = 0; + uint16_t l_data_rank4 = 0; + uint16_t l_data_rank5 = 0; + uint16_t l_data_rank6 = 0; + uint16_t l_data_rank7 = 0; + uint16_t l_data_curr_vpd = 0; + + if (prg[prank][port] == rg_invalid[prank]) // invalid rank + { + FAPI_DBG("Primary rank group %i is INVALID, continuing...", + prank); + continue; + } + + FAPI_DBG("Port%i, dimm=%i, prg%i rank=%i", port, dimm, prank, rank); + for ( uint8_t i=0; i < DP18_INSTANCES; i++ ) // dp18 [0:4] + { + + + l_data_rank0 = db_reg_dimm0_rank0.getHalfWord(i); + l_data_rank1 = db_reg_dimm0_rank1.getHalfWord(i); + l_data_rank2 = db_reg_dimm0_rank2.getHalfWord(i); + l_data_rank3 = db_reg_dimm0_rank3.getHalfWord(i); + l_data_rank4 = db_reg_dimm1_rank0.getHalfWord(i); + l_data_rank5 = db_reg_dimm1_rank1.getHalfWord(i); + l_data_rank6 = db_reg_dimm1_rank2.getHalfWord(i); + l_data_rank7 = db_reg_dimm1_rank3.getHalfWord(i); + + + + if (dimm == 0) + { + if (rank == 0) + { + l_data = l_data_rank0; + } + else if (rank == 1) + { + l_data = l_data_rank1; + } + else if (rank == 2) + { + l_data = l_data_rank2; + } + else if (rank == 3) + { + l_data = l_data_rank3; + } + } + else if (dimm == 1) + { + if (rank == 0) + { + l_data = l_data_rank4; + } + else if (rank == 1) + { + l_data = l_data_rank5; + } + else if (rank == 2) + { + l_data = l_data_rank6; + } + else if (rank == 3) + { + l_data = l_data_rank7; + } + } + + + uint8_t is_clean = 1; + rc = getC4dq2reg(mba_target, port, dimm, rank, db_reg_vpd, is_clean); + l_data_curr_vpd = db_reg_vpd.getHalfWord(i); + + uint16_t mask = 0xF000; + // Temp remove of 0xE case + //uint16_t emask = 0xE000; + for (uint8_t n=0; n < 4; n++) { // check each nibble + uint16_t nmask = mask >> (4*n); + // Temp remove of 0xE case + //uint16_t e_nmask = emask >> (4*n); + + + if ((nmask & l_data_curr_vpd) == nmask) { + FAPI_DBG("BYTE DISABLE WORKAROUND: Found a 0XF on nibble=%i Port%i, dimm=%i, prg%i rank=%i data= 0x%04X", n, port, dimm, prank, rank, l_data); + FAPI_DBG("BYTE DISABLE WORKAROUND: data rank 0 =0x%04X rank 1 =0x%04X rank 2 =0x%04X rank 3 =0x%04X rank 4 =0x%04X rank 5 =0x%04X rank 6 =0x%04X rank 7 =0x%04X", l_data_rank0,l_data_rank1,l_data_rank2,l_data_rank3,l_data_rank4,l_data_rank5,l_data_rank6,l_data_rank7 ); + if (i_training_success) + { //Leave it an F. + FAPI_DBG("BYTE DISABLE WORKAROUND: Training was successful so writing an 0xF to VPD. PRE data: 0x%04X", l_data); + l_data = l_data | nmask; + FAPI_DBG("BYTE DISABLE WORKAROUND: POST DATA: 0x%04X", l_data); + } + else + { + if ( ( ((nmask & l_data_rank0) == nmask) || (l_rank0_invalid) ) && + ( ((nmask & l_data_rank1) == nmask) || (l_rank1_invalid) ) && + ( ((nmask & l_data_rank2) == nmask) || (l_rank2_invalid) ) && + ( ((nmask & l_data_rank3) == nmask) || (l_rank3_invalid) ) && + ( ((nmask & l_data_rank4) == nmask) || (l_rank4_invalid) ) && + ( ((nmask & l_data_rank5) == nmask) || (l_rank5_invalid) ) && + ( ((nmask & l_data_rank6) == nmask) || (l_rank6_invalid) ) && + ( ((nmask & l_data_rank7) == nmask) || (l_rank7_invalid) ) ) + { + FAPI_DBG("BYTE DISABLE WORKAROUND: All ranks were F's and training was not successful. Uncool."); + continue; + } + else + { + + //Temprorarily removing 0xE version. Skipping Straight to 0xFs to all ranks. + /* + //Replacing F nibble with E nibble + FAPI_DBG("BYTE DISABLE WORKAROUND: Training was not successful so writing an 0xE to VPD. PRE DATA: 0x%04X", l_data); + l_data = (l_data & ~(nmask)) | e_nmask; + FAPI_DBG("BYTE DISABLE WORKAROUND: POST DATA: 0x%04X", l_data); + */ + + //Replacing E nibble with F nibble + FAPI_DBG("BYTE DISABLE WORKAROUND: Training failed so writing an 0xF to VPD for all ranks."); + l_data = l_data | nmask; + l_data_rank0 = l_data_rank0 | nmask; + l_data_rank1 = l_data_rank1 | nmask; + l_data_rank2 = l_data_rank2 | nmask; + l_data_rank3 = l_data_rank3 | nmask; + l_data_rank4 = l_data_rank4 | nmask; + l_data_rank5 = l_data_rank5 | nmask; + l_data_rank6 = l_data_rank6 | nmask; + l_data_rank7 = l_data_rank7 | nmask; + + } + } + } + else if ( ((nmask & l_data_curr_vpd) != nmask) && ((nmask & l_data_curr_vpd) > 0)) { + FAPI_DBG("BYTE DISABLE WORKAROUND: Found a non-zero, non-F nibble. Applying to all ranks."); + + if (l_dram_width == 4) + { + FAPI_DBG("BYTE DISABLE WORKAROUND: Its a x4 so turning it to a 0xF. PRE DATA: 0x%04X", l_data); + l_data = l_data | nmask; + FAPI_DBG("BYTE DISABLE WORKAROUND: POST DATA: 0x%04X", l_data); + + FAPI_DBG("BYTE DISABLE WORKAROUND: PRE data rank 0 =0x%04X rank 1 =0x%04X rank 2 =0x%04X rank 3 =0x%04X rank 4 =0x%04X rank 5 =0x%04X rank 6 =0x%04X rank 7 =0x%04X", l_data_rank0,l_data_rank1,l_data_rank2,l_data_rank3,l_data_rank4,l_data_rank5,l_data_rank6,l_data_rank7 ); + l_data_rank0 = l_data_rank0 | nmask; + l_data_rank1 = l_data_rank1 | nmask; + l_data_rank2 = l_data_rank2 | nmask; + l_data_rank3 = l_data_rank3 | nmask; + l_data_rank4 = l_data_rank4 | nmask; + l_data_rank5 = l_data_rank5 | nmask; + l_data_rank6 = l_data_rank6 | nmask; + l_data_rank7 = l_data_rank7 | nmask; + FAPI_DBG("BYTE DISABLE WORKAROUND: POST data rank 0 =0x%04X rank 1 =0x%04X rank 2 =0x%04X rank 3 =0x%04X rank 4 =0x%04X rank 5 =0x%04X rank 6 =0x%04X rank 7 =0x%04X", l_data_rank0,l_data_rank1,l_data_rank2,l_data_rank3,l_data_rank4,l_data_rank5,l_data_rank6,l_data_rank7 ); + + } + else if (l_dram_width == 8) + { + FAPI_DBG("BYTE DISABLE WORKAROUND: Its a x8 so leaving it the same."); + + FAPI_DBG("BYTE DISABLE WORKAROUND: PRE data rank 0 =0x%04X rank 1 =0x%04X rank 2 =0x%04X rank 3 =0x%04X rank 4 =0x%04X rank 5 =0x%04X rank 6 =0x%04X rank 7 =0x%04X", l_data_rank0,l_data_rank1,l_data_rank2,l_data_rank3,l_data_rank4,l_data_rank5,l_data_rank6,l_data_rank7 ); + l_data_rank0 = (l_data_rank0) | ( l_data & nmask); + l_data_rank1 = (l_data_rank1) | ( l_data & nmask); + l_data_rank2 = (l_data_rank2) | ( l_data & nmask); + l_data_rank3 = (l_data_rank3) | ( l_data & nmask); + l_data_rank4 = (l_data_rank4) | ( l_data & nmask); + l_data_rank5 = (l_data_rank5) | ( l_data & nmask); + l_data_rank6 = (l_data_rank6) | ( l_data & nmask); + l_data_rank7 = (l_data_rank7) | ( l_data & nmask); + + FAPI_DBG("BYTE DISABLE WORKAROUND: POST data rank 0 =0x%04X rank 1 =0x%04X rank 2 =0x%04X rank 3 =0x%04X rank 4 =0x%04X rank 5 =0x%04X rank 6 =0x%04X rank 7 =0x%04X", l_data_rank0,l_data_rank1,l_data_rank2,l_data_rank3,l_data_rank4,l_data_rank5,l_data_rank6,l_data_rank7 ); + } + + + + + } + // Temporarily Removing the 0xE case with this workaround. + /* + else if ((nmask & l_data_curr_vpd) == e_nmask) { + FAPI_DBG("BYTE DISABLE WORKAROUND: Found a 0XE on nibble=%i Port%i, dimm=%i, prg%i rank=%i data= 0x%04X", n, port, dimm, prank, rank, l_data); + if (i_training_success) + { + //Leave it an E. + FAPI_DBG("BYTE DISABLE WORKAROUND: Training was successful so writing an 0xE to VPD."); + } + else + { + //Replacing E nibble with F nibble + FAPI_DBG("BYTE DISABLE WORKAROUND: Training failed so writing an 0xF to VPD for all ranks."); + l_data = l_data | nmask; + l_data_rank0 = l_data_rank0 | nmask; + l_data_rank1 = l_data_rank1 | nmask; + l_data_rank2 = l_data_rank2 | nmask; + l_data_rank3 = l_data_rank3 | nmask; + l_data_rank4 = l_data_rank4 | nmask; + l_data_rank5 = l_data_rank5 | nmask; + l_data_rank6 = l_data_rank6 | nmask; + l_data_rank7 = l_data_rank7 | nmask; + } + } + */ + } + + if (dimm == 0) + { + if (rank == 0) + { + l_data_rank0 = l_data; + } + else if (rank == 1) + { + l_data_rank1 = l_data; + } + else if (rank == 2) + { + l_data_rank2 = l_data; + } + else if (rank == 3) + { + l_data_rank3 = l_data; + } + } + else if (dimm == 1) + { + if (rank == 0) + { + l_data_rank4 = l_data; + } + else if (rank == 1) + { + l_data_rank5 = l_data; + } + else if (rank == 2) + { + l_data_rank6 = l_data; + } + else if (rank == 3) + { + l_data_rank7 = l_data; + } + } + + + l_ecmdRc |= db_reg_dimm0_rank0.setHalfWord(i, l_data_rank0); + l_ecmdRc |= db_reg_dimm0_rank1.setHalfWord(i, l_data_rank1); + l_ecmdRc |= db_reg_dimm0_rank2.setHalfWord(i, l_data_rank2); + l_ecmdRc |= db_reg_dimm0_rank3.setHalfWord(i, l_data_rank3); + + l_ecmdRc |= db_reg_dimm1_rank0.setHalfWord(i, l_data_rank4); + l_ecmdRc |= db_reg_dimm1_rank1.setHalfWord(i, l_data_rank5); + l_ecmdRc |= db_reg_dimm1_rank2.setHalfWord(i, l_data_rank6); + l_ecmdRc |= db_reg_dimm1_rank3.setHalfWord(i, l_data_rank7); + + if (l_ecmdRc != ECMD_DBUF_SUCCESS) + { + FAPI_ERR("Error from ecmdDataBuffer flushTo0() " + "- rc 0x%.8X", l_ecmdRc); + rc.setEcmdError(l_ecmdRc); + return rc; + } + + + } + + + }// end of primary rank loop + + + // loop through primary ranks [0:3] + for (uint8_t prank = 0; prank < MAX_PRI_RANKS; prank++ ) + { + dimm = prg[prank][port] >> 2; + uint8_t rank = prg[prank][port] & 0x03; + FAPI_DBG("BYTE DISABLE WORKAROUND: Looping through dimm: %d rank: %d ", dimm, rank); + + if (prg[prank][port] == rg_invalid[prank]) // invalid rank + { + FAPI_DBG("Primary rank group %i is INVALID, continuing...", + prank); + continue; + } + + if (dimm == 0) + { + if (rank == 0) + { + l_ecmdRc |= db_reg_dimm0_rank0.copy(db_reg); + } + else if (rank == 1) + { + l_ecmdRc |= db_reg_dimm0_rank1.copy(db_reg); + } + else if (rank == 2) + { + l_ecmdRc |= db_reg_dimm0_rank2.copy(db_reg); + } + else if (rank == 3) + { + + l_ecmdRc |= db_reg_dimm0_rank3.copy(db_reg); + } + } + else if (dimm == 1) + { + if (rank == 0) + { + l_ecmdRc |= db_reg_dimm1_rank0.copy(db_reg); + } + else if (rank == 1) + { + l_ecmdRc |= db_reg_dimm1_rank1.copy(db_reg); + } + else if (rank == 2) + { + l_ecmdRc |= db_reg_dimm1_rank2.copy(db_reg); + } + else if (rank == 3) + { + l_ecmdRc |= db_reg_dimm1_rank3.copy(db_reg); + } + } + + if (l_ecmdRc != ECMD_DBUF_SUCCESS) + { + FAPI_ERR("Error from ecmdDataBuffer flushTo0() " + "- rc 0x%.8X", l_ecmdRc); + rc.setEcmdError(l_ecmdRc); + return rc; + } + + FAPI_INF("Setting BBM across dimm: %d rank: %d", dimm, rank); + rc = setC4dq2reg(mba_target, port, dimm, rank, db_reg); + if (rc) + { + FAPI_ERR("Error from setting register bitmap p%i: " + "dimm=%i, rank=%i rc=%i", port, dimm, rank, + static_cast<uint32_t>(rc)); + return rc; + } + + }// end of primary rank loop + + + + } // end port loop return rc; } // end mss_get_bbm_regs ReturnCode getC4dq2reg(const Target & i_mba, const uint8_t i_port, - const uint8_t i_dimm, const uint8_t i_rank, ecmdDataBufferBase &o_reg, uint8_t &is_clean) + const uint8_t i_dimm, const uint8_t i_rank, ecmdDataBufferBase &o_reg, uint8_t &is_clean) { // used by set_bbm(flash to registers) // calls dimmGetBadDqBitmap and converts the data to phy order in a databuffer // output reg = in phy based order(lanes) - uint8_t l_bbm[TOTAL_BYTES] = {0}; // bad bitmap from dimmGetBadDqBitmap + uint8_t l_bbm[TOTAL_BYTES] = {0}; // bad bitmap from dimmGetBadDqBitmap ReturnCode rc; uint32_t ecmdrc = ECMD_DBUF_SUCCESS; - uint8_t dq; - uint8_t phy_lane, phy_block; + uint8_t dq; + uint8_t phy_lane, phy_block; - ecmdrc = o_reg.flushTo0(); // clear output databuffer + ecmdrc = o_reg.flushTo0(); // clear output databuffer if (ecmdrc != ECMD_DBUF_SUCCESS) { - FAPI_ERR("Error from ecmdDataBuffer flushTo0() " - "- rc 0x%.8X", ecmdrc); + FAPI_ERR("Error from ecmdDataBuffer flushTo0() " + "- rc 0x%.8X", ecmdrc); - rc.setEcmdError(ecmdrc); - return rc; + rc.setEcmdError(ecmdrc); + return rc; } // get Centaur dq bitmap (C4 signal) order=[0:79], array of bytes - rc = dimmGetBadDqBitmap(i_mba, i_port, i_dimm, i_rank, l_bbm); + rc = dimmGetBadDqBitmap(i_mba, i_port, i_dimm, i_rank, l_bbm); if (rc) { - FAPI_ERR("Error from dimmGetBadDqBitmap on port %i: " - "dimm=%i, rank=%i rc=%i", i_port, i_dimm, i_rank, - static_cast<uint32_t>(rc)); - return rc; - } - - uint8_t dimm_spare[MAX_PORTS][MAX_DIMMS][MAX_PRI_RANKS]; - rc = FAPI_ATTR_GET(ATTR_VPD_DIMM_SPARE, &i_mba, dimm_spare); - if(rc) return rc; - - for (uint8_t byte=0; byte < TOTAL_BYTES; byte++) - { - if (l_bbm[byte] != 0) - { - if (byte == (TOTAL_BYTES-1)) // spare byte - { - uint8_t spare_bitmap = 0; - - switch (dimm_spare[i_port][i_dimm][i_rank]) - { - case ENUM_ATTR_VPD_DIMM_SPARE_NO_SPARE: // 0xFF - continue; // ignore bbm data for nonexistent spare - break; - case ENUM_ATTR_VPD_DIMM_SPARE_LOW_NIBBLE: - spare_bitmap = 0x0F; - break; - case ENUM_ATTR_VPD_DIMM_SPARE_HIGH_NIBBLE: - spare_bitmap = 0xF0; - break; - case ENUM_ATTR_VPD_DIMM_SPARE_FULL_BYTE: - spare_bitmap = 0x00; - break; - default: - - //DECONFIG and FFDC INFO - const fapi::Target & TARGET_MBA_ERROR = i_mba; - const uint8_t & SPARE = dimm_spare[i_port][i_dimm][i_rank]; - const uint8_t & PORT = i_port; - const uint8_t & DIMM = i_dimm; - const uint8_t & RANK = i_rank; - - FAPI_ERR("ATTR_VPD_DIMM_SPARE is invalid %u", - dimm_spare[i_port][i_dimm][i_rank]); - FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_DIMM_SPARE_INPUT_ERROR); - return rc; - } - - if (l_bbm[byte] == spare_bitmap) // spare already set via initfile - continue; - } - - uint8_t bs=0; - uint8_t be=8; - uint8_t loc=0; - is_clean = 0; - - if ((l_bbm[byte] & 0xF0) == 0xF0) // 0xF? - { - dq = (byte * 8); // for first lane - // input=cen_c4_dq, output=phy block, lane - rc = mss_c4_phy(i_mba, i_port, 0, RD_DQ,dq, - 0, phy_lane,phy_block, 0); - if (rc) return rc; - - if (l_bbm[byte] == 0xFF) - { // block lanes + 1st lane{0,8} - loc = (phy_block * 16) + (phy_lane & 0x08); - o_reg.setBit(loc, 8); // set dq byte - FAPI_DBG("0xFF byte=%i, lbbm=0x%02x dp%i_%i dq=%i o=%i", - byte, l_bbm[byte], phy_block, phy_lane, dq, loc); - continue; - } - // block lanes + 1st lane{0,4,8,12} - loc = (phy_block * 16) + (phy_lane & 0x0C); - o_reg.setBit(loc, 4); // set dq nibble0 - FAPI_DBG("0xF0 byte=%i, lbbm=0x%02x dp%i_%i dq=%i o=%i", - byte, l_bbm[byte], phy_block, phy_lane, dq, loc); - - if (l_bbm[byte] == 0xF0) // done with byte - continue; - bs=4; // processed the first 4 bits already - } - else if ((l_bbm[byte] & 0x0F) == 0x0F) // 0x?F - { - dq = (byte * 8) + 4; // for first lane of dq - rc = mss_c4_phy(i_mba, i_port, 0, RD_DQ,dq, - 0, phy_lane, phy_block, 0); - if (rc) return rc; - // block lanes + 1st lane{0,4,8,12} - loc = (phy_block * 16) + (phy_lane & 0x0C); - FAPI_DBG("0x0F byte=%i, lbbm=0x%02x dp%i_%i dq=%i o=%i", - byte, l_bbm[byte], phy_block, phy_lane, dq, loc); - o_reg.setBit(loc, 4); // set dq nibble1 - if (l_bbm[byte] == 0x0F) // done with byte - continue; - be=4; // processed the last 4 bits already - } - else if ((l_bbm[byte] >> 4) == 0) // 0x0? - bs=4; - else if ((l_bbm[byte] & 0x0F) == 0) // 0x?0 - be=4; - - for (uint8_t b=bs; b < be; b++) // test each bit - { - if ((l_bbm[byte] & (0x80 >> b)) > 0) // bit is set, - { - dq = (byte * 8) + b; - rc=mss_c4_phy(i_mba, i_port, 0, RD_DQ,dq, - 0, phy_lane, phy_block, 0); - if (rc) return rc; - loc = (phy_block * 16) + phy_lane; - o_reg.setBit(loc); - FAPI_DBG("b=%i byte=%i, lbbm=0x%02x dp%i_%i dq=%i " - "loc=%i bs=%i be=%i", b, byte, l_bbm[byte], - phy_block, phy_lane, dq, loc, bs, be); - } - } - } // end if not clean - } // end byte - return rc; + FAPI_ERR("Error from dimmGetBadDqBitmap on port %i: " + "dimm=%i, rank=%i rc=%i", i_port, i_dimm, i_rank, + static_cast<uint32_t>(rc)); + return rc; + } + + uint8_t dimm_spare[MAX_PORTS][MAX_DIMMS][MAX_PRI_RANKS]; + rc = FAPI_ATTR_GET(ATTR_VPD_DIMM_SPARE, &i_mba, dimm_spare); + if(rc) return rc; + + for (uint8_t byte=0; byte < TOTAL_BYTES; byte++) + { + if (l_bbm[byte] != 0) + { + if (byte == (TOTAL_BYTES-1)) // spare byte + { + uint8_t spare_bitmap = 0; + + switch (dimm_spare[i_port][i_dimm][i_rank]) + { + case ENUM_ATTR_VPD_DIMM_SPARE_NO_SPARE: // 0xFF + continue; // ignore bbm data for nonexistent spare + break; + case ENUM_ATTR_VPD_DIMM_SPARE_LOW_NIBBLE: + spare_bitmap = 0x0F; + break; + case ENUM_ATTR_VPD_DIMM_SPARE_HIGH_NIBBLE: + spare_bitmap = 0xF0; + break; + case ENUM_ATTR_VPD_DIMM_SPARE_FULL_BYTE: + spare_bitmap = 0x00; + break; + default: + + //DECONFIG and FFDC INFO + const fapi::Target & TARGET_MBA_ERROR = i_mba; + const uint8_t & SPARE = dimm_spare[i_port][i_dimm][i_rank]; + const uint8_t & PORT = i_port; + const uint8_t & DIMM = i_dimm; + const uint8_t & RANK = i_rank; + + FAPI_ERR("ATTR_VPD_DIMM_SPARE is invalid %u", + dimm_spare[i_port][i_dimm][i_rank]); + FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_DIMM_SPARE_INPUT_ERROR); + return rc; + } + + if (l_bbm[byte] == spare_bitmap) // spare already set via initfile + continue; + } + + uint8_t bs=0; + uint8_t be=8; + uint8_t loc=0; + is_clean = 0; + + if ((l_bbm[byte] & 0xF0) == 0xF0) // 0xF? + { + dq = (byte * 8); // for first lane + // input=cen_c4_dq, output=phy block, lane + rc = mss_c4_phy(i_mba, i_port, 0, RD_DQ,dq, + 0, phy_lane,phy_block, 0); + if (rc) return rc; + + if (l_bbm[byte] == 0xFF) + { // block lanes + 1st lane{0,8} + loc = (phy_block * 16) + (phy_lane & 0x08); + o_reg.setBit(loc, 8); // set dq byte + FAPI_DBG("0xFF byte=%i, lbbm=0x%02x dp%i_%i dq=%i o=%i", + byte, l_bbm[byte], phy_block, phy_lane, dq, loc); + continue; + } + // block lanes + 1st lane{0,4,8,12} + loc = (phy_block * 16) + (phy_lane & 0x0C); + o_reg.setBit(loc, 4); // set dq nibble0 + FAPI_DBG("0xF0 byte=%i, lbbm=0x%02x dp%i_%i dq=%i o=%i", + byte, l_bbm[byte], phy_block, phy_lane, dq, loc); + + if (l_bbm[byte] == 0xF0) // done with byte + continue; + bs=4; // processed the first 4 bits already + } + else if ((l_bbm[byte] & 0x0F) == 0x0F) // 0x?F + { + dq = (byte * 8) + 4; // for first lane of dq + rc = mss_c4_phy(i_mba, i_port, 0, RD_DQ,dq, + 0, phy_lane, phy_block, 0); + if (rc) return rc; + // block lanes + 1st lane{0,4,8,12} + loc = (phy_block * 16) + (phy_lane & 0x0C); + FAPI_DBG("0x0F byte=%i, lbbm=0x%02x dp%i_%i dq=%i o=%i", + byte, l_bbm[byte], phy_block, phy_lane, dq, loc); + o_reg.setBit(loc, 4); // set dq nibble1 + if (l_bbm[byte] == 0x0F) // done with byte + continue; + be=4; // processed the last 4 bits already + } + else if ((l_bbm[byte] >> 4) == 0) // 0x0? + bs=4; + else if ((l_bbm[byte] & 0x0F) == 0) // 0x?0 + be=4; + + for (uint8_t b=bs; b < be; b++) // test each bit + { + if ((l_bbm[byte] & (0x80 >> b)) > 0) // bit is set, + { + dq = (byte * 8) + b; + rc=mss_c4_phy(i_mba, i_port, 0, RD_DQ,dq, + 0, phy_lane, phy_block, 0); + if (rc) return rc; + loc = (phy_block * 16) + phy_lane; + o_reg.setBit(loc); + FAPI_DBG("b=%i byte=%i, lbbm=0x%02x dp%i_%i dq=%i " + "loc=%i bs=%i be=%i", b, byte, l_bbm[byte], + phy_block, phy_lane, dq, loc, bs, be); + } + } + } // end if not clean + } // end byte + return rc; } // end getC4dq2reg @@ -7200,115 +7362,115 @@ ReturnCode setC4dq2reg(const Target &i_mba, const uint8_t i_port, // Converts the data from phy order (i_reg) to cen_c4_dq array // for dimmSetBadDqBitmap to write flash with - ReturnCode rc; - uint8_t l_bbm [TOTAL_BYTES] = {0}; - uint8_t dq=0; - uint8_t phy_lane; - uint8_t phy_block; - uint8_t data; + ReturnCode rc; + uint8_t l_bbm [TOTAL_BYTES] = {0}; + uint8_t dq=0; + uint8_t phy_lane; + uint8_t phy_block; + uint8_t data; // get Centaur dq bitmap (C4 signal) order=[0:79], array of bytes - rc = dimmGetBadDqBitmap(i_mba, i_port, i_dimm, i_rank, l_bbm); + rc = dimmGetBadDqBitmap(i_mba, i_port, i_dimm, i_rank, l_bbm); if (rc) { - FAPI_ERR("Error from dimmGetBadDqBitmap on port %i: " - "dimm=%i, rank=%i rc=%i", i_port, i_dimm, i_rank, - static_cast<uint32_t>(rc)); - return rc; - } - - for (uint8_t byte=0; byte < TOTAL_BYTES; byte++) - { - data = i_reg.getByte(byte); - if (data != 0) // need to check bits - { - uint8_t bs=0; - uint8_t be=8; - - phy_block = (byte / 2); // byte=[0..9], block=[0..4] - FAPI_DBG("\n\t\t\t\t\t\tbyte=%i, data=0x%02x phy_block=%i ", - byte, data, phy_block); - if ((data & 0xF0) == 0xF0) // 0xF? - { - phy_lane = 8 * (byte % 2); // lane=[0,8] - // input=block, lane output=cen_dq - rc = mss_c4_phy(i_mba, i_port, 0, RD_DQ,dq, - 0, phy_lane, phy_block, 1); - if (rc) return rc; - - if (data == 0xFF) - { // set 8 consecutive bits of the cen_c4_dq - l_bbm[(dq/8)] = 0xFF; - FAPI_DBG("0xFF dp%i_%i dq=%i, lbbm=0x%02x", - phy_block, phy_lane, dq, l_bbm[dq/8]); - continue; - } - - l_bbm[(dq/8)] |= ((dq % 8) < 4) ? 0xF0 : 0x0F; - FAPI_DBG("0xF0 dp%i_%i dq=%i, lbbm=0x%02x", - phy_block, phy_lane, dq, l_bbm[dq/8]); - - if (data == 0xF0) // done with byte - continue; - bs=4; // need to work on other bits - } - else if ((data & 0x0F) == 0x0F) // 0x?F - { - phy_lane = (8 * (byte % 2)) + 4; // lane=[4,12] - rc = mss_c4_phy(i_mba, i_port, 0, RD_DQ, dq, - 0, phy_lane, phy_block, 1); - if (rc) return rc; - - l_bbm[(dq/8)] |= ((dq % 8) < 4) ? 0xF0 : 0x0F; - FAPI_DBG("0x0F dp%i_%i dq=%i, lbbm=0x%02x", - phy_block, phy_lane, dq, l_bbm[dq/8]); - - if (data == 0x0F) // done with byte - continue; - be=4; // need to work on other bits - } - else if ((data >> 4) == 0) // 0x0? - bs=4; - else if ((data & 0x0F) == 0) // 0x?0 - be=4; - - for (uint8_t b=bs; b < be; b++) // test each bit - { - if ((data & (0x80 >> b)) > 0) // bit is set, - { - phy_lane = (8 * (byte % 2)) + b; - rc = mss_c4_phy(i_mba, i_port, 0, RD_DQ, dq, - 0, phy_lane, phy_block, 1); - if (rc) return rc; - l_bbm[(dq/8)] |= (0x80 >> (dq % 8)); - - } - else // bit is not set, - { - phy_lane = (8 * (byte % 2)) + b; - rc = mss_c4_phy(i_mba, i_port, 0, RD_DQ, dq, - 0, phy_lane, phy_block, 1); - if (rc) return rc; - l_bbm[(dq/8)] &= (~(0x80 >> (dq % 8))); - - } - } - } //end if not clean - } //end byte - - // set Centaur dq bitmap (C4 signal) order=[0:79], array of bytes - rc = dimmSetBadDqBitmap(i_mba, i_port, i_dimm, i_rank, l_bbm); - if (rc) - { - - FAPI_ERR("Error from dimmSetBadDqBitmap on port %i: " - "dimm=%i, rank=%i rc=%i", i_port, i_dimm, i_rank, - static_cast<uint32_t>(rc)); - return rc; - } - - return rc; + FAPI_ERR("Error from dimmGetBadDqBitmap on port %i: " + "dimm=%i, rank=%i rc=%i", i_port, i_dimm, i_rank, + static_cast<uint32_t>(rc)); + return rc; + } + + for (uint8_t byte=0; byte < TOTAL_BYTES; byte++) + { + data = i_reg.getByte(byte); + if (data != 0) // need to check bits + { + uint8_t bs=0; + uint8_t be=8; + + phy_block = (byte / 2); // byte=[0..9], block=[0..4] + FAPI_DBG("\n\t\t\t\t\t\tbyte=%i, data=0x%02x phy_block=%i ", + byte, data, phy_block); + if ((data & 0xF0) == 0xF0) // 0xF? + { + phy_lane = 8 * (byte % 2); // lane=[0,8] + // input=block, lane output=cen_dq + rc = mss_c4_phy(i_mba, i_port, 0, RD_DQ,dq, + 0, phy_lane, phy_block, 1); + if (rc) return rc; + + if (data == 0xFF) + { // set 8 consecutive bits of the cen_c4_dq + l_bbm[(dq/8)] = 0xFF; + FAPI_DBG("0xFF dp%i_%i dq=%i, lbbm=0x%02x", + phy_block, phy_lane, dq, l_bbm[dq/8]); + continue; + } + + l_bbm[(dq/8)] |= ((dq % 8) < 4) ? 0xF0 : 0x0F; + FAPI_DBG("0xF0 dp%i_%i dq=%i, lbbm=0x%02x", + phy_block, phy_lane, dq, l_bbm[dq/8]); + + if (data == 0xF0) // done with byte + continue; + bs=4; // need to work on other bits + } + else if ((data & 0x0F) == 0x0F) // 0x?F + { + phy_lane = (8 * (byte % 2)) + 4; // lane=[4,12] + rc = mss_c4_phy(i_mba, i_port, 0, RD_DQ, dq, + 0, phy_lane, phy_block, 1); + if (rc) return rc; + + l_bbm[(dq/8)] |= ((dq % 8) < 4) ? 0xF0 : 0x0F; + FAPI_DBG("0x0F dp%i_%i dq=%i, lbbm=0x%02x", + phy_block, phy_lane, dq, l_bbm[dq/8]); + + if (data == 0x0F) // done with byte + continue; + be=4; // need to work on other bits + } + else if ((data >> 4) == 0) // 0x0? + bs=4; + else if ((data & 0x0F) == 0) // 0x?0 + be=4; + + for (uint8_t b=bs; b < be; b++) // test each bit + { + if ((data & (0x80 >> b)) > 0) // bit is set, + { + phy_lane = (8 * (byte % 2)) + b; + rc = mss_c4_phy(i_mba, i_port, 0, RD_DQ, dq, + 0, phy_lane, phy_block, 1); + if (rc) return rc; + l_bbm[(dq/8)] |= (0x80 >> (dq % 8)); + + } + else // bit is not set, + { + phy_lane = (8 * (byte % 2)) + b; + rc = mss_c4_phy(i_mba, i_port, 0, RD_DQ, dq, + 0, phy_lane, phy_block, 1); + if (rc) return rc; + l_bbm[(dq/8)] &= (~(0x80 >> (dq % 8))); + + } + } + } //end if not clean + } //end byte + + // set Centaur dq bitmap (C4 signal) order=[0:79], array of bytes + rc = dimmSetBadDqBitmap(i_mba, i_port, i_dimm, i_rank, l_bbm); + if (rc) + { + + FAPI_ERR("Error from dimmSetBadDqBitmap on port %i: " + "dimm=%i, rank=%i rc=%i", i_port, i_dimm, i_rank, + static_cast<uint32_t>(rc)); + return rc; + } + + return rc; } //end setC4dq2reg @@ -7317,17 +7479,17 @@ fapi::ReturnCode mss_setup_dqs_offset(Target &i_target) { fapi::ReturnCode rc; uint32_t rc_num = 0; ecmdDataBufferBase buffer(64); - uint64_t scom_addr_array[10] = {DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P0_0_0x800000370301143F , - DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P0_1_0x800004370301143F , - DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P0_2_0x800008370301143F , - DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P0_3_0x80000C370301143F , - DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P0_4_0x800010370301143F , - DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P1_0_0x800100370301143F , - DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P1_1_0x800104370301143F , - DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P1_2_0x800108370301143F , - DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P1_3_0x80010C370301143F , + uint64_t scom_addr_array[10] = {DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P0_0_0x800000370301143F , + DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P0_1_0x800004370301143F , + DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P0_2_0x800008370301143F , + DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P0_3_0x80000C370301143F , + DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P0_4_0x800010370301143F , + DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P1_0_0x800100370301143F , + DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P1_1_0x800104370301143F , + DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P1_2_0x800108370301143F , + DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P1_3_0x80010C370301143F , DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P1_4_0x800110370301143F}; - + FAPI_INF("DDR4: setting up DQS offset to be 16"); for(uint8_t scom_addr = 0; scom_addr < 10; ++scom_addr) { rc = fapiGetScom(i_target, scom_addr_array[scom_addr], buffer); @@ -7337,13 +7499,13 @@ fapi::ReturnCode mss_setup_dqs_offset(Target &i_target) { if (rc_num) { FAPI_ERR( "mss_setup_dqs: Error setting up buffers"); - rc.setEcmdError(rc_num); - return rc; + rc.setEcmdError(rc_num); + return rc; } rc = fapiPutScom(i_target, scom_addr_array[scom_addr], buffer); if(rc) return rc; } - + return rc; } |
