PRD: Collect FFDC for Centaur Checkstops

Change-Id: Id65e1b961a0f47ac2456e45fa6cbe536fd659f91
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/4302
Tested-by: Jenkins Server
Reviewed-by: BENJAMIN J. WEISENBECK <bweisenb@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Reviewed-by: Christopher T. Phan <cphan@us.ibm.com>
Reviewed-by: Zane Shelley <zshelle@us.ibm.com>
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/4515

7 files changed, 315 insertions, 34 deletions

diff --git a/src/usr/diag/prdf/common/plat/pegasus/Mba.rule b/src/usr/diag/prdf/common/plat/pegasus/Mba.rule
index f70185446..d09d63997 100755
--- a/src/usr/diag/prdf/common/plat/pegasus/Mba.rule
+++ b/src/usr/diag/prdf/common/plat/pegasus/Mba.rule
@@ -66,7 +66,7 @@ chip Mba
         scomaddr    0x03010600;
         reset       (&, 0x03010601);
         mask        (|, 0x03010605);
-        capture     group default;
+        capture     group FirRegs;
     };
 
     register MBAFIR_MASK
@@ -74,7 +74,7 @@ chip Mba
         name        "MBU.MBA01.MBA_MCBIST.SCOMFIR.MBAFIRMASK";
         scomaddr    0x03010603;
         capture     type secondary;
-        capture     group default;
+        capture     group FirRegs;
     };
 
     register MBAFIR_ACT0
@@ -82,7 +82,7 @@ chip Mba
         name        "MBU.MBA01.MBA_MCBIST.SCOMFIR.MBAFIRACT0";
         scomaddr    0x03010606;
         capture     type secondary;
-        capture     group default;
+        capture     group FirRegs;
     };
 
     register MBAFIR_ACT1
@@ -90,7 +90,7 @@ chip Mba
         name        "MBU.MBA01.MBA_MCBIST.SCOMFIR.MBAFIRACT1";
         scomaddr    0x03010607;
         capture     type secondary;
-        capture     group default;
+        capture     group FirRegs;
     };
 
     ############################################################################
@@ -104,7 +104,7 @@ chip Mba
         name        "MBU.MBA01.MBA_SRQ.MBASIRQ";
         scomaddr    0x0301041b;
         reset       (&, 0x0301041c);
-        capture     group default;
+        capture     group FirRegs;
     };
 
     ############################################################################
@@ -117,7 +117,7 @@ chip Mba
         scomaddr    0x800200900301143F;
         reset       (&, 0x800200910301143F);
         mask        (|, 0x800200950301143F);
-        capture     group default;
+        capture     group FirRegs;
     };
 
     register MBADDRPHYFIR_MASK
@@ -125,7 +125,7 @@ chip Mba
         name        "DPHY01.PHY01_DDRPHY_FIR_MASK_REG";
         scomaddr    0x800200930301143F;
         capture     type secondary;
-        capture     group default;
+        capture     group FirRegs;
     };
 
     register MBADDRPHYFIR_ACT0
@@ -133,7 +133,7 @@ chip Mba
         name        "DPHY01.PHY01_DDRPHY_FIR_ACTION0_REG";
         scomaddr    0x800200960301143F;
         capture     type secondary;
-        capture     group default;
+        capture     group FirRegs;
     };
 
     register MBADDRPHYFIR_ACT1
@@ -141,7 +141,7 @@ chip Mba
         name        "DPHY01.PHY01_DDRPHY_FIR_ACTION1_REG";
         scomaddr    0x800200970301143F;
         capture     type secondary;
-        capture     group default;
+        capture     group FirRegs;
     };
 
     ############################################################################
@@ -154,7 +154,7 @@ chip Mba
         scomaddr    0x03010400;
         reset       (&, 0x03010401);
         mask        (|, 0x03010405);
-        capture     group default;
+        capture     group FirRegs;
     };
 
     register MBACALFIR_MASK
@@ -162,7 +162,7 @@ chip Mba
         name        "MBU.MBA01.MBA_SRQ.MBACALFIR_MASK";
         scomaddr    0x03010403;
         capture     type secondary;
-        capture     group default;
+        capture     group FirRegs;
     };
 
     register MBACALFIR_ACT0
@@ -170,7 +170,7 @@ chip Mba
         name        "MBU.MBA01.MBA_SRQ.MBACALFIR_ACTION0";
         scomaddr    0x03010406;
         capture     type secondary;
-        capture     group default;
+        capture     group FirRegs;
     };
 
     register MBACALFIR_ACT1
@@ -178,7 +178,7 @@ chip Mba
         name        "MBU.MBA01.MBA_SRQ.MBACALFIR_ACTION1";
         scomaddr    0x03010407;
         capture     type secondary;
-        capture     group default;
+        capture     group FirRegs;
     };
 
     ############################################################################
@@ -192,7 +192,7 @@ chip Mba
         reset       (&, 0x03010612);
         #FIXME : There is no OR register for mask. Is it right to use  mask register value
         mask        (|, 0x03010614);
-        capture     group default;
+        capture     group FirRegs;
     };
 
     register MBASPA_MASK
@@ -200,7 +200,54 @@ chip Mba
         name        "MBU.MBA01.MBA_MCBIST.SCOMFIR.MBSPAMSKQ";
         scomaddr    0x03010614;
         capture     type secondary;
-        capture     group default;
+        capture     group FirRegs;
+    };
+
+    ############################################################################
+    # Error Report Registers
+    ############################################################################
+
+    register MBA_ERR_REPORT
+    {
+        name        "MBU.MBA01.MBA_SRQ.MBA_ERR_REPORTQ";
+        scomaddr    0x0301041A;
+        capture     group CerrRegs;
+    };
+
+    register MBA_MCBERRPTQ
+    {
+        name        "MBU.MBA01.MBA_MCBIST.SCOMFIR.MBA_MCBERRPTQ";
+        scomaddr    0x030106E7;
+        capture     group CerrRegs;
+    };
+
+
+    register DDRPHY_APB_FIR_ERR0_P0
+    {
+        name        "DPHY01.DDRPHY_APB_FIR_ERR0_P0";
+        scomaddr    0x8000D0060301143F;
+        capture     group CerrRegs;
+    };
+
+    register DDRPHY_APB_FIR_ERR1_P0
+    {
+        name        "DPHY01.DDRPHY_APB_FIR_ERR1_P0";
+        scomaddr    0x8000D0070301143F;
+        capture     group CerrRegs;
+    };
+
+    register DDRPHY_APB_FIR_ERR0_P1
+    {
+        name        "DPHY01.DDRPHY_APB_FIR_ERR0_P1";
+        scomaddr    0x8001D0060301143F;
+        capture     group CerrRegs;
+    };
+
+    register DDRPHY_APB_FIR_ERR1_P1
+    {
+        name        "DPHY01.DDRPHY_APB_FIR_ERR1_P1";
+        scomaddr    0x8001D0070301143F;
+        capture     group CerrRegs;
     };
 
     ############################################################################
diff --git a/src/usr/diag/prdf/common/plat/pegasus/Mcs.rule b/src/usr/diag/prdf/common/plat/pegasus/Mcs.rule
index ef118c038..e5e211d34 100755
--- a/src/usr/diag/prdf/common/plat/pegasus/Mcs.rule
+++ b/src/usr/diag/prdf/common/plat/pegasus/Mcs.rule
@@ -74,6 +74,7 @@ chip Mcs
         reset       (&, 0x02011841);
         mask        (|, 0x02011845);
         capture     group default;
+        capture     group FirRegs;
     };
 
     register MCIFIR_AND
@@ -89,6 +90,7 @@ chip Mcs
         scomaddr    0x02011843;
         capture     type secondary;
         capture     group default;
+        capture     group FirRegs;
     };
 
     register MCIFIR_ACT0
@@ -97,6 +99,7 @@ chip Mcs
         scomaddr    0x02011846;
         capture     type secondary;
         capture     group default;
+        capture     group FirRegs;
     };
 
     register MCIFIR_ACT1
@@ -105,7 +108,29 @@ chip Mcs
         scomaddr    0x02011847;
         capture     type secondary;
         capture     group default;
+        capture     group FirRegs;
     };
+
+    ############################################################################
+    # Error Report Registers
+    ############################################################################
+
+    register MCERPT0
+    {
+        name        "MC0.MCS0.LEFT.LEFT.MCERPT0";
+        scomaddr    0x0201181E;
+        capture     group default;
+        capture     group CerrRegs;
+    };
+
+    register MCIERPT0
+    {
+        name        "MC0.MCS0.RIGHT.MCI.MCIERPT0";
+        scomaddr    0x0201184E;
+        capture     group default;
+        capture     group CerrRegs;
+    };
+
 };
 
  ##############################################################################
diff --git a/src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_MEM.rule b/src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_MEM.rule
index 794d910fe..8542e7bcc 100755
--- a/src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_MEM.rule
+++ b/src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_MEM.rule
@@ -30,6 +30,7 @@
         name        "TCM.XFIR";
         scomaddr    0x03040000;
         capture     group default;
+        capture     group FirRegs;
     };
 
     register MEM_CHIPLET_RE_FIR
@@ -37,6 +38,7 @@
         name        "TCM.RFIR";
         scomaddr    0x03040001;
         capture     group default;
+        capture     group FirRegs;
     };
 
     register MEM_CHIPLET_FIR_MASK
@@ -45,6 +47,7 @@
         scomaddr    0x03040002;
         capture     type secondary;
         capture     group default;
+        capture     group FirRegs;
     };
 
     register MEM_CHIPLET_SPA
@@ -52,6 +55,7 @@
         name        "TCM.EPS.FIR.SPATTN";
         scomaddr    0x03040004;
         capture     group default;
+        capture     group FirRegs;
     };
 
     register MEM_CHIPLET_SPA_MASK
@@ -60,6 +64,7 @@
         scomaddr    0x03040007;
         capture     type secondary;
         capture     group default;
+        capture     group FirRegs;
     };
 
     ############################################################################
@@ -73,6 +78,7 @@
         reset       (&, 0x0304000b);
         mask        (|, 0x0304000f);
         capture     group default;
+        capture     group FirRegs;
     };
 
     register MEM_LFIR_MASK
@@ -81,6 +87,7 @@
         scomaddr    0x0304000d;
         capture     type secondary;
         capture     group default;
+        capture     group FirRegs;
     };
 
     register MEM_LFIR_ACT0
@@ -89,6 +96,7 @@
         scomaddr    0x03040010;
         capture     type secondary;
         capture     group default;
+        capture     group FirRegs;
     };
 
     register MEM_LFIR_ACT1
@@ -97,6 +105,7 @@
         scomaddr    0x03040011;
         capture     type secondary;
         capture     group default;
+        capture     group FirRegs;
     };
 
     ############################################################################
@@ -110,6 +119,7 @@
         reset       (&, 0x03010481);
         mask        (|, 0x03010485);
         capture     group default;
+        capture     group FirRegs;
     };
 
     register MEMFBISTFIR_MASK
@@ -118,6 +128,7 @@
         scomaddr    0x03010483;
         capture     type secondary;
         capture     group default;
+        capture     group FirRegs;
     };
 
     register MEMFBISTFIR_ACT0
@@ -126,6 +137,7 @@
         scomaddr    0x03010486;
         capture     type secondary;
         capture     group default;
+        capture     group FirRegs;
     };
 
     register MEMFBISTFIR_ACT1
@@ -134,5 +146,18 @@
         scomaddr    0x03010487;
         capture     type secondary;
         capture     group default;
+        capture     group FirRegs;
+    };
+
+    ############################################################################
+    # Error Report Registers
+    ############################################################################
+
+    register MEM_ERROR_STATUS
+    {
+        name        "TCM.ERROR_STATUS";
+        scomaddr    0x03030009;
+        capture     group default;
+        capture     group CerrRegs;
     };
 
diff --git a/src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_NEST.rule b/src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_NEST.rule
index 5c6dd316b..911d9a2cc 100755
--- a/src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_NEST.rule
+++ b/src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_NEST.rule
@@ -30,6 +30,7 @@
         name        "TCN.XFIR";
         scomaddr    0x02040000;
         capture     group default;
+        capture     group FirRegs;
     };
 
     register NEST_CHIPLET_RE_FIR
@@ -37,6 +38,7 @@
         name        "TCN.RFIR";
         scomaddr    0x02040001;
         capture     group default;
+        capture     group FirRegs;
     };
 
     register NEST_CHIPLET_FIR_MASK
@@ -45,6 +47,7 @@
         scomaddr    0x02040002;
         capture     type secondary;
         capture     group default;
+        capture     group FirRegs;
     };
 
     ############################################################################
@@ -58,6 +61,7 @@
         reset       (&, 0x0204000b);
         mask        (|, 0x0204000f);
         capture     group default;
+        capture     group FirRegs;
     };
 
     register NEST_LFIR_MASK
@@ -66,6 +70,7 @@
         scomaddr    0x0204000d;
         capture     type secondary;
         capture     group default;
+        capture     group FirRegs;
     };
 
     register NEST_LFIR_ACT0
@@ -74,6 +79,7 @@
         scomaddr    0x02040010;
         capture     type secondary;
         capture     group default;
+        capture     group FirRegs;
     };
 
     register NEST_LFIR_ACT1
@@ -82,6 +88,7 @@
         scomaddr    0x02040011;
         capture     type secondary;
         capture     group default;
+        capture     group FirRegs;
     };
 
     ############################################################################
@@ -95,6 +102,7 @@
         reset       (&, 0x02010401);
         mask        (|, 0x02010405);
         capture     group default;
+        capture     group FirRegs;
     };
 
     register DMIFIR_MASK
@@ -103,6 +111,7 @@
         scomaddr    0x02010403;
         capture     type secondary;
         capture     group default;
+        capture     group FirRegs;
     };
 
     register DMIFIR_ACT0
@@ -111,6 +120,7 @@
         scomaddr    0x02010406;
         capture     type secondary;
         capture     group default;
+        capture     group FirRegs;
     };
 
     register DMIFIR_ACT1
@@ -119,6 +129,7 @@
         scomaddr    0x02010407;
         capture     type secondary;
         capture     group default;
+        capture     group FirRegs;
     };
 
     ############################################################################
@@ -132,6 +143,7 @@
         reset       (&, 0x02010801);
         mask        (|, 0x02010805);
         capture     group default;
+        capture     group FirRegs;
     };
 
     register MBIFIR_MASK
@@ -140,6 +152,7 @@
         scomaddr    0x02010803;
         capture     type secondary;
         capture     group default;
+        capture     group FirRegs;
     };
 
     register MBIFIR_ACT0
@@ -148,6 +161,7 @@
         scomaddr    0x02010806;
         capture     type secondary;
         capture     group default;
+        capture     group FirRegs;
     };
 
     register MBIFIR_ACT1
@@ -156,6 +170,7 @@
         scomaddr    0x02010807;
         capture     type secondary;
         capture     group default;
+        capture     group FirRegs;
     };
 
     ############################################################################
@@ -169,6 +184,7 @@
         reset       (&, 0x02011401);
         mask        (|, 0x02011405);
         capture     group default;
+        capture     group FirRegs;
     };
 
     register MBSFIR_MASK
@@ -177,6 +193,7 @@
         scomaddr    0x02011403;
         capture     type secondary;
         capture     group default;
+        capture     group FirRegs;
     };
 
     register MBSFIR_ACT0
@@ -185,6 +202,7 @@
         scomaddr    0x02011406;
         capture     type secondary;
         capture     group default;
+        capture     group FirRegs;
     };
 
     register MBSFIR_ACT1
@@ -193,6 +211,7 @@
         scomaddr    0x02011407;
         capture     type secondary;
         capture     group default;
+        capture     group FirRegs;
     };
 
     ############################################################################
@@ -206,6 +225,7 @@
         reset       (&, 0x02011441);
         mask        (|, 0x02011445);
         capture     group default;
+        capture     group FirRegs;
     };
 
     register MBSECC01FIR_MASK
@@ -214,6 +234,7 @@
         scomaddr    0x02011443;
         capture     type secondary;
         capture     group default;
+        capture     group FirRegs;
     };
 
     register MBSECC01FIR_ACT0
@@ -222,6 +243,7 @@
         scomaddr    0x02011446;
         capture     type secondary;
         capture     group default;
+        capture     group FirRegs;
     };
 
     register MBSECC01FIR_ACT1
@@ -230,6 +252,7 @@
         scomaddr    0x02011447;
         capture     type secondary;
         capture     group default;
+        capture     group FirRegs;
     };
 
     ############################################################################
@@ -243,6 +266,7 @@
         reset       (&, 0x02011481);
         mask        (|, 0x02011485);
         capture     group default;
+        capture     group FirRegs;
     };
 
     register MBSECC23FIR_MASK
@@ -251,6 +275,7 @@
         scomaddr    0x02011483;
         capture     type secondary;
         capture     group default;
+        capture     group FirRegs;
     };
 
     register MBSECC23FIR_ACT0
@@ -259,6 +284,7 @@
         scomaddr    0x02011486;
         capture     type secondary;
         capture     group default;
+        capture     group FirRegs;
     };
 
     register MBSECC23FIR_ACT1
@@ -267,6 +293,7 @@
         scomaddr    0x02011487;
         capture     type secondary;
         capture     group default;
+        capture     group FirRegs;
     };
 
     ############################################################################
@@ -280,6 +307,7 @@
         reset       (&, 0x02011601);
         mask        (|, 0x02011605);
         capture     group default;
+        capture     group FirRegs;
     };
 
     register MCBIST01FIR_MASK
@@ -288,6 +316,7 @@
         scomaddr    0x02011603;
         capture     type secondary;
         capture     group default;
+        capture     group FirRegs;
     };
 
     register MCBIST01FIR_ACT0
@@ -296,6 +325,7 @@
         scomaddr    0x02011606;
         capture     type secondary;
         capture     group default;
+        capture     group FirRegs;
     };
 
     register MCBIST01FIR_ACT1
@@ -304,6 +334,7 @@
         scomaddr    0x02011607;
         capture     type secondary;
         capture     group default;
+        capture     group FirRegs;
     };
 
     ############################################################################
@@ -317,6 +348,7 @@
         reset       (&, 0x02011701);
         mask        (|, 0x02011705);
         capture     group default;
+        capture     group FirRegs;
     };
 
     register MCBIST23FIR_MASK
@@ -325,6 +357,7 @@
         scomaddr    0x02011703;
         capture     type secondary;
         capture     group default;
+        capture     group FirRegs;
     };
 
     register MCBIST23FIR_ACT0
@@ -333,6 +366,7 @@
         scomaddr    0x02011706;
         capture     type secondary;
         capture     group default;
+        capture     group FirRegs;
     };
 
     register MCBIST23FIR_ACT1
@@ -341,6 +375,7 @@
         scomaddr    0x02011707;
         capture     type secondary;
         capture     group default;
+        capture     group FirRegs;
     };
 
     ############################################################################
@@ -354,6 +389,7 @@
         reset       (&, 0x02010881);
         mask        (|, 0x02010885);
         capture     group default;
+        capture     group FirRegs;
     };
 
     register NESTFBISTFIR_MASK
@@ -362,6 +398,7 @@
         scomaddr    0x02010883;
         capture     type secondary;
         capture     group default;
+        capture     group FirRegs;
     };
 
     register NESTFBISTFIR_ACT0
@@ -370,6 +407,7 @@
         scomaddr    0x02010886;
         capture     type secondary;
         capture     group default;
+        capture     group FirRegs;
     };
 
     register NESTFBISTFIR_ACT1
@@ -378,6 +416,7 @@
         scomaddr    0x02010887;
         capture     type secondary;
         capture     group default;
+        capture     group FirRegs;
     };
 
     ############################################################################
@@ -391,6 +430,7 @@
         reset       (&, 0x020115c1);
         mask        (|, 0x020115c5);
         capture     group default;
+        capture     group FirRegs;
     };
 
     register SENSORCACHEFIR_MASK
@@ -399,6 +439,7 @@
         scomaddr    0x020115c3;
         capture     type secondary;
         capture     group default;
+        capture     group FirRegs;
     };
 
     register SENSORCACHEFIR_ACT0
@@ -407,6 +448,7 @@
         scomaddr    0x020115c6;
         capture     type secondary;
         capture     group default;
+        capture     group FirRegs;
     };
 
     register SENSORCACHEFIR_ACT1
@@ -415,6 +457,7 @@
         scomaddr    0x020115c7;
         capture     type secondary;
         capture     group default;
+        capture     group FirRegs;
     };
 
     ############################################################################
@@ -429,6 +472,98 @@
         scomaddr    0x0201141e;
         reset       (&, 0x0201141f);
         capture     group default;
+        capture     group FirRegs;
+    };
+
+    ############################################################################
+    # Error Report Registers
+    ############################################################################
+
+    register NEST_ERROR_STATUS
+    {
+        name        "TCN.ERROR_STATUS";
+        scomaddr    0x02030009;
+        capture     group default;
+        capture     group CerrRegs;
+    };
+
+    register MBIERPT
+    {
+        name        "MBU.MBI.MBI.MBIERPT0";
+        scomaddr    0x0201080F;
+        capture     group default;
+        capture     group CerrRegs;
+    };
+
+    register MBSCERR1
+    {
+        name        "MBU.MBS.MBSCERR1Q";
+        scomaddr    0x02011413;
+        capture     group default;
+        capture     group CerrRegs;
+    };
+
+    register MBSCERR2
+    {
+        name        "MBU.MBS.MBSCERR2Q";
+        scomaddr    0x0201142C;
+        capture     group default;
+        capture     group CerrRegs;
+    };
+
+    register MBSECC01ERRPT_0
+    {
+        name        "MBU.MBS.ECC01.MBSECCERR0";
+        scomaddr    0x02011466;
+        capture     group default;
+        capture     group CerrRegs;
+    };
+
+    register MBSECC01ERRPT_1
+    {
+        name        "MBU.MBS.ECC01.MBSECCERR1";
+        scomaddr    0x02011467;
+        capture     group default;
+        capture     group CerrRegs;
+    };
+    register MBSECC23ERRPT_0
+    {
+        name        "MBU.MBS.ECC23.MBSECCERR0";
+        scomaddr    0x020114A6;
+        capture     group default;
+        capture     group CerrRegs;
+    };
+
+    register MBSECC23ERRPT_1
+    {
+        name        "MBU.MBS.ECC23.MBSECCERR1";
+        scomaddr    0x020114A7;
+        capture     group default;
+        capture     group CerrRegs;
+    };
+
+    register MBXERRSTAT_0
+    {
+        name        "MBU.MBS.MCBISTS01.SCOMFIR.MBXERRSTATQ";
+        scomaddr    0x0201168f;
+        capture     group default;
+        capture     group CerrRegs;
+    };
+
+    register MBXERRSTAT_1
+    {
+        name        "MBU.MBS.MCBISTS23.SCOMFIR.MBXERRSTATQ";
+        scomaddr    0x0201178f;
+        capture     group default;
+        capture     group CerrRegs;
+    };
+
+    register SENSORCACHEERRPT
+    {
+        name        "SCAC.SCAC_ERRRPT";
+        scomaddr    0x020115D4;
+        capture     group default;
+        capture     group CerrRegs;
     };
 
     ############################################################################
diff --git a/src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_TP.rule b/src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_TP.rule
index f255bfcb7..be8218e30 100755
--- a/src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_TP.rule
+++ b/src/usr/diag/prdf/common/plat/pegasus/Membuf_regs_TP.rule
@@ -30,6 +30,7 @@
         name        "TPTOP.TPC.XFIR";
         scomaddr    0x01040000;
         capture     group default;
+        capture     group FirRegs;
     };
 
     register TP_CHIPLET_RE_FIR
@@ -37,6 +38,7 @@
         name        "TPTOP.TPC.RFIR";
         scomaddr    0x01040001;
         capture     group default;
+        capture     group FirRegs;
     };
 
     register TP_CHIPLET_FIR_MASK
@@ -45,6 +47,7 @@
         scomaddr    0x01040002;
         capture     type secondary;
         capture     group default;
+        capture     group FirRegs;
     };
 
     ############################################################################
@@ -58,6 +61,7 @@
         reset       (&, 0x0104000b);
         mask        (|, 0x0104000f);
         capture     group default;
+        capture     group FirRegs;
     };
 
     register TP_LFIR_AND
@@ -74,6 +78,7 @@
         scomaddr    0x0104000d;
         capture     type secondary;
         capture     group default;
+        capture     group FirRegs;
     };
 
     register TP_LFIR_MASK_AND
@@ -96,6 +101,7 @@
         scomaddr    0x01040010;
         capture     type secondary;
         capture     group default;
+        capture     group FirRegs;
     };
 
     register TP_LFIR_ACT1
@@ -104,5 +110,18 @@
         scomaddr    0x01040011;
         capture     type secondary;
         capture     group default;
+        capture     group FirRegs;
+    };
+
+    ############################################################################
+    # Error Report Registers
+    ############################################################################
+
+    register TP_ERROR_STATUS
+    {
+        name        "TPTOP.TPC.ERROR_STATUS";
+        scomaddr    0x01030009;
+        capture     group default;
+        capture     group CerrRegs;
     };
 
diff --git a/src/usr/diag/prdf/common/plat/pegasus/prdfCenMembuf.C b/src/usr/diag/prdf/common/plat/pegasus/prdfCenMembuf.C
index 4083d449a..b35326c15 100755
--- a/src/usr/diag/prdf/common/plat/pegasus/prdfCenMembuf.C
+++ b/src/usr/diag/prdf/common/plat/pegasus/prdfCenMembuf.C
@@ -33,6 +33,7 @@
 #include <prdfGlobal.H>
 #include <iipSystem.h>
 #include <prdfLaneRepair.H>
+#include <UtilHash.H>
 
 using namespace TARGETING;
 
@@ -40,6 +41,7 @@ using namespace TARGETING;
 
 namespace PRDF
 {
+
 namespace Membuf
 {
 
@@ -200,6 +202,26 @@ int32_t PreAnalysis( ExtensibleChip * i_mbChip, STEP_CODE_DATA_STRUCT & i_sc,
 
     o_analyzed = false;
 
+    // Get memory capture data.
+    CaptureData & cd = i_sc.service_data->GetCaptureData();
+    CenMembufDataBundle * mbdb = getMembufDataBundle( i_mbChip );
+    ExtensibleChip * mcsChip = mbdb->getMcsChip();
+    if ( NULL != mcsChip )
+    {
+        mcsChip->CaptureErrorData( cd, Util::hashString("FirRegs") );
+        mcsChip->CaptureErrorData( cd, Util::hashString("CerrRegs") );
+
+        for ( uint32_t i = 0; i < MAX_MBA_PER_MEMBUF; i++ )
+        {
+            ExtensibleChip * mbaChip = mbdb->getMbaChip(i);
+            if ( NULL != mbaChip )
+            {
+                mbaChip->CaptureErrorData( cd, Util::hashString("FirRegs") );
+                mbaChip->CaptureErrorData( cd, Util::hashString("CerrRegs") );
+            }
+        }
+    }
+
     // Check for a Centaur Checkstop
     do
     {
@@ -207,8 +229,6 @@ int32_t PreAnalysis( ExtensibleChip * i_mbChip, STEP_CODE_DATA_STRUCT & i_sc,
         if ( i_sc.service_data->GetFlag(ServiceDataCollector::UNIT_CS) )
             break;
 
-        CenMembufDataBundle * mbdb = getMembufDataBundle(i_mbChip);
-        ExtensibleChip * mcsChip = mbdb->getMcsChip();
         if ( NULL == mcsChip )
         {
             PRDF_ERR( PRDF_FUNC"CenMembufDataBundle::getMcsChip() failed" );
diff --git a/src/usr/diag/prdf/common/plat/pegasus/prdfP8Mcs.C b/src/usr/diag/prdf/common/plat/pegasus/prdfP8Mcs.C
index 4177f59d9..b74e8b44e 100755
--- a/src/usr/diag/prdf/common/plat/pegasus/prdfP8Mcs.C
+++ b/src/usr/diag/prdf/common/plat/pegasus/prdfP8Mcs.C
@@ -32,6 +32,7 @@
 #include <prdfGlobal.H>
 #include <iipSystem.h>
 #include <prdfP8McsDataBundle.H>
+#include <prdfCenMembufDataBundle.H>
 
 //##############################################################################
 //
@@ -94,20 +95,6 @@ int32_t CheckCentaurCheckstop( ExtensibleChip * i_mcsChip,
         // Set the cause attention type
         i_sc.service_data->SetCauseAttentionType(UNIT_CS);
 
-        // Collect FFDC
-        // FIXME: RTC: 63753 (CENT_XSTP_FFDC capture group still needs to be
-        // populated with list of registers provided by Marc or Ken).
-        i_mcsChip->CaptureErrorData(i_sc.service_data->GetCaptureData(),
-                                    Util::hashString("CENT_XSTP_FFDC"));
-
-        P8McsDataBundle * mcsdb = getMcsDataBundle( i_mcsChip );
-        ExtensibleChip * membChip = mcsdb->getMembChip();
-        if ( NULL != membChip )
-        {
-            membChip->CaptureErrorData( i_sc.service_data->GetCaptureData(),
-                                        Util::hashString("CENT_XSTP_FFDC") );
-        }
-
     } while (0);
 
     return l_rc;
@@ -125,12 +112,35 @@ int32_t PreAnalysis ( ExtensibleChip * i_mcsChip, STEP_CODE_DATA_STRUCT & i_sc,
 {
     o_analyzed = false;
 
-    int32_t l_rc = SUCCESS;
+    // Get memory capture data.
+    CaptureData & cd = i_sc.service_data->GetCaptureData();
+    P8McsDataBundle * mcsdb = getMcsDataBundle( i_mcsChip );
+    ExtensibleChip * membChip = mcsdb->getMembChip();
+    if ( NULL != membChip )
+    {
+        membChip->CaptureErrorData( cd, Util::hashString("FirRegs") );
+        membChip->CaptureErrorData( cd, Util::hashString("CerrRegs") );
+
+        CenMembufDataBundle * mbdb = getMembufDataBundle( membChip );
+        for ( uint32_t i = 0; i < MAX_MBA_PER_MEMBUF; i++ )
+        {
+            ExtensibleChip * mbaChip = mbdb->getMbaChip(i);
+            if ( NULL != mbaChip )
+            {
+                mbaChip->CaptureErrorData( cd, Util::hashString("FirRegs") );
+                mbaChip->CaptureErrorData( cd, Util::hashString("CerrRegs") );
+            }
+        }
+    }
 
     // Check for a Centaur Checkstop
-    l_rc = CheckCentaurCheckstop(i_mcsChip, i_sc);
+    int32_t o_rc = CheckCentaurCheckstop( i_mcsChip, i_sc );
+    if ( SUCCESS != o_rc )
+    {
+        PRDF_ERR( "[Mcs::PreAnalysis] CheckCentaurCheckstop() failed" );
+    }
 
-    return l_rc;
+    return o_rc;
 }
 PRDF_PLUGIN_DEFINE( Mcs, PreAnalysis );