Disable SLW bars after Master Winkle.

Change-Id: I915d6cb9068a7a065ce7ffaa675309caa871f79a
RTC: 46350
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/2121
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

6 files changed, 845 insertions, 709 deletions

diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pba_bar_config.C b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pba_bar_config.C
index 08b078fe0..0ad332f02 100644
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pba_bar_config.C
+++ b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pba_bar_config.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_pba_bar_config.C,v 1.2 2012/09/25 20:18:50 stillgs Exp $
+// $Id: p8_pba_bar_config.C,v 1.3 2012/10/23 16:09:37 stillgs Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pba_bar_config.C,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -29,134 +29,151 @@
 //------------------------------------------------------------------------------
 // *! OWNER NAME: Klaus P. Gungl         Email: kgungl@de.ibm.com
 // *!
-// *! 
+// *!
 /// \file p8_pba_bar_config.C
 /// \brief Initialize PAB and PAB_MSK of PBA
-// *!        
-// *! The purpose of this procedure is to set the PBA BAR, PBA BAR Mask and PBA scope value / registers
-// *! 
-// *! Following proposals here: pass values for one set of pbabar, pass reference to structure for one set of pbabar, pass struct of struct containing  
-// *! all setup values  
-// *!   
-// *! High-level procedure flow:
-// *!   parameter checking
-// *!   set PBA_BAR
-// *!   set PBA_BARMSK
-// *!  
-// *! Procedure Prereq:
-// *!   o System clocks are running
-// *!
-// *! list of changes
-// *! 2011/11/22 all variables / passing calling parameters are uint64_t, cmd_scope is enum, MASK is not bitmask parameter but size
-// *!            structure for init contain uint64_t only.       
-// *!
+///
+/// \verbatim
+///     The purpose of this procedure is to set the PBA BAR, PBA BAR Mask and
+///     PBA scope value / registers
+///
+///     Following proposals here: pass values for one set of pbabar, pass reference to structure for one set of pbabar, pass struct of struct containing
+///     all setup values
+///
+///     High-level procedure flow:
+///       parameter checking
+///       set PBA_BAR
+///      set PBA_BARMSK
+///
+///    Procedure Prereq:
+///      o System clocks are running
+///
+///  CQ Class:  power_management
+/// \endverbatim
+///
+///   list of changes
+///     2011/11/2   all variables / passing calling parameters are uint64_t,    
+///                 cmd_scope is enum, MASK is not bitmask parameter but size    
+///                 structure for init contain uint64_t only.                    
+///
+///     2012/10/0   made isPowerofTwo() and PowerOfTwoRoundedup() inline
+///                 included pba_firmware_registers.h vs pba_firmware_register.H  
+///
+///     2012/10/18  Added support for BAR reset (BAR=0, Size=0) as being legal
+///                 Added 1M alignment checking
+///
 //------------------------------------------------------------------------------
 
-    
-// ----------------------------------------------------------------------
+
+// -----------------------------------------------------------------------------
 // Includes
-// ----------------------------------------------------------------------
+// -----------------------------------------------------------------------------
 #include <fapi.H>
 #include "p8_scom_addresses.H"
 #include "p8_pba_init.H"
 #include "p8_pba_bar_config.H"
-#include "pba_firmware_register.H"
+//#include "pba_firmware_register.H"
+#include "pba_firmware_registers.h"
 #include "p8_pm.H"
 
 
 extern "C" {
 
 
-using namespace fapi;  
+using namespace fapi;
 
-// ---------------------------------------------------------------------- 
+// -----------------------------------------------------------------------------
 // Constant definitions
-// ----------------------------------------------------------------------
-                              
+// -----------------------------------------------------------------------------
+
 // for range checking            0x0123456701234567
 #define BAR_ADDR_RANGECHECK_     0x0003FFFFFFF00000ull
 #define BAR_ADDR_RANGECHECK_HIGH 0xFFFC000000000000ull
 #define BAR_ADDR_RANGECHECK_LOW  0x00000000000FFFFFull
-#define BAR_SIZE_RANGECHECK      0x000001FFFFF00000ull
-#define BAR_SIZE_RANGECHECK_HIGH 0xFFFFFE0000000000ull
-#define BAR_SIZE_RANGECHECK_LOW  0x00000000000FFFFFull
 
-// ----------------------------------------------------------------------
+// -----------------------------------------------------------------------------
 // Global variables
-// ----------------------------------------------------------------------
+// -----------------------------------------------------------------------------
 
-// ----------------------------------------------------------------------
+// -----------------------------------------------------------------------------
 // Prototypes
-// ----------------------------------------------------------------------
+// -----------------------------------------------------------------------------
 
-// ---------------------------------------------------------------------- 
+// -----------------------------------------------------------------------------
 // Function definitions
-// ----------------------------------------------------------------------
-
-uint64_t PowerOf2Roundedup (uint64_t value);
-
-
-// --------------------------------------------- p8_pba_bar_config ----
-// function: 
-// initialize initialize a specific set of PBA_BAR (=cmd_scope and address), PBA_BARMSK (mask/size)
-// pass values directly
-//! init_pba_bar_ps
-//! initialize a set of  PBA_BAR and PBA_BARMSK registers, calling parameters: reference to structure of initialization values
-/*!
-@param i_target the target 
-@param i_index specifies which set of BAR / BARMSK registers to set. [0..3]
-@param i_pba_bar_addr PBA base address - 1MB grandularity
-@param i_pba_bar_size PBA region size in MB;  if not a power of two value, 
-        the value will be rounded up to the next power of 2 for setting the 
-        hardware mask
-@param i_pba_cmd_scope command scope according to pba spec
-*/ 
-
-fapi::ReturnCode 
+// -----------------------------------------------------------------------------
+
+inline bool isPowerOfTwo (uint64_t value);
+inline uint64_t PowerOf2Roundedup (uint64_t value);
+
+
+/// --------------------------------------------- p8_pba_bar_config ------------
+/// Initialize a specific set of PBA_BAR (=cmd_scope and address),
+///  PBA_BARMSK (mask/size)
+///
+///  @param i_target the target
+///  @param i_index specifies which set of BAR/BARMSK registers to set. [0..3]
+///  @param i_pba_bar_addr PBA base address - 1MB grandularity
+///  @param i_pba_bar_size PBA region size in MB;  if not a power of two value,
+///          the value will be rounded up to the next power of 2 for setting the
+///          hardware mask
+///  @param i_pba_cmd_scope command scope according to pba spec
+fapi::ReturnCode
 p8_pba_bar_config (const Target&  i_target,
-		             uint32_t       i_index, 
+		             uint32_t       i_index,
 		             uint64_t       i_pba_bar_addr,
 		             uint64_t       i_pba_bar_size,
-		             uint64_t       i_pba_cmd_scope 
+		             uint64_t       i_pba_cmd_scope
                      )
 {
 
 
-    ecmdDataBufferBase  data(64); 
+    ecmdDataBufferBase  data(64);
     fapi::ReturnCode    l_rc;
     uint32_t            l_ecmdRc = 0;
-    
-    pba_barn_t          bar;  
+
+    pba_barn_t          bar;
     pba_barmskn_t       barmask;
-    
+
     uint64_t            work_size;
 
-    FAPI_DBG("Called with index %x, address 0x%16llX, size 0x%16llX scope 0x%16llX", 
-                        i_index, i_pba_bar_addr, i_pba_bar_size, i_pba_cmd_scope);
+    FAPI_DBG("Called with index %x, address 0x%16llX, size 0x%llX scope 0x%llX",
+                       i_index, i_pba_bar_addr, i_pba_bar_size, i_pba_cmd_scope);
 
     // check if pba_bar scope in range
-    if ( i_pba_cmd_scope > PBA_CMD_SCOPE_FOREIGN1 ) 
+    if ( i_pba_cmd_scope > PBA_CMD_SCOPE_FOREIGN1 )
     {
         FAPI_ERR("ERROR: PB Command Scope out of Range");
         FAPI_SET_HWP_ERROR(l_rc, RC_PROC_PBA_BAR_SCOPE_OUT_OF_RANGE);
         return l_rc;
     }
 
-    // check if pba_addr amd pba_size are within range, high order bits checked, not low order!
-    // this means if we need a check for "is this value on the correct boundary value => needs to be implemented
-    if ( (BAR_ADDR_RANGECHECK_HIGH & i_pba_bar_addr) != 0x0ull) 
+    // Check if pba_addr amd pba_size are within range,
+    // High order bits checked to ensure a valid real address
+    if ( (BAR_ADDR_RANGECHECK_HIGH & i_pba_bar_addr) != 0x0ull )
     {
         FAPI_ERR("ERROR: Address out of Range");
         FAPI_SET_HWP_ERROR(l_rc, RC_PROC_PBA_ADDR_OUT_OF_RANGE);
         return l_rc;
-    } 
-    if ( (i_pba_bar_size) == 0x0ull) 
+    }
+
+    // Low order bits checked for alignment
+    if ( (BAR_ADDR_RANGECHECK_LOW & i_pba_bar_addr) != 0x0ull )
+    {
+        FAPI_ERR("ERROR: Address must be on a 1MB boundary");
+        FAPI_SET_HWP_ERROR(l_rc, RC_PROC_PBA_ADDR_ALIGNMENT_ERROR);
+        return l_rc;
+    }
+
+    // Check if the size is 0 but the BAR is not zero.  If so, return error.
+    // The combination of both the size and BAR being zero is legal.
+    if ( (i_pba_bar_size == 0x0ull) && (i_pba_bar_size != 0x0ull) )
     {
         FAPI_ERR("ERROR: Size must be 1MB or greater");
-        FAPI_SET_HWP_ERROR(l_rc, RC_PROC_PBA_BAR_MASK_OUT_OF_RANGE);  // \todo change xml!!!
+        FAPI_SET_HWP_ERROR(l_rc, RC_PROC_PBA_BAR_SIZE_INVALID);
         return l_rc;
-    } 
-    
+    }
+
     // The PBA Mask indicates which bits from 23:43 (1MB grandularity) are
     // enabled to be passed from the OCI addresses.  Inverting this mask
     // indicates which address bits are going to come from the PBA BAR value.
@@ -193,95 +210,88 @@ p8_pba_bar_config (const Target&  i_target,
     //    FAPI_SET_HWP_ERROR(rc, RC_PROCPM_POREBAR_IMAGE_ADDR_ERROR);
     //    return rc;
     //}
-    
-    
-    
-    // put the parameters into the correct fields 
+
+
+
+    // put the parameters into the correct fields
     bar.value=0;
     bar.fields.cmd_scope = i_pba_cmd_scope;
     bar.fields.addr = i_pba_bar_addr >> 20;
-    
-    FAPI_DBG("bar.fields   address  0x%16llX, scope  0x%16llX", 
+
+    FAPI_DBG("\tbar.fields addr  0x%16llX, scope  0x%llX",
                         bar.fields.addr, bar.fields.cmd_scope);
-    FAPI_DBG("bar.value             0x%16llX", bar.value);
-    
-     // Write the BAR
+    FAPI_DBG("\tbar.value        0x%16llX", bar.value);
+
+    // Write the BAR
     l_ecmdRc |= data.setDoubleWord(0, bar.value);
-    if (l_ecmdRc) 
+    if (l_ecmdRc)
     {
        FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", l_ecmdRc);
        l_rc.setEcmdError(l_ecmdRc);
        return l_rc;
     }
-    
-    FAPI_DBG("  PBA_BAR%x:  %16llX", i_index,  data.getDoubleWord(0));
+
+    FAPI_DBG("\tPBA_BAR%x:        0x%16llX", i_index,  data.getDoubleWord(0));
     l_rc = fapiPutScom(i_target, PBA_BARs[i_index], data);
-    if(l_rc) 
-    { 
+    if(l_rc)
+    {
         FAPI_ERR("PBA_BAR Putscom failed");
         return l_rc;
     }
-  
+
     // Compute and write the mask based on passed region size.
-    
-    // If the size is already a power of 2, then set the mask to that value - 1. 
+
+    // If the size is already a power of 2, then set the mask to that value - 1.
     // If the is not a power of 2, then set the mask the rounded up power of 2
     // value minus 1.
-    
+
     work_size = PowerOf2Roundedup(i_pba_bar_size);
-    FAPI_DBG("  i_pba_bar_size %16llu work_size:  %16llu", i_pba_bar_size, work_size);   
-    
-    barmask.value=0;   
+    FAPI_DBG("\ti_pba_bar_size: 0x%llX work_size: 0x%llX", i_pba_bar_size, work_size);
+
+    barmask.value=0;
     barmask.fields.mask = work_size-1;
-    
-    FAPI_DBG("bar.fields   mask  0x%16llX", barmask.fields.mask);
-   
-    
+
+    FAPI_DBG("\tbar.fields mask  0x%16llX", barmask.fields.mask);
+    FAPI_DBG("\tbar.value        0x%16llX", barmask.value);
+
     // Write the MASK
-     
-    // The size is tranlated to a mask by:
-    //  Shifting the s
-    //
-    //
-    //
-    
     l_ecmdRc |= data.setDoubleWord(0, barmask.value);
-    if (l_ecmdRc) 
+    if (l_ecmdRc)
     {
-       FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", l_ecmdRc);
-       l_rc.setEcmdError(l_ecmdRc);
-       return l_rc;
+        FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", l_ecmdRc);
+        l_rc.setEcmdError(l_ecmdRc);
+        return l_rc;
     }
-     
-    FAPI_DBG("  PBA_BARMSK%x:  %16llu", i_index,  data.getDoubleWord(0));
+
+    FAPI_DBG("  PBA_BARMSK%x:     0x%16llX", i_index,  data.getDoubleWord(0));
     l_rc = fapiPutScom(i_target, PBA_BARMSKs[i_index], data);
-    if(l_rc) 
-    { 
-      FAPI_ERR("PBA_MASK Putscom failed");
-      return l_rc;
+    if(l_rc)
+    {
+        FAPI_ERR("PBA_MASK Putscom failed");
+        return l_rc;
     }
 
     return l_rc;
-}  
+}
 
 ///-----------------------------------------------------------------------------
 /// Determine if a number is a power of two or not
-///----------------------------------------------------------------------------- 
-bool
+///-----------------------------------------------------------------------------
+inline bool
 isPowerOfTwo(uint64_t value)
 {
-    // if value ANDed with the value-1 is 0, then value is a power of 2. 
+    // if value ANDed with the value-1 is 0, then value is a power of 2.
     // if value is 0, this is considered not a power of 2 and will return false.
-   
+
     return !(value & (value - 1));
-   
-} 
- 
-///----------------------------------------------------------------------------- 
-/// Round up to next higher power of 2 (return value if it's already a power of 
+
+}
+
+///-----------------------------------------------------------------------------
+/// Round up to next higher power of 2 (return value if it's already a power of
 /// 2).
-///----------------------------------------------------------------------------- 
-uint64_t
+///-----------------------------------------------------------------------------
+inline uint64_t
 PowerOf2Roundedup (uint64_t value)
 {
     if (value < 0)
@@ -295,6 +305,6 @@ PowerOf2Roundedup (uint64_t value)
     return value+1;
 }
 
- 
+
 } //end extern C
 
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_set_pore_bar.C b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_set_pore_bar.C
index fabf56d25..ef587eef0 100644
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_set_pore_bar.C
+++ b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_set_pore_bar.C
@@ -20,7 +20,8 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_set_pore_bar.C,v 1.1 2012/08/23 04:58:48 stillgs Exp $
+
+// $Id: p8_set_pore_bar.C,v 1.3 2012/10/23 20:52:31 stillgs Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_set_pore_bar.C,v $
 //-------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -44,30 +45,40 @@
 ///     image is placed is passed.  This is used to establish the PBA BAR and
 ///     mask hardware to set the legal bounds for SLW accesses.
 ///
-///     The BAR defines address bits 14:43 in natural bit alignment (eg no shifting)
-///     The Mask defines validity for bits 23:43 in natural bit alignment.  This
-///         is a "thermometer" mask to define a power of 2 size.
+///     The BAR defines address bits 14:43 in natural bit alignment (eg no
+///     shifting)
+///
+///     The Size (in MB) of the region where image is located.
+///         If not a power of two value, the value will be rounded up to the
+///         next power of 2 for setting the hardware mask
+///
+///         If 0 is defined and the BAR is also defined as 0, then the BAR
+///         is set (to 0) but no image accessing is done as this is considered
+///         a BAR reset condition.  The TBA and MRR values in the PORE-SLW are
+///         not altered.
 ///
-///         A "1" in the mask indicates that bit location comes from the SLW; a "0"
-///         indicates the bit comes from the BAR.  Thus, the size of the region is
-///         ((mask+1)) MB.  (eg the mask value 7 yields an 8MB region)
+///         If 0 is defined and the BAR is NOT 0, an error is returned as this
+///         is defining a zero sized, real region.
 ///
-///     Check that passed address is within the 50 bit real address range
-///     Check that image address + image size does not extend past the 50 bit
-///         boundary
+///     Flow (given BAR and Size are ok per the above)
+///        Check that passed address is within the 50 bit real address range
+///        Check that image address + image size does not extend past the 50 bit
+///            boundary
 ///
-///     Read image link address at image offset 0x10
-///     Link Address(0:1) is the OCI region that will invoke the MRR.  These
-///         are set into MRR(30:31).
-///     Calculate MRR address (32:63) = image address - link address (32 bit)
-///     Store MRR to PORE SLW
+///        Read image link address at image offset 0x10
+///        Link Address(0:1) is the OCI region that will invoke the MRR.  These
+///            are set into MRR(30:31).
+///        Calculate MRR address (32:63) = image address - link address (32 bit)
+///        Store MRR to PORE SLW
 ///
-///     Call p8_pba_bar_config to set up PBA BAR 2 with the address and
-///         size of the SLW region as passed via calling parameters
+///        Call p8_pba_bar_config to set up PBA BAR 2 with the address and
+///            size of the SLW region as passed via calling parameters
 ///         i_mem_bar and i_mem_mask.
 ///
 ///  Procedure Prereq:
 ///     - SLW image memory region has been allocated and XIP image loaded.
+///
+///  CQ Class:  power_management
 /// \endverbatim
 ///
 //-------------------------------------------------------------------------------
@@ -83,7 +94,7 @@
 #include "p8_pm.H"
 #include "p8_pba_init.H"
 #include "p8_pba_bar_config.H"
-#include "pba_firmware_register.H"
+//#include "pba_firmware_registers.h"
 #include "pgp_pba.h"
 #include "sbe_xip_image.h"
 
@@ -122,7 +133,8 @@ fapi::ReturnCode pba_slave_reset(   const fapi::Target& i_target,
 /// \param[in] i_mem_size   Size (in MB) of the region where image is located
 ///                         if not a power of two value, the value will be
 ///                         rounded up to the next power of 2 for setting the
-///                         hardware mask
+///                         hardware mask.  The value of 0 is only legal if
+///                         i_mem_bar is also 0;  else an error is indicated.
 /// \param[in] i_mem_type   Defines where the SLW image was loaded.  See
 ///                         p8_set_pore_bar.H enum for valid values.
 ///
@@ -131,7 +143,6 @@ fapi::ReturnCode pba_slave_reset(   const fapi::Target& i_target,
 /// \retval RC_PROCPM_POREBAR_LOC_ERROR
 /// \retval RC_PROCPM_POREBAR_IMAGE_ADDR_ERROR (future version)
 /// \retval RC_PROCPM_POREBAR_IMAGE_PLACEMENT_ERROR (future version)
-
 fapi::ReturnCode
 p8_set_pore_bar(      const fapi::Target& i_target,
                         void                *i_image,
@@ -165,304 +176,315 @@ p8_set_pore_bar(      const fapi::Target& i_target,
 
 
     // -----------------------------------------------------------------
-
-    FAPI_INF("Executing p8_set_pore_bar...");
-    image_address = (uint64_t) i_image;
-    FAPI_DBG("Passed address 0x%16llX ", image_address);
-
-    // Get the Table Base Address from the image
-    l_ecmdRc = sbe_xip_get_scalar((void*)   i_image,
-                                            "slw_branch_table",
-                                            &slw_branch_table_address);
-    if (l_ecmdRc)
-    {
-        FAPI_ERR("Get XIP of slw_branch_table failed. rc = %x\n", l_ecmdRc);
-        FAPI_SET_HWP_ERROR(rc, RC_PROCPM_POREBAR_IMAGE_BRANCH_VALUE_ERROR);
-        return rc;
-    }
-    FAPI_DBG("slw_branch_table_address:   %16llX", slw_branch_table_address);
-
-    // Initialize the ecmdDataBuffer
-    l_ecmdRc |= data.clear();
-    l_ecmdRc |= data.setBitLength(64);
-    if(l_ecmdRc)
+    do
     {
-        FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", l_ecmdRc);
-        rc.setEcmdError(l_ecmdRc);
-        return rc;
-    }
+        FAPI_INF("Executing p8_set_pore_bar...");
+        image_address = (uint64_t) i_image;
+        FAPI_DBG("Passed address 0x%16llX ", image_address);
 
+        // Check if this is a BAR reset case.
+        if (i_mem_size == 0)
+        {
+            if(i_mem_bar != 0)
+            {
+                FAPI_ERR("SLW Size is 0 but BAR is non-zero:  0x%16llx", i_mem_bar );
+                FAPI_SET_HWP_ERROR(rc, RC_PROCPM_POREBAR_SIZE0_ERROR);
+                break;
+            }
+            else
+            {
+                FAPI_DBG("Calling pba_bar_config to BAR %x Addr: 0x%16llX  Size: 0x%16llX",
+                           pba_bar, i_mem_bar, i_mem_size);
+
+                // Set the PBA BAR for the SLW region
+                FAPI_EXEC_HWP(rc, p8_pba_bar_config, i_target,
+                                                       pba_bar,
+                                                       i_mem_bar,
+                                                       i_mem_size,
+                                                       slw_pba_cmd_scope);
+
+                // No rc check is made as we're exiting anyway.
+
+                // Exit the procedure as we don't want to access the image nor
+                // touch the SLW TBA or MRR settings.
+                break;
+            }
+        }
 
-    // Setup the the table base address register
-    //
-    //  Table Base Address Register layout
-    //  16      Interface (0=PIB, 1=OCI)
-    //  17      Reserved
-    //  18:23   Chiplet ID (used only for PIB fetch; unused for OCI)-SLW unused
-    //  24:27   PIB ID (used only for PIB fetch; unused for OCI)-SLW unused
-    //  28:31   PORT ID (used only for PIB fetch; unused for OCI)-SLW unused
-    //  32:64   Table base address for jump table
-    //
-    //  1   2         3  3     6
-    //  6789012345678901 2-----3
-    //  1                           OCI
-    //   0
-    //    000000                    Chiplet ID
-    //          0000                PIB  ID
-    //              0000            PORT ID
-    //
-    //  For SLW images that will run on PORE-SLW, the PORT ID is set to C
-    //
-    //
-
-    // Set the table base address (32:63) with passed value
-    l_ecmdRc |= data.setDoubleWord( 0, slw_branch_table_address);
-    if(l_ecmdRc)
-    {
-        FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", l_ecmdRc);
-        rc.setEcmdError(l_ecmdRc);
-        return rc;
-    }
-    rc = fapiPutScom(i_target, PORE_SLW_TABLE_BASE_ADDR_0x00068008, data);
-    if (rc)
-    {
-        FAPI_ERR("Put SCOM error for Table Base Address");
-        return rc;
-    }
-    FAPI_INF("SLW PORE Table Base Address set to 0x%16llx", data.getDoubleWord(0));
-
-
-
-    // Setup the memory relocation register
-    //
-    // This is hardcoded as the SLW image build process has all images to be:
-    //  1) Relocatable and thus must have the region match bits set
-    //  2) Built for region 0x80000XXX
-    //
-    //  MRR Layout
-    //      30:31:  Memory Reloc Region - 2 MSbs of 32 bit address that
-    //          defines the region match
-    //      32:51   Memory Relocation Base Address added to 0:19 of the OCI
-    //              address
-    //
-    //    Table Base Address Register layout
-    //    16      Interface (0=PIB, 1=OCI)
-    //    17      Reserved
-    //    18:23   Chiplet ID (used only for PIB fetch; unused for OCI)-SLW unused
-    //    24:27   PIB ID (used only for PIB fetch; unused for OCI)-SLW unused
-    //    28:31   PORT ID (used only for PIB fetch; unused for OCI)-SLW unused
-    //    32:64   Table base address for jump table
-    //
-    //    1   2         3  3     6
-    //    6789012345678901 2-----3
-    //    1                           OCI
-    //     0
-    //      000000                    Chiplet ID
-    //            0000                PIB  ID
-    //                0000            PORT ID
-    //
-    //    For SLW images that will run on PORE-SLW, the PORT ID is set to C in
-    //    the image but this is unused by the hardware.
-
-    l_ecmdRc |= data.flushTo0();
-
-    // Set 30:31 to 10 to yield a region of 0x8XXXXXXX (eg unused OCI region)
-    l_ecmdRc |= data.setBit( 30, 1);
 
-    if(l_ecmdRc)
-    {
-        FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", l_ecmdRc);
-        rc.setEcmdError(l_ecmdRc);
-        return rc;
-    }
+        // Get the Table Base Address from the image
+        l_ecmdRc = sbe_xip_get_scalar((void*)   i_image,
+                                                "slw_branch_table",
+                                                &slw_branch_table_address);
+        if (l_ecmdRc)
+        {
+            FAPI_ERR("Get XIP of slw_branch_table failed. rc = %x\n", l_ecmdRc);
+            FAPI_SET_HWP_ERROR(rc, RC_PROCPM_POREBAR_IMAGE_BRANCH_VALUE_ERROR);
+            break;
+        }
+        FAPI_DBG("slw_branch_table_address:   %16llX", slw_branch_table_address);
 
-    // SLW image has effective addresses in the form of 0x8XXXXXXX.
-    // The PORE memory relocation function adds the mem_reloc(32:52) to
-    // effective address 0:19 to form the real address where:
-    //      effective address(0:1) defines the region: 00 = memory/L3, 11 = SRAM
-    //      effective address(2:3) defines the PBA BAR to use (if memory/L3)
+        // Initialize the ecmdDataBuffer
+        l_ecmdRc |= data.clear();
+        l_ecmdRc |= data.setBitLength(64);
+        if(l_ecmdRc)
+        {
+            FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", l_ecmdRc);
+            rc.setEcmdError(l_ecmdRc);
+            break;
+        }
 
-    // Set the Memory Relocation Base based on the placement of the SLW image
-    if (i_mem_type == SLW_SRAM)
-    {
-        // Set the beginning of 512KB SRAM tank.
 
-        FAPI_DBG("SLW PORE Memory Relocation Register before SRAM 0x%16llx", data.getDoubleWord(0));
+        // Setup the the table base address register
+        //
+        //  Table Base Address Register layout
+        //  16      Interface (0=PIB, 1=OCI)
+        //  17      Reserved
+        //  18:23   Chiplet ID (used only for PIB fetch; unused for OCI)-SLW unused
+        //  24:27   PIB ID (used only for PIB fetch; unused for OCI)-SLW unused
+        //  28:31   PORT ID (used only for PIB fetch; unused for OCI)-SLW unused
+        //  32:64   Table base address for jump table
+        //
+        //  1   2         3  3     6
+        //  6789012345678901 2-----3
+        //  1                           OCI
+        //   0
+        //    000000                    Chiplet ID
+        //          0000                PIB  ID
+        //              0000            PORT ID
+        //
+        //  For SLW images that will run on PORE-SLW, the PORT ID is set to C
+        //
+        //
 
-        l_ecmdRc |= data.setOr(0x7FF80<<12, 32, 20);
+        // Set the table base address (32:63) with passed value
+        l_ecmdRc |= data.setDoubleWord( 0, slw_branch_table_address);
         if(l_ecmdRc)
         {
-            FAPI_ERR("Error (0x%x) manipulating ecmdDataBufferBase", l_ecmdRc);
+            FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", l_ecmdRc);
             rc.setEcmdError(l_ecmdRc);
-            return rc;
+            break;
         }
-    }
-    else if (i_mem_type == SLW_MEMORY || i_mem_type == SLW_L3)
-    {
-        // The 00 (from the buffer flush) in 0:1 goes toward PBA (memory or L3)
-        // Set to use the PBA with BAR(0:3) encoded in bits 2:3 (eg shift of 30)
-        // 0x80000 + 0xA0000 => 20000 (upper overflow discarded)
-        // The 00 in 0:1 goes toward PBA; 2:3 for PBA BAR 2
-        FAPI_DBG("SLW PORE PBA BAR %x", pba_bar_slw);
-        FAPI_DBG("SLW PORE Memory Relocation Register before MEM 0x%16llx", data.getDoubleWord(0));
-
-        l_ecmdRc |= data.setOr(pba_bar_slw<<28, 32, 20);
-        if(l_ecmdRc)
+        rc = fapiPutScom(i_target, PORE_SLW_TABLE_BASE_ADDR_0x00068008, data);
+        if (rc)
         {
-            FAPI_ERR("Error (0x%x) manipulating ecmdDataBufferBase", l_ecmdRc);
-            rc.setEcmdError(l_ecmdRc);
-            return rc;
+            FAPI_ERR("Put SCOM error for Table Base Address");
+            break;
         }
+        FAPI_INF("SLW PORE Table Base Address set to 0x%16llx", data.getDoubleWord(0));
 
-        FAPI_DBG("SLW PORE Memory Relocation Register after MEM 0x%16llx", data.getDoubleWord(0));
 
-        // Check that the bar address passed is 1MB aligned (eg bits 44:63 are zero)
+
+        // Setup the memory relocation register
+        //
+        // This is hardcoded as the SLW image build process has all images to be:
+        //  1) Relocatable and thus must have the region match bits set
+        //  2) Built for region 0x80000XXX
         //
-        region_masked_address = i_mem_bar & 0x00000000000FFFFF;
-        if (region_masked_address != 0 )
+        //  MRR Layout
+        //      30:31:  Memory Reloc Region - 2 MSbs of 32 bit address that
+        //          defines the region match
+        //      32:51   Memory Relocation Base Address added to 0:19 of the OCI
+        //              address
+        //
+        //    Table Base Address Register layout
+        //    16      Interface (0=PIB, 1=OCI)
+        //    17      Reserved
+        //    18:23   Chiplet ID (used only for PIB fetch; unused for OCI)-SLW unused
+        //    24:27   PIB ID (used only for PIB fetch; unused for OCI)-SLW unused
+        //    28:31   PORT ID (used only for PIB fetch; unused for OCI)-SLW unused
+        //    32:64   Table base address for jump table
+        //
+        //    1   2         3  3     6
+        //    6789012345678901 2-----3
+        //    1                           OCI
+        //     0
+        //      000000                    Chiplet ID
+        //            0000                PIB  ID
+        //                0000            PORT ID
+        //
+        //    For SLW images that will run on PORE-SLW, the PORT ID is set to C in
+        //    the image but this is unused by the hardware.
+
+        l_ecmdRc |= data.flushTo0();
+
+        // Set 30:31 to 10 to yield a region of 0x8XXXXXXX (eg unused OCI region)
+        l_ecmdRc |= data.setBit( 30, 1);
+
+        if(l_ecmdRc)
         {
-            FAPI_ERR("SLW BAR address is not 1MB aligned:  0x%16llx", i_mem_bar );
-            FAPI_SET_HWP_ERROR(rc, RC_PROCPM_POREBAR_PBABAR_ERROR);
-            return rc;
+            FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", l_ecmdRc);
+            rc.setEcmdError(l_ecmdRc);
+            break;
         }
 
+        // SLW image has effective addresses in the form of 0x8XXXXXXX.
+        // The PORE memory relocation function adds the mem_reloc(32:52) to
+        // effective address 0:19 to form the real address where:
+        //      effective address(0:1) defines the region: 00 = memory/L3, 11 = SRAM
+        //      effective address(2:3) defines the PBA BAR to use (if memory/L3)
 
-        // The PBA Mask indicates which bits from 23:43 (1MB grandularity) are
-        // enabled to be passed from the OCI addresses.  Inverting this mask
-        // indicates which address bits are going to come from the PBA BAR value.
-        // The image address (the starting address) must match these post mask bits
-        // to be resident in the range.
-        //
-        // Starting bit number: 64 bit Big Endian
-        //                                          12223344
-        //                                          60482604
-        // region_inverted_mask = i_mem_mask ^ BAR_MASK_LIMIT;  // XOR
+        // Set the Memory Relocation Base based on the placement of the SLW image
+        if (i_mem_type == SLW_SRAM)
+        {
+            // Set the beginning of 512KB SRAM tank.
 
+            FAPI_DBG("SLW PORE Memory Relocation Register before SRAM 0x%16llx", data.getDoubleWord(0));
 
-        // Check that the image address passed is within the memory region that
-        // is also passed.
-        //
-        // The PBA Mask indicates which bits from 23:43 (1MB grandularity) are
-        // enabled to be passed from the OCI addresses.  Inverting this mask
-        // indicates which address bits are going to come from the PBA BAR value.
-        // The image address (the starting address) must match these post mask bits
-        // to be resident in the range.
-        //
-        // Starting bit number: 64 bit Big Endian
-        //                                          12223344
-        //                                          60482604
-        // region_inverted_mask = i_mem_mask ^ BAR_MASK_LIMIT;  // XOR
-
-        // Set bits 14:22 as these are unconditional address bits
-        //region_inverted_mask = region_inverted_mask | BAR_ADDR_UNMASKED;
-        //computed_image_address = region_inverted_mask && image_address;
-        // Need to AND the address
-        //if (computed_image_address != i_mem_bar )
-        //{
-        //    FAPI_ERR("SLW image address check failure. ");
-        //    FAPI_SET_HWP_ERROR(rc, RC_PROCPM_POREBAR_IMAGE_ADDR_ERROR);
-        //    return rc;
-        //}
-
-
-        // Additionally, the size of the image must not extend beyond the above
-        // masked range either.
-
-        // Get the image size from the image itself
-        l_ecmdRc = sbe_xip_get_scalar((void*)   i_image,
-                                                "image_size",
-                                                 &image_size);
+            l_ecmdRc |= data.setOr(0x7FF80<<12, 32, 20);
+            if(l_ecmdRc)
+            {
+                FAPI_ERR("Error (0x%x) manipulating ecmdDataBufferBase", l_ecmdRc);
+                rc.setEcmdError(l_ecmdRc);
+                break;
+            }
+        }
+        else if (i_mem_type == SLW_MEMORY || i_mem_type == SLW_L3)
+        {
+            // The 00 (from the buffer flush) in 0:1 goes toward PBA (memory or L3)
+            // Set to use the PBA with BAR(0:3) encoded in bits 2:3 (eg shift of 30)
+            // 0x80000 + 0xA0000 => 20000 (upper overflow discarded)
+            // The 00 in 0:1 goes toward PBA; 2:3 for PBA BAR 2
+            FAPI_DBG("SLW PORE PBA BAR %x", pba_bar_slw);
+            FAPI_DBG("SLW PORE Memory Relocation Register before MEM 0x%16llx", data.getDoubleWord(0));
+
+            l_ecmdRc |= data.setOr(pba_bar_slw<<28, 32, 20);
+            if(l_ecmdRc)
+            {
+                FAPI_ERR("Error (0x%x) manipulating ecmdDataBufferBase", l_ecmdRc);
+                rc.setEcmdError(l_ecmdRc);
+                break;
+            }
+
+            FAPI_DBG("SLW PORE Memory Relocation Register after MEM 0x%16llx", data.getDoubleWord(0));
+
+            // Check that the bar address passed is 1MB aligned (eg bits 44:63 are zero)
+            //
+            region_masked_address = i_mem_bar & 0x00000000000FFFFF;
+            if (region_masked_address != 0 )
+            {
+                FAPI_ERR("SLW BAR address is not 1MB aligned:  0x%16llx", i_mem_bar );
+                FAPI_SET_HWP_ERROR(rc, RC_PROCPM_POREBAR_PBABAR_ERROR);
+                break;
+            }
+
+
+            // The PBA Mask indicates which bits from 23:43 (1MB grandularity) are
+            // enabled to be passed from the OCI addresses.  Inverting this mask
+            // indicates which address bits are going to come from the PBA BAR value.
+            // The image address (the starting address) must match these post mask bits
+            // to be resident in the range.
+            //
+            // Starting bit number: 64 bit Big Endian
+            //                                          12223344
+            //                                          60482604
+            // region_inverted_mask = i_mem_mask ^ BAR_MASK_LIMIT;  // XOR
+
+
+            // Check that the image address passed is within the memory region that
+            // is also passed.
+            //
+            // The PBA Mask indicates which bits from 23:43 (1MB grandularity) are
+            // enabled to be passed from the OCI addresses.  Inverting this mask
+            // indicates which address bits are going to come from the PBA BAR value.
+            // The image address (the starting address) must match these post mask bits
+            // to be resident in the range.
+            //
+            // Starting bit number: 64 bit Big Endian
+            //                                          12223344
+            //                                          60482604
+            // region_inverted_mask = i_mem_mask ^ BAR_MASK_LIMIT;  // XOR
+
+            // Set bits 14:22 as these are unconditional address bits
+            //region_inverted_mask = region_inverted_mask | BAR_ADDR_UNMASKED;
+            //computed_image_address = region_inverted_mask && image_address;
+            // Need to AND the address
+            //if (computed_image_address != i_mem_bar )
+            //{
+            //    FAPI_ERR("SLW image address check failure. ");
+            //    FAPI_SET_HWP_ERROR(rc, RC_PROCPM_POREBAR_IMAGE_ADDR_ERROR);
+            //    return rc;
+            //}
+
+
+            // Additionally, the size of the image must not extend beyond the above
+            // masked range either.
+
+            // Get the image size from the image itself
+            l_ecmdRc = sbe_xip_get_scalar((void*)   i_image,
+                                                    "image_size",
+                                                     &image_size);
+
+            if (l_ecmdRc)
+            {
+                FAPI_ERR("Get of XIP Image size failed");
+                FAPI_SET_HWP_ERROR(rc, RC_PROCPM_POREBAR_IMAGE_SIZE_ERROR);
+                break;
+            }
+
+            FAPI_DBG("SLW image size: 0x%08llX", image_size );
+            //  computed_last_image_address = image_address + image_size;
+            //
+            //  if (computed_last_image_address > region_end_address)
+            //    {
+            //        FAPI_ERR("SLW image placement error.");
+            //        FAPI_SET_HWP_ERROR(rc, RC_PROCPM_POREBAR_IMAGE_PLACEMENT_ERROR);
+            //        return rc;
+            //    }
 
-        if (l_ecmdRc)
+        }
+        else
         {
-            FAPI_ERR("Get of XIP Image size failed");
-            FAPI_SET_HWP_ERROR(rc, RC_PROCPM_POREBAR_IMAGE_SIZE_ERROR);
-            return rc;
+            FAPI_ERR("Invalid image location passed %x ", i_mem_type);
+            FAPI_SET_HWP_ERROR(rc, RC_PROCPM_POREBAR_LOC_ERROR);
+            break;
         }
 
-        FAPI_DBG("SLW image size: 0x%08llX", image_size );
-        //  computed_last_image_address = image_address + image_size;
-        //
-        //  if (computed_last_image_address > region_end_address)
-        //    {
-        //        FAPI_ERR("SLW image placement error.");
-        //        FAPI_SET_HWP_ERROR(rc, RC_PROCPM_POREBAR_IMAGE_PLACEMENT_ERROR);
-        //        return rc;
-        //    }
+        FAPI_INF("SLW PORE Memory Relocation Register set to 0x%16llx", data.getDoubleWord(0));
+        rc = fapiPutScom(i_target, PORE_SLW_MEMORY_RELOC_0x00068016, data);
+        if (rc)
+        {
+            FAPI_ERR("Put SCOM error for Memory Relocation Address");
+            break;
+        }
 
-    }
-    else
-    {
-        FAPI_ERR("Invalid image location passed %x ", i_mem_type);
-        FAPI_SET_HWP_ERROR(rc, RC_PROCPM_POREBAR_LOC_ERROR);
-        return rc;
-    }
+        FAPI_DBG("Calling pba_bar_config to BAR %x Addr: 0x%16llX  Size: 0x%16llX",
+                        pba_bar, i_mem_bar, i_mem_size);
 
-    FAPI_INF("SLW PORE Memory Relocation Register set to 0x%16llx", data.getDoubleWord(0));
-    rc = fapiPutScom(i_target, PORE_SLW_MEMORY_RELOC_0x00068016, data);
-    if (rc)
-    {
-        FAPI_ERR("Put SCOM error for Memory Relocation Address");
-        return rc;
-    }
+        // Set the PBA BAR for the SLW region
+        FAPI_EXEC_HWP(rc, p8_pba_bar_config, i_target,
+                                               pba_bar,
+                                               i_mem_bar,
+                                               i_mem_size,
+                                               slw_pba_cmd_scope);
+        if(rc)
+        {
+            break;
+        }
 
-    FAPI_DBG("Calling pba_bar_config to BAR %x Addr: 0x%16llX  Size: 0x%16llX",
-                    pba_bar, i_mem_bar, i_mem_size);
-
-    // Set the PBA BAR for the SLW region
-    FAPI_EXEC_HWP(rc, p8_pba_bar_config, i_target,
-                                           pba_bar,
-                                           i_mem_bar,
-                                           i_mem_size,
-                                           slw_pba_cmd_scope);
-    if(rc) { return rc; }
-
-    // Set the PBA Slave to use the above BAR
-    // \todo Does not yet comprehend the 24x7 setting to allow writing!!
-    //
-    // enable = 1;                 // Enable the slave
-    // mid_match_value=0x4;        // PORE-SLW engine
-    // mid_care_mask=0x7;          // Only the PORE-SLW
-    // write_ttype=0;              // DMA - though NA
-    // read_ttype=0;               // CL_RD_NC
-    // read_prefetch_ctl=0;        // Auto Early
-    // buf_invalidate_ctl=0;       // Disabled
-    // buf_alloc_w=0;              // SLW does not write.  24x7 will
-    // buf_alloc_a=1;              // SLW uses Buf A
-    // buf_alloc_b=0;              // SLW does not use buffer B
-    // buf_alloc_c=0;              // SLW does not use buffer C
-    // dis_write_gather=0;         // SLW does not write.  \todo 24x7
-    // wr_gather_timeout=0;        // SLW does not write   \todo 24x7
-    // write_tsize=0;              // SLW does not write   \todo 24x7
-    // extaddr=0;                  // Bits 23:36.  NA for SLW
-    //
-
-/*
-    // Clear the data buffer (for cleanliness)
-    l_ecmdRc |= data.flushTo0();
-
-
-    // set the PBASLVCTL reg
-    l_ecmdRc |= data.setBit(0);     // Enable the slave
-    l_ecmdRc |= data.setBit(1);     // PORE-SLW engine - 0b100
-    l_ecmdRc |= data.setBit(5,3);   // Care mask-only PORE-SLW
-    l_ecmdRc |= data.setBit(5,3);   // Allocate read buffer
-    l_ecmdRc |= data.setBit(5,3);   // Care mask-only PORE-SLW
-*/
-
-    // Slave 2 (PORE-SLW).  This is a read/write slave. Write gathering is
-    // allowed, but with the shortest possible timeout.  The slave is set up
-    // to allow normal reads and writes at initialization.  The 24x7 code may
-    // reprogram this slave for IMA writes using special code sequences that
-    // restore normal DMA writes after each IMA sequence.
-
-    rc = pba_slave_reset(i_target, SLW_PBA_SLAVE);
-    if (rc)
-    {
-        FAPI_ERR("PBA Slave Reset failed");
-        // \todo add FFDC
-        return rc;
-    }
+        // Set the PBA Slave to use the above BAR
+        // \todo Does not yet comprehend the 24x7 setting to allow writing!!
+        //
+        // enable = 1;                 // Enable the slave
+        // mid_match_value=0x4;        // PORE-SLW engine
+        // mid_care_mask=0x7;          // Only the PORE-SLW
+        // write_ttype=0;              // DMA - though NA
+        // read_ttype=0;               // CL_RD_NC
+        // read_prefetch_ctl=0;        // Auto Early
+        // buf_invalidate_ctl=0;       // Disabled
+        // buf_alloc_w=0;              // SLW does not write.  24x7 will
+        // buf_alloc_a=1;              // SLW uses Buf A
+        // buf_alloc_b=0;              // SLW does not use buffer B
+        // buf_alloc_c=0;              // SLW does not use buffer C
+        // dis_write_gather=0;         // SLW does not write.  \todo 24x7
+        // wr_gather_timeout=0;        // SLW does not write   \todo 24x7
+        // write_tsize=0;              // SLW does not write   \todo 24x7
+        // extaddr=0;                  // Bits 23:36.  NA for SLW
+        //
+
+    /*
+        // Clear the data buffer (for cleanliness)
+        l_ecmdRc |= data.flushTo0();
 
 
     ps.value = 0;
@@ -485,15 +507,58 @@ p8_set_pore_bar(      const fapi::Target& i_target,
         rc.setEcmdError(l_ecmdRc);
         return rc;
     }
+        // set the PBASLVCTL reg
+        l_ecmdRc |= data.setBit(0);     // Enable the slave
+        l_ecmdRc |= data.setBit(1);     // PORE-SLW engine - 0b100
+        l_ecmdRc |= data.setBit(5,3);   // Care mask-only PORE-SLW
+        l_ecmdRc |= data.setBit(5,3);   // Allocate read buffer
+        l_ecmdRc |= data.setBit(5,3);   // Care mask-only PORE-SLW
+    */
+
+        // Slave 2 (PORE-SLW).  This is a read/write slave. Write gathering is
+        // allowed, but with the shortest possible timeout.  The slave is set up
+        // to allow normal reads and writes at initialization.  The 24x7 code may
+        // reprogram this slave for IMA writes using special code sequences that
+        // restore normal DMA writes after each IMA sequence.
+
+        rc = pba_slave_reset(i_target, SLW_PBA_SLAVE);
+        if (rc)
+        {
+            FAPI_ERR("PBA Slave Reset failed");
+            // \todo add FFDC
+             break;
+        }
 
-    FAPI_DBG("  PBA_SLVCTL%x: 0x%16llx", pba_slave, data.getDoubleWord(0));
-    rc = fapiPutScom(i_target, PBA_SLVCTLs[pba_slave], data);
-    if (rc)
-    {
-        FAPI_ERR("Put SCOM error for PBA Slave Control");
-        return rc;
-    }
 
+        ps.value = 0;
+        ps.fields.enable = 1;
+        ps.fields.mid_match_value = OCI_MASTER_ID_PORE_SLW;
+        ps.fields.mid_care_mask = 0x7;
+        ps.fields.read_ttype = PBA_READ_TTYPE_CL_RD_NC;
+        ps.fields.read_prefetch_ctl = PBA_READ_PREFETCH_NONE;
+        ps.fields.write_ttype = PBA_WRITE_TTYPE_DMA_PR_WR;
+        ps.fields.wr_gather_timeout = PBA_WRITE_GATHER_TIMEOUT_2_PULSES;
+        ps.fields.buf_alloc_a = 1;
+        ps.fields.buf_alloc_b = 1;
+        ps.fields.buf_alloc_c = 1;
+        ps.fields.buf_alloc_w = 1;
+
+        l_ecmdRc |=  data.setDoubleWord(0, ps.value);
+        if(l_ecmdRc)
+        {
+            FAPI_ERR("Error (0x%x) manipulating ecmdDataBufferBase for PBASLVCTL", l_ecmdRc);
+            rc.setEcmdError(l_ecmdRc);
+            return rc;
+        }
+
+        FAPI_DBG("  PBA_SLVCTL%x: 0x%16llx", pba_slave, data.getDoubleWord(0));
+        rc = fapiPutScom(i_target, PBA_SLVCTLs[pba_slave], data);
+        if (rc)
+        {
+            FAPI_ERR("Put SCOM error for PBA Slave Control");
+            return rc;
+        }
+    } while (0);
     return rc;
 }
 
@@ -544,41 +609,41 @@ pba_slave_reset(const fapi::Target& i_target, uint32_t id)
     if (rc)
     {
         FAPI_ERR("Put SCOM error for PBA Slave Reset");
-        return rc;
     }
-
-    do
+    else
     {
-        rc = fapiGetScom(i_target, PBA_SLVRST_0x00064001, data);
-        if (rc)
+        do
         {
-            FAPI_ERR("Put SCOM error for PBA Slave Reset");
-            return rc;
-        }
-
-        psr.value = data.getDoubleWord(0);
-        if(l_ecmdRc)
-        {
-            FAPI_ERR("Error (0x%x) manipulating ecmdDataBufferBase for PBA_SLVRST", l_ecmdRc);
-            rc.setEcmdError(l_ecmdRc);
-            return rc;
-        }
-
-
-        if (!(psr.fields.in_prog & PBA_SLVRST_IN_PROG(id)))
-        {
-	        break;
-	    }
-
-        poll_count++;
-	    if (poll_count == PBA_SLAVE_RESET_TIMEOUT)
-        {
-	        FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PBA_SLVRST_TIMED_OUT);
-            break;
-	    }
-
-    } while (1);
-
+            rc = fapiGetScom(i_target, PBA_SLVRST_0x00064001, data);
+            if (rc)
+            {
+                FAPI_ERR("Put SCOM error for PBA Slave Reset");
+                break;
+            }
+
+            psr.value = data.getDoubleWord(0);
+            if(l_ecmdRc)
+            {
+                FAPI_ERR("Error (0x%x) manipulating ecmdDataBufferBase for PBA_SLVRST", l_ecmdRc);
+                rc.setEcmdError(l_ecmdRc);
+                break;
+            }
+
+
+            if (!(psr.fields.in_prog & PBA_SLVRST_IN_PROG(id)))
+            {
+	            break;
+	        }
+
+            poll_count++;
+	        if (poll_count == PBA_SLAVE_RESET_TIMEOUT)
+            {
+	            FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PBA_SLVRST_TIMED_OUT);
+                break;
+	        }
+
+        } while (1);
+    }
     return rc;
 }
 
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_set_pore_bar_errors.xml b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_set_pore_bar_errors.xml
index 14bcf0fc6..7c46057aa 100644
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_set_pore_bar_errors.xml
+++ b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_set_pore_bar_errors.xml
@@ -45,11 +45,15 @@
   <!-- *********************************************************************** -->
   <hwpError>
     <rc>RC_PROCPM_POREBAR_IMAGE_SIZE_ERROR</rc>
-    <description>XIP access to size value failed in p8_set_pore_bar</description>
     <description>Image address plus image size overflows PBA region in p8_set_pore_bar</description>
   </hwpError>
   <!-- *********************************************************************** -->
   <hwpError>
+    <rc>RC_PROCPM_POREBAR_SIZE0_ERROR</rc>
+    <description>An image  size of 0 was specified to p8_set_pore_bar but the BAR was not 0</description>
+  </hwpError>
+  <!-- *********************************************************************** -->
+  <hwpError>
     <rc>RC_PROCPM_POREBAR_IMAGE_PLACEMENT_ERROR</rc>
     <description>Image address plus image size overflows PBA region in p8_set_pore_bar</description>
   </hwpError>
diff --git a/src/usr/hwpf/hwp/core_activate/core_activate.C b/src/usr/hwpf/hwp/core_activate/core_activate.C
index a0e597bc1..1818ee32f 100644
--- a/src/usr/hwpf/hwp/core_activate/core_activate.C
+++ b/src/usr/hwpf/hwp/core_activate/core_activate.C
@@ -67,6 +67,7 @@
 //  Uncomment these files as they become available:
 #include    "proc_prep_master_winkle.H"
 #include    "proc_stop_deadman_timer.H"
+#include    "p8_set_pore_bar.H"
 // #include    "host_activate_slave_cores/host_activate_slave_cores.H"
 #include    "proc_switch_cfsim.H"
 
@@ -84,242 +85,243 @@ using   namespace   ISTEP_ERROR;
 //  Wrapper function to call 16.1 :
 //      host_activate_master
 //
-    void*    call_host_activate_master( void    *io_pArgs )
-    {
+void*    call_host_activate_master( void    *io_pArgs )
+{
 
-        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                   "call_host_activate_master entry" );
+    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+               "call_host_activate_master entry" );
 
-        errlHndl_t  l_errl  =   NULL;
-        IStepError  l_stepError;
+    errlHndl_t  l_errl  =   NULL;
+    IStepError  l_stepError;
 
-        // @@@@@    CUSTOM BLOCK:   @@@@@
+    // @@@@@    CUSTOM BLOCK:   @@@@@
 
-        do  {
+    do  {
 
-            // find the master core, i.e. the one we are running on
-            TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                       "call_host_activate_master: Find master core: " );
+        // find the master core, i.e. the one we are running on
+        TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+                   "call_host_activate_master: Find master core: " );
 
-            const TARGETING::Target*  l_masterCore  = getMasterCore( );
-            assert( l_masterCore != NULL );
+        const TARGETING::Target*  l_masterCore  = getMasterCore( );
+        assert( l_masterCore != NULL );
 
-            TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                       "call_host_activate_master: Find master chip: " );
-            TARGETING::Target* l_cpu_target = const_cast<TARGETING::Target *>
-                                              ( getParentChip( l_masterCore ) );
+        TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+                   "call_host_activate_master: Find master chip: " );
+        TARGETING::Target* l_cpu_target = const_cast<TARGETING::Target *>
+                                          ( getParentChip( l_masterCore ) );
 
-            //  dump physical path to target
-            EntityPath l_path;
-            l_path  =   l_cpu_target->getAttr<ATTR_PHYS_PATH>();
-            l_path.dump();
+        //  dump physical path to target
+        EntityPath l_path;
+        l_path  =   l_cpu_target->getAttr<ATTR_PHYS_PATH>();
+        l_path.dump();
+
+        // cast OUR type of target to a FAPI type of target.
+        const fapi::Target l_fapi_cpu_target(
+                                            TARGET_TYPE_PROC_CHIP,
+                                            reinterpret_cast<void *>
+                                            (const_cast<TARGETING::Target*>
+                                                        (l_cpu_target)) );
 
-            // cast OUR type of target to a FAPI type of target.
-            const fapi::Target l_fapi_cpu_target(
-                                                TARGET_TYPE_PROC_CHIP,
-                                                reinterpret_cast<void *>
-                                                (const_cast<TARGETING::Target*>
-                                                            (l_cpu_target)) );
 
 #if 1
-            //  SIMICS HACK - The values written by simics are not correct -
-            //  Write them here until we can get the actions files fixed.
-            //  @todo RTC 41384
-            const  uint64_t PORE_SBE_CONTROL_0x000E0001 =   0x00000000000E0001 ;
-            const  uint64_t MBOX_SBEVITAL_0x0005001C    =   0x000000000005001C ;
-            fapi::ReturnCode    rc;
-            ecmdDataBufferBase data(64);
-            uint32_t    sbe_code    =   0;
-
-            rc = fapiGetScom(   l_fapi_cpu_target,
+        //  SIMICS HACK - The values written by simics are not correct -
+        //  Write them here until we can get the actions files fixed.
+        //  @todo RTC 41384
+        const  uint64_t PORE_SBE_CONTROL_0x000E0001 =   0x00000000000E0001 ;
+        const  uint64_t MBOX_SBEVITAL_0x0005001C    =   0x000000000005001C ;
+        fapi::ReturnCode    rc;
+        ecmdDataBufferBase data(64);
+        uint32_t    sbe_code    =   0;
+
+        rc = fapiGetScom(   l_fapi_cpu_target,
+                            PORE_SBE_CONTROL_0x000E0001,
+                            data );
+        if(!rc.ok()) { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,"ERROR: reading scom" ); }
+
+        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+                   "DEBUG: PORE_SBE_CONTROL_0x000E0001  =   0x%lx",
+                   data.getDoubleWord( 0 ) );
+
+        if ( !is_vpo() )
+        {
+            //  proc_prep_master_winkle expects bit 0 to be off (SBE running)
+            data.clearBit(0);
+            rc = fapiPutScom(   l_fapi_cpu_target,
                                 PORE_SBE_CONTROL_0x000E0001,
                                 data );
-            if(!rc.ok()) { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,"ERROR: reading scom" ); }
+        }
 
-            TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                       "DEBUG: PORE_SBE_CONTROL_0x000E0001  =   0x%lx",
-                       data.getDoubleWord( 0 ) );
+        rc = fapiGetScom(   l_fapi_cpu_target,
+                            MBOX_SBEVITAL_0x0005001C,
+                            data );
+        if(!rc.ok()) { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,"ERROR: reading scom" ); }
+
+        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+                   "DEBUG: MBOX_SBEVITAL_0x0005001C =   0x%lx",
+                   data.getDoubleWord( 0 ) );
 
-            if ( !is_vpo() )
-            {
-                //  proc_prep_master_winkle expects bit 0 to be off (SBE running)
-                data.clearBit(0);
-                rc = fapiPutScom(   l_fapi_cpu_target,
-                                    PORE_SBE_CONTROL_0x000E0001,
-                                    data );
-            }
 
-            rc = fapiGetScom(   l_fapi_cpu_target,
+        if ( !is_vpo() )
+        {
+            //  prop_prep_master_winkle expects the SBE to write F011 to
+            //  SBE_VITAL   before we get here.
+            sbe_code    =   0xF011;
+            data.insertFromRight( &sbe_code,
+                                  16,           // ISTEP_NUM_BIT_POSITION
+                                  16 );         // number of bits
+            rc = fapiPutScom(   l_fapi_cpu_target,
                                 MBOX_SBEVITAL_0x0005001C,
                                 data );
-            if(!rc.ok()) { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,"ERROR: reading scom" ); }
+            if(!rc.ok()) { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,"ERROR: writing scom" ); }
+        }
+#else
+        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+                   "Simics has been fixed..." );
+#endif
 
-            TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                       "DEBUG: MBOX_SBEVITAL_0x0005001C =   0x%lx",
-                       data.getDoubleWord( 0 ) );
+        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+               "call_host_activate_master: call proc_prep_master_winkle." );
 
 
-            if ( !is_vpo() )
-            {
-                //  prop_prep_master_winkle expects the SBE to write F011 to
-                //  SBE_VITAL   before we get here.
-                sbe_code    =   0xF011;
-                data.insertFromRight( &sbe_code,
-                                      16,           // ISTEP_NUM_BIT_POSITION
-                                      16 );         // number of bits
-                rc = fapiPutScom(   l_fapi_cpu_target,
-                                    MBOX_SBEVITAL_0x0005001C,
-                                    data );
-                if(!rc.ok()) { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,"ERROR: writing scom" ); }
-            }
-#else
+        //  call the HWP with each fapi::Target
+        FAPI_INVOKE_HWP( l_errl,
+                         proc_prep_master_winkle,
+                         l_fapi_cpu_target,
+                         true  );
+        if ( l_errl )
+        {
             TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                       "Simics has been fixed..." );
-#endif
-
+            "proc_prep_master_winkle ERROR : Returning errorlog, PLID=0x%x",
+                l_errl->plid() );
+            break;
+        }
+        else
+        {
             TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                   "call_host_activate_master: call proc_prep_master_winkle." );
+                       "proc_prep_master_winkle SUCCESS"  );
+        }
 
-            //  call the HWP with each fapi::Target
-            FAPI_INVOKE_HWP( l_errl,
-                             proc_prep_master_winkle,
-                             l_fapi_cpu_target,
-                             true  );
-            if ( l_errl )
-            {
-                TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                "proc_prep_master_winkle ERROR : Returning errorlog, PLID=0x%x",
-                    l_errl->plid() );
-                break;
-            }
-            else
-            {
-                TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                           "proc_prep_master_winkle SUCCESS"  );
-            }
 
+        //  put the master into winkle.
+        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+                   "call_host_activate_master: put master into winkle..." );
 
-            //  put the master into winkle.
-            //  Simics should work after build b0815a_1233.810 .
-            TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                       "call_host_activate_master: put master into winkle..." );
+        int l_rc    =   cpu_master_winkle( );
+        if ( l_rc )
+        {
+            TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
+                      "ERROR : failed to winkle master, rc=0x%x",
+                      l_rc  );
+            /*@
+             * @errortype
+             * @reasoncode  ISTEP_FAIL_MASTER_WINKLE_RC
+             * @severity    ERRORLOG::ERRL_SEV_UNRECOVERABLE
+             * @moduleid    ISTEP_HOST_ACTIVATE_MASTER
+             * @userdata1   return code from cpu_master_winkle
+             *
+             * @devdesc p8_pore_gen_cpureg returned an error when
+             *          attempting to change a reg value in the PORE image.
+             */
+            l_errl =
+            new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_UNRECOVERABLE,
+                                    ISTEP_HOST_ACTIVATE_MASTER,
+                                    ISTEP_FAIL_MASTER_WINKLE_RC,
+                                    l_rc  );
+            break;
+        }
 
-            int l_rc    =   cpu_master_winkle( );
-            if ( l_rc )
-            {
-                TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                          "ERROR : failed to winkle master, rc=0x%x",
-                          l_rc  );
-                /*@
-                 * @errortype
-                 * @reasoncode  ISTEP_FAIL_MASTER_WINKLE_RC
-                 * @severity    ERRORLOG::ERRL_SEV_UNRECOVERABLE
-                 * @moduleid    ISTEP_HOST_ACTIVATE_MASTER
-                 * @userdata1   return code from cpu_master_winkle
-                 *
-                 * @devdesc p8_pore_gen_cpureg returned an error when
-                 *          attempting to change a reg value in the PORE image.
-                 */
-                l_errl =
-                new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_UNRECOVERABLE,
-                                        ISTEP_HOST_ACTIVATE_MASTER,
-                                        ISTEP_FAIL_MASTER_WINKLE_RC,
-                                        l_rc  );
-                break;
-            }
 
-            //  --------------------------------------------------------
-            //  should return from Winkle at this point
-            //  --------------------------------------------------------
-            TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                       "Returned from Winkle." );
+        //  --------------------------------------------------------
+        //  should return from Winkle at this point
+        //  --------------------------------------------------------
+        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+                   "Returned from Winkle." );
 
 #if 1
-            //  SIMICS HACK - The values written by simics are not correct -
-            //  Write them here until we can get the actions files fixed.
+        //  SIMICS HACK - The values written by simics are not correct -
+        //  Write them here until we can get the actions files fixed.
 
-            rc = fapiGetScom(   l_fapi_cpu_target,
-                                MBOX_SBEVITAL_0x0005001C,
-                                data );
-            if(!rc.ok()) { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,"ERROR: reading scom" ); }
+        rc = fapiGetScom(   l_fapi_cpu_target,
+                            MBOX_SBEVITAL_0x0005001C,
+                            data );
+        if(!rc.ok()) { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,"ERROR: reading scom" ); }
 
-            TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                       "DEBUG: MBOX_SBEVITAL_0x0005001C =   0x%lx",
-                       data.getDoubleWord( 0 ) );
+        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+                   "DEBUG: MBOX_SBEVITAL_0x0005001C =   0x%lx",
+                   data.getDoubleWord( 0 ) );
 
-            if ( !is_vpo() )
-            {
-                //  prop_stop_deadman_timer expects the SBE to write F015 to
-                //  SBE_VITAL   before we get here.
-                sbe_code    =   0xF015;
-                data.insertFromRight( &sbe_code,
-                                  16,           // ISTEP_NUM_BIT_POSITION
-                                  16 );         // number of bits
-                rc = fapiPutScom(   l_fapi_cpu_target,
-                                    MBOX_SBEVITAL_0x0005001C,
-                                    data );
-                if(!rc.ok()) { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,"ERROR: writing scom" ); }
-            }
+        if ( !is_vpo() )
+        {
+            //  prop_stop_deadman_timer expects the SBE to write F015 to
+            //  SBE_VITAL   before we get here.
+            sbe_code    =   0xF015;
+            data.insertFromRight( &sbe_code,
+                              16,           // ISTEP_NUM_BIT_POSITION
+                              16 );         // number of bits
+            rc = fapiPutScom(   l_fapi_cpu_target,
+                                MBOX_SBEVITAL_0x0005001C,
+                                data );
+            if(!rc.ok()) { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,"ERROR: writing scom" ); }
+        }
 
 #else
-            TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                       "Simics has been fixed..." );
+        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+                   "Simics has been fixed..." );
 #endif
 
+        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+                   "Call proc_stop_deadman_timer..." );
 
+        //  call the HWP with each fapi::Target
+        FAPI_INVOKE_HWP( l_errl,
+                         proc_stop_deadman_timer,
+                         l_fapi_cpu_target  );
+        if ( l_errl )
+        {
             TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                       "Call proc_stop_deadman_timer..." );
-
-            //  call the HWP with each fapi::Target
-            FAPI_INVOKE_HWP( l_errl,
-                             proc_stop_deadman_timer,
-                             l_fapi_cpu_target  );
-            if ( l_errl )
-            {
-                TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                           "proc_stop_deadman_timer ERROR : Returning errorlog, PLID=0x%x",
-                           l_errl->plid() );
-                break;
-            }
-            else
-            {
-                TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                           "proc_stop_deadman_timer SUCCESS"  );
-            }
-
-        }   while ( 0 );
-
-        // @@@@@    END CUSTOM BLOCK:   @@@@@
-        if( l_errl )
+                       "proc_stop_deadman_timer ERROR : Returning errorlog, PLID=0x%x",
+                       l_errl->plid() );
+            break;
+        }
+        else
         {
-            /*@
-             * @errortype
-             * @reasoncode      ISTEP_CORE_ACTIVATE_FAILED
-             * @severity        ERRORLOG::ERRL_SEV_UNRECOVERABLE
-             * @moduleid        ISTEP_HOST_ACTIVATE_MASTER
-             * @userdata1       bytes 0-1: plid identifying first error
-             *                  bytes 2-3: reason code of first error
-             * @userdata2       bytes 0-1: total number of elogs included
-             *                  bytes 2-3: N/A
-             * @devdesc         call to host_activate_master failed see
-             *                  error identified by the plid in user data
-             *                  field.
-             */
-            l_stepError.addErrorDetails(ISTEP_CORE_ACTIVATE_FAILED,
-                             ISTEP_HOST_ACTIVATE_MASTER,
-                             l_errl );
-
-            errlCommit( l_errl, HWPF_COMP_ID );
+            TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+                       "proc_prep_master_winkle SUCCESS"  );
         }
 
-        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                   "call_host_activate_master exit" );
+    }   while ( 0 );
 
-        // end task, returning any errorlogs to IStepDisp
-        return l_stepError.getErrorHandle();
+    // @@@@@    END CUSTOM BLOCK:   @@@@@
+    if( l_errl )
+    {
+        /*@
+         * @errortype
+         * @reasoncode      ISTEP_CORE_ACTIVATE_FAILED
+         * @severity        ERRORLOG::ERRL_SEV_UNRECOVERABLE
+         * @moduleid        ISTEP_HOST_ACTIVATE_MASTER
+         * @userdata1       bytes 0-1: plid identifying first error
+         *                  bytes 2-3: reason code of first error
+         * @userdata2       bytes 0-1: total number of elogs included
+         *                  bytes 2-3: N/A
+         * @devdesc         call to host_activate_master failed see
+         *                  error identified by the plid in user data
+         *                  field.
+         */
+        l_stepError.addErrorDetails(ISTEP_CORE_ACTIVATE_FAILED,
+                         ISTEP_HOST_ACTIVATE_MASTER,
+                         l_errl );
 
+        errlCommit( l_errl, HWPF_COMP_ID );
     }
 
+    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+               "call_host_activate_master exit" );
+
+    // end task, returning any errorlogs to IStepDisp
+    return l_stepError.getErrorHandle();
+
+}
+
 
 
 //
@@ -399,30 +401,81 @@ void*    call_host_activate_slave_cores( void    *io_pArgs )
     }
 
 #endif
-    // @@@@@    END CUSTOM BLOCK:   @@@@@
 
-    if( l_errl )
+    if ( ! l_errl )
     {
-        /*@
-         * @errortype
-         * @reasoncode      ISTEP_CORE_ACTIVATE_FAILED
-         * @severity        ERRORLOG::ERRL_SEV_UNRECOVERABLE
-         * @moduleid        ISTEP_HOST_ACTIVATE_SLAVE_CORES
-         * @userdata1       bytes 0-1: plid identifying first error
-         *                  bytes 2-3: reason code of first error
-         * @userdata2       bytes 0-1: total number of elogs included
-         *                  bytes 2-3: N/A
-         *
-         * @devdesc         call to host_activate_master failed see
-         *                  error identified by the plid in user data
-         *                  field.
-         */
-        l_stepError.addErrorDetails(ISTEP_CORE_ACTIVATE_FAILED,
-                                    ISTEP_HOST_ACTIVATE_SLAVE_CORES,
-                                    l_errl );
+        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+                   "set PORE bars back to 0" );
 
-        errlCommit( l_errl, HWPF_COMP_ID );
-    }
+        //  @todo   see RTC 51264 -
+        //  This has to be modified if we are loading other AVP's instead
+        //  of PHYP
+        TARGETING::TargetHandleList l_procTargetList;
+        getAllChips(l_procTargetList, TYPE_PROC);
+
+        // loop thru all the cpu's
+        for ( uint8_t l_procNum=0; l_procNum < l_procTargetList.size(); l_procNum++)
+        {
+            //  make a local copy of the CPU target
+            TARGETING::Target*  l_proc_target = l_procTargetList[l_procNum];
+
+            //  dump physical path to target
+            EntityPath l_path;
+            l_path  =   l_proc_target->getAttr<ATTR_PHYS_PATH>();
+            l_path.dump();
+
+            // cast OUR type of target to a FAPI type of target.
+            fapi::Target l_fapi_proc_target(
+                                           TARGET_TYPE_PROC_CHIP,
+                                           reinterpret_cast<void *>
+                                           (const_cast<TARGETING::Target*>(l_proc_target)) );
+
+            //  reset pore bar notes:
+            //  A mem_size of 0 means to ignore the image address
+            //  This image should have been moved to memory after winkle
+
+            //  call the HWP with each fapi::Target
+            FAPI_INVOKE_HWP( l_errl,
+                             p8_set_pore_bar,
+                             l_fapi_proc_target,
+                             0,
+                             0,
+                             0,
+                             SLW_MEMORY
+                           );
+            if ( l_errl )
+            {
+                /*@
+                 * @errortype
+                 * @reasoncode      ISTEP_RESET_PORE_BARS_FAILED
+                 * @severity        ERRORLOG::ERRL_SEV_UNRECOVERABLE
+                 * @moduleid        ISTEP_HOST_ACTIVATE_SLAVE_CORES
+                 * @userdata1       0
+                 * @userdata2       0
+                 * @devdesc         call to set_pore_bars failed.
+                 *                  see error identified by the plid in
+                 *                  user data field.
+                 */
+                l_stepError.addErrorDetails(ISTEP_RESET_PORE_BARS_FAILED,
+                                            ISTEP_HOST_ACTIVATE_SLAVE_CORES,
+                                            l_errl );
+
+                errlCommit( l_errl, HWPF_COMP_ID );
+
+                TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
+                          "ERROR : p8_set_pore_bar, PLID=0x%x",
+                          l_errl->plid()  );
+            }
+            else
+            {
+                TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+                           "SUCCESS : p8_set_pore_bar" );
+            }
+
+        }   // end for
+    }   // end if
+
+    // @@@@@    END CUSTOM BLOCK:   @@@@@
 
     TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
                "call_host_activate_slave_cores exit" );
@@ -447,51 +500,43 @@ void*    call_host_ipl_complete( void    *io_pArgs )
                "call_host_ipl_complete entry" );
     do
     {
-        uint8_t l_cpuNum = 0;
-        TARGETING::TargetHandleList l_cpuTargetList;
-        getAllChips(l_cpuTargetList, TYPE_PROC);
-        for ( l_cpuNum=0; l_cpuNum < l_cpuTargetList.size(); l_cpuNum++ )
-        {
-            const TARGETING::Target*  l_cpu_target = l_cpuTargetList[l_cpuNum];
-            const fapi::Target l_fapi_proc_target(
-                    TARGET_TYPE_PROC_CHIP,
-                    reinterpret_cast<void *>
-                    ( const_cast<TARGETING::Target*>(l_cpu_target) ) );
+        // We only need to do this to the master Processor.
 
-            TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                        "Running proc_switch_cfsim HWP on...");
-            EntityPath l_path;
-            l_path  =   l_cpu_target->getAttr<ATTR_PHYS_PATH>();
-            l_path.dump();
+        TARGETING::Target * l_masterProc =   NULL;
+        (void)TARGETING::targetService().masterProcChipTargetHandle( l_masterProc );
 
-            //  call proc_switch_cfsim
-            FAPI_INVOKE_HWP(l_err, proc_switch_cfsim, l_fapi_proc_target,
-                            true, // RESET
-                            true, // RESET_OPB_SWITCH
-                            true, // FENCE_FSI0
-                            true, // FENCE_PIB_NH
-                            true, // FENCE_PIB_H
-                            true, // FENCE_FSI1
-                            true); // FENCE_PIB_SW1
-            if (l_err)
-            {
-                TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                          "ERROR 0x%.8X: proc_switch_cfsim HWP returns error",
-                          l_err->reasonCode());
-                break;
-            }
-            else
-            {
-                TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                           "SUCCESS: proc_switch_cfsim HWP( )" );
-            }
-        }
+        const fapi::Target l_fapi_proc_target(
+                TARGET_TYPE_PROC_CHIP,
+                reinterpret_cast<void *>
+                ( const_cast<TARGETING::Target*>(l_masterProc) ) );
 
-        if( l_err )
+        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+                    "Running proc_switch_cfsim HWP on ...");
+        EntityPath l_path;
+        l_path  =   l_masterProc->getAttr<ATTR_PHYS_PATH>();
+        l_path.dump();
+
+        //  call proc_switch_cfsim
+        FAPI_INVOKE_HWP(l_err, proc_switch_cfsim, l_fapi_proc_target,
+                        true, // RESET
+                        true, // RESET_OPB_SWITCH
+                        true, // FENCE_FSI0
+                        true, // FENCE_PIB_NH
+                        true, // FENCE_PIB_H
+                        true, // FENCE_FSI1
+                        true); // FENCE_PIB_SW1
+        if (l_err)
         {
+            TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
+                      "ERROR 0x%.8X: proc_switch_cfsim HWP returns error",
+                      l_err->reasonCode());
             break;
         }
-
+        else
+        {
+            TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+                       "SUCCESS: proc_switch_cfsim HWP( )" );
+        }
 
         // Sync attributes to Fsp
         l_err = syncAllAttributesToFsp();
diff --git a/src/usr/hwpf/hwp/core_activate/makefile b/src/usr/hwpf/hwp/core_activate/makefile
index 824ee02cb..686ef6649 100644
--- a/src/usr/hwpf/hwp/core_activate/makefile
+++ b/src/usr/hwpf/hwp/core_activate/makefile
@@ -43,7 +43,10 @@ EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/core_activate
 EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle
 EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer
 EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/core_activate/proc_switch_cfsim
-
+##  @todo   RTC Story 51709 and Story 51711 : revisit this later -
+##  proc_set_pore_bar is used by multiple isteps, so it should be in its own
+##  "utility" library
+EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar
 
 ##  NOTE: add new object files when you add a new HWP
 OBJS =  core_activate.o \
diff --git a/src/usr/hwpf/hwp/thread_activate/proc_thread_control/proc_thread_control.xml b/src/usr/hwpf/hwp/thread_activate/proc_thread_control/proc_thread_control.xml
index 299f99b76..98d252c7d 100644
--- a/src/usr/hwpf/hwp/thread_activate/proc_thread_control/proc_thread_control.xml
+++ b/src/usr/hwpf/hwp/thread_activate/proc_thread_control/proc_thread_control.xml
@@ -40,6 +40,15 @@
   </hwpError>
   <!-- ********************************************************************* -->
   <hwpError>
+    <rc>RC_PROC_PBA_ADDR_ALIGNMENT_ERROR</rc>
+    <description>pba BAR must be on a 1MB boundary</description>
+  </hwpError>
+  <!-- *********************************************************************** -->
+  <hwpError>
+    <rc>RC_PROC_PBA_BAR_SIZE_INVALID</rc>
+    <description>Non-zero PBA BAR defined with region size of 0. Size must be 1MB or greater</description>
+  </hwpError>
+  <hwpError>
     <rc>RC_PROC_THREAD_CONTROL_START_FAIL</rc>
     <description>Sreset command failed: RAS STAT instruction completed bit was not set after start command.</description>
   </hwpError>