diff options
| author | Van Lee <vanlee@us.ibm.com> | 2012-05-16 19:55:35 -0500 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2012-06-06 17:05:08 -0500 |
| commit | 068764225969bfd45cc47ad1e6f2d00a2d7331f2 (patch) | |
| tree | 76a8e24f2846736488c26b61cc3d4243e44675e5 /src/usr | |
| parent | 200c99f2adcf88697a2fce80becee61ef405094d (diff) | |
| download | talos-hostboot-068764225969bfd45cc47ad1e6f2d00a2d7331f2.tar.gz talos-hostboot-068764225969bfd45cc47ad1e6f2d00a2d7331f2.zip | |
Pick up latest mss_eff_config HWP
Implemented util functions getAllChips, getAllChiplets, getChildChiplets,
getAffinityChips.
RTC: 41712
Change-Id: I625695a85d768e03365a91fb44b4f9d6525a4276
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1073
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr')
20 files changed, 1873 insertions, 635 deletions
diff --git a/src/usr/hwpf/hwp/build_winkle_images/build_winkle_images.C b/src/usr/hwpf/hwp/build_winkle_images/build_winkle_images.C index d4525095e..fa39e9b26 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/build_winkle_images.C +++ b/src/usr/hwpf/hwp/build_winkle_images/build_winkle_images.C @@ -45,6 +45,7 @@ // targeting support #include <targeting/common/commontargeting.H> +#include <targeting/common/utilFilter.H> // fapi support #include <fapi.H> @@ -158,7 +159,6 @@ errlHndl_t loadPoreImage( TARGETING::Target *i_CpuTarget, void call_host_build_winkle( void *io_pArgs ) { errlHndl_t l_errl = NULL; - TARGETING::TargetService& l_targetService = targetService(); uint8_t l_cpuNum = 0; const char *l_pPoreImage = NULL; @@ -176,24 +176,14 @@ void call_host_build_winkle( void *io_pArgs ) // customize any other inputs // set up loops to go through all targets (if parallel, spin off a task) - // Use PredicateIsFunctional to filter only functional chips - TARGETING::PredicateIsFunctional l_isFunctional; - - TARGETING::PredicateCTM l_procChipFilter( CLASS_CHIP, TYPE_PROC ); - TARGETING::PredicatePostfixExpr l_functionalAndProcChipFilter; - l_functionalAndProcChipFilter - .push(&l_procChipFilter) - .push(&l_isFunctional) - .And(); - TARGETING::TargetRangeFilter l_cpuFilter( - l_targetService.begin(), - l_targetService.end(), - &l_functionalAndProcChipFilter ); - - for ( l_cpuNum=0; l_cpuFilter; ++l_cpuFilter, l_cpuNum++ ) + + TARGETING::TargetHandleList l_cpuTargetList; + getAllChips(l_cpuTargetList, TYPE_PROC); + + for ( l_cpuNum=0; l_cpuNum < l_cpuTargetList.size(); l_cpuNum++ ) { // make a local copy of the CPU target - TARGETING::Target* l_cpu_target = *l_cpuFilter; + TARGETING::Target* l_cpu_target = l_cpuTargetList[l_cpuNum]; TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "Run cpuNum 0x%x", diff --git a/src/usr/hwpf/hwp/dmi_training/dmi_training.C b/src/usr/hwpf/hwp/dmi_training/dmi_training.C index a6673c867..e37554e29 100644 --- a/src/usr/hwpf/hwp/dmi_training/dmi_training.C +++ b/src/usr/hwpf/hwp/dmi_training/dmi_training.C @@ -49,6 +49,7 @@ // targeting support. #include <targeting/common/commontargeting.H> +#include <targeting/common/utilFilter.H> // fapi support #include <fapi.H> @@ -117,59 +118,34 @@ void call_dmi_io_dccal( void *io_pArgs ) void call_dmi_io_run_training( void *io_pArgs ) { errlHndl_t l_err = NULL; - TARGETING::TargetService& l_targetService = targetService(); - uint8_t l_cpuNum = 0; TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "dmi_io_run_training entry" ); - // Use PredicateIsFunctional to filter only functional chips - TARGETING::PredicateIsFunctional l_isFunctional; + TARGETING::TargetHandleList l_cpuTargetList; + getAllChips(l_cpuTargetList, TYPE_PROC); - // filter for functional Proc Chips - TARGETING::PredicateCTM l_procChipFilter( CLASS_CHIP, TYPE_PROC ); - TARGETING::PredicatePostfixExpr l_functionalAndProcChipFilter; - l_functionalAndProcChipFilter.push(&l_procChipFilter).push(&l_isFunctional).And(); - TARGETING::TargetRangeFilter l_cpuFilter( - l_targetService.begin(), - l_targetService.end(), - &l_functionalAndProcChipFilter ); - - for ( l_cpuNum=0; l_cpuFilter; ++l_cpuFilter, l_cpuNum++ ) + for ( size_t i = 0; i < l_cpuTargetList.size(); i++ ) { // make a local copy of the CPU target - const TARGETING::Target* l_cpu_target = *l_cpuFilter; + const TARGETING::Target* l_cpu_target = l_cpuTargetList[i]; + + uint8_t l_cpuNum = l_cpu_target->getAttr<ATTR_POSITION>(); - // get the mcs chiplets associated with this cpu - TARGETING::PredicateCTM l_mcsChipFilter(CLASS_UNIT, TYPE_MCS); - TARGETING::PredicatePostfixExpr l_functionalAndMcsChipFilter; - l_functionalAndMcsChipFilter.push(&l_mcsChipFilter).push(&l_isFunctional).And(); + // find all MCS chiplets of the proc TARGETING::TargetHandleList l_mcsTargetList; - l_targetService.getAssociated( - l_mcsTargetList, - l_cpu_target, - TARGETING::TargetService::CHILD, - TARGETING::TargetService::IMMEDIATE, - &l_functionalAndMcsChipFilter ); - - for ( uint8_t j=0; j < l_mcsTargetList.size(); j++ ) + getChildChiplets( l_mcsTargetList, l_cpu_target, TYPE_MCS ); + + for ( size_t j = 0; j < l_mcsTargetList.size(); j++ ) { // make a local copy of the MCS target const TARGETING::Target* l_mcs_target = l_mcsTargetList[j]; uint8_t l_mcsNum = l_mcs_target->getAttr<ATTR_CHIP_UNIT>(); // find all the Centaurs that are associated with this MCS - TARGETING::PredicateCTM l_membufChipFilter(CLASS_CHIP, TYPE_MEMBUF); - TARGETING::PredicatePostfixExpr l_functionalAndMembufChipFilter; - l_functionalAndMembufChipFilter.push(&l_membufChipFilter).push(&l_isFunctional).And(); TARGETING::TargetHandleList l_memTargetList; - l_targetService.getAssociated( - l_memTargetList, - l_mcs_target, - TARGETING::TargetService::CHILD_BY_AFFINITY, - TARGETING::TargetService::ALL, - &l_functionalAndMembufChipFilter); - - for ( uint8_t k=0, l_memNum=0; k < l_memTargetList.size(); k++, l_memNum++ ) + getAffinityChips(l_memTargetList, l_mcs_target, TYPE_MEMBUF); + + for ( size_t k = 0; k < l_memTargetList.size(); k++ ) { // make a local copy of the MEMBUF target const TARGETING::Target* l_mem_target = l_memTargetList[k]; @@ -206,7 +182,7 @@ void call_dmi_io_run_training( void *io_pArgs ) "===== Call dmi_io_run_training HWP( cpu 0x%x, mcs 0x%x, mem 0x%x ) : ", l_cpuNum, l_mcsNum, - l_memNum ); + k ); EntityPath l_path; l_path = l_cpu_target->getAttr<ATTR_PHYS_PATH>(); @@ -230,7 +206,7 @@ void call_dmi_io_run_training( void *io_pArgs ) l_err->reasonCode(), l_cpuNum, l_mcsNum, - l_memNum ); + k ); break; // Break out mem target loop } else @@ -239,7 +215,7 @@ void call_dmi_io_run_training( void *io_pArgs ) "SUCCESS : io_run_training HWP( cpu 0x%x, mcs 0x%x, mem 0x%x ) ", l_cpuNum, l_mcsNum, - l_memNum ); + k ); } } //end for l_mem_target @@ -304,38 +280,23 @@ void call_proc_cen_framelock( void *io_pArgs ) errlHndl_t l_err = NULL; proc_cen_framelock_args l_args; - // Use PredicateIsFunctional to filter only functional chips - TARGETING::PredicateIsFunctional l_isFunctional; - TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_proc_cen_framework entry" ); - // get the mcs chiplets associated with this cpu - TARGETING::PredicateCTM l_mcsChipFilter(CLASS_UNIT, TYPE_MCS); - TARGETING::PredicatePostfixExpr l_functionalAndMcsChipFilter; - l_functionalAndMcsChipFilter.push(&l_mcsChipFilter).push(&l_isFunctional).And(); - - TARGETING::TargetRangeFilter l_mcsFilter( - TARGETING::targetService().begin(), - TARGETING::targetService().end(), - &l_functionalAndMcsChipFilter ); + // get the mcs chiplets + TARGETING::TargetHandleList l_mcsTargetList; + getAllChiplets(l_mcsTargetList, TYPE_MCS); - for ( ; l_mcsFilter ; ++l_mcsFilter ) + for ( size_t i = 0; i < l_mcsTargetList.size() ; ++i ) { // make a local copy of the MCS target - const TARGETING::Target* l_mcs_target = *l_mcsFilter ; + const TARGETING::Target* l_mcs_target = l_mcsTargetList[i]; // find all the Centaurs that are associated with this MCS - TARGETING::PredicateCTM l_membufChipFilter(CLASS_CHIP, TYPE_MEMBUF); - TARGETING::PredicatePostfixExpr l_functionalAndMembufChipFilter; - l_functionalAndMembufChipFilter.push(&l_membufChipFilter).push(&l_isFunctional).And(); TARGETING::TargetHandleList l_memTargetList; - TARGETING::targetService().getAssociated(l_memTargetList, - l_mcs_target, - TARGETING::TargetService::CHILD_BY_AFFINITY, - TARGETING::TargetService::ALL, - &l_functionalAndMembufChipFilter); + getAffinityChips(l_memTargetList, l_mcs_target, TYPE_MEMBUF); - for ( uint8_t k=0, l_memNum=0; k < l_memTargetList.size(); k++, l_memNum++ ) + for ( uint8_t k = 0, l_memNum = 0; k < l_memTargetList.size(); + k++, l_memNum++ ) { // make a local copy of the MEMBUF target const TARGETING::Target* l_mem_target = l_memTargetList[k]; diff --git a/src/usr/hwpf/hwp/dram_initialization/dram_initialization.C b/src/usr/hwpf/hwp/dram_initialization/dram_initialization.C index 09404b559..8f1bf1607 100644 --- a/src/usr/hwpf/hwp/dram_initialization/dram_initialization.C +++ b/src/usr/hwpf/hwp/dram_initialization/dram_initialization.C @@ -46,6 +46,7 @@ // targeting support #include <targeting/common/commontargeting.H> +#include <targeting/common/utilFilter.H> // fapi support #include <fapi.H> @@ -195,27 +196,8 @@ void call_mss_memdiag( void *io_pArgs ) TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_memdiag entry" ); - PredicateIsFunctional l_isFunctional; - - // To filter MBAs - PredicateCTM l_mbaFilter(CLASS_UNIT, TYPE_MBA); - - // Filter functional MBAs - PredicatePostfixExpr l_functionalAndMbaFilter; - l_functionalAndMbaFilter.push(&l_mbaFilter).push(&l_isFunctional).And(); - - TargetRangeFilter l_pMbas( - targetService().begin(), - targetService().end(), - &l_functionalAndMbaFilter ); - TargetHandleList l_mbaList; - - // populate MBA TargetHandlelist - for(;l_pMbas;++l_pMbas) - { - l_mbaList.push_back(*l_pMbas); - } + getAllChiplets(l_mbaList, TYPE_MBA); errlHndl_t l_err = runStep(l_mbaList); if(NULL != l_err) diff --git a/src/usr/hwpf/hwp/dram_training/dram_training.C b/src/usr/hwpf/hwp/dram_training/dram_training.C index 5e57b43fa..bf95a1b06 100644 --- a/src/usr/hwpf/hwp/dram_training/dram_training.C +++ b/src/usr/hwpf/hwp/dram_training/dram_training.C @@ -47,6 +47,7 @@ // targeting support #include <targeting/common/commontargeting.H> #include <targeting/common/util.H> +#include <targeting/common/utilFilter.H> // fapi support #include <fapi.H> @@ -216,25 +217,13 @@ void call_mem_startclocks( void *io_pArgs ) TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mem_startclocks entry" ); // Get all Centaur targets - // Use PredicateIsFunctional to filter only functional chips - TARGETING::PredicateIsFunctional l_isFunctional; - // find all the Centaurs in the system - TARGETING::PredicateCTM l_ctaurFilter(CLASS_CHIP, TYPE_MEMBUF); - // declare a postfix expression widget - TARGETING::PredicatePostfixExpr l_functionalAndCtaurFilter; - // is-a-membuf-chip is-functional AND - l_functionalAndCtaurFilter.push(&l_ctaurFilter).push(&l_isFunctional).And(); - // loop through all the targets, applying the filter, and put the results - // in l_pMemBufs - TARGETING::TargetRangeFilter l_pMemBufs( - TARGETING::targetService().begin(), - TARGETING::targetService().end(), - &l_functionalAndCtaurFilter ); - - for ( ; l_pMemBufs ; ++l_pMemBufs ) + TARGETING::TargetHandleList l_membufTargetList; + getAllChips(l_membufTargetList, TYPE_MEMBUF); + + for ( size_t i = 0; i < l_membufTargetList.size(); i++ ) { // make a local copy of the target for ease of use - const TARGETING::Target* l_pCentaur = *l_pMemBufs; + const TARGETING::Target* l_pCentaur = l_membufTargetList[i]; // Dump current run on target TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, @@ -403,19 +392,8 @@ void call_mss_ddr_phy_reset( void *io_pArgs ) TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_ddr_phy_reset entry" ); // Get all MBA targets - // Use PredicateIsFunctional to filter only functional chips - TARGETING::PredicateIsFunctional l_isFunctional; - // find all the MBA's in the system - TARGETING::PredicateCTM l_mbaFilter(CLASS_UNIT, TYPE_MBA); - // declare a postfix expression widget - TARGETING::PredicatePostfixExpr l_functionalAndMbaFilter; - // is-a-membuf-chip is-functional AND - l_functionalAndMbaFilter.push(&l_mbaFilter).push(&l_isFunctional).And(); - // loop through all the targets, applying the filter, and put the results in l_pMemBufs - TARGETING::TargetRangeFilter l_pMbas( - TARGETING::targetService().begin(), - TARGETING::targetService().end(), - &l_functionalAndMbaFilter ); + TARGETING::TargetHandleList l_mbaTargetList; + getAllChiplets(l_mbaTargetList, TYPE_MBA); // Limit the number of MBAs to run in VPO environment to save time. uint8_t l_mbaLimit = UNLIMITED_RUN; @@ -425,11 +403,11 @@ void call_mss_ddr_phy_reset( void *io_pArgs ) } for ( uint8_t l_mbaNum=0 ; - (l_mbaNum < l_mbaLimit) && l_pMbas ; - l_mbaNum++, ++l_pMbas ) + (l_mbaNum < l_mbaLimit) && (l_mbaNum < l_mbaTargetList.size()) ; + l_mbaNum++ ) { // make a local copy of the target for ease of use - const TARGETING::Target* l_mba_target = *l_pMbas; + const TARGETING::Target* l_mba_target = l_mbaTargetList[l_mbaNum]; // Dump current run on target TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "Running call_mss_ddr_phy_reset HWP on..." ); @@ -474,19 +452,8 @@ void call_mss_draminit( void *io_pArgs ) TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_draminit entry" ); // Get all MBA targets - // Use PredicateIsFunctional to filter only functional chips - TARGETING::PredicateIsFunctional l_isFunctional; - // find all the MBA's in the system - TARGETING::PredicateCTM l_mbaFilter(CLASS_UNIT, TYPE_MBA); - // declare a postfix expression widget - TARGETING::PredicatePostfixExpr l_functionalAndMbaFilter; - // is-a-membuf-chip is-functional AND - l_functionalAndMbaFilter.push(&l_mbaFilter).push(&l_isFunctional).And(); - // loop through all the targets, applying the filter, and put the results in l_pMemBufs - TARGETING::TargetRangeFilter l_pMbas( - TARGETING::targetService().begin(), - TARGETING::targetService().end(), - &l_functionalAndMbaFilter ); + TARGETING::TargetHandleList l_mbaTargetList; + getAllChiplets(l_mbaTargetList, TYPE_MBA); // Limit the number of MBAs to run in VPO environment to save time. uint8_t l_mbaLimit = UNLIMITED_RUN; @@ -496,11 +463,11 @@ void call_mss_draminit( void *io_pArgs ) } for ( uint8_t l_mbaNum=0 ; - (l_mbaNum < l_mbaLimit) && l_pMbas ; - l_mbaNum++, ++l_pMbas ) + (l_mbaNum < l_mbaLimit) && (l_mbaNum < l_mbaTargetList.size()); + l_mbaNum++ ) { // Make a local copy of the target for ease of use - const TARGETING::Target* l_mba_target = *l_pMbas; + const TARGETING::Target* l_mba_target = l_mbaTargetList[l_mbaNum]; // Dump current run on target TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "Running mss_draminit HWP on..."); @@ -606,19 +573,8 @@ void call_mss_draminit_training( void *io_pArgs ) TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_draminit_training entry" ); // Get all MBA targets - // Use PredicateIsFunctional to filter only functional chips - TARGETING::PredicateIsFunctional l_isFunctional; - // find all the MBA's in the system - TARGETING::PredicateCTM l_mbaFilter(CLASS_UNIT, TYPE_MBA); - // declare a postfix expression widget - TARGETING::PredicatePostfixExpr l_functionalAndMbaFilter; - // is-a-membuf-chip is-functional AND - l_functionalAndMbaFilter.push(&l_mbaFilter).push(&l_isFunctional).And(); - // loop through all the targets, applying the filter, and put the results in l_pMemBufs - TARGETING::TargetRangeFilter l_pMbas( - TARGETING::targetService().begin(), - TARGETING::targetService().end(), - &l_functionalAndMbaFilter ); + TARGETING::TargetHandleList l_mbaTargetList; + getAllChiplets(l_mbaTargetList, TYPE_MBA); // Limit the number of MBAs to run in VPO environment to save time. uint8_t l_mbaLimit = UNLIMITED_RUN; @@ -628,11 +584,11 @@ void call_mss_draminit_training( void *io_pArgs ) } for ( uint8_t l_mbaNum=0 ; - (l_mbaNum < l_mbaLimit) && l_pMbas ; - l_mbaNum++, ++l_pMbas ) + (l_mbaNum < l_mbaLimit) && (l_mbaNum < l_mbaTargetList.size()); + l_mbaNum++ ) { // make a local copy of the target for ease of use - const TARGETING::Target* l_mba_target = *l_pMbas; + const TARGETING::Target* l_mba_target = l_mbaTargetList[l_mbaNum]; // Dump current run on target TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "Running mss_draminit_training HWP on..." ); @@ -737,19 +693,8 @@ void call_mss_draminit_mc( void *io_pArgs ) TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_draminit_mc entry" ); // Get all centaur targets - // Use PredicateIsFunctional to filter only functional chips - TARGETING::PredicateIsFunctional l_isFunctional; - // filter for functional Centaur Chips - TARGETING::PredicateCTM l_membufChipFilter(CLASS_CHIP, TYPE_MEMBUF); - // declare a postfix expression widget - TARGETING::PredicatePostfixExpr l_functionalAndMembufChipFilter; - // is-a-membuf-chip is-functional AND - l_functionalAndMembufChipFilter.push(&l_membufChipFilter).push(&l_isFunctional).And(); - // loop through all the targets, applying the filter, and put the results in l_pMemBufs - TARGETING::TargetRangeFilter l_pMemBufs( - TARGETING::targetService().begin(), - TARGETING::targetService().end(), - &l_functionalAndMembufChipFilter ); + TARGETING::TargetHandleList l_mBufTargetList; + getAllChips(l_mBufTargetList, TYPE_MEMBUF); // Limit the number of MBAs to run in VPO environment to save time. uint8_t l_memBufLimit = UNLIMITED_RUN; @@ -758,12 +703,12 @@ void call_mss_draminit_mc( void *io_pArgs ) l_memBufLimit = VPO_NUM_OF_MEMBUF_TO_RUN ; } - for (uint8_t l_memBufNum=0 ; - (l_memBufNum < l_memBufLimit) && l_pMemBufs ; - l_memBufNum++, ++l_pMemBufs) + for (uint8_t l_mBufNum=0 ; + (l_mBufNum < l_memBufLimit) && (l_mBufNum < l_mBufTargetList.size()); + l_mBufNum++) { - const TARGETING::Target* l_membuf_target = *l_pMemBufs; + const TARGETING::Target* l_membuf_target = l_mBufTargetList[l_mBufNum]; // Dump current run on target TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "Running mss_draminit_mc HWP on..." ); diff --git a/src/usr/hwpf/hwp/edi_ei_initialization/edi_ei_initialization.C b/src/usr/hwpf/hwp/edi_ei_initialization/edi_ei_initialization.C index 224536aa4..a2f2df13c 100644 --- a/src/usr/hwpf/hwp/edi_ei_initialization/edi_ei_initialization.C +++ b/src/usr/hwpf/hwp/edi_ei_initialization/edi_ei_initialization.C @@ -46,6 +46,7 @@ // targeting support #include <targeting/common/commontargeting.H> +#include <targeting/common/utilFilter.H> // fapi support #include <fapi.H> @@ -347,28 +348,17 @@ void call_proc_fab_iovalid( void *io_pArgs ) "call_proc_fab_iovalid entry" ); // Get all chip/chiplet targets - // Use PredicateIsFunctional to filter only functional chips/chiplets - TARGETING::PredicateIsFunctional l_isFunctional; - // filter for functional Chips/Chiplets - TARGETING::PredicateCTM l_Filter(CLASS_CHIP, TYPE_PROC); - // declare a postfix expression widget - TARGETING::PredicatePostfixExpr l_goodFilter; - // is-a--chip is-functional AND - l_goodFilter.push(&l_Filter).push(&l_isFunctional).And(); - // apply the filter through all targets. - TARGETING::TargetRangeFilter l_Procs( - TARGETING::targetService().begin(), - TARGETING::targetService().end(), - &l_goodFilter ); + TARGETING::TargetHandleList l_cpuTargetList; + getAllChips(l_cpuTargetList, TYPE_PROC); std::vector<proc_fab_smp_proc_chip *> l_smp; - for ( ; l_Procs; ++l_Procs ) + for ( size_t i = 0; i < l_cpuTargetList.size(); i++ ) { proc_fab_smp_proc_chip *l_proc = new proc_fab_smp_proc_chip(); l_smp.push_back( l_proc ); - const TARGETING::Target * l_pTarget = *l_Procs; + const TARGETING::Target * l_pTarget = l_cpuTargetList[i]; fapi::Target l_fapiproc_target( TARGET_TYPE_PROC_CHIP, reinterpret_cast<void *> (const_cast<TARGETING::Target*>(l_pTarget)) ); diff --git a/src/usr/hwpf/hwp/mc_init/makefile b/src/usr/hwpf/hwp/mc_init/makefile index 39e8fb91d..0dbd28630 100644 --- a/src/usr/hwpf/hwp/mc_init/makefile +++ b/src/usr/hwpf/hwp/mc_init/makefile @@ -44,7 +44,10 @@ EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/mc_init/mss_freq OBJS = mc_init.o \ mss_volt.o \ mss_freq.o \ - mss_eff_config_sim.o + mss_eff_config.o \ + mss_eff_config_thermal.o \ + mss_eff_config_termination.o \ + mss_eff_config_rank_group.o ## NOTE: add a new directory onto the vpaths when you add a new HWP ##@ VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/??? diff --git a/src/usr/hwpf/hwp/mc_init/mc_init.C b/src/usr/hwpf/hwp/mc_init/mc_init.C index e42a1275a..9a636b29e 100644 --- a/src/usr/hwpf/hwp/mc_init/mc_init.C +++ b/src/usr/hwpf/hwp/mc_init/mc_init.C @@ -46,6 +46,7 @@ // targeting support #include <targeting/common/commontargeting.H> +#include <targeting/common/utilFilter.H> // fapi support #include <fapi.H> @@ -63,7 +64,7 @@ // #include "host_collect_dimm_spd/host_collect_dimm_spd.H" #include "mss_volt/mss_volt.H" #include "mss_freq/mss_freq.H" -#include "mss_eff_config/mss_eff_config_sim.H" +#include "mss_eff_config/mss_eff_config.H" namespace MC_INIT { @@ -142,29 +143,17 @@ void call_mss_volt( void *io_pArgs ) TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_volt entry" ); - // figure out what targets we need - // Use PredicateIsFunctional to filter only functional chips - TARGETING::PredicateIsFunctional l_isFunctional; - // filter for functional Centaur Chips - TARGETING::PredicateCTM l_membufChipFilter(CLASS_CHIP, TYPE_MEMBUF); - // declare a postfix expression widget - TARGETING::PredicatePostfixExpr l_functionalAndMembufChipFilter; - // is-a-membuf-chip is-functional AND - l_functionalAndMembufChipFilter.push(&l_membufChipFilter).push(&l_isFunctional).And(); - // loop through all the targets, applying the filter, and put the results in l_pMemBufs - TARGETING::TargetRangeFilter l_pMemBufs( - TARGETING::targetService().begin(), - TARGETING::targetService().end(), - &l_functionalAndMembufChipFilter ); + TARGETING::TargetHandleList l_membufTargetList; + getAllChips(l_membufTargetList, TYPE_MEMBUF); // declare a vector of fapi targets to pass to mss_volt std::vector<fapi::Target> l_membufFapiTargets; // fill in the vector - for ( uint8_t l_membufNum=0 ; l_pMemBufs ; l_membufNum++, ++l_pMemBufs ) + for ( size_t i = 0; i < l_membufTargetList.size(); i++ ) { // make a local copy of the target for ease of use - const TARGETING::Target* l_membuf_target = *l_pMemBufs; + const TARGETING::Target* l_membuf_target = l_membufTargetList[i]; TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "===== add to fapi::Target vector..." ); @@ -213,33 +202,16 @@ void call_mss_freq( void *io_pArgs ) TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_freq entry" ); + TARGETING::TargetHandleList l_membufTargetList; + getAllChips(l_membufTargetList, TYPE_MEMBUF); - // figure out what targets we need - // Use PredicateIsFunctional to filter only functional chips - TARGETING::PredicateIsFunctional l_isFunctional; - // filter for functional Centaur Chips - TARGETING::PredicateCTM l_membufChipFilter(CLASS_CHIP, TYPE_MEMBUF); - // declare a postfix expression widget - TARGETING::PredicatePostfixExpr l_functionalAndMembufChipFilter; - // is-a-membuf-chip is-functional AND - l_functionalAndMembufChipFilter.push(&l_membufChipFilter).push(&l_isFunctional).And(); - // loop through all the targets, applying the filter, and put the results in l_pMemBufs - TARGETING::TargetRangeFilter l_pMemBufs( - TARGETING::targetService().begin(), - TARGETING::targetService().end(), - &l_functionalAndMembufChipFilter ); - - for ( uint8_t l_memBufNum=0 ; - l_pMemBufs ; - l_memBufNum++, ++l_pMemBufs - ) + for ( size_t i = 0; i < l_membufTargetList.size(); i++ ) { // make a local copy of the target for ease of use - const TARGETING::Target* l_membuf_target = *l_pMemBufs; + const TARGETING::Target* l_membuf_target = l_membufTargetList[i]; TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "===== mss_freq HWP( %d )", - l_memBufNum ); + "===== mss_freq HWP( %d )", i ); EntityPath l_path; l_path = l_membuf_target->getAttr<ATTR_PHYS_PATH>(); l_path.dump(); @@ -259,13 +231,13 @@ void call_mss_freq( void *io_pArgs ) TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "ERROR 0x%.8X: mss_freq HWP( %d ) ", l_err->reasonCode(), - l_memBufNum ); + i ); break; // break out memBuf loop } else { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "SUCCESS : mss_freq HWP( %d )", l_memBufNum ); + "SUCCESS : mss_freq HWP( %d )", i ); } } // End memBuf loop @@ -283,33 +255,17 @@ void call_mss_eff_config( void *io_pArgs ) TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_mss_eff_config entry" ); + TARGETING::TargetHandleList l_mbaTargetList; + getAllChiplets(l_mbaTargetList, TYPE_MBA); - // Use PredicateIsFunctional to filter only functional chips - TARGETING::PredicateIsFunctional l_isFunctional; - // filter for functional Centaur Chips - TARGETING::PredicateCTM l_mbaFilter(CLASS_UNIT, TYPE_MBA); - // declare a postfix expression widget - TARGETING::PredicatePostfixExpr l_functionalAndMbaFilter; - // is-a-membuf-chip is-functional AND - l_functionalAndMbaFilter.push(&l_mbaFilter).push(&l_isFunctional).And(); - // loop through all the targets, applying the filter, and put the results in l_pMemBufs - TARGETING::TargetRangeFilter l_pMbas( - TARGETING::targetService().begin(), - TARGETING::targetService().end(), - &l_functionalAndMbaFilter ); - - for ( uint8_t l_mbaNum=0 ; - l_pMbas ; - l_mbaNum++, ++l_pMbas - ) + for ( size_t i = 0; i < l_mbaTargetList.size(); i++ ) { // make a local copy of the target for ease of use - const TARGETING::Target* l_mba_target = *l_pMbas; + const TARGETING::Target* l_mba_target = l_mbaTargetList[i]; // print call to hwp and dump physical path of the target(s) TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "===== mss_eff_config HWP( mba %d )", - l_mbaNum ); + "===== mss_eff_config HWP( mba %d )", i ); // dump physical path to targets EntityPath l_path; l_path = l_mba_target->getAttr<ATTR_PHYS_PATH>(); @@ -323,21 +279,20 @@ void call_mss_eff_config( void *io_pArgs ) (const_cast<TARGETING::Target*>(l_mba_target)) ); // call the HWP with each fapi::Target - FAPI_INVOKE_HWP(l_err, mss_eff_config_sim, l_fapi_mba_target); + FAPI_INVOKE_HWP(l_err, mss_eff_config, l_fapi_mba_target); // process return code. if ( l_err ) { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "ERROR 0x%.8X: mss_eff_config HWP( mba %d ) ", - l_err->reasonCode(), l_mbaNum ); + l_err->reasonCode(), i ); break; // break out mba loop } else { TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "SUCCESS : mss_eff_config HWP( mba %d )", - l_mbaNum ); + "SUCCESS : mss_eff_config HWP( mba %d )", i ); } } // endfor diff --git a/src/usr/hwpf/hwp/mc_init/mss_eff_config/mss_eff_config.C b/src/usr/hwpf/hwp/mc_init/mss_eff_config/mss_eff_config.C new file mode 100644 index 000000000..09788a584 --- /dev/null +++ b/src/usr/hwpf/hwp/mc_init/mss_eff_config/mss_eff_config.C @@ -0,0 +1,615 @@ +// IBM_PROLOG_BEGIN_TAG +// This is an automatically generated prolog. +// +// $Source: src/usr/hwpf/hwp/mc_init/mss_eff_config/mss_eff_config.C $ +// +// IBM CONFIDENTIAL +// +// COPYRIGHT International Business Machines Corp. 2012 +// +// p1 +// +// Object Code Only (OCO) source materials +// Licensed Internal Code Source Materials +// IBM HostBoot Licensed Internal Code +// +// The source code for this program is not published or other- +// wise divested of its trade secrets, irrespective of what has +// been deposited with the U.S. Copyright Office. +// +// Origin: 30 +// +// IBM_PROLOG_END +// $Id: mss_eff_config.C,v 1.7 2012/05/04 19:58:50 asaetow Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config.C,v $ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! TITLE : mss_eff_config +// *! DESCRIPTION : see additional comments below +// *! OWNER NAME : Anuwat Saetow Email: asaetow@us.ibm.com +// *! BACKUP NAME : Mark Bellows Email: bellows@us.ibm.com +// *! ADDITIONAL COMMENTS : +// +// The purpose of this procedure is to setup attributes used in other mss procedures. +// +//------------------------------------------------------------------------------ +// Don't forget to create CVS comments when you check in your changes! +//------------------------------------------------------------------------------ +// CHANGE HISTORY: +//------------------------------------------------------------------------------ +// Version:| Author: | Date: | Comment: +//---------|----------|---------|----------------------------------------------- +// 1.8 | | | +// 1.7 | asaetow |04-MAY-12| Removed calc_u8_timing_in_clk(). +// | | | Changed calc_u32_timing_in_clk() to calc_timing_in_clk() and changed params. +// | | | Removed currently unused vars. +// 1.6 | asaetow |03-MAY-12| Removed FAPI_ATTR_SET(ATTR_EFF_DRAM_CL), moved to mss_freq.C. +// | | | Fixed "suggest parentheses around && within ||", per Mike Jones. +// | | | Changed tCK_in_ps calc to reduce num of operations. +// 1.5 | asaetow |02-MAY-12| Removed #include <*.C>, per FW. +// | | | Added #include <mss_eff_config_thermal.H> +// | | | Added call to sub-procedure mss_eff_config_thermal(). +// 1.4 | asaetow |30-APR-12| Changed procedure to use SPD attributes. +// | | | Added calls to sub-procedures mss_eff_config_rank_group() and mss_eff_config_termination(). +// 1.3 | asaetow |18-APR-12| Changed procedure to print use mss_eff_config_sim.C until 30APR2012. +// 1.2 | asaetow |03-NOV-11| Fixed to comply with mss_eff_config.H. +// | | | Added calls to mss_eff_config_rank_group() and mss_eff_config_thermal(). +// 1.1 | asaetow |01-NOV-11| First Draft. + + + +//---------------------------------------------------------------------- +// My Includes +//---------------------------------------------------------------------- +#include <mss_eff_config.H> +#include <mss_eff_config_rank_group.H> +#include <mss_eff_config_termination.H> +#include <mss_eff_config_thermal.H> + + + +//---------------------------------------------------------------------- +// Includes +//---------------------------------------------------------------------- +#include <fapi.H> + + + +//---------------------------------------------------------------------- +// ENUMs +//---------------------------------------------------------------------- +enum { + EMPTY = 0, + SINGLE_DROP = 1, + DUAL_DROP = 2, + VALID = 255, +}; + + + +extern "C" { + + + +//****************************************************************************** +//* name=calc_timing_in_clk, param=my_tCK_in_ps,my_mtb_in_ps,my_ftb_in_fs,my_unit,my_offset, return=my_timing_in_clk +//****************************************************************************** +uint32_t calc_timing_in_clk(uint32_t my_tCK_in_ps, uint32_t my_mtb_in_ps, uint32_t my_ftb_in_fs, uint32_t my_unit, uint8_t my_offset) { + + uint64_t my_timing = (my_unit * my_mtb_in_ps) + (my_offset * my_ftb_in_fs); + // ceiling() + uint32_t my_timing_in_clk = my_timing / my_tCK_in_ps; + if ((my_timing_in_clk * my_tCK_in_ps) < my_timing) { + my_timing_in_clk += 1; + } + // DEBUG HERE: + //FAPI_INF("calc_timing_in_clk: my_timing_in_clk = %d, my_tCK_in_ps = %d, my_mtb_in_ps = %d, my_ftb_in_fs = %d, my_unit = %d, my_offset = %d", my_timing_in_clk, my_tCK_in_ps, my_mtb_in_ps, my_ftb_in_fs, my_unit, my_offset ); + + return my_timing_in_clk; +} + + + +//****************************************************************************** +//* name=mss_eff_config, param=i_target_mba, return=ReturnCode +//****************************************************************************** +fapi::ReturnCode mss_eff_config(const fapi::Target i_target_mba) { + fapi::ReturnCode rc = fapi::FAPI_RC_SUCCESS; + const char * const PROCEDURE_NAME = "mss_eff_config"; + FAPI_INF("*** Running %s on %s ... ***", PROCEDURE_NAME, i_target_mba.toEcmdString()); + + // Define attribute array size + const uint8_t PORT_SIZE = 2; + const uint8_t DIMM_SIZE = 2; + + // Define spd attribute array size + // HERE const uint8_t SPD_ATTR_SIZE_18 = 18; + // HERE const uint8_t SPD_ATTR_SIZE_57 = 57; + // HERE const uint8_t SPD_ATTR_SIZE_80 = 80; + + // Define local variables + uint8_t plug_config = EMPTY; + uint8_t cur_dimm_spd_valid_u8array[PORT_SIZE][DIMM_SIZE] = {{0}}; + uint8_t cur_mba_port = 0; + uint8_t cur_mba_dimm = 0; + uint8_t cur_dram_density = 0; + uint32_t mss_freq = 0; + uint32_t mss_volt = 0; + uint32_t tCK_in_ps= 0; + uint32_t mtb_in_ps_u32array[PORT_SIZE][DIMM_SIZE] = {{0}}; + uint32_t ftb_in_fs_u32array[PORT_SIZE][DIMM_SIZE] = {{0}}; + //uint8_t my_dram_taa = 0; + uint32_t my_dram_tfaw = 0; + uint32_t my_dram_tras = 0; + uint32_t my_dram_trc = 0; + uint8_t my_dram_trcd = 0; + uint32_t my_dram_trfc = 0; + uint8_t my_dram_trp = 0; + uint8_t my_dram_trrd = 0; + uint8_t my_dram_trtp = 0; + uint8_t my_dram_twtr = 0; + uint8_t my_dram_wr = 0; + + // Define local attribute variables + uint8_t my_attr_eff_dimm_ranks_configed[PORT_SIZE][DIMM_SIZE] = {{0}}; + uint64_t my_attr_eff_dimm_rcd_cntl_word_0_15[PORT_SIZE][DIMM_SIZE] = {{0}}; // AST HERE: Needs SPD byte68:76 + uint8_t my_attr_eff_dimm_size[PORT_SIZE][DIMM_SIZE] = {{0}}; + uint8_t my_attr_eff_dimm_type = 0; + uint8_t my_attr_eff_dram_al = 1; + uint8_t my_attr_eff_dram_asr = 0; + uint8_t my_attr_eff_dram_bl = 0; + // See mss_freq.C + //uint8_t my_attr_eff_dram_cl = 0; + uint8_t my_attr_eff_dram_cwl = 0; + uint8_t my_attr_eff_dram_density = 0; + uint8_t my_attr_eff_dram_dll_enable = 0; + uint8_t my_attr_eff_dram_dll_ppd = 0; + uint8_t my_attr_eff_dram_dll_reset = 1; + uint8_t my_attr_eff_dram_gen = 0; + uint8_t my_attr_eff_dram_output_buffer = 0; + uint8_t my_attr_eff_dram_pasr = 0; + uint8_t my_attr_eff_dram_rbt = 0; + uint8_t my_attr_eff_dram_srt = 1; + uint8_t my_attr_eff_dram_tdqs = 0; + uint8_t my_attr_eff_dram_tfaw = 0; + uint32_t my_attr_eff_dram_tfaw_u32 = 0; + uint8_t my_attr_eff_dram_tm = 0; + uint8_t my_attr_eff_dram_tras = 0; + uint32_t my_attr_eff_dram_tras_u32 = 0; + uint8_t my_attr_eff_dram_trc = 0; + uint32_t my_attr_eff_dram_trc_u32 = 0; + uint8_t my_attr_eff_dram_trcd = 0; + uint32_t my_attr_eff_dram_trfc = 0; + uint32_t my_attr_eff_dram_trfi = 0; + uint8_t my_attr_eff_dram_trp = 0; + uint8_t my_attr_eff_dram_trrd = 0; + uint8_t my_attr_eff_dram_trtp = 0; + uint8_t my_attr_eff_dram_twtr = 0; + uint8_t my_attr_eff_dram_width = 0; + uint8_t my_attr_eff_dram_wr = 0; + uint8_t my_attr_eff_dram_wr_lvl_enable = 0; + uint32_t my_attr_eff_memcal_interval = 0; + uint8_t my_attr_eff_mpr_loc = 0x0; + uint8_t my_attr_eff_mpr_mode = 0; + uint8_t my_attr_eff_num_ranks_per_dimm[PORT_SIZE][DIMM_SIZE] = {{0}}; + uint8_t my_attr_eff_schmoo_mode = 0; + uint8_t my_attr_eff_schmoo_param_valid = 0x0; + uint8_t my_attr_eff_schmoo_test_valid = 0x0; + uint32_t my_attr_eff_zqcal_interval = 0; + + // Define local spd attribute variables + uint8_t spd_dram_device_type_u8array[PORT_SIZE][DIMM_SIZE] = {{0}}; + uint8_t spd_module_type_u8array[PORT_SIZE][DIMM_SIZE] = {{0}}; + uint8_t spd_sdram_banks_u8array[PORT_SIZE][DIMM_SIZE] = {{0}}; + uint8_t spd_sdram_density_u8array[PORT_SIZE][DIMM_SIZE] = {{0}}; + uint8_t spd_sdram_rows_u8array[PORT_SIZE][DIMM_SIZE] = {{0}}; + uint8_t spd_sdram_columns_u8array[PORT_SIZE][DIMM_SIZE] = {{0}}; + //uint8_t spd_module_nominal_voltage_u8array[PORT_SIZE][DIMM_SIZE] = {{0}}; + uint8_t spd_num_ranks_u8array[PORT_SIZE][DIMM_SIZE] = {{0}}; + uint8_t spd_dram_width_u8array[PORT_SIZE][DIMM_SIZE] = {{0}}; + uint8_t spd_module_memory_bus_width_u8array[PORT_SIZE][DIMM_SIZE] = {{0}}; + uint8_t spd_ftb_dividend_u8array[PORT_SIZE][DIMM_SIZE] = {{0}}; + uint8_t spd_ftb_divisor_u8array[PORT_SIZE][DIMM_SIZE] = {{0}}; + uint8_t spd_mtb_dividend_u8array[PORT_SIZE][DIMM_SIZE] = {{0}}; + uint8_t spd_mtb_divisor_u8array[PORT_SIZE][DIMM_SIZE] = {{0}}; + //uint8_t spd_tckmin_u8array[PORT_SIZE][DIMM_SIZE] = {{0}}; + //uint32_t spd_cas_latencies_supported_u32array[PORT_SIZE][DIMM_SIZE] = {{0}}; + //uint8_t spd_taamin_u8array[PORT_SIZE][DIMM_SIZE] = {{0}}; + uint8_t spd_twrmin_u8array[PORT_SIZE][DIMM_SIZE] = {{0}}; + uint8_t spd_trcdmin_u8array[PORT_SIZE][DIMM_SIZE] = {{0}}; + uint8_t spd_trrdmin_u8array[PORT_SIZE][DIMM_SIZE] = {{0}}; + uint8_t spd_trpmin_u8array[PORT_SIZE][DIMM_SIZE] = {{0}}; + uint32_t spd_trasmin_u32array[PORT_SIZE][DIMM_SIZE] = {{0}}; + uint32_t spd_trcmin_u32array[PORT_SIZE][DIMM_SIZE] = {{0}}; + uint32_t spd_trfcmin_u32array[PORT_SIZE][DIMM_SIZE] = {{0}}; + uint8_t spd_twtrmin_u8array[PORT_SIZE][DIMM_SIZE] = {{0}}; + uint8_t spd_trtpmin_u8array[PORT_SIZE][DIMM_SIZE] = {{0}}; + uint32_t spd_tfawmin_u32array[PORT_SIZE][DIMM_SIZE] = {{0}}; + //uint8_t spd_sdram_optional_features_u8array[PORT_SIZE][DIMM_SIZE] = {{0}}; + //uint8_t spd_sdram_thermal_and_refresh_options_u8array[PORT_SIZE][DIMM_SIZE] = {{0}}; + //uint8_t spd_module_thermal_sensor_u8array[PORT_SIZE][DIMM_SIZE] = {{0}}; + uint8_t spd_fine_offset_tckmin_u8array[PORT_SIZE][DIMM_SIZE] = {{0}}; + uint8_t spd_fine_offset_taamin_u8array[PORT_SIZE][DIMM_SIZE] = {{0}}; + uint8_t spd_fine_offset_trcdmin_u8array[PORT_SIZE][DIMM_SIZE] = {{0}}; + uint8_t spd_fine_offset_trpmin_u8array[PORT_SIZE][DIMM_SIZE] = {{0}}; + uint8_t spd_fine_offset_trcmin_u8array[PORT_SIZE][DIMM_SIZE] = {{0}}; + // HERE uint8_t spd_module_specific_section_u8array[PORT_SIZE][DIMM_SIZE][SPD_ATTR_SIZE_57] = {{{0}}}; + //uint32_t spd_module_id_module_manufacturers_jedec_id_code_u32array[PORT_SIZE][DIMM_SIZE] = {{0}}; + //uint8_t spd_module_id_module_manufacturing_location_u8array[PORT_SIZE][DIMM_SIZE] = {{0}}; + //uint32_t spd_module_id_module_manufacturing_date_u32array[PORT_SIZE][DIMM_SIZE] = {{0}}; + //uint32_t spd_module_id_module_serial_number_u32array[PORT_SIZE][DIMM_SIZE] = {{0}}; + //uint32_t spd_cyclical_redundancy_code_u32array[PORT_SIZE][DIMM_SIZE] = {{0}}; + // HERE uint8_t spd_module_part_number_u8array[PORT_SIZE][DIMM_SIZE][SPD_ATTR_SIZE_18] = {{{0}}}; + //uint32_t spd_module_revision_code_u32array[PORT_SIZE][DIMM_SIZE] = {{0}}; + //uint32_t spd_dram_manufacturer_jedec_id_code_u32array[PORT_SIZE][DIMM_SIZE] = {{0}}; + // HERE uint8_t spd_bad_dq_data_u8array[PORT_SIZE][DIMM_SIZE][SPD_ATTR_SIZE_80] = {{{0}}}; + + + // Grab freq/volt data. + fapi::Target l_target_centaur; + rc = fapiGetParentChip(i_target_mba, l_target_centaur); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_target_centaur, mss_freq); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_MSS_VOLT, &l_target_centaur, mss_volt); if(rc) return rc; + tCK_in_ps = 2000000/mss_freq; + FAPI_INF("mss_freq = %d, tCK_in_ps= %d on %s.", mss_freq, tCK_in_ps, l_target_centaur.toEcmdString()); + FAPI_INF("mss_volt = %d on %s.", mss_volt, l_target_centaur.toEcmdString()); + + + // Grab all DIMM/SPD data. + std::vector<fapi::Target> l_target_dimm_array; + rc = fapiGetAssociatedDimms(i_target_mba, l_target_dimm_array); if(rc) return rc; + for (uint8_t dimm_index = 0; dimm_index < l_target_dimm_array.size(); dimm_index += 1) { + + rc = FAPI_ATTR_GET(ATTR_MBA_PORT, &l_target_dimm_array[dimm_index], cur_mba_port); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_MBA_DIMM, &l_target_dimm_array[dimm_index], cur_mba_dimm); if(rc) return rc; + cur_dimm_spd_valid_u8array[cur_mba_port][cur_mba_dimm] = VALID; + + rc = FAPI_ATTR_GET(ATTR_SPD_DRAM_DEVICE_TYPE, &l_target_dimm_array[dimm_index], spd_dram_device_type_u8array[cur_mba_port][cur_mba_dimm]); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_TYPE, &l_target_dimm_array[dimm_index], spd_module_type_u8array[cur_mba_port][cur_mba_dimm]); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_SPD_SDRAM_BANKS, &l_target_dimm_array[dimm_index], spd_sdram_banks_u8array[cur_mba_port][cur_mba_dimm]); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_SPD_SDRAM_DENSITY, &l_target_dimm_array[dimm_index], spd_sdram_density_u8array[cur_mba_port][cur_mba_dimm]); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_SPD_SDRAM_ROWS, &l_target_dimm_array[dimm_index], spd_sdram_rows_u8array[cur_mba_port][cur_mba_dimm]); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_SPD_SDRAM_COLUMNS, &l_target_dimm_array[dimm_index], spd_sdram_columns_u8array[cur_mba_port][cur_mba_dimm]); if(rc) return rc; + //rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_NOMINAL_VOLTAGE, &l_target_dimm_array[dimm_index], spd_module_nominal_voltage_u8array[cur_mba_port][cur_mba_dimm]); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_SPD_NUM_RANKS, &l_target_dimm_array[dimm_index], spd_num_ranks_u8array[cur_mba_port][cur_mba_dimm]); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_SPD_DRAM_WIDTH, &l_target_dimm_array[dimm_index], spd_dram_width_u8array[cur_mba_port][cur_mba_dimm]); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_MEMORY_BUS_WIDTH, &l_target_dimm_array[dimm_index], spd_module_memory_bus_width_u8array[cur_mba_port][cur_mba_dimm]); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_SPD_FTB_DIVIDEND, &l_target_dimm_array[dimm_index], spd_ftb_dividend_u8array[cur_mba_port][cur_mba_dimm]); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_SPD_FTB_DIVISOR, &l_target_dimm_array[dimm_index], spd_ftb_divisor_u8array[cur_mba_port][cur_mba_dimm]); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_SPD_MTB_DIVIDEND, &l_target_dimm_array[dimm_index], spd_mtb_dividend_u8array[cur_mba_port][cur_mba_dimm]); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_SPD_MTB_DIVISOR, &l_target_dimm_array[dimm_index], spd_mtb_divisor_u8array[cur_mba_port][cur_mba_dimm]); if(rc) return rc; + //rc = FAPI_ATTR_GET(ATTR_SPD_TCKMIN, &l_target_dimm_array[dimm_index], spd_tckmin_u8array[cur_mba_port][cur_mba_dimm]); if(rc) return rc; + //rc = FAPI_ATTR_GET(ATTR_SPD_CAS_LATENCIES_SUPPORTED, &l_target_dimm_array[dimm_index], spd_cas_latencies_supported_u32array[cur_mba_port][cur_mba_dimm]); if(rc) return rc; + //rc = FAPI_ATTR_GET(ATTR_SPD_TAAMIN, &l_target_dimm_array[dimm_index], spd_taamin_u8array[cur_mba_port][cur_mba_dimm]); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_SPD_TWRMIN, &l_target_dimm_array[dimm_index], spd_twrmin_u8array[cur_mba_port][cur_mba_dimm]); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_SPD_TRCDMIN, &l_target_dimm_array[dimm_index], spd_trcdmin_u8array[cur_mba_port][cur_mba_dimm]); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_SPD_TRRDMIN, &l_target_dimm_array[dimm_index], spd_trrdmin_u8array[cur_mba_port][cur_mba_dimm]); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_SPD_TRPMIN, &l_target_dimm_array[dimm_index], spd_trpmin_u8array[cur_mba_port][cur_mba_dimm]); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_SPD_TRASMIN, &l_target_dimm_array[dimm_index], spd_trasmin_u32array[cur_mba_port][cur_mba_dimm]); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_SPD_TRCMIN, &l_target_dimm_array[dimm_index], spd_trcmin_u32array[cur_mba_port][cur_mba_dimm]); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_SPD_TRFCMIN, &l_target_dimm_array[dimm_index], spd_trfcmin_u32array[cur_mba_port][cur_mba_dimm]); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_SPD_TWTRMIN, &l_target_dimm_array[dimm_index], spd_twtrmin_u8array[cur_mba_port][cur_mba_dimm]); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_SPD_TRTPMIN, &l_target_dimm_array[dimm_index], spd_trtpmin_u8array[cur_mba_port][cur_mba_dimm]); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_SPD_TFAWMIN, &l_target_dimm_array[dimm_index], spd_tfawmin_u32array[cur_mba_port][cur_mba_dimm]); if(rc) return rc; + //rc = FAPI_ATTR_GET(ATTR_SPD_SDRAM_OPTIONAL_FEATURES, &l_target_dimm_array[dimm_index], spd_sdram_optional_features_u8array[cur_mba_port][cur_mba_dimm]); if(rc) return rc; + //rc = FAPI_ATTR_GET(ATTR_SPD_SDRAM_THERMAL_AND_REFRESH_OPTIONS, &l_target_dimm_array[dimm_index], spd_sdram_thermal_and_refresh_options_u8array[cur_mba_port][cur_mba_dimm]); if(rc) return rc; + //rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_THERMAL_SENSOR, &l_target_dimm_array[dimm_index], spd_module_thermal_sensor_u8array[cur_mba_port][cur_mba_dimm]); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_SPD_FINE_OFFSET_TCKMIN, &l_target_dimm_array[dimm_index], spd_fine_offset_tckmin_u8array[cur_mba_port][cur_mba_dimm]); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_SPD_FINE_OFFSET_TAAMIN, &l_target_dimm_array[dimm_index], spd_fine_offset_taamin_u8array[cur_mba_port][cur_mba_dimm]); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_SPD_FINE_OFFSET_TRCDMIN, &l_target_dimm_array[dimm_index], spd_fine_offset_trcdmin_u8array[cur_mba_port][cur_mba_dimm]); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_SPD_FINE_OFFSET_TRPMIN, &l_target_dimm_array[dimm_index], spd_fine_offset_trpmin_u8array[cur_mba_port][cur_mba_dimm]); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_SPD_FINE_OFFSET_TRCMIN, &l_target_dimm_array[dimm_index], spd_fine_offset_trcmin_u8array[cur_mba_port][cur_mba_dimm]); if(rc) return rc; + // HERE rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_SPECIFIC_SECTION, &l_target_dimm_array[dimm_index], spd_module_specific_section_u8array[cur_mba_port][cur_mba_dimm]); if(rc) return rc; + //rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_ID_MODULE_MANUFACTURERS_JEDEC_ID_CODE, &l_target_dimm_array[dimm_index], spd_module_id_module_manufacturers_jedec_id_code_u32array[cur_mba_port][cur_mba_dimm]); if(rc) return rc; + //rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_ID_MODULE_MANUFACTURING_LOCATION, &l_target_dimm_array[dimm_index], spd_module_id_module_manufacturing_location_u8array[cur_mba_port][cur_mba_dimm]); if(rc) return rc; + //rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_ID_MODULE_MANUFACTURING_DATE, &l_target_dimm_array[dimm_index], spd_module_id_module_manufacturing_date_u32array[cur_mba_port][cur_mba_dimm]); if(rc) return rc; + //rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_ID_MODULE_SERIAL_NUMBER, &l_target_dimm_array[dimm_index], spd_module_id_module_serial_number_u32array[cur_mba_port][cur_mba_dimm]); if(rc) return rc; + //rc = FAPI_ATTR_GET(ATTR_SPD_CYCLICAL_REDUNDANCY_CODE, &l_target_dimm_array[dimm_index], spd_cyclical_redundancy_code_u32array[cur_mba_port][cur_mba_dimm]); if(rc) return rc; + // HERE rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_PART_NUMBER, &l_target_dimm_array[dimm_index], spd_module_part_number_u8array[cur_mba_port][cur_mba_dimm]); if(rc) return rc; + //rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_REVISION_CODE, &l_target_dimm_array[dimm_index], spd_module_revision_code_u32array[cur_mba_port][cur_mba_dimm]); if(rc) return rc; + //rc = FAPI_ATTR_GET(ATTR_SPD_DRAM_MANUFACTURER_JEDEC_ID_CODE, &l_target_dimm_array[dimm_index], spd_dram_manufacturer_jedec_id_code_u32array[cur_mba_port][cur_mba_dimm]); if(rc) return rc; + // HERE rc = FAPI_ATTR_GET(ATTR_SPD_BAD_DQ_DATA, &l_target_dimm_array[dimm_index], spd_bad_dq_data_u8array[cur_mba_port][cur_mba_dimm]); if(rc) return rc; + } + + + // Identify/Verify DIMM plug rule + if ((cur_dimm_spd_valid_u8array[0][0] == EMPTY) && ((cur_dimm_spd_valid_u8array[0][1] == VALID) || (cur_dimm_spd_valid_u8array[1][0] == VALID) || (cur_dimm_spd_valid_u8array[1][1] == VALID))) { + FAPI_ERR("Plug rule violation on %s!", i_target_mba.toEcmdString()); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; + } + if (((cur_dimm_spd_valid_u8array[0][0] == VALID) && (cur_dimm_spd_valid_u8array[1][0] == EMPTY)) || ((cur_dimm_spd_valid_u8array[0][1] == VALID) && (cur_dimm_spd_valid_u8array[1][1] == EMPTY))) { + FAPI_ERR("Plug rule violation on %s!", i_target_mba.toEcmdString()); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; + } + if ((cur_dimm_spd_valid_u8array[0][0] == VALID) && (cur_dimm_spd_valid_u8array[0][1] == VALID)) { + plug_config = DUAL_DROP; + } else if ((cur_dimm_spd_valid_u8array[0][0] == VALID) && (cur_dimm_spd_valid_u8array[0][1] == EMPTY)) { + plug_config = SINGLE_DROP; + } else { + plug_config = EMPTY; + } + + + // Start Identify/Verify/Assigning values to attributes + if (plug_config != EMPTY) { + + // Identify/Verify DIMM compatability + if ((spd_dram_device_type_u8array[0][0] != spd_dram_device_type_u8array[1][0]) || ((plug_config == DUAL_DROP) && ((spd_dram_device_type_u8array[0][1] != spd_dram_device_type_u8array[1][1]) || (spd_dram_device_type_u8array[0][0] != spd_dram_device_type_u8array[0][1])))) { + FAPI_ERR("Incompatable DRAM generation on %s!", i_target_mba.toEcmdString()); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; + } + if ((spd_module_type_u8array[0][0] != spd_module_type_u8array[1][0]) || ((plug_config == DUAL_DROP) && ((spd_module_type_u8array[0][1] != spd_module_type_u8array[1][1]) || (spd_module_type_u8array[0][0] != spd_module_type_u8array[0][1])))) { + FAPI_ERR("Incompatable DIMM type on %s!", i_target_mba.toEcmdString()); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; + } + if ((spd_num_ranks_u8array[0][0] != spd_num_ranks_u8array[1][0]) || ((plug_config == DUAL_DROP) && ((spd_num_ranks_u8array[0][1] != spd_num_ranks_u8array[1][1]) || (spd_num_ranks_u8array[0][0] != spd_num_ranks_u8array[0][1])))) { + FAPI_ERR("Incompatable DIMM ranks on %s!", i_target_mba.toEcmdString()); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; + } + if ((spd_module_memory_bus_width_u8array[0][0] != spd_module_memory_bus_width_u8array[1][0]) || ((plug_config == DUAL_DROP) && ((spd_module_memory_bus_width_u8array[0][1] != spd_module_memory_bus_width_u8array[1][1]) || (spd_module_memory_bus_width_u8array[0][0] != spd_module_memory_bus_width_u8array[0][1])))) { + FAPI_ERR("Incompatable DRAM primary bus width on %s!", i_target_mba.toEcmdString()); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; + } + /* AST HERE: Needs SPD byte8[4:3] + if ((spd_module_memory_bus_width_extension_u8array[0][0] != spd_module_memory_bus_width_extension_u8array[1][0]) || ((plug_config == DUAL_DROP) && ((spd_module_memory_bus_width_extension_u8array[0][1] != spd_module_memory_bus_width_extension_u8array[1][1])) || ((spd_module_memory_bus_width_extension_u8array[0][0] != spd_module_memory_bus_width_extension_u8array[0][1])))) { + FAPI_ERR("Incompatable DRAM bus width extension on %s!", i_target_mba.toEcmdString()); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; + } + if ((spd_module_memory_bus_width_u8array[0][0] != fapi::ENUM_ATTR_SPD_MODULE_MEMORY_BUS_WIDTH_W64) || (spd_module_memory_bus_width_extension_u8array[0][0] != fapi::ENUM_ATTR_SPD_MODULE_MEMORY_BUS_WIDTH_EXTENSION_W8)) { + FAPI_ERR("Unsupported DRAM bus width on %s!", i_target_mba.toEcmdString()); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; + } + */ + if ((spd_dram_width_u8array[0][0] != spd_dram_width_u8array[1][0]) || ((plug_config == DUAL_DROP) && ((spd_dram_width_u8array[0][1] != spd_dram_width_u8array[1][1]) || (spd_dram_width_u8array[0][0] != spd_dram_width_u8array[0][1])))) { + FAPI_ERR("Incompatable DRAM width on %s!", i_target_mba.toEcmdString()); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; + } + + // Assigning values to attributes + if (spd_dram_device_type_u8array[0][0] == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR3) { + my_attr_eff_dram_gen = fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR3; + } else if (spd_dram_device_type_u8array[0][0] == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR4) { + my_attr_eff_dram_gen = fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4; + } else { + FAPI_ERR("Unknown DRAM type on %s!", i_target_mba.toEcmdString()); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; + } + if (spd_module_type_u8array[0][0] == fapi::ENUM_ATTR_SPD_MODULE_TYPE_CDIMM) { + my_attr_eff_dimm_type = fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM; + } else if (spd_module_type_u8array[0][0] == fapi::ENUM_ATTR_SPD_MODULE_TYPE_RDIMM) { + my_attr_eff_dimm_type = fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM; + } else if (spd_module_type_u8array[0][0] == fapi::ENUM_ATTR_SPD_MODULE_TYPE_UDIMM) { + my_attr_eff_dimm_type = fapi::ENUM_ATTR_EFF_DIMM_TYPE_UDIMM; + } else if (spd_module_type_u8array[0][0] == fapi::ENUM_ATTR_SPD_MODULE_TYPE_LRDIMM) { + my_attr_eff_dimm_type = fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM; + } else { + FAPI_ERR("Unknown DIMM type on %s!", i_target_mba.toEcmdString()); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; + } + if (spd_dram_width_u8array[0][0] == fapi::ENUM_ATTR_SPD_DRAM_WIDTH_W4) { + my_attr_eff_dram_width = fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X4; + } else if (spd_dram_width_u8array[0][0] == fapi::ENUM_ATTR_SPD_DRAM_WIDTH_W8) { + my_attr_eff_dram_width = fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X8; + // NOTE: TDQS enable MR1(A11) is only avaliable for X8 in DDR3 + my_attr_eff_dram_tdqs = 1; + } else if (spd_dram_width_u8array[0][0] == fapi::ENUM_ATTR_SPD_DRAM_WIDTH_W16) { + my_attr_eff_dram_width = fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X16; + FAPI_ERR("Unsupported DRAM width x16 on %s!", i_target_mba.toEcmdString()); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; + } else if (spd_dram_width_u8array[0][0] == fapi::ENUM_ATTR_SPD_DRAM_WIDTH_W32) { + my_attr_eff_dram_width = fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X32; + FAPI_ERR("Unsupported DRAM width x32 on %s!", i_target_mba.toEcmdString()); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; + } else { + FAPI_ERR("Unknown DRAM width on %s!", i_target_mba.toEcmdString()); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; + } + my_attr_eff_dram_density = 16; + for (cur_mba_port = 0; cur_mba_port < PORT_SIZE; cur_mba_port += 1) { + for (cur_mba_dimm = 0; cur_mba_dimm < plug_config; cur_mba_dimm += 1) { + if (spd_sdram_density_u8array[cur_mba_port][cur_mba_dimm] == fapi::ENUM_ATTR_SPD_SDRAM_DENSITY_D16GB) { + cur_dram_density = 16; + } else if (spd_sdram_density_u8array[cur_mba_port][cur_mba_dimm] == fapi::ENUM_ATTR_SPD_SDRAM_DENSITY_D8GB) { + cur_dram_density = 8; + } else if (spd_sdram_density_u8array[cur_mba_port][cur_mba_dimm] == fapi::ENUM_ATTR_SPD_SDRAM_DENSITY_D4GB) { + cur_dram_density = 4; + } else if (spd_sdram_density_u8array[cur_mba_port][cur_mba_dimm] == fapi::ENUM_ATTR_SPD_SDRAM_DENSITY_D2GB) { + cur_dram_density = 2; + } else if (spd_sdram_density_u8array[cur_mba_port][cur_mba_dimm] == fapi::ENUM_ATTR_SPD_SDRAM_DENSITY_D1GB) { + cur_dram_density = 1; + } else { + FAPI_ERR("Unsupported DRAM density on %s!", i_target_mba.toEcmdString()); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; + } + if (my_attr_eff_dram_density > cur_dram_density) { + my_attr_eff_dram_density = cur_dram_density; + } + + // Identify/Verify DIMM voltage compatability + // See mss_volt.C + + // Identify/Assign minimum timing + mtb_in_ps_u32array[cur_mba_port][cur_mba_dimm] = (spd_mtb_dividend_u8array[cur_mba_port][cur_mba_dimm] * 1000) / spd_mtb_divisor_u8array[cur_mba_port][cur_mba_dimm]; + ftb_in_fs_u32array[cur_mba_port][cur_mba_dimm] = (spd_ftb_dividend_u8array[cur_mba_port][cur_mba_dimm] * 1000) / spd_ftb_divisor_u8array[cur_mba_port][cur_mba_dimm]; + + // Calculate CL + // See mss_freq.C + + my_dram_wr = calc_timing_in_clk(tCK_in_ps, mtb_in_ps_u32array[cur_mba_port][cur_mba_dimm], ftb_in_fs_u32array[cur_mba_port][cur_mba_dimm], spd_twrmin_u8array[cur_mba_port][cur_mba_dimm], 0); + if (my_dram_wr > my_attr_eff_dram_wr) { + my_attr_eff_dram_wr = my_dram_wr; + } + my_dram_trcd = calc_timing_in_clk(tCK_in_ps, mtb_in_ps_u32array[cur_mba_port][cur_mba_dimm], ftb_in_fs_u32array[cur_mba_port][cur_mba_dimm], spd_trcdmin_u8array[cur_mba_port][cur_mba_dimm], spd_fine_offset_trcdmin_u8array[cur_mba_port][cur_mba_dimm]); + if (my_dram_trcd > my_attr_eff_dram_trcd) { + my_attr_eff_dram_trcd = my_dram_trcd; + } + my_dram_trrd = calc_timing_in_clk(tCK_in_ps, mtb_in_ps_u32array[cur_mba_port][cur_mba_dimm], ftb_in_fs_u32array[cur_mba_port][cur_mba_dimm], spd_trrdmin_u8array[cur_mba_port][cur_mba_dimm], 0); + if (my_dram_trrd > my_attr_eff_dram_trrd) { + my_attr_eff_dram_trrd = my_dram_trrd; + } + my_dram_trp = calc_timing_in_clk(tCK_in_ps, mtb_in_ps_u32array[cur_mba_port][cur_mba_dimm], ftb_in_fs_u32array[cur_mba_port][cur_mba_dimm], spd_trpmin_u8array[cur_mba_port][cur_mba_dimm], spd_fine_offset_trpmin_u8array[cur_mba_port][cur_mba_dimm]); + if (my_dram_trp > my_attr_eff_dram_trp) { + my_attr_eff_dram_trp = my_dram_trp; + } + my_dram_twtr = calc_timing_in_clk(tCK_in_ps, mtb_in_ps_u32array[cur_mba_port][cur_mba_dimm], ftb_in_fs_u32array[cur_mba_port][cur_mba_dimm], spd_twtrmin_u8array[cur_mba_port][cur_mba_dimm], 0); + if (my_dram_twtr > my_attr_eff_dram_twtr) { + my_attr_eff_dram_twtr = my_dram_twtr; + } + my_dram_trtp = calc_timing_in_clk(tCK_in_ps, mtb_in_ps_u32array[cur_mba_port][cur_mba_dimm], ftb_in_fs_u32array[cur_mba_port][cur_mba_dimm], spd_trtpmin_u8array[cur_mba_port][cur_mba_dimm], 0); + if (my_dram_trtp > my_attr_eff_dram_trtp) { + my_attr_eff_dram_trtp = my_dram_trtp; + } + my_dram_tras = calc_timing_in_clk(tCK_in_ps, mtb_in_ps_u32array[cur_mba_port][cur_mba_dimm], ftb_in_fs_u32array[cur_mba_port][cur_mba_dimm], spd_trasmin_u32array[cur_mba_port][cur_mba_dimm], 0); + if (my_dram_tras > my_attr_eff_dram_tras_u32) { + my_attr_eff_dram_tras_u32 = my_dram_tras; + } + my_dram_trc = calc_timing_in_clk(tCK_in_ps, mtb_in_ps_u32array[cur_mba_port][cur_mba_dimm], ftb_in_fs_u32array[cur_mba_port][cur_mba_dimm], spd_trcmin_u32array[cur_mba_port][cur_mba_dimm], spd_fine_offset_trcmin_u8array[cur_mba_port][cur_mba_dimm]); + if (my_dram_trc > my_attr_eff_dram_trc_u32) { + my_attr_eff_dram_trc_u32 = my_dram_trc; + } + my_dram_trfc = calc_timing_in_clk(tCK_in_ps, mtb_in_ps_u32array[cur_mba_port][cur_mba_dimm], ftb_in_fs_u32array[cur_mba_port][cur_mba_dimm], spd_trfcmin_u32array[cur_mba_port][cur_mba_dimm], 0); if(rc) return rc; + if (my_dram_trfc > my_attr_eff_dram_trfc) { + my_attr_eff_dram_trfc = my_dram_trfc; + } + my_dram_tfaw = calc_timing_in_clk(tCK_in_ps, mtb_in_ps_u32array[cur_mba_port][cur_mba_dimm], ftb_in_fs_u32array[cur_mba_port][cur_mba_dimm], spd_tfawmin_u32array[cur_mba_port][cur_mba_dimm], 0); if(rc) return rc; + if (my_dram_tfaw > my_attr_eff_dram_tfaw_u32) { + my_attr_eff_dram_tfaw_u32 = my_dram_tfaw; + } + } + } + + // Calculate CWL + if ((2000000/mss_freq) >= 2500) { + my_attr_eff_dram_cwl = 5; + } else if ((2000000/mss_freq) >= 1875) { + my_attr_eff_dram_cwl = 6; + } else if ((2000000/mss_freq) >= 1500) { + my_attr_eff_dram_cwl = 7; + } else if ((2000000/mss_freq) >= 1250) { + my_attr_eff_dram_cwl = 8; + } else if ((2000000/mss_freq) >= 1070) { + my_attr_eff_dram_cwl = 9; + } else if ((2000000/mss_freq) >= 935) { + my_attr_eff_dram_cwl = 10; + } else if ((2000000/mss_freq) >= 833) { + my_attr_eff_dram_cwl = 11; + } else if ((2000000/mss_freq) >= 750) { + my_attr_eff_dram_cwl = 12; + } + + // Calculate tRFI + my_attr_eff_dram_trfi = (3900 * mss_freq) / 2000; + + // Assigning dependent values to attributes + for (cur_mba_port = 0; cur_mba_port < PORT_SIZE; cur_mba_port += 1) { + for (cur_mba_dimm = 0; cur_mba_dimm < DIMM_SIZE; cur_mba_dimm += 1) { + if (spd_num_ranks_u8array[cur_mba_port][cur_mba_dimm] == fapi::ENUM_ATTR_SPD_NUM_RANKS_R4) { + my_attr_eff_num_ranks_per_dimm[cur_mba_port][cur_mba_dimm] = 4; + my_attr_eff_dimm_ranks_configed[cur_mba_port][cur_mba_dimm] = 0xF0; + } else if (spd_num_ranks_u8array[cur_mba_port][cur_mba_dimm] == fapi::ENUM_ATTR_SPD_NUM_RANKS_R2) { + my_attr_eff_num_ranks_per_dimm[cur_mba_port][cur_mba_dimm] = 2; + my_attr_eff_dimm_ranks_configed[cur_mba_port][cur_mba_dimm] = 0xC0; + } else if (spd_num_ranks_u8array[cur_mba_port][cur_mba_dimm] == fapi::ENUM_ATTR_SPD_NUM_RANKS_R1) { + my_attr_eff_num_ranks_per_dimm[cur_mba_port][cur_mba_dimm] = 1; + my_attr_eff_dimm_ranks_configed[cur_mba_port][cur_mba_dimm] = 0x80; + } else { + my_attr_eff_num_ranks_per_dimm[cur_mba_port][cur_mba_dimm] = 0; + my_attr_eff_dimm_ranks_configed[cur_mba_port][cur_mba_dimm] = 0x00; + } + + if (my_attr_eff_num_ranks_per_dimm != 0) { + + // dimm_size = dram_density / 8 * primary_bus_width / dram_width * num_ranks_per_dimm + // AST HERE: Temp definition for my_attr_eff_dram_width, will redefine attribute XML + //my_attr_eff_dimm_size[cur_mba_port][cur_mba_dimm] = (my_attr_eff_dram_density * my_attr_eff_num_ranks_per_dimm[cur_mba_port][cur_mba_dimm] * 64) / (8 * my_attr_eff_dram_width); + uint8_t actual_dram_width = 0; + if (my_attr_eff_dram_width == fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X4) { + actual_dram_width = 4; + } else if (my_attr_eff_dram_width == fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X8) { + actual_dram_width = 8; + } else if (my_attr_eff_dram_width == fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X16) { + actual_dram_width = 16; + } else if (my_attr_eff_dram_width == fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X32) { + actual_dram_width = 32; + } else { + FAPI_ERR("Unknown DRAM width on %s!", i_target_mba.toEcmdString()); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc; + } + my_attr_eff_dimm_size[cur_mba_port][cur_mba_dimm] = (my_attr_eff_dram_density * my_attr_eff_num_ranks_per_dimm[cur_mba_port][cur_mba_dimm] * 64) / (8 * actual_dram_width); + + } else { + my_attr_eff_dimm_size[cur_mba_port][cur_mba_dimm] = 0; + } + // DEBUG HERE: + //FAPI_INF("size=%d density=%d ranks=%d width=%d on %s", my_attr_eff_dimm_size[cur_mba_port][cur_mba_dimm], my_attr_eff_dram_density, my_attr_eff_num_ranks_per_dimm[cur_mba_port][cur_mba_dimm], my_attr_eff_dram_width, i_target_mba.toEcmdString()); + } + } + } + + + my_attr_eff_dram_tras = uint8_t (my_attr_eff_dram_tras_u32); + my_attr_eff_dram_trc = uint8_t (my_attr_eff_dram_trc_u32); + my_attr_eff_dram_tfaw = uint8_t (my_attr_eff_dram_tfaw_u32); + + + // Set attributes + rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RANKS_CONFIGED, &i_target_mba, my_attr_eff_dimm_ranks_configed); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15, &i_target_mba, my_attr_eff_dimm_rcd_cntl_word_0_15); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_SIZE, &i_target_mba, my_attr_eff_dimm_size); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_TYPE, &i_target_mba, my_attr_eff_dimm_type); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_AL, &i_target_mba, my_attr_eff_dram_al); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_ASR, &i_target_mba, my_attr_eff_dram_asr); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_BL, &i_target_mba, my_attr_eff_dram_bl); if(rc) return rc; + // See mss_freq.C + //rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_CL, &i_target_mba, my_attr_eff_dram_cl); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_CWL, &i_target_mba, my_attr_eff_dram_cwl); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_DENSITY, &i_target_mba, my_attr_eff_dram_density); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_DLL_ENABLE, &i_target_mba, my_attr_eff_dram_dll_enable); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_DLL_PPD, &i_target_mba, my_attr_eff_dram_dll_ppd); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_DLL_RESET, &i_target_mba, my_attr_eff_dram_dll_reset); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_GEN, &i_target_mba, my_attr_eff_dram_gen); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_OUTPUT_BUFFER, &i_target_mba, my_attr_eff_dram_output_buffer); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_PASR, &i_target_mba, my_attr_eff_dram_pasr); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_RBT, &i_target_mba, my_attr_eff_dram_rbt); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_SRT, &i_target_mba, my_attr_eff_dram_srt); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_TDQS, &i_target_mba, my_attr_eff_dram_tdqs); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_TFAW, &i_target_mba, my_attr_eff_dram_tfaw); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_TM, &i_target_mba, my_attr_eff_dram_tm); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_TRAS, &i_target_mba, my_attr_eff_dram_tras); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_TRC, &i_target_mba, my_attr_eff_dram_trc); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_TRCD, &i_target_mba, my_attr_eff_dram_trcd); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_TRFC, &i_target_mba, my_attr_eff_dram_trfc); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_TRFI, &i_target_mba, my_attr_eff_dram_trfi); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_TRP, &i_target_mba, my_attr_eff_dram_trp); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_TRRD, &i_target_mba, my_attr_eff_dram_trrd); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_TRTP, &i_target_mba, my_attr_eff_dram_trtp); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_TWTR, &i_target_mba, my_attr_eff_dram_twtr); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_WIDTH, &i_target_mba, my_attr_eff_dram_width); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_WR, &i_target_mba, my_attr_eff_dram_wr); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_WR_LVL_ENABLE, &i_target_mba, my_attr_eff_dram_wr_lvl_enable); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_MEMCAL_INTERVAL, &i_target_mba, my_attr_eff_memcal_interval); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_MPR_LOC, &i_target_mba, my_attr_eff_mpr_loc); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_MPR_MODE, &i_target_mba, my_attr_eff_mpr_mode); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, my_attr_eff_num_ranks_per_dimm); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_MODE, &i_target_mba, my_attr_eff_schmoo_mode); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_PARAM_VALID, &i_target_mba, my_attr_eff_schmoo_param_valid); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_TEST_VALID, &i_target_mba, my_attr_eff_schmoo_test_valid); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_ZQCAL_INTERVAL, &i_target_mba, my_attr_eff_zqcal_interval); if(rc) return rc; + + + // Calls to sub-procedures + rc = mss_eff_config_rank_group(i_target_mba); if(rc) return rc; + rc = mss_eff_config_termination(i_target_mba); if(rc) return rc; + rc = mss_eff_config_thermal(i_target_mba); if(rc) return rc; + + + FAPI_INF("%s on %s COMPLETE\n", PROCEDURE_NAME, i_target_mba.toEcmdString()); + return rc; +} + + + +} // extern "C" diff --git a/src/usr/hwpf/hwp/mc_init/mss_eff_config/mss_eff_config_sim.H b/src/usr/hwpf/hwp/mc_init/mss_eff_config/mss_eff_config.H index d3242403e..724085e02 100644 --- a/src/usr/hwpf/hwp/mc_init/mss_eff_config/mss_eff_config_sim.H +++ b/src/usr/hwpf/hwp/mc_init/mss_eff_config/mss_eff_config.H @@ -1,7 +1,7 @@ // IBM_PROLOG_BEGIN_TAG // This is an automatically generated prolog. // -// $Source: src/usr/hwpf/hwp/mc_init/mss_eff_config/mss_eff_config_sim.H $ +// $Source: src/usr/hwpf/hwp/mc_init/mss_eff_config/mss_eff_config.H $ // // IBM CONFIDENTIAL // @@ -20,15 +20,15 @@ // Origin: 30 // // IBM_PROLOG_END -// $Id: mss_eff_config_sim.H,v 1.2 2012/02/15 01:15:56 asaetow Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config_sim.H,v $ +// $Id: mss_eff_config.H,v 1.2 2012/02/15 01:34:45 asaetow Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config.H,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 // *! All Rights Reserved -- Property of IBM // *! *** IBM Confidential *** //------------------------------------------------------------------------------ -// *! TITLE : mss_eff_config_sim.H -// *! DESCRIPTION : Header file for mss_eff_config_sim. +// *! TITLE : mss_eff_config.H +// *! DESCRIPTION : Header file for mss_eff_config. // *! OWNER NAME : Anuwat Saetow Email: asaetow@us.ibm.com // *! BACKUP NAME : Mark Bellows Email: bellows@us.ibm.com // *! ADDITIONAL COMMENTS : @@ -44,11 +44,11 @@ //---------|----------|---------|----------------------------------------------- // 1.3 | | | // 1.2 | asaetow |14-FEB-12| Fixed "fapi::" for hostboot, added "const", renamed "i_target_mba", and changed comments. -// 1.1 | asaetow |13-FEB-12| First Draft. +// 1.1 | asaetow |03-NOV-11| First Draft. -#ifndef MSS_EFF_CONFIG_SIM_H_ -#define MSS_EFF_CONFIG_SIM_H_ +#ifndef MSS_EFF_CONFIG_H_ +#define MSS_EFF_CONFIG_H_ //---------------------------------------------------------------------- // My Includes @@ -61,15 +61,15 @@ #include <fapi.H> -typedef fapi::ReturnCode (*mss_eff_config_sim_FP_t)(const fapi::Target i_target_mba); +typedef fapi::ReturnCode (*mss_eff_config_FP_t)(const fapi::Target i_target_mba); extern "C" { //****************************************************************************** -//* name=mss_eff_config_sim, param=i_target_mba, return=ReturnCode +//* name=mss_eff_config, param=i_target_mba, return=ReturnCode //****************************************************************************** -fapi::ReturnCode mss_eff_config_sim(const fapi::Target i_target_mba); +fapi::ReturnCode mss_eff_config(const fapi::Target i_target_mba); } // extern "C" -#endif // MSS_EFF_CONFIG_SIM_H_ +#endif // MSS_EFF_CONFIG_H_ diff --git a/src/usr/hwpf/hwp/mc_init/mss_eff_config/mss_eff_config_rank_group.C b/src/usr/hwpf/hwp/mc_init/mss_eff_config/mss_eff_config_rank_group.C new file mode 100644 index 000000000..ec3c6f353 --- /dev/null +++ b/src/usr/hwpf/hwp/mc_init/mss_eff_config/mss_eff_config_rank_group.C @@ -0,0 +1,250 @@ +// IBM_PROLOG_BEGIN_TAG +// This is an automatically generated prolog. +// +// $Source: src/usr/hwpf/hwp/mc_init/mss_eff_config/mss_eff_config_rank_group.C $ +// +// IBM CONFIDENTIAL +// +// COPYRIGHT International Business Machines Corp. 2012 +// +// p1 +// +// Object Code Only (OCO) source materials +// Licensed Internal Code Source Materials +// IBM HostBoot Licensed Internal Code +// +// The source code for this program is not published or other- +// wise divested of its trade secrets, irrespective of what has +// been deposited with the U.S. Copyright Office. +// +// Origin: 30 +// +// IBM_PROLOG_END +// $Id: mss_eff_config_rank_group.C,v 1.6 2012/04/30 15:11:46 asaetow Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config_rank_group.C,v $ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! TITLE : mss_eff_config_rank_group +// *! DESCRIPTION : see additional comments below +// *! OWNER NAME : Anuwat Saetow Email: asaetow@us.ibm.com +// *! BACKUP NAME : Mark Bellows Email: bellows@us.ibm.com +// *! ADDITIONAL COMMENTS : +// +// This procedure takes in attributes and determines proper rank groupings that will be apply to the system and used during draminit_training and draminit_training_adv. Each valid rank in the system will be assigned to one of twelve attributes below. Only the primary rank group will be calibrated and have values stored in the delay registers. +// EFF_PRIMARY_RANK_GROUP0, EFF_PRIMARY_RANK_GROUP1, EFF_PRIMARY_RANK_GROUP2, EFF_PRIMARY_RANK_GROUP3 +// EFF_SECONDARY_RANK_GROUP0, EFF_SECONDARY_RANK_GROUP1, EFF_SECONDARY_RANK_GROUP2, EFF_SECONDARY_RANK_GROUP3 +// EFF_TERTIARY_RANK_GROUP0, EFF_TERTIARY_RANK_GROUP1, EFF_TERTIARY_RANK_GROUP2, EFF_TERTIARY_RANK_GROUP3 +// EFF_QUATERNARY_RANK_GROUP0, EFF_QUATERNARY_RANK_GROUP1, EFF_QUATERNARY_RANK_GROUP2, EFF_QUATERNARY_RANK_GROUP3 +// +//------------------------------------------------------------------------------ +// Don't forget to create CVS comments when you check in your changes! +//------------------------------------------------------------------------------ +// CHANGE HISTORY: +//------------------------------------------------------------------------------ +// Version:| Author: | Date: | Comment: +//---------|----------|---------|----------------------------------------------- +// 1.7 | | | +// 1.6 | asaetow |30-APR-12| Fixed "fapi::" for hostboot, added "const", renamed "i_target_mba", and changed comments. +// | | | Changed message to standardized format. +// | | | Changed BACKUP to Mark Bellows. +// 1.5 | asaetow |20-MAR-12| Changed EFF_CONFIG_RANK_GROUP_RC_ERROR_001A to RC_MSS_PLACE_HOLDER_ERROR temporary until Cronus is ready to pick up error code xml. +// 1.4 | asaetow |08-FEB-12| Added INVALID(255) into ranks that do not exist. +// | | | Removed support for mix ATTR_EFF_NUM_RANKS_PER_DIMM within a port. +// | | | Changed "rc =" to "FAPI_SET_HWP_ERROR(rc, EFF_CONFIG_RANK_GROUP_RC_ERROR_001A)". +// 1.3 | asaetow |24-JAN-12| Removed all temp hard code work around and enabled FAPI_ATTR_GET(). +// | | | Added mem_attr write back support, enabled FAPI_ATTR_SET(). +// | | | Removed triple-drop support. +// | | | Changed PORT_SIZE and DIMM_SIZE to const 2 to match mem_attr. +// | | | Added extern "C" so that procedure can be run independently. +// 1.2 | asaetow |03-NOV-11| Fixed to comply with mss_eff_config_rank_group.H +// 1.1 | asaetow |01-NOV-11| First Draft. + + + +//---------------------------------------------------------------------- +// My Includes +//---------------------------------------------------------------------- + + + +//---------------------------------------------------------------------- +// Includes +//---------------------------------------------------------------------- +#include <fapi.H> + + + +//---------------------------------------------------------------------- +// ENUMs +//---------------------------------------------------------------------- +enum { + CDIMM = 0, + RDIMM = 1, + UDIMM = 2, + LRDIMM = 3, + INVALID = 255, +}; + + + +extern "C" { + + + +//****************************************************************************** +//* name=mss_eff_config_rank_group, param=i_target_mba, return=ReturnCode +//****************************************************************************** +fapi::ReturnCode mss_eff_config_rank_group(const fapi::Target i_target_mba) { + fapi::ReturnCode rc = fapi::FAPI_RC_SUCCESS; + const char * const PROCEDURE_NAME = "mss_eff_config_rank_group"; + FAPI_INF("*** Running %s on %s ... ***", PROCEDURE_NAME, i_target_mba.toEcmdString()); + + const uint8_t PORT_SIZE = 2; + const uint8_t DIMM_SIZE = 2; + // ATTR_EFF_DRAM_GEN: EMPTY = 0, DDR3 = 1, DDR4 = 2, + // ATTR_EFF_DIMM_TYPE: CDIMM = 0, RDIMM = 1, UDIMM = 2, LRDIMM = 3, + uint8_t num_ranks_per_dimm_u8array[PORT_SIZE][DIMM_SIZE]; + uint8_t dram_gen_u8; + uint8_t dimm_type_u8; + + rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, num_ranks_per_dimm_u8array); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_GEN, &i_target_mba, dram_gen_u8); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target_mba, dimm_type_u8); if(rc) return rc; + + uint8_t primary_rank_group0_u8array[PORT_SIZE]; + uint8_t primary_rank_group1_u8array[PORT_SIZE]; + uint8_t primary_rank_group2_u8array[PORT_SIZE]; + uint8_t primary_rank_group3_u8array[PORT_SIZE]; + uint8_t secondary_rank_group0_u8array[PORT_SIZE]; + uint8_t secondary_rank_group1_u8array[PORT_SIZE]; + uint8_t secondary_rank_group2_u8array[PORT_SIZE]; + uint8_t secondary_rank_group3_u8array[PORT_SIZE]; + uint8_t tertiary_rank_group0_u8array[PORT_SIZE]; + uint8_t tertiary_rank_group1_u8array[PORT_SIZE]; + uint8_t tertiary_rank_group2_u8array[PORT_SIZE]; + uint8_t tertiary_rank_group3_u8array[PORT_SIZE]; + uint8_t quanternary_rank_group0_u8array[PORT_SIZE]; + uint8_t quanternary_rank_group1_u8array[PORT_SIZE]; + uint8_t quanternary_rank_group2_u8array[PORT_SIZE]; + uint8_t quanternary_rank_group3_u8array[PORT_SIZE]; + + for (uint8_t cur_port = 0; cur_port < PORT_SIZE; cur_port += 1) { + if (dimm_type_u8 == LRDIMM) { + // HERE: NOT correct, need to account for ATTR_EFF_DIMM_RANKS_CONFIGED for LRDIMMs /w multi master ranks + primary_rank_group0_u8array[cur_port] = 0; + primary_rank_group1_u8array[cur_port] = 4; + primary_rank_group2_u8array[cur_port] = 8; + primary_rank_group3_u8array[cur_port] = 12; + secondary_rank_group0_u8array[cur_port] = 1; + secondary_rank_group1_u8array[cur_port] = 5; + secondary_rank_group2_u8array[cur_port] = 9; + secondary_rank_group3_u8array[cur_port] = 13; + tertiary_rank_group0_u8array[cur_port] = 2; + tertiary_rank_group1_u8array[cur_port] = 6; + tertiary_rank_group2_u8array[cur_port] = 10; + tertiary_rank_group3_u8array[cur_port] = 14; + quanternary_rank_group0_u8array[cur_port] = 3; + quanternary_rank_group1_u8array[cur_port] = 7; + quanternary_rank_group2_u8array[cur_port] = 11; + quanternary_rank_group3_u8array[cur_port] = 15; + } else { // RDIMM or CDIMM + if ((num_ranks_per_dimm_u8array[cur_port][0] > 0) && (num_ranks_per_dimm_u8array[cur_port][1] == 0)) { + primary_rank_group0_u8array[cur_port] = 0; + if (num_ranks_per_dimm_u8array[cur_port][0] > 1) { + primary_rank_group1_u8array[cur_port] = 1; + } else { + primary_rank_group1_u8array[cur_port] = INVALID; + } + if (num_ranks_per_dimm_u8array[cur_port][0] > 2) { + primary_rank_group2_u8array[cur_port] = 2; + primary_rank_group3_u8array[cur_port] = 3; + } else { + primary_rank_group2_u8array[cur_port] = INVALID; + primary_rank_group3_u8array[cur_port] = INVALID; + } + secondary_rank_group0_u8array[cur_port] = INVALID; + secondary_rank_group1_u8array[cur_port] = INVALID; + secondary_rank_group2_u8array[cur_port] = INVALID; + secondary_rank_group3_u8array[cur_port] = INVALID; + } else if ((num_ranks_per_dimm_u8array[cur_port][0] > 0) && (num_ranks_per_dimm_u8array[cur_port][1] > 0)) { + if (num_ranks_per_dimm_u8array[cur_port][0] != num_ranks_per_dimm_u8array[cur_port][1]) { + FAPI_ERR("%s: FAILED!", PROCEDURE_NAME); + FAPI_ERR("Plug rule violation, num_ranks_per_dimm=%d[0],%d[1] on %s PORT%d!", num_ranks_per_dimm_u8array[cur_port][0], num_ranks_per_dimm_u8array[cur_port][1], i_target_mba.toEcmdString(), cur_port); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); + return rc; + } + primary_rank_group0_u8array[cur_port] = 0; + primary_rank_group1_u8array[cur_port] = 4; + if (num_ranks_per_dimm_u8array[cur_port][0] == 2) { + primary_rank_group2_u8array[cur_port] = 1; + primary_rank_group3_u8array[cur_port] = 5; + secondary_rank_group0_u8array[cur_port] = INVALID; + secondary_rank_group1_u8array[cur_port] = INVALID; + secondary_rank_group2_u8array[cur_port] = INVALID; + secondary_rank_group3_u8array[cur_port] = INVALID; + } else if (num_ranks_per_dimm_u8array[cur_port][0] == 4) { + primary_rank_group2_u8array[cur_port] = 2; + primary_rank_group3_u8array[cur_port] = 6; + secondary_rank_group0_u8array[cur_port] = 1; + secondary_rank_group1_u8array[cur_port] = 5; + secondary_rank_group2_u8array[cur_port] = 3; + secondary_rank_group3_u8array[cur_port] = 7; + } else if (num_ranks_per_dimm_u8array[cur_port][0] != 1) { + FAPI_ERR("%s: FAILED!", PROCEDURE_NAME); + FAPI_ERR("Plug rule violation, num_ranks_per_dimm=%d[0],%d[1] on %s PORT%d!", num_ranks_per_dimm_u8array[cur_port][0], num_ranks_per_dimm_u8array[cur_port][1], i_target_mba.toEcmdString(), cur_port); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); + return rc; + } + } else if ((num_ranks_per_dimm_u8array[cur_port][0] == 0) && (num_ranks_per_dimm_u8array[cur_port][1] == 0)) { + primary_rank_group0_u8array[cur_port] = INVALID; + primary_rank_group1_u8array[cur_port] = INVALID; + primary_rank_group2_u8array[cur_port] = INVALID; + primary_rank_group3_u8array[cur_port] = INVALID; + secondary_rank_group0_u8array[cur_port] = INVALID; + secondary_rank_group1_u8array[cur_port] = INVALID; + secondary_rank_group2_u8array[cur_port] = INVALID; + secondary_rank_group3_u8array[cur_port] = INVALID; + } else { + FAPI_ERR("%s: FAILED!", PROCEDURE_NAME); + FAPI_ERR("Plug rule violation, num_ranks_per_dimm=%d[0],%d[1] on %s PORT%d!", num_ranks_per_dimm_u8array[cur_port][0], num_ranks_per_dimm_u8array[cur_port][1], i_target_mba.toEcmdString(), cur_port); + FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); + return rc; + } + tertiary_rank_group0_u8array[cur_port] = INVALID; + tertiary_rank_group1_u8array[cur_port] = INVALID; + tertiary_rank_group2_u8array[cur_port] = INVALID; + tertiary_rank_group3_u8array[cur_port] = INVALID; + quanternary_rank_group0_u8array[cur_port] = INVALID; + quanternary_rank_group1_u8array[cur_port] = INVALID; + quanternary_rank_group2_u8array[cur_port] = INVALID; + quanternary_rank_group3_u8array[cur_port] = INVALID; + } + FAPI_INF("P[%02d][%02d][%02d][%02d],S[%02d][%02d][%02d][%02d],T[%02d][%02d][%02d][%02d],Q[%02d][%02d][%02d][%02d] on %s PORT%d.", primary_rank_group0_u8array[cur_port], primary_rank_group1_u8array[cur_port], primary_rank_group2_u8array[cur_port], primary_rank_group3_u8array[cur_port], secondary_rank_group0_u8array[cur_port], secondary_rank_group1_u8array[cur_port], secondary_rank_group2_u8array[cur_port], secondary_rank_group3_u8array[cur_port], tertiary_rank_group0_u8array[cur_port], tertiary_rank_group1_u8array[cur_port], tertiary_rank_group2_u8array[cur_port], tertiary_rank_group3_u8array[cur_port], quanternary_rank_group0_u8array[cur_port], quanternary_rank_group1_u8array[cur_port], quanternary_rank_group2_u8array[cur_port], quanternary_rank_group3_u8array[cur_port], i_target_mba.toEcmdString(), cur_port); + } + rc = FAPI_ATTR_SET(ATTR_EFF_PRIMARY_RANK_GROUP0, &i_target_mba, primary_rank_group0_u8array); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_PRIMARY_RANK_GROUP1, &i_target_mba, primary_rank_group1_u8array); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_PRIMARY_RANK_GROUP2, &i_target_mba, primary_rank_group2_u8array); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_PRIMARY_RANK_GROUP3, &i_target_mba, primary_rank_group3_u8array); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_SECONDARY_RANK_GROUP0, &i_target_mba, secondary_rank_group0_u8array); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_SECONDARY_RANK_GROUP1, &i_target_mba, secondary_rank_group1_u8array); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_SECONDARY_RANK_GROUP2, &i_target_mba, secondary_rank_group2_u8array); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_SECONDARY_RANK_GROUP3, &i_target_mba, secondary_rank_group3_u8array); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_TERTIARY_RANK_GROUP0, &i_target_mba, tertiary_rank_group0_u8array); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_TERTIARY_RANK_GROUP1, &i_target_mba, tertiary_rank_group1_u8array); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_TERTIARY_RANK_GROUP2, &i_target_mba, tertiary_rank_group2_u8array); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_TERTIARY_RANK_GROUP3, &i_target_mba, tertiary_rank_group3_u8array); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_QUATERNARY_RANK_GROUP0, &i_target_mba, quanternary_rank_group0_u8array); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_QUATERNARY_RANK_GROUP1, &i_target_mba, quanternary_rank_group1_u8array); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_QUATERNARY_RANK_GROUP2, &i_target_mba, quanternary_rank_group2_u8array); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_QUATERNARY_RANK_GROUP3, &i_target_mba, quanternary_rank_group3_u8array); if(rc) return rc; + + FAPI_INF("%s on %s COMPLETE", PROCEDURE_NAME, i_target_mba.toEcmdString()); + return rc; +} + + + +} // extern "C" diff --git a/src/usr/hwpf/hwp/mc_init/mss_eff_config/mss_eff_config_rank_group.H b/src/usr/hwpf/hwp/mc_init/mss_eff_config/mss_eff_config_rank_group.H new file mode 100644 index 000000000..f5197c008 --- /dev/null +++ b/src/usr/hwpf/hwp/mc_init/mss_eff_config/mss_eff_config_rank_group.H @@ -0,0 +1,76 @@ +// IBM_PROLOG_BEGIN_TAG +// This is an automatically generated prolog. +// +// $Source: src/usr/hwpf/hwp/mc_init/mss_eff_config/mss_eff_config_rank_group.H $ +// +// IBM CONFIDENTIAL +// +// COPYRIGHT International Business Machines Corp. 2012 +// +// p1 +// +// Object Code Only (OCO) source materials +// Licensed Internal Code Source Materials +// IBM HostBoot Licensed Internal Code +// +// The source code for this program is not published or other- +// wise divested of its trade secrets, irrespective of what has +// been deposited with the U.S. Copyright Office. +// +// Origin: 30 +// +// IBM_PROLOG_END +// $Id: mss_eff_config_rank_group.H,v 1.3 2012/02/15 01:39:30 asaetow Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config_rank_group.H,v $ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! TITLE : mss_eff_config_rank_group.H +// *! DESCRIPTION : Header file for mss_eff_config_rank_group. +// *! OWNER NAME : Anuwat Saetow Email: asaetow@us.ibm.com +// *! BACKUP NAME : Mark Bellows Email: bellows@us.ibm.com +// *! ADDITIONAL COMMENTS : +// +// +// +//------------------------------------------------------------------------------ +// Don't forget to create CVS comments when you check in your changes! +//------------------------------------------------------------------------------ +// CHANGE HISTORY: +//------------------------------------------------------------------------------ +// Version:| Author: | Date: | Comment: +//---------|----------|---------|----------------------------------------------- +// 1.4 | | | +// 1.3 | asaetow |14-FEB-12| Fixed "fapi::" for hostboot, added "const", renamed "i_target_mba", and changed comments. +// 1.2 | asaetow |24-JAN-12| Added typedef and extern "C". +// 1.1 | asaetow |03-NOV-11| First Draft. + + +#ifndef MSS_EFF_CONFIG_RANK_GROUP_H_ +#define MSS_EFF_CONFIG_RANK_GROUP_H_ + +//---------------------------------------------------------------------- +// My Includes +//---------------------------------------------------------------------- + + +//---------------------------------------------------------------------- +// Includes +//---------------------------------------------------------------------- +#include <fapi.H> + + +typedef fapi::ReturnCode (*mss_eff_config_rank_group_FP_t)(const fapi::Target i_target_mba); + +extern "C" { + +//****************************************************************************** +//* name=mss_eff_config_rank_group, param=i_target_mba, return=ReturnCode +//****************************************************************************** +fapi::ReturnCode mss_eff_config_rank_group(const fapi::Target i_target_mba); + +} // extern "C" + +#endif // MSS_EFF_CONFIG_RANK_GROUP_H_ diff --git a/src/usr/hwpf/hwp/mc_init/mss_eff_config/mss_eff_config_sim.C b/src/usr/hwpf/hwp/mc_init/mss_eff_config/mss_eff_config_sim.C deleted file mode 100644 index 94512cda6..000000000 --- a/src/usr/hwpf/hwp/mc_init/mss_eff_config/mss_eff_config_sim.C +++ /dev/null @@ -1,326 +0,0 @@ -// IBM_PROLOG_BEGIN_TAG -// This is an automatically generated prolog. -// -// $Source: src/usr/hwpf/hwp/mc_init/mss_eff_config/mss_eff_config_sim.C $ -// -// IBM CONFIDENTIAL -// -// COPYRIGHT International Business Machines Corp. 2012 -// -// p1 -// -// Object Code Only (OCO) source materials -// Licensed Internal Code Source Materials -// IBM HostBoot Licensed Internal Code -// -// The source code for this program is not published or other- -// wise divested of its trade secrets, irrespective of what has -// been deposited with the U.S. Copyright Office. -// -// Origin: 30 -// -// IBM_PROLOG_END -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2011 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -//------------------------------------------------------------------------------ -// *! TITLE : mss_eff_config_sim.C -// *! DESCRIPTION : This code was auto generated by mss_eff_config_sim_gen.pl -// *! OWNER NAME : asaetow -// *! ADDITIONAL COMMENTS : -// -// FOR SIM ONLY! -// -//------------------------------------------------------------------------------ -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:| Author: | Date: | Comment: -//---------|---------------------------|-----------|---------------------------- -// X.X | mss_eff_config_sim_gen.pl |07-Mar-2012| Machine generated code. - - -//---------------------------------------------------------------------- -// My Includes -//---------------------------------------------------------------------- -#include <mss_eff_config_sim.H> - - -//---------------------------------------------------------------------- -// Includes -//---------------------------------------------------------------------- -#include <fapi.H> - - -extern "C" { - -//****************************************************************************** -//* name=mss_eff_config_sim, param=i_target_mba, return=ReturnCode -//****************************************************************************** -fapi::ReturnCode mss_eff_config_sim(const fapi::Target i_target_mba) { - fapi::ReturnCode rc = fapi::FAPI_RC_SUCCESS; - const char * const PROCEDURE_NAME = "mss_eff_config_sim"; - FAPI_INF("*** Running %s ... ***", PROCEDURE_NAME); - uint8_t my_attr_eff_cen_drv_imp_cmd = 15; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_CMD, &i_target_mba, my_attr_eff_cen_drv_imp_cmd); if(rc) return rc; - uint8_t my_attr_eff_cen_drv_imp_cntl = 15; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_CNTL, &i_target_mba, my_attr_eff_cen_drv_imp_cntl); if(rc) return rc; - uint8_t my_attr_eff_cen_drv_imp_dq_dqs = 24; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS, &i_target_mba, my_attr_eff_cen_drv_imp_dq_dqs); if(rc) return rc; - uint8_t my_attr_eff_cen_rcv_imp_dq_dqs = 15; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RCV_IMP_DQ_DQS, &i_target_mba, my_attr_eff_cen_rcv_imp_dq_dqs); if(rc) return rc; - uint32_t my_attr_eff_cen_rd_vref = 50000; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RD_VREF, &i_target_mba, my_attr_eff_cen_rd_vref); if(rc) return rc; - uint8_t my_attr_eff_cen_slew_rate_cmd = 0x0; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_CMD, &i_target_mba, my_attr_eff_cen_slew_rate_cmd); if(rc) return rc; - uint8_t my_attr_eff_cen_slew_rate_cntl = 0x0; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_CNTL, &i_target_mba, my_attr_eff_cen_slew_rate_cntl); if(rc) return rc; - uint8_t my_attr_eff_cen_slew_rate_dq_dqs = 0x0; - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS, &i_target_mba, my_attr_eff_cen_slew_rate_dq_dqs); if(rc) return rc; - uint8_t my_attr_eff_dimm_ranks_configed[2][2]; - my_attr_eff_dimm_ranks_configed[0][0] = 0x80; - my_attr_eff_dimm_ranks_configed[0][1] = 0x0; - my_attr_eff_dimm_ranks_configed[1][0] = 0x80; - my_attr_eff_dimm_ranks_configed[1][1] = 0x0; - rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RANKS_CONFIGED, &i_target_mba, my_attr_eff_dimm_ranks_configed); if(rc) return rc; - uint64_t my_attr_eff_dimm_rcd_cntl_word_0_15[2][2]; - my_attr_eff_dimm_rcd_cntl_word_0_15[0][0] = 0x0000000000000000; - my_attr_eff_dimm_rcd_cntl_word_0_15[0][1] = 0x0000000000000000; - my_attr_eff_dimm_rcd_cntl_word_0_15[1][0] = 0x0000000000000000; - my_attr_eff_dimm_rcd_cntl_word_0_15[1][1] = 0x0000000000000000; - rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15, &i_target_mba, my_attr_eff_dimm_rcd_cntl_word_0_15); if(rc) return rc; - uint8_t my_attr_eff_dimm_size[2][2]; - my_attr_eff_dimm_size[0][0] = 0x4; - my_attr_eff_dimm_size[0][1] = 0x0; - my_attr_eff_dimm_size[1][0] = 0x4; - my_attr_eff_dimm_size[1][1] = 0x0; - rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_SIZE, &i_target_mba, my_attr_eff_dimm_size); if(rc) return rc; - uint8_t my_attr_eff_dimm_type = 0; - rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_TYPE, &i_target_mba, my_attr_eff_dimm_type); if(rc) return rc; - uint8_t my_attr_eff_dram_al = 1; - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_AL, &i_target_mba, my_attr_eff_dram_al); if(rc) return rc; - uint8_t my_attr_eff_dram_asr = 0; - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_ASR, &i_target_mba, my_attr_eff_dram_asr); if(rc) return rc; - uint8_t my_attr_eff_dram_bl = 0; - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_BL, &i_target_mba, my_attr_eff_dram_bl); if(rc) return rc; - uint8_t my_attr_eff_dram_cl = 0xB; - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_CL, &i_target_mba, my_attr_eff_dram_cl); if(rc) return rc; - uint8_t my_attr_eff_dram_cwl = 0x8; - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_CWL, &i_target_mba, my_attr_eff_dram_cwl); if(rc) return rc; - uint8_t my_attr_eff_dram_density = 0x4; - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_DENSITY, &i_target_mba, my_attr_eff_dram_density); if(rc) return rc; - uint8_t my_attr_eff_dram_dll_enable = 0; - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_DLL_ENABLE, &i_target_mba, my_attr_eff_dram_dll_enable); if(rc) return rc; - uint8_t my_attr_eff_dram_dll_ppd = 0; - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_DLL_PPD, &i_target_mba, my_attr_eff_dram_dll_ppd); if(rc) return rc; - uint8_t my_attr_eff_dram_dll_reset = 1; - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_DLL_RESET, &i_target_mba, my_attr_eff_dram_dll_reset); if(rc) return rc; - uint8_t my_attr_eff_dram_gen = 1; - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_GEN, &i_target_mba, my_attr_eff_dram_gen); if(rc) return rc; - uint8_t my_attr_eff_dram_output_buffer = 0; - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_OUTPUT_BUFFER, &i_target_mba, my_attr_eff_dram_output_buffer); if(rc) return rc; - uint8_t my_attr_eff_dram_pasr = 0; - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_PASR, &i_target_mba, my_attr_eff_dram_pasr); if(rc) return rc; - uint8_t my_attr_eff_dram_rbt = 0; - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_RBT, &i_target_mba, my_attr_eff_dram_rbt); if(rc) return rc; - uint8_t my_attr_eff_dram_ron[2][2]; - my_attr_eff_dram_ron[0][0] = 34; - my_attr_eff_dram_ron[0][1] = 40; - my_attr_eff_dram_ron[1][0] = 34; - my_attr_eff_dram_ron[1][1] = 40; - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_RON, &i_target_mba, my_attr_eff_dram_ron); if(rc) return rc; - uint8_t my_attr_eff_dram_rtt_nom[2][2][4]; - my_attr_eff_dram_rtt_nom[0][0][0] = 0; - my_attr_eff_dram_rtt_nom[0][0][1] = 0; - my_attr_eff_dram_rtt_nom[0][0][2] = 0; - my_attr_eff_dram_rtt_nom[0][0][3] = 0; - my_attr_eff_dram_rtt_nom[0][1][0] = 0; - my_attr_eff_dram_rtt_nom[0][1][1] = 0; - my_attr_eff_dram_rtt_nom[0][1][2] = 0; - my_attr_eff_dram_rtt_nom[0][1][3] = 0; - my_attr_eff_dram_rtt_nom[1][0][0] = 0; - my_attr_eff_dram_rtt_nom[1][0][1] = 0; - my_attr_eff_dram_rtt_nom[1][0][2] = 0; - my_attr_eff_dram_rtt_nom[1][0][3] = 0; - my_attr_eff_dram_rtt_nom[1][1][0] = 0; - my_attr_eff_dram_rtt_nom[1][1][1] = 0; - my_attr_eff_dram_rtt_nom[1][1][2] = 0; - my_attr_eff_dram_rtt_nom[1][1][3] = 0; - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_RTT_NOM, &i_target_mba, my_attr_eff_dram_rtt_nom); if(rc) return rc; - uint8_t my_attr_eff_dram_rtt_wr[2][2][4]; - my_attr_eff_dram_rtt_wr[0][0][0] = 60; - my_attr_eff_dram_rtt_wr[0][0][1] = 0; - my_attr_eff_dram_rtt_wr[0][0][2] = 0; - my_attr_eff_dram_rtt_wr[0][0][3] = 0; - my_attr_eff_dram_rtt_wr[0][1][0] = 0; - my_attr_eff_dram_rtt_wr[0][1][1] = 0; - my_attr_eff_dram_rtt_wr[0][1][2] = 0; - my_attr_eff_dram_rtt_wr[0][1][3] = 0; - my_attr_eff_dram_rtt_wr[1][0][0] = 60; - my_attr_eff_dram_rtt_wr[1][0][1] = 0; - my_attr_eff_dram_rtt_wr[1][0][2] = 0; - my_attr_eff_dram_rtt_wr[1][0][3] = 0; - my_attr_eff_dram_rtt_wr[1][1][0] = 0; - my_attr_eff_dram_rtt_wr[1][1][1] = 0; - my_attr_eff_dram_rtt_wr[1][1][2] = 0; - my_attr_eff_dram_rtt_wr[1][1][3] = 0; - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_RTT_WR, &i_target_mba, my_attr_eff_dram_rtt_wr); if(rc) return rc; - uint8_t my_attr_eff_dram_srt = 1; - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_SRT, &i_target_mba, my_attr_eff_dram_srt); if(rc) return rc; - uint8_t my_attr_eff_dram_tdqs = 1; - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_TDQS, &i_target_mba, my_attr_eff_dram_tdqs); if(rc) return rc; - uint8_t my_attr_eff_dram_tfaw = 0x18; - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_TFAW, &i_target_mba, my_attr_eff_dram_tfaw); if(rc) return rc; - uint8_t my_attr_eff_dram_tm = 0; - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_TM, &i_target_mba, my_attr_eff_dram_tm); if(rc) return rc; - uint8_t my_attr_eff_dram_tras = 0x1C; - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_TRAS, &i_target_mba, my_attr_eff_dram_tras); if(rc) return rc; - uint8_t my_attr_eff_dram_trc = 0x27; - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_TRC, &i_target_mba, my_attr_eff_dram_trc); if(rc) return rc; - uint8_t my_attr_eff_dram_trcd = 0xB; - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_TRCD, &i_target_mba, my_attr_eff_dram_trcd); if(rc) return rc; - uint32_t my_attr_eff_dram_trfc = 0x000000D0; - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_TRFC, &i_target_mba, my_attr_eff_dram_trfc); if(rc) return rc; - uint32_t my_attr_eff_dram_trfi = 0x00000C30; - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_TRFI, &i_target_mba, my_attr_eff_dram_trfi); if(rc) return rc; - uint8_t my_attr_eff_dram_trp = 0xB; - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_TRP, &i_target_mba, my_attr_eff_dram_trp); if(rc) return rc; - uint8_t my_attr_eff_dram_trrd = 0x5; - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_TRRD, &i_target_mba, my_attr_eff_dram_trrd); if(rc) return rc; - uint8_t my_attr_eff_dram_trtp = 0x6; - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_TRTP, &i_target_mba, my_attr_eff_dram_trtp); if(rc) return rc; - uint8_t my_attr_eff_dram_twtr = 0x6; - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_TWTR, &i_target_mba, my_attr_eff_dram_twtr); if(rc) return rc; - uint8_t my_attr_eff_dram_width = 1; - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_WIDTH, &i_target_mba, my_attr_eff_dram_width); if(rc) return rc; - uint8_t my_attr_eff_dram_wr = 0xC; - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_WR, &i_target_mba, my_attr_eff_dram_wr); if(rc) return rc; - uint8_t my_attr_eff_dram_wr_lvl_enable = 0; - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_WR_LVL_ENABLE, &i_target_mba, my_attr_eff_dram_wr_lvl_enable); if(rc) return rc; - uint32_t my_attr_eff_dram_wr_vref = 500; - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_WR_VREF, &i_target_mba, my_attr_eff_dram_wr_vref); if(rc) return rc; - uint32_t my_attr_eff_memcal_interval = 0; - rc = FAPI_ATTR_SET(ATTR_EFF_MEMCAL_INTERVAL, &i_target_mba, my_attr_eff_memcal_interval); if(rc) return rc; - uint8_t my_attr_eff_mpr_loc = 0x0; - rc = FAPI_ATTR_SET(ATTR_EFF_MPR_LOC, &i_target_mba, my_attr_eff_mpr_loc); if(rc) return rc; - uint8_t my_attr_eff_mpr_mode = 0; - rc = FAPI_ATTR_SET(ATTR_EFF_MPR_MODE, &i_target_mba, my_attr_eff_mpr_mode); if(rc) return rc; - uint8_t my_attr_eff_num_ranks_per_dimm[2][2]; - my_attr_eff_num_ranks_per_dimm[0][0] = 0x1; - my_attr_eff_num_ranks_per_dimm[0][1] = 0x0; - my_attr_eff_num_ranks_per_dimm[1][0] = 0x1; - my_attr_eff_num_ranks_per_dimm[1][1] = 0x0; - rc = FAPI_ATTR_SET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, my_attr_eff_num_ranks_per_dimm); if(rc) return rc; - uint8_t my_attr_eff_odt_rd[2][2][4]; - my_attr_eff_odt_rd[0][0][0] = 0x0; - my_attr_eff_odt_rd[0][0][1] = 0x0; - my_attr_eff_odt_rd[0][0][2] = 0x0; - my_attr_eff_odt_rd[0][0][3] = 0x0; - my_attr_eff_odt_rd[0][1][0] = 0x0; - my_attr_eff_odt_rd[0][1][1] = 0x0; - my_attr_eff_odt_rd[0][1][2] = 0x0; - my_attr_eff_odt_rd[0][1][3] = 0x0; - my_attr_eff_odt_rd[1][0][0] = 0x0; - my_attr_eff_odt_rd[1][0][1] = 0x0; - my_attr_eff_odt_rd[1][0][2] = 0x0; - my_attr_eff_odt_rd[1][0][3] = 0x0; - my_attr_eff_odt_rd[1][1][0] = 0x0; - my_attr_eff_odt_rd[1][1][1] = 0x0; - my_attr_eff_odt_rd[1][1][2] = 0x0; - my_attr_eff_odt_rd[1][1][3] = 0x0; - rc = FAPI_ATTR_SET(ATTR_EFF_ODT_RD, &i_target_mba, my_attr_eff_odt_rd); if(rc) return rc; - uint8_t my_attr_eff_odt_wr[2][2][4]; - my_attr_eff_odt_wr[0][0][0] = 0x0; - my_attr_eff_odt_wr[0][0][1] = 0x0; - my_attr_eff_odt_wr[0][0][2] = 0x0; - my_attr_eff_odt_wr[0][0][3] = 0x0; - my_attr_eff_odt_wr[0][1][0] = 0x0; - my_attr_eff_odt_wr[0][1][1] = 0x0; - my_attr_eff_odt_wr[0][1][2] = 0x0; - my_attr_eff_odt_wr[0][1][3] = 0x0; - my_attr_eff_odt_wr[1][0][0] = 0x0; - my_attr_eff_odt_wr[1][0][1] = 0x0; - my_attr_eff_odt_wr[1][0][2] = 0x0; - my_attr_eff_odt_wr[1][0][3] = 0x0; - my_attr_eff_odt_wr[1][1][0] = 0x0; - my_attr_eff_odt_wr[1][1][1] = 0x0; - my_attr_eff_odt_wr[1][1][2] = 0x0; - my_attr_eff_odt_wr[1][1][3] = 0x0; - rc = FAPI_ATTR_SET(ATTR_EFF_ODT_WR, &i_target_mba, my_attr_eff_odt_wr); if(rc) return rc; - uint8_t my_attr_eff_primary_rank_group0[2]; - my_attr_eff_primary_rank_group0[0] = 0x0; - my_attr_eff_primary_rank_group0[1] = 0x0; - rc = FAPI_ATTR_SET(ATTR_EFF_PRIMARY_RANK_GROUP0, &i_target_mba, my_attr_eff_primary_rank_group0); if(rc) return rc; - uint8_t my_attr_eff_primary_rank_group1[2]; - my_attr_eff_primary_rank_group1[0] = 255; - my_attr_eff_primary_rank_group1[1] = 255; - rc = FAPI_ATTR_SET(ATTR_EFF_PRIMARY_RANK_GROUP1, &i_target_mba, my_attr_eff_primary_rank_group1); if(rc) return rc; - uint8_t my_attr_eff_primary_rank_group2[2]; - my_attr_eff_primary_rank_group2[0] = 255; - my_attr_eff_primary_rank_group2[1] = 255; - rc = FAPI_ATTR_SET(ATTR_EFF_PRIMARY_RANK_GROUP2, &i_target_mba, my_attr_eff_primary_rank_group2); if(rc) return rc; - uint8_t my_attr_eff_primary_rank_group3[2]; - my_attr_eff_primary_rank_group3[0] = 255; - my_attr_eff_primary_rank_group3[1] = 255; - rc = FAPI_ATTR_SET(ATTR_EFF_PRIMARY_RANK_GROUP3, &i_target_mba, my_attr_eff_primary_rank_group3); if(rc) return rc; - uint8_t my_attr_eff_quaternary_rank_group0[2]; - my_attr_eff_quaternary_rank_group0[0] = 255; - my_attr_eff_quaternary_rank_group0[1] = 255; - rc = FAPI_ATTR_SET(ATTR_EFF_QUATERNARY_RANK_GROUP0, &i_target_mba, my_attr_eff_quaternary_rank_group0); if(rc) return rc; - uint8_t my_attr_eff_quaternary_rank_group1[2]; - my_attr_eff_quaternary_rank_group1[0] = 255; - my_attr_eff_quaternary_rank_group1[1] = 255; - rc = FAPI_ATTR_SET(ATTR_EFF_QUATERNARY_RANK_GROUP1, &i_target_mba, my_attr_eff_quaternary_rank_group1); if(rc) return rc; - uint8_t my_attr_eff_quaternary_rank_group2[2]; - my_attr_eff_quaternary_rank_group2[0] = 255; - my_attr_eff_quaternary_rank_group2[1] = 255; - rc = FAPI_ATTR_SET(ATTR_EFF_QUATERNARY_RANK_GROUP2, &i_target_mba, my_attr_eff_quaternary_rank_group2); if(rc) return rc; - uint8_t my_attr_eff_quaternary_rank_group3[2]; - my_attr_eff_quaternary_rank_group3[0] = 255; - my_attr_eff_quaternary_rank_group3[1] = 255; - rc = FAPI_ATTR_SET(ATTR_EFF_QUATERNARY_RANK_GROUP3, &i_target_mba, my_attr_eff_quaternary_rank_group3); if(rc) return rc; - uint8_t my_attr_eff_schmoo_mode = 0; - rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_MODE, &i_target_mba, my_attr_eff_schmoo_mode); if(rc) return rc; - uint8_t my_attr_eff_schmoo_param_valid = 0x0; - rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_PARAM_VALID, &i_target_mba, my_attr_eff_schmoo_param_valid); if(rc) return rc; - uint8_t my_attr_eff_schmoo_test_valid = 0x0; - rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_TEST_VALID, &i_target_mba, my_attr_eff_schmoo_test_valid); if(rc) return rc; - uint8_t my_attr_eff_secondary_rank_group0[2]; - my_attr_eff_secondary_rank_group0[0] = 255; - my_attr_eff_secondary_rank_group0[1] = 255; - rc = FAPI_ATTR_SET(ATTR_EFF_SECONDARY_RANK_GROUP0, &i_target_mba, my_attr_eff_secondary_rank_group0); if(rc) return rc; - uint8_t my_attr_eff_secondary_rank_group1[2]; - my_attr_eff_secondary_rank_group1[0] = 255; - my_attr_eff_secondary_rank_group1[1] = 255; - rc = FAPI_ATTR_SET(ATTR_EFF_SECONDARY_RANK_GROUP1, &i_target_mba, my_attr_eff_secondary_rank_group1); if(rc) return rc; - uint8_t my_attr_eff_secondary_rank_group2[2]; - my_attr_eff_secondary_rank_group2[0] = 255; - my_attr_eff_secondary_rank_group2[1] = 255; - rc = FAPI_ATTR_SET(ATTR_EFF_SECONDARY_RANK_GROUP2, &i_target_mba, my_attr_eff_secondary_rank_group2); if(rc) return rc; - uint8_t my_attr_eff_secondary_rank_group3[2]; - my_attr_eff_secondary_rank_group3[0] = 255; - my_attr_eff_secondary_rank_group3[1] = 255; - rc = FAPI_ATTR_SET(ATTR_EFF_SECONDARY_RANK_GROUP3, &i_target_mba, my_attr_eff_secondary_rank_group3); if(rc) return rc; - uint8_t my_attr_eff_tertiary_rank_group0[2]; - my_attr_eff_tertiary_rank_group0[0] = 255; - my_attr_eff_tertiary_rank_group0[1] = 255; - rc = FAPI_ATTR_SET(ATTR_EFF_TERTIARY_RANK_GROUP0, &i_target_mba, my_attr_eff_tertiary_rank_group0); if(rc) return rc; - uint8_t my_attr_eff_tertiary_rank_group1[2]; - my_attr_eff_tertiary_rank_group1[0] = 255; - my_attr_eff_tertiary_rank_group1[1] = 255; - rc = FAPI_ATTR_SET(ATTR_EFF_TERTIARY_RANK_GROUP1, &i_target_mba, my_attr_eff_tertiary_rank_group1); if(rc) return rc; - uint8_t my_attr_eff_tertiary_rank_group2[2]; - my_attr_eff_tertiary_rank_group2[0] = 255; - my_attr_eff_tertiary_rank_group2[1] = 255; - rc = FAPI_ATTR_SET(ATTR_EFF_TERTIARY_RANK_GROUP2, &i_target_mba, my_attr_eff_tertiary_rank_group2); if(rc) return rc; - uint8_t my_attr_eff_tertiary_rank_group3[2]; - my_attr_eff_tertiary_rank_group3[0] = 255; - my_attr_eff_tertiary_rank_group3[1] = 255; - rc = FAPI_ATTR_SET(ATTR_EFF_TERTIARY_RANK_GROUP3, &i_target_mba, my_attr_eff_tertiary_rank_group3); if(rc) return rc; - uint32_t my_attr_eff_zqcal_interval = 0; - rc = FAPI_ATTR_SET(ATTR_EFF_ZQCAL_INTERVAL, &i_target_mba, my_attr_eff_zqcal_interval); if(rc) return rc; - FAPI_INF("%s COMPLETE", PROCEDURE_NAME); - return rc; -} - -} // extern "C" diff --git a/src/usr/hwpf/hwp/mc_init/mss_eff_config/mss_eff_config_termination.C b/src/usr/hwpf/hwp/mc_init/mss_eff_config/mss_eff_config_termination.C new file mode 100644 index 000000000..1204b0205 --- /dev/null +++ b/src/usr/hwpf/hwp/mc_init/mss_eff_config/mss_eff_config_termination.C @@ -0,0 +1,192 @@ +// IBM_PROLOG_BEGIN_TAG +// This is an automatically generated prolog. +// +// $Source: src/usr/hwpf/hwp/mc_init/mss_eff_config/mss_eff_config_termination.C $ +// +// IBM CONFIDENTIAL +// +// COPYRIGHT International Business Machines Corp. 2012 +// +// p1 +// +// Object Code Only (OCO) source materials +// Licensed Internal Code Source Materials +// IBM HostBoot Licensed Internal Code +// +// The source code for this program is not published or other- +// wise divested of its trade secrets, irrespective of what has +// been deposited with the U.S. Copyright Office. +// +// Origin: 30 +// +// IBM_PROLOG_END +// $Id: mss_eff_config_termination.C,v 1.1 2012/04/30 16:42:50 asaetow Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config_termination.C,v $ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! TITLE : mss_eff_config_termination +// *! DESCRIPTION : see additional comments below +// *! OWNER NAME : Anuwat Saetow Email: asaetow@us.ibm.com +// *! BACKUP NAME : Mark Bellows Email: bellows@us.ibm.com +// *! ADDITIONAL COMMENTS : +// +// This procedure is a place holder for attributes set by the machine parsable workbook. +// +//------------------------------------------------------------------------------ +// Don't forget to create CVS comments when you check in your changes! +//------------------------------------------------------------------------------ +// CHANGE HISTORY: +//------------------------------------------------------------------------------ +// Version:| Author: | Date: | Comment: +//---------|----------|---------|----------------------------------------------- +// 1.2 | | | +// 1.1 | asaetow |30-APR-12| First Draft. + + + +//---------------------------------------------------------------------- +// My Includes +//---------------------------------------------------------------------- + + + +//---------------------------------------------------------------------- +// Includes +//---------------------------------------------------------------------- +#include <fapi.H> + + + +//---------------------------------------------------------------------- +// ENUMs +//---------------------------------------------------------------------- + + + +extern "C" { + + + +//****************************************************************************** +//* name=mss_eff_config_termination, param=i_target_mba, return=ReturnCode +//****************************************************************************** +fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba) { + fapi::ReturnCode rc = fapi::FAPI_RC_SUCCESS; + const char * const PROCEDURE_NAME = "mss_eff_config_termination"; + FAPI_INF("*** Running %s on %s ... ***", PROCEDURE_NAME, i_target_mba.toEcmdString()); + + // Define attribute array size + const uint8_t PORT_SIZE = 2; + const uint8_t DIMM_SIZE = 2; + const uint8_t RANK_SIZE = 4; + + // Define local attribute variables + uint8_t my_attr_eff_cen_drv_imp_cmd = 15; + uint8_t my_attr_eff_cen_drv_imp_cntl = 15; + uint8_t my_attr_eff_cen_drv_imp_dq_dqs = 24; + uint8_t my_attr_eff_cen_rcv_imp_dq_dqs = 15; + uint32_t my_attr_eff_cen_rd_vref = 50000; + uint8_t my_attr_eff_cen_slew_rate_cmd = 0x0; + uint8_t my_attr_eff_cen_slew_rate_cntl = 0x0; + uint8_t my_attr_eff_cen_slew_rate_dq_dqs = 0x0; + uint8_t my_attr_eff_dram_ron[PORT_SIZE][DIMM_SIZE]; + my_attr_eff_dram_ron[0][0] = 34; + my_attr_eff_dram_ron[0][1] = 34; + my_attr_eff_dram_ron[1][0] = 34; + my_attr_eff_dram_ron[1][1] = 34; + uint8_t my_attr_eff_dram_rtt_nom[PORT_SIZE][DIMM_SIZE][RANK_SIZE]; + my_attr_eff_dram_rtt_nom[0][0][0] = 20; + my_attr_eff_dram_rtt_nom[0][0][1] = 0; + my_attr_eff_dram_rtt_nom[0][0][2] = 0; + my_attr_eff_dram_rtt_nom[0][0][3] = 0; + my_attr_eff_dram_rtt_nom[0][1][0] = 20; + my_attr_eff_dram_rtt_nom[0][1][1] = 0; + my_attr_eff_dram_rtt_nom[0][1][2] = 0; + my_attr_eff_dram_rtt_nom[0][1][3] = 0; + my_attr_eff_dram_rtt_nom[1][0][0] = 20; + my_attr_eff_dram_rtt_nom[1][0][1] = 0; + my_attr_eff_dram_rtt_nom[1][0][2] = 0; + my_attr_eff_dram_rtt_nom[1][0][3] = 0; + my_attr_eff_dram_rtt_nom[1][1][0] = 20; + my_attr_eff_dram_rtt_nom[1][1][1] = 0; + my_attr_eff_dram_rtt_nom[1][1][2] = 0; + my_attr_eff_dram_rtt_nom[1][1][3] = 0; + uint8_t my_attr_eff_dram_rtt_wr[PORT_SIZE][DIMM_SIZE][RANK_SIZE]; + my_attr_eff_dram_rtt_wr[0][0][0] = 60; + my_attr_eff_dram_rtt_wr[0][0][1] = 60; + my_attr_eff_dram_rtt_wr[0][0][2] = 0; + my_attr_eff_dram_rtt_wr[0][0][3] = 0; + my_attr_eff_dram_rtt_wr[0][1][0] = 60; + my_attr_eff_dram_rtt_wr[0][1][1] = 60; + my_attr_eff_dram_rtt_wr[0][1][2] = 0; + my_attr_eff_dram_rtt_wr[0][1][3] = 0; + my_attr_eff_dram_rtt_wr[1][0][0] = 60; + my_attr_eff_dram_rtt_wr[1][0][1] = 60; + my_attr_eff_dram_rtt_wr[1][0][2] = 0; + my_attr_eff_dram_rtt_wr[1][0][3] = 0; + my_attr_eff_dram_rtt_wr[1][1][0] = 60; + my_attr_eff_dram_rtt_wr[1][1][1] = 60; + my_attr_eff_dram_rtt_wr[1][1][2] = 0; + my_attr_eff_dram_rtt_wr[1][1][3] = 0; + uint32_t my_attr_eff_dram_wr_vref = 500; + uint8_t my_attr_eff_odt_rd[PORT_SIZE][DIMM_SIZE][RANK_SIZE]; + my_attr_eff_odt_rd[0][0][0] = 0x0; + my_attr_eff_odt_rd[0][0][1] = 0x0; + my_attr_eff_odt_rd[0][0][2] = 0x0; + my_attr_eff_odt_rd[0][0][3] = 0x0; + my_attr_eff_odt_rd[0][1][0] = 0x0; + my_attr_eff_odt_rd[0][1][1] = 0x0; + my_attr_eff_odt_rd[0][1][2] = 0x0; + my_attr_eff_odt_rd[0][1][3] = 0x0; + my_attr_eff_odt_rd[1][0][0] = 0x0; + my_attr_eff_odt_rd[1][0][1] = 0x0; + my_attr_eff_odt_rd[1][0][2] = 0x0; + my_attr_eff_odt_rd[1][0][3] = 0x0; + my_attr_eff_odt_rd[1][1][0] = 0x0; + my_attr_eff_odt_rd[1][1][1] = 0x0; + my_attr_eff_odt_rd[1][1][2] = 0x0; + my_attr_eff_odt_rd[1][1][3] = 0x0; + uint8_t my_attr_eff_odt_wr[PORT_SIZE][DIMM_SIZE][RANK_SIZE]; + my_attr_eff_odt_wr[0][0][0] = 0x0; + my_attr_eff_odt_wr[0][0][1] = 0x0; + my_attr_eff_odt_wr[0][0][2] = 0x0; + my_attr_eff_odt_wr[0][0][3] = 0x0; + my_attr_eff_odt_wr[0][1][0] = 0x0; + my_attr_eff_odt_wr[0][1][1] = 0x0; + my_attr_eff_odt_wr[0][1][2] = 0x0; + my_attr_eff_odt_wr[0][1][3] = 0x0; + my_attr_eff_odt_wr[1][0][0] = 0x0; + my_attr_eff_odt_wr[1][0][1] = 0x0; + my_attr_eff_odt_wr[1][0][2] = 0x0; + my_attr_eff_odt_wr[1][0][3] = 0x0; + my_attr_eff_odt_wr[1][1][0] = 0x0; + my_attr_eff_odt_wr[1][1][1] = 0x0; + my_attr_eff_odt_wr[1][1][2] = 0x0; + my_attr_eff_odt_wr[1][1][3] = 0x0; + + // Set attributes + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_CMD, &i_target_mba, my_attr_eff_cen_drv_imp_cmd); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_CNTL, &i_target_mba, my_attr_eff_cen_drv_imp_cntl); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS, &i_target_mba, my_attr_eff_cen_drv_imp_dq_dqs); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RCV_IMP_DQ_DQS, &i_target_mba, my_attr_eff_cen_rcv_imp_dq_dqs); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RD_VREF, &i_target_mba, my_attr_eff_cen_rd_vref); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_CMD, &i_target_mba, my_attr_eff_cen_slew_rate_cmd); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_CNTL, &i_target_mba, my_attr_eff_cen_slew_rate_cntl); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS, &i_target_mba, my_attr_eff_cen_slew_rate_dq_dqs); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_RON, &i_target_mba, my_attr_eff_dram_ron); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_RTT_NOM, &i_target_mba, my_attr_eff_dram_rtt_nom); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_RTT_WR, &i_target_mba, my_attr_eff_dram_rtt_wr); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_WR_VREF, &i_target_mba, my_attr_eff_dram_wr_vref); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_ODT_RD, &i_target_mba, my_attr_eff_odt_rd); if(rc) return rc; + rc = FAPI_ATTR_SET(ATTR_EFF_ODT_WR, &i_target_mba, my_attr_eff_odt_wr); if(rc) return rc; + + FAPI_INF("%s on %s COMPLETE", PROCEDURE_NAME, i_target_mba.toEcmdString()); + return rc; +} + + + +} // extern "C" diff --git a/src/usr/hwpf/hwp/mc_init/mss_eff_config/mss_eff_config_termination.H b/src/usr/hwpf/hwp/mc_init/mss_eff_config/mss_eff_config_termination.H new file mode 100644 index 000000000..bf23c5bfd --- /dev/null +++ b/src/usr/hwpf/hwp/mc_init/mss_eff_config/mss_eff_config_termination.H @@ -0,0 +1,74 @@ +// IBM_PROLOG_BEGIN_TAG +// This is an automatically generated prolog. +// +// $Source: src/usr/hwpf/hwp/mc_init/mss_eff_config/mss_eff_config_termination.H $ +// +// IBM CONFIDENTIAL +// +// COPYRIGHT International Business Machines Corp. 2012 +// +// p1 +// +// Object Code Only (OCO) source materials +// Licensed Internal Code Source Materials +// IBM HostBoot Licensed Internal Code +// +// The source code for this program is not published or other- +// wise divested of its trade secrets, irrespective of what has +// been deposited with the U.S. Copyright Office. +// +// Origin: 30 +// +// IBM_PROLOG_END +// $Id: mss_eff_config_termination.H,v 1.1 2012/04/26 00:08:52 asaetow Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config_termination.H,v $ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! TITLE : mss_eff_config_termination.H +// *! DESCRIPTION : Header file for mss_eff_config_termination. +// *! OWNER NAME : Anuwat Saetow Email: asaetow@us.ibm.com +// *! BACKUP NAME : Mark Bellows Email: bellows@us.ibm.com +// *! ADDITIONAL COMMENTS : +// +// +// +//------------------------------------------------------------------------------ +// Don't forget to create CVS comments when you check in your changes! +//------------------------------------------------------------------------------ +// CHANGE HISTORY: +//------------------------------------------------------------------------------ +// Version:| Author: | Date: | Comment: +//---------|----------|---------|----------------------------------------------- +// 1.2 | | | +// 1.1 | asaetow |25-APR-12| First Draft. + + +#ifndef MSS_EFF_CONFIG_TERMINATION_H_ +#define MSS_EFF_CONFIG_TERMINATION_H_ + +//---------------------------------------------------------------------- +// My Includes +//---------------------------------------------------------------------- + + +//---------------------------------------------------------------------- +// Includes +//---------------------------------------------------------------------- +#include <fapi.H> + + +typedef fapi::ReturnCode (*mss_eff_config_termination_FP_t)(const fapi::Target i_target_mba); + +extern "C" { + +//****************************************************************************** +//* name=mss_eff_config_termination, param=i_target_mba, return=ReturnCode +//****************************************************************************** +fapi::ReturnCode mss_eff_config_termination(const fapi::Target i_target_mba); + +} // extern "C" + +#endif // MSS_EFF_CONFIG_TERMINATION_H_ diff --git a/src/usr/hwpf/hwp/mc_init/mss_eff_config/mss_eff_config_thermal.C b/src/usr/hwpf/hwp/mc_init/mss_eff_config/mss_eff_config_thermal.C new file mode 100644 index 000000000..650a77ab8 --- /dev/null +++ b/src/usr/hwpf/hwp/mc_init/mss_eff_config/mss_eff_config_thermal.C @@ -0,0 +1,314 @@ +// IBM_PROLOG_BEGIN_TAG +// This is an automatically generated prolog. +// +// $Source: src/usr/hwpf/hwp/mc_init/mss_eff_config/mss_eff_config_thermal.C $ +// +// IBM CONFIDENTIAL +// +// COPYRIGHT International Business Machines Corp. 2012 +// +// p1 +// +// Object Code Only (OCO) source materials +// Licensed Internal Code Source Materials +// IBM HostBoot Licensed Internal Code +// +// The source code for this program is not published or other- +// wise divested of its trade secrets, irrespective of what has +// been deposited with the U.S. Copyright Office. +// +// Origin: 30 +// +// IBM_PROLOG_END +// $Id: mss_eff_config_thermal.C,v 1.7 2012/05/04 15:53:44 pardeik Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config_thermal.C,v $ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! TITLE : mss_eff_config_thermal +// *! DESCRIPTION : see additional comments below +// *! OWNER NAME : Joab Henderson Email: joabhend@us.ibm.com +// *! BACKUP NAME : Michael Pardeik Email: pardeik@us.ibm.com +// *! ADDITIONAL COMMENTS : +// +// DESCRIPTION: +// The purpose of this procedure is to set the default throttle and power attributes for dimms in a given system +// -- The throttles here are intended to be the thermal runtime throttles for dimm/channel N/M +// -- The power attributes are the slope/intercept values. Note that these values are in cW. +// -- The values are determined by system based on power/thermal characterization +// -- Thermal values are system dependent and will need to come from the machine readable workbook +// -- Power values are going to be based on measurements and uplifted as needed based on voltage, frequency, termination, etc. +// +// TODO: +// 1. Thermal attributes (IPL and Runtime Throttles) need to come from machine readable workbook +// 2. Uplifts need to be done based on volt, freq, termination, etc. +// 3. Power values need to be updated/added for the dimms that will be supported +// +//------------------------------------------------------------------------------ +// Don't forget to create CVS comments when you check in your changes! +//------------------------------------------------------------------------------ +// CHANGE HISTORY: +//------------------------------------------------------------------------------ +// Version:| Author: | Date: | Comment: +//---------|----------|---------|----------------------------------------------- +// 1.7 | pardeik |04-MAY-12| removed typedef from structures, use fapi to define dimm type enums +// 1.6 | pardeik |10-APR-12| update cdimm power/int default, change power_thermal_values_t to use int32_t instead of uint32_t in order to identify a negative value correctly, added dimm config to the messages printed out +// 1.5 | pardeik |03-APR-12| fix cdimm size/rank addition to cycle through both mba's +// 1.4 | pardeik |26-MAR-12| Rewrite to iterate through the MBA's using fapi functions +// | pardeik |01-DEC-11| Updated to align with procedure definition +// 1.3 | asaetow |03-NOV-11| Fixed to comply with mss_eff_config_thermal.H +// 1.2 | asaetow |03-NOV-11| Changed format of file and made function lower case. +// 1.1 | pardeik |01-NOV-11| First Draft. + + +//---------------------------------------------------------------------- +// Includes +//---------------------------------------------------------------------- +#include <fapi.H> +#include <mss_eff_config_thermal.H> + +extern "C" { + + using namespace fapi; + +// Procedures in this file + fapi::ReturnCode mss_eff_config_thermal(const fapi::Target & i_target); + +//****************************************************************************** +// +//****************************************************************************** + + fapi::ReturnCode mss_eff_config_thermal(const fapi::Target & i_target) + { + + fapi::ReturnCode l_rc; + + char procedure_name[32]; + sprintf(procedure_name, "mss_eff_config_thermal"); + FAPI_INF("*** Running %s ***", procedure_name); + + enum + { + CDIMM = fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM, + RDIMM = fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM, + UDIMM = fapi::ENUM_ATTR_EFF_DIMM_TYPE_UDIMM, + LRDIMM = fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM, + }; + +// number of dimms on channel/port + enum + { + SINGLEDROP = 0, + DOUBLEDROP = 1, + DIMM_CONFIG_TYPES = 2, // count of all possible various dimm configurations on port + }; + +// Structure type for the table that holds dimm power slope and intercept values +// use int32_t for slope and intercept in case values are entered wrong (ie. negative values will then be flagged) + struct power_thermal_values_t + { + int32_t power_slope; + int32_t power_int; + }; + struct power_thermal_data_t + { + uint32_t dimm_type; + uint32_t dimm_size; + uint8_t dimm_ranks; + power_thermal_values_t data[DIMM_CONFIG_TYPES]; + }; +// Default values defined here + const uint8_t l_num_ports = 2; // number of ports per MBA + const uint8_t l_num_dimms = 2; // number of dimms per MBA port + const uint32_t l_dimm_power_slope_default = 800; // default power slope for rdimm, udimm, lrdimm + const uint32_t l_dimm_power_int_default = 900; // default power intercept for rdimm, udimm, lrdimm + const uint32_t l_cdimm_power_slope_default = 2000; // default power slope for cdimm + const uint32_t l_cdimm_power_int_default = 700; // default power intercept for cdimm + const uint32_t l_dimm_throttle_n_default = 100; // default dimm throttle numerator + const uint32_t l_dimm_throttle_d_default = 100; // default dimm throttle denominator + const uint32_t l_channel_throttle_n_default = 100; // default channel throttle numerator + const uint32_t l_channel_throttle_d_default = 100; // default channel throttle denominator +// other variables used in this procedure + uint8_t port; + uint8_t dimm; + uint8_t entry; + uint8_t l_dimm_type; + uint8_t l_dimm_size_array[l_num_ports][l_num_dimms]; + uint8_t l_dimm_ranks_array[l_num_ports][l_num_dimms]; + uint32_t l_half_cdimm_size = 0; + uint8_t l_half_cdimm_ranks = 0; + uint32_t l_list_sz; + uint32_t l_power_slope_array[l_num_ports][l_num_dimms]; + uint32_t l_power_int_array[l_num_ports][l_num_dimms]; + uint32_t l_power_int_uplift; + uint32_t l_dimm_throttle_n_array[l_num_ports][l_num_dimms]; + uint32_t l_dimm_throttle_d_array[l_num_ports][l_num_dimms]; + uint32_t l_channel_throttle_n_array[l_num_ports]; + uint32_t l_channel_throttle_d_array[l_num_ports]; + uint8_t l_found_entry_in_table; + uint8_t l_dimm_config[l_num_ports]; + +// This sets up the power curve values for the DIMMs +// NOTE: If a value of zero is in the slope or intercept fields, then the default settings will be used +// NOTE: Power Slope and Intercept values are in cW +// NOTE: For CDIMM, the power values need to be based on the dimm within the CDIMM (not based on power for whole CDIMM) +// DIMM, Size, Ranks, Double drop config power slope and intercept, Single drop config power slope and intercept + + power_thermal_data_t l_power_thermal_values[]= + { +// SINGLE DOUBLE +// DROP DROP +// Type, Size, Ranks, slope,int, slope,int +// RDIMMs - data from P7 based ISDIMMs (1066MHz and 1.35V) + { RDIMM, 2, 1, {{ 522, 154}, { 526, 153}}}, // example RDIMM 2GB 1Rx8 2Gb + { RDIMM, 4, 2, {{ 472, 187}, { 512, 182}}}, // example RDIMM 4GB 2Rx8 2Gb + { RDIMM, 4, 1, {{ 472, 187}, { 512, 182}}}, // example RDIMM 4GB 1Rx8 4Gb + { RDIMM, 8, 4, {{ 654, 274}, { 657, 262}}}, // example RDIMM 8GB 4Rx8 2Gb + { RDIMM, 8, 2, {{ 654, 274}, { 657, 262}}}, // example RDIMM 8GB 2Rx4 2Gb OR 8GB 2Rx8 4Gb + { RDIMM, 16, 4, {{ 770, 458}, { 738, 479}}}, // example RDIMM 16GB 4Rx4 2Gb + { RDIMM, 16, 2, {{ 770, 458}, { 738, 479}}}, // example RDIMM 16GB 2Rx4 4Gb + { RDIMM, 32, 4, {{ 770, 458}, { 738, 479}}}, // example RDIMM 32GB 4Rx4 4Gb +// CDIMMs - projections based on Warren's dimm support table + 3% spread + 10% uplift +// power values here are HALF of the cdimm power (since we handle one mba at a time) - need to divide this up and give each dimm an equal power amount +// SingleDrop DoubleDrop +// TYPE Size/X, Ranks/X, Slope,Int, Slope, Int +// where X=number of MBA port pairs populated on CDIMM + { CDIMM, 16/2, 4/2, {{ 957, 153}, { 957, 153}}}, // example short CDIMM 16GB 4Rx8 4Gb OR 8GB 2Rx8 4Gb (Channel A/B populated) + { CDIMM, 32/2, 8/2, {{1130, 254}, {1130, 254}}}, // example short CDIMM 32GB 4Rx8 4Gb + { CDIMM, 64/2, 8/2, {{1763, 469}, {1763, 469}}}, // example short CDIMM 64GB 4Rx4 4Gb + { CDIMM, 128/2, 8/2, {{1763, 599}, {1763, 599}}}, // example tall CDIMM 128GB 4Rx4 4Gb (2H 3DS) +// UDIMMs +// LRDIMMs + }; + l_list_sz = (sizeof(l_power_thermal_values))/(sizeof(power_thermal_data_t)); + +// Get input attributes + l_rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target, l_dimm_type); + if(l_rc) return l_rc; + l_rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_SIZE, &i_target, l_dimm_size_array); + if(l_rc) return l_rc; + l_rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target, l_dimm_ranks_array); + if(l_rc) return l_rc; + +// Add up DIMM Size and Ranks if a CDIMM - this will be for half of the cdimm - and dimm config for each mba port (1 or 2 dimms per channel) + for (port=0; port < l_num_ports; port++) + { + l_dimm_config[port] = 0; + for (dimm=0; dimm < l_num_dimms; dimm++) + { + if ((l_dimm_type == CDIMM) && (l_dimm_ranks_array[port][dimm] > 0)) + { + l_half_cdimm_size = l_half_cdimm_size + l_dimm_size_array[port][dimm]; + l_half_cdimm_ranks = l_half_cdimm_ranks + l_dimm_ranks_array[port][dimm]; + } + if (l_dimm_ranks_array[port][dimm] > 0) + { + l_dimm_config[port]++; + } + } + if (l_dimm_config[port] == 1) + { + l_dimm_config[port] = SINGLEDROP; + } + else if (l_dimm_config[port] == 2) + { + l_dimm_config[port] = DOUBLEDROP; + } + else + { + l_dimm_config[port] = DIMM_CONFIG_TYPES; + } + } + + +// iterate through the MBA ports to define power and thermal attributes + for (port=0; port < l_num_ports; port++) + { +// initialize entries to zero + l_channel_throttle_n_array[port] = 0; + l_channel_throttle_d_array[port] = 0; + for (dimm=0; dimm < l_num_dimms; dimm++) + { +// initialize entries to zero + l_dimm_throttle_n_array[port][dimm] = 0; + l_dimm_throttle_d_array[port][dimm] = 0; + l_power_slope_array[port][dimm] = 0; + l_power_int_array[port][dimm] = 0; +// only update values for dimms that are physically present (with default value or table entry value) + if (l_dimm_ranks_array[port][dimm] > 0) + { +// TODO: Placeholder for thermal attributes from machine readable workbook (runtime throttles) - Hardcode these for now. IPL throttles will need to be added into an initfile once available. +// Can remove this section once infrastructure is in place to get these from the MRW (probably done in a different firmware procedure) + l_dimm_throttle_n_array[port][dimm] = l_dimm_throttle_n_default; + l_dimm_throttle_d_array[port][dimm] = l_dimm_throttle_d_default; + l_channel_throttle_n_array[port] = l_channel_throttle_n_default; + l_channel_throttle_d_array[port] = l_channel_throttle_d_default; +// Look up DIMM in Table, get size and ranks first, set slope/int to default values first in case entry is not found in table +// If table entry is less than zero, then set value to default values + if (l_dimm_type == CDIMM) + { + l_dimm_size_array[port][dimm] = l_half_cdimm_size; + l_dimm_ranks_array[port][dimm] = l_half_cdimm_ranks; + l_power_slope_array[port][dimm] = l_cdimm_power_slope_default; + l_power_int_array[port][dimm] = l_cdimm_power_int_default; + } + else + { + l_power_slope_array[port][dimm] = l_dimm_power_slope_default; + l_power_int_array[port][dimm] = l_dimm_power_int_default; + } + l_found_entry_in_table = 0; + for (entry = 0; entry < l_list_sz; entry++) { + if ((l_power_thermal_values[entry].dimm_type == l_dimm_type) && (l_power_thermal_values[entry].dimm_size == l_dimm_size_array[port][dimm]) && (l_power_thermal_values[entry].dimm_ranks == l_dimm_ranks_array[port][dimm])) + { + if ((l_power_thermal_values[entry].data[l_dimm_config[port]].power_slope > 0) && (l_power_thermal_values[entry].data[l_dimm_config[port]].power_int > 0)) + { + l_power_slope_array[port][dimm]=l_power_thermal_values[entry].data[l_dimm_config[port]].power_slope; + l_power_int_array[port][dimm]=l_power_thermal_values[entry].data[l_dimm_config[port]].power_int; + FAPI_INF("Found DIMM Entry in Power Table [%d:%d:%d:%d:%d:%d][%d:%d]", port, dimm, l_dimm_type, l_dimm_size_array[port][dimm], l_dimm_ranks_array[port][dimm], l_dimm_config[port], l_power_slope_array[port][dimm], l_power_int_array[port][dimm]); + } + else + { + FAPI_ERR( "DIMM Entry in Power Table not greater than zero, so default values will be used [%d:%d:%d:%d:%d:%d][%d:%d]", port, dimm, l_dimm_type, l_dimm_size_array[port][dimm], l_dimm_ranks_array[port][dimm], l_dimm_config[port], l_power_slope_array[port][dimm], l_power_int_array[port][dimm]); + } +// break out since first match was found + l_found_entry_in_table = 1; + break; + } + } +// Apply any uplifts to the Slope or intercept values based on various parameters if entry is found in table +// TODO: What uplifts do we need to do (Frequency, Voltage, Termination, etc) - Use zero uplift for now. + if (l_found_entry_in_table == 1) + { + l_power_int_uplift = 0; + l_power_int_array[port][dimm] = l_power_int_array[port][dimm] + l_power_int_uplift; + } +// post error if entry was not found + else + { + FAPI_ERR( "Failed to Find DIMM Entry in Power Table, so default values will be used [%d:%d:%d:%d:%d:%d][%d:%d]", port, dimm, l_dimm_type, l_dimm_size_array[port][dimm], l_dimm_ranks_array[port][dimm], l_dimm_config[port], l_power_slope_array[port][dimm], l_power_int_array[port][dimm] ); + } + } + } + } +// write output attributes + l_rc = FAPI_ATTR_SET(ATTR_MSS_POWER_SLOPE, &i_target, l_power_slope_array); + if(l_rc) return l_rc; + l_rc = FAPI_ATTR_SET(ATTR_MSS_POWER_INT, &i_target, l_power_int_array); + if(l_rc) return l_rc; + l_rc = FAPI_ATTR_SET(ATTR_MSS_THROTTLE_NUMERATOR, &i_target, l_dimm_throttle_n_array); + if(l_rc) return l_rc; + l_rc = FAPI_ATTR_SET(ATTR_MSS_THROTTLE_DENOMINATOR, &i_target, l_dimm_throttle_d_array); + if(l_rc) return l_rc; + l_rc = FAPI_ATTR_SET(ATTR_MSS_THROTTLE_CHANNEL_NUMERATOR, &i_target, l_channel_throttle_n_array); + if(l_rc) return l_rc; + l_rc = FAPI_ATTR_SET(ATTR_MSS_THROTTLE_CHANNEL_DENOMINATOR, &i_target, l_channel_throttle_d_array); + if(l_rc) return l_rc; + + FAPI_INF("*** %s COMPLETE ***", procedure_name); + return l_rc; + } + +} //end extern C diff --git a/src/usr/hwpf/hwp/mc_init/mss_eff_config/mss_eff_config_thermal.H b/src/usr/hwpf/hwp/mc_init/mss_eff_config/mss_eff_config_thermal.H new file mode 100644 index 000000000..d52e8b754 --- /dev/null +++ b/src/usr/hwpf/hwp/mc_init/mss_eff_config/mss_eff_config_thermal.H @@ -0,0 +1,77 @@ +// IBM_PROLOG_BEGIN_TAG +// This is an automatically generated prolog. +// +// $Source: src/usr/hwpf/hwp/mc_init/mss_eff_config/mss_eff_config_thermal.H $ +// +// IBM CONFIDENTIAL +// +// COPYRIGHT International Business Machines Corp. 2012 +// +// p1 +// +// Object Code Only (OCO) source materials +// Licensed Internal Code Source Materials +// IBM HostBoot Licensed Internal Code +// +// The source code for this program is not published or other- +// wise divested of its trade secrets, irrespective of what has +// been deposited with the U.S. Copyright Office. +// +// Origin: 30 +// +// IBM_PROLOG_END +// $Id: mss_eff_config_thermal.H,v 1.3 2012/04/03 22:13:03 pardeik Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config_thermal.H,v $ +//------------------------------------------------------------------------------ +// *! (C) Copyright International Business Machines Corp. 2011 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//------------------------------------------------------------------------------ +// *! TITLE : mss_eff_config_thermal.H +// *! DESCRIPTION : see additional comments below +// *! OWNER NAME : Joab Henderson Email: joabhend@us.ibm.com +// *! BACKUP NAME : Michael Pardeik Email: pardeik@us.ibm.com +// *! ADDITIONAL COMMENTS : +// +// Header file for mss_eff_config_thermal. +// +//------------------------------------------------------------------------------ +// Don't forget to create CVS comments when you check in your changes! +//------------------------------------------------------------------------------ +// CHANGE HISTORY: +//------------------------------------------------------------------------------ +// Version:| Author: | Date: | Comment: +//---------|----------|---------|----------------------------------------------- +// 1.3 | pardeik |03-APR-12| use mba target instead of mbs +// 1.2 | pardeik |26-MAR-12| Removed structure (going into .C file) +// | pardeik |01-DEC-11| Added structures and defines +// 1.1 | asaetow |03-NOV-11| First Draft. + + + +#ifndef MSS_EFF_CONFIG_THERMAL_H_ +#define MSS_EFF_CONFIG_THERMAL_H_ + +//---------------------------------------------------------------------- +// Includes +//---------------------------------------------------------------------- +#include <fapi.H> + + +typedef fapi::ReturnCode (*mss_eff_config_thermal_FP_t)(const fapi::Target & i_target); + + +extern "C" { +/** + * @brief mss_eff_config_thermal procedure. Sets up dimm power curve attributes and dimm and channel throttle attributes + * + * @param[in] i_target Reference to centaur mba target + * + * @return ReturnCode + */ + + fapi::ReturnCode mss_eff_config_thermal(const fapi::Target & i_target); + +} //extern C + +#endif // MSS_EFF_CONFIG_THERMAL_H_ diff --git a/src/usr/hwpf/hwp/sbe_centaur_init/sbe_centaur_init.C b/src/usr/hwpf/hwp/sbe_centaur_init/sbe_centaur_init.C index 4530cb9c5..dfe64e1ed 100644 --- a/src/usr/hwpf/hwp/sbe_centaur_init/sbe_centaur_init.C +++ b/src/usr/hwpf/hwp/sbe_centaur_init/sbe_centaur_init.C @@ -42,6 +42,7 @@ #include <errl/errlentry.H> #include <initservice/isteps_trace.H> #include <targeting/common/commontargeting.H> +#include <targeting/common/utilFilter.H> #include <fapi.H> #include <fapiPoreVeArg.H> #include <fapiTarget.H> @@ -82,20 +83,8 @@ void call_cen_sbe_tp_chiplet_init1( void *io_pArgs ) TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_cen_sbe_tp_chiplet_init1 entry" ); // Get target list to pass in procedure - - // Use PredicateIsFunctional to filter only functional chips - TARGETING::PredicateIsFunctional l_isFunctional; - // filter for functional Centaur Chips - TARGETING::PredicateCTM l_membufChipFilter(CLASS_CHIP, TYPE_MEMBUF); - // declare a postfix expression widget - TARGETING::PredicatePostfixExpr l_functionalAndMembufChipFilter; - // is-a-membuf-chip is-functional AND - l_functionalAndMembufChipFilter.push(&l_membufChipFilter).push(&l_isFunctional).And(); - // loop through all the targets, applying the filter, and put the results in l_pMemBufs - TARGETING::TargetRangeFilter l_pMemBufs( - TARGETING::targetService().begin(), - TARGETING::targetService().end(), - &l_functionalAndMembufChipFilter ); + TARGETING::TargetHandleList l_membufTargetList; + getAllChips(l_membufTargetList, TYPE_MEMBUF); bool l_unloadSbePnorImg = false; size_t l_sbePnorSize = 0; @@ -165,10 +154,10 @@ void call_cen_sbe_tp_chiplet_init1( void *io_pArgs ) myArgs.push_back(fapiArg); // Loop thru all Centaurs in list - for ( ; l_pMemBufs; ++l_pMemBufs ) + for ( size_t i = 0; i < l_membufTargetList.size(); i++ ) { // Create a FAPI Target - const TARGETING::Target* l_membuf_target = *l_pMemBufs; + const TARGETING::Target* l_membuf_target = l_membufTargetList[i]; const fapi::Target l_fapiTarget( fapi::TARGET_TYPE_MEMBUF_CHIP, reinterpret_cast<void *> @@ -214,7 +203,7 @@ void call_cen_sbe_tp_chiplet_init1( void *io_pArgs ) TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, "call_cen_sbe_tp_chiplet_init1 - VSBE engine runs successfully on this Centaur"); } - } // end for l_pMemBufs + } // end for // Freeing memory if (l_otherArg) diff --git a/src/usr/hwpf/hwp/start_clocks_on_nest_chiplets/start_clocks_on_nest_chiplets.C b/src/usr/hwpf/hwp/start_clocks_on_nest_chiplets/start_clocks_on_nest_chiplets.C index c178d0783..ecde868cc 100644 --- a/src/usr/hwpf/hwp/start_clocks_on_nest_chiplets/start_clocks_on_nest_chiplets.C +++ b/src/usr/hwpf/hwp/start_clocks_on_nest_chiplets/start_clocks_on_nest_chiplets.C @@ -46,6 +46,7 @@ // targeting support #include <targeting/common/commontargeting.H> +#include <targeting/common/utilFilter.H> // fapi support #include <fapi.H> @@ -144,23 +145,14 @@ void call_proc_startclock_chiplets( void *io_pArgs ) TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_proc_startclock_chiplets entry" ); - TARGETING::TargetService& l_targetService = targetService(); uint8_t l_cpuNum = 0; - // Use PredicateIsFunctional to filter only functional chips - TARGETING::PredicateIsFunctional l_isFunctional; - // filter for functional Proc Chips - TARGETING::PredicateCTM l_procChipFilter( CLASS_CHIP, TYPE_PROC ); - TARGETING::PredicatePostfixExpr l_functionalAndProcChipFilter; - l_functionalAndProcChipFilter.push(&l_procChipFilter).push(&l_isFunctional).And(); - TARGETING::TargetRangeFilter l_cpuFilter( - l_targetService.begin(), - l_targetService.end(), - &l_functionalAndProcChipFilter ); - - for ( l_cpuNum=0; l_cpuFilter; ++l_cpuFilter, l_cpuNum++ ) + TARGETING::TargetHandleList l_cpuTargetList; + getAllChips(l_cpuTargetList, TYPE_PROC); + + for ( l_cpuNum=0; l_cpuNum < l_cpuTargetList.size(); l_cpuNum++ ) { - const TARGETING::Target* l_cpu_target = *l_cpuFilter; + const TARGETING::Target* l_cpu_target = l_cpuTargetList[l_cpuNum]; const fapi::Target l_fapi_proc_target( TARGET_TYPE_PROC_CHIP, reinterpret_cast<void *> diff --git a/src/usr/targeting/common/common.mk b/src/usr/targeting/common/common.mk index 1d7bf231f..a6e32c169 100644 --- a/src/usr/targeting/common/common.mk +++ b/src/usr/targeting/common/common.mk @@ -48,7 +48,7 @@ TARGET_OBJS = \ entitypath.o OTHER_OBJS = \ - util.o + util.o utilFilter.o # Common COMMON_TARGETING_OBJS = \ diff --git a/src/usr/targeting/common/utilFilter.C b/src/usr/targeting/common/utilFilter.C new file mode 100644 index 000000000..02ee6079e --- /dev/null +++ b/src/usr/targeting/common/utilFilter.C @@ -0,0 +1,159 @@ +/* IBM_PROLOG_BEGIN_TAG + * This is an automatically generated prolog. + * + * $Source: src/usr/targeting/common/utilFilter.C $ + * + * IBM CONFIDENTIAL + * + * COPYRIGHT International Business Machines Corp. 2012 + * + * p1 + * + * Object Code Only (OCO) source materials + * Licensed Internal Code Source Materials + * IBM HostBoot Licensed Internal Code + * + * The source code for this program is not published or other- + * wise divested of its trade secrets, irrespective of what has + * been deposited with the U.S. Copyright Office. + * + * Origin: 30 + * + * IBM_PROLOG_END_TAG + */ +//****************************************************************************** +// Includes +//****************************************************************************** +#include <targeting/common/commontargeting.H> +#include <targeting/common/entitypath.H> +#include <attributeenums.H> +#include <targeting/common/iterators/rangefilter.H> +#include <targeting/common/predicates/predicateisfunctional.H> +#include <targeting/common/predicates/predicatepostfixexpr.H> + + +/** + * Miscellaneous Filter Utility Functions + */ + +namespace TARGETING +{ + +/** + * @brief Populate the o_vector with target object pointers based on the + * requested class, type, and functional state. + * + * @parm[out] o_vector, reference of vector of target pointers. + * @parm[in] i_class, the class of the targets to be obtained + * @parm[in] i_type, the type of the targets to be obtained + * @parm[in] i_functional, set to true to return only functional targets + * + * @return N/A + */ +void _getAllChipsOrChiplets( TARGETING::TargetHandleList & o_vector, + CLASS i_class, TYPE i_type, bool i_functional = true ) +{ + // Get all chip/chiplet targets + // Use PredicateIsFunctional to filter only functional chips/chiplets + TARGETING::PredicateIsFunctional l_isFunctional; + // filter for functional Chips/Chiplets + TARGETING::PredicateCTM l_Filter(i_class, i_type); + // declare a postfix expression widget + TARGETING::PredicatePostfixExpr l_goodFilter; + // is-a--chip is-functional AND + l_goodFilter.push(&l_Filter).push(&l_isFunctional).And(); + // apply the filter through all targets. + TARGETING::TargetRangeFilter l_filter( TARGETING::targetService().begin(), + TARGETING::targetService().end(), &l_goodFilter ); + if (!i_functional) + { + l_filter.setPredicate(&l_Filter); + } + + o_vector.clear(); + for ( ; l_filter; ++l_filter) + { + o_vector.push_back( *l_filter ); + } +} + + +void getAllChips( TARGETING::TargetHandleList & o_vector, + TYPE i_chipType, bool i_functional = true ) +{ + _getAllChipsOrChiplets(o_vector, CLASS_CHIP, i_chipType, i_functional); +} + + +void getAllChiplets( TARGETING::TargetHandleList & o_vector, + TYPE i_chipletType, bool i_functional = true ) +{ + _getAllChipsOrChiplets(o_vector, CLASS_UNIT, i_chipletType, i_functional); +} + + +void getChildChiplets( TARGETING::TargetHandleList& o_vector, + const Target * i_chip, TYPE i_type, bool i_functional ) +{ + // get the chiplets associated with this cpu + TARGETING::PredicateCTM l_chipletFilter(CLASS_UNIT, i_type); + + o_vector.clear(); + if (i_functional) + { + // Use PredicateIsFunctional to filter only functional chiplets + TARGETING::PredicateIsFunctional l_functional; + TARGETING::PredicatePostfixExpr l_functionalChiplets; + l_functionalChiplets.push(&l_chipletFilter).push(&l_functional).And(); + TARGETING::targetService().getAssociated( + o_vector, + i_chip, + TARGETING::TargetService::CHILD, + TARGETING::TargetService::ALL, + &l_functionalChiplets ); + } + else + { + TARGETING::targetService().getAssociated( + o_vector, + i_chip, + TARGETING::TargetService::CHILD, + TARGETING::TargetService::ALL, + &l_chipletFilter ); + } + +} + +void getAffinityChips( TARGETING::TargetHandleList& o_vector, + const Target * i_chiplet, TYPE i_type, bool i_functional ) +{ + // find all the chip that are affinity-associated with i_chiplet + TARGETING::PredicateCTM l_chipFilter(CLASS_CHIP, i_type); + + o_vector.clear(); + if (i_functional) + { + // Use PredicateIsFunctional to filter only functional chips + TARGETING::PredicateIsFunctional l_functional; + TARGETING::PredicatePostfixExpr l_functionalChips; + l_functionalChips.push(&l_chipFilter).push(&l_functional).And(); + TARGETING::targetService().getAssociated( + o_vector, + i_chiplet, + TARGETING::TargetService::CHILD_BY_AFFINITY, + TARGETING::TargetService::ALL, + &l_functionalChips ); + } + else + { + TARGETING::targetService().getAssociated( + o_vector, + i_chiplet, + TARGETING::TargetService::CHILD_BY_AFFINITY, + TARGETING::TargetService::ALL, + &l_chipFilter ); + } + +} + +}; |
