Remove old PROC_PCIE_LANE_EQUALIZATION attribute

Change-Id: I2a0d8831a797a227724089887525e8efe89122d1
RTC:160417
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32327
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Reviewed-by: Corey V. Swenson <cswenson@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

6 files changed, 1 insertions, 54 deletions

diff --git a/src/usr/devtree/bld_devtree.C b/src/usr/devtree/bld_devtree.C
index ee2b15505..ca4e2b60f 100644
--- a/src/usr/devtree/bld_devtree.C
+++ b/src/usr/devtree/bld_devtree.C
@@ -802,9 +802,6 @@ void bld_xscom_node(devTree * i_dt, dtOffset_t & i_parentNode,
     /*PCIE*/
     uint8_t l_phbActive =
         i_pProc->getAttr<TARGETING::ATTR_PROC_PCIE_PHB_ACTIVE>();
-    TARGETING::ATTR_PROC_PCIE_LANE_EQUALIZATION_type l_laneEq = {{0}};
-    assert(i_pProc->tryGetAttr<TARGETING::ATTR_PROC_PCIE_LANE_EQUALIZATION>(
-        l_laneEq));
 
     TRACFCOMP( g_trac_devtree, "Chip %X PHB Active mask %X",
                i_chipid, l_phbActive);
@@ -831,9 +828,6 @@ void bld_xscom_node(devTree * i_dt, dtOffset_t & i_parentNode,
         i_dt->addPropertyCells32(pcieNode, "reg", pcie_prop, 6);
         i_dt->addPropertyCell32(pcieNode, "ibm,phb-index", l_phb);
         i_dt->addProperty(pcieNode, "ibm,use-ab-detect");
-        i_dt->addPropertyCells32(pcieNode, "ibm,lane-eq",
-            reinterpret_cast<uint32_t*>(l_laneEq[l_phb]),
-            (sizeof(l_laneEq[l_phb])/sizeof(uint32_t)));
     }
 
     /*I2C Masters*/
diff --git a/src/usr/targeting/common/genHwsvMrwXml.pl b/src/usr/targeting/common/genHwsvMrwXml.pl
index 1e34f165e..901a32336 100755
--- a/src/usr/targeting/common/genHwsvMrwXml.pl
+++ b/src/usr/targeting/common/genHwsvMrwXml.pl
@@ -756,7 +756,7 @@ sub unhexify {
 
 # Determine values of proc pcie attributes
 # Currently
-#   PROC_PCIE_LANE_EQUALIZATION PROC_PCIE_IOP_CONFIG PROC_PCIE_PHB_ACTIVE
+#   PROC_PCIE_LANE_EQUALIZATION_GEN3/4 PROC_PCIE_IOP_CONFIG PROC_PCIE_PHB_ACTIVE
 sub pcie_init ($)
 {
     my $proc = $_[0];
diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml
index b2b1cf9d0..c9382e9bb 100644
--- a/src/usr/targeting/common/xmltohb/attribute_types.xml
+++ b/src/usr/targeting/common/xmltohb/attribute_types.xml
@@ -16828,38 +16828,6 @@ Measured in GB</description>
     <readable/>
 </attribute>
 
-<attribute><!-- Deprecated : @todo-Remove with RTC:160417 -->
-    <id>PROC_PCIE_LANE_EQUALIZATION</id>
-    <description>PCIE Lane Equalization values for each PHB
-        Creator: MRW
-        Purpose: Holds settings which are loaded into the HW to optimize the
-            PCIE lane signal eye between the chips + PCIE endpoints
-        Data Format: 4 PHBs x 32 bytes of EQ data per PHB.  Each PHB has an EQ
-            value for each of its 16 lanes.  Each value is a uint16 formatted as
-            follows:
-                Bit 0:3   - up_rx_hint (bit 0 reserved)
-                Bit 4:7   - up_tx_preset
-                Bit 8:11  - dn_rx_hint (bit 0 reserved)
-                Bit 12:15 - dn_tx_preset
-    </description>
-    <simpleType>
-        <uint8_t><default>0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,
-            0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,
-            0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,
-            0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x0,
-            0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x77,
-            0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,
-            0x77,0x77,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,
-            0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,
-            0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,
-            0x0,0x0</default>
-        </uint8_t>
-        <array>4,32</array>
-    </simpleType>
-    <persistency>non-volatile</persistency>
-    <readable/>
-</attribute>
-
 <attribute>
     <id>PROC_PCIE_IS_SLOT</id>
     <description>Indicates whether PCIE lanes terminate at a pluggable slot
diff --git a/src/usr/targeting/common/xmltohb/simics_NIMBUS.system.xml b/src/usr/targeting/common/xmltohb/simics_NIMBUS.system.xml
index dceb3d538..9a55d1955 100644
--- a/src/usr/targeting/common/xmltohb/simics_NIMBUS.system.xml
+++ b/src/usr/targeting/common/xmltohb/simics_NIMBUS.system.xml
@@ -5349,13 +5349,6 @@
     </attribute>
     <!-- End PHYP Memory Map -->
 
-    <!-- PROC_PCIE_ attributes -->
-    <attribute>
-        <id>PROC_PCIE_LANE_EQUALIZATION</id>
-        <default>0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x68,0x68,0x68,0x68,0x68,0x68,0x68,0x68,0x68,0x68,0x68,0x68,0x68,0x68,0x68,0x68,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
-        </default>
-    </attribute>
-    <!-- End PROC_PCIE_ attributes -->
     <!-- PM_ attributes -->
     <attribute>
         <id>PM_UNDERVOLTING_FRQ_MINIMUM</id>
diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml
index 3e4362112..c45d89791 100755
--- a/src/usr/targeting/common/xmltohb/target_types.xml
+++ b/src/usr/targeting/common/xmltohb/target_types.xml
@@ -269,7 +269,6 @@
             <field><id>reserved</id><value>0</value></field>
         </default>
     </attribute>
-    <attribute><id>PROC_PCIE_LANE_EQUALIZATION</id></attribute>
     <attribute><id>CDM_DOMAIN</id><default>FABRIC</default></attribute>
     <attribute><id>HOT_PLUG_POWER_CONTROLLER_INFO</id></attribute>
     <attribute><id>PROC_R_LOADLINE_VDD_UOHM</id></attribute>
diff --git a/src/usr/targeting/common/xmltohb/vbu_NIMBUS.system.xml b/src/usr/targeting/common/xmltohb/vbu_NIMBUS.system.xml
index f7cb3dc58..d81674c7b 100644
--- a/src/usr/targeting/common/xmltohb/vbu_NIMBUS.system.xml
+++ b/src/usr/targeting/common/xmltohb/vbu_NIMBUS.system.xml
@@ -5340,13 +5340,6 @@
     </attribute>
     <!-- End PHYP Memory Map -->
 
-    <!-- PROC_PCIE_ attributes -->
-    <attribute>
-        <id>PROC_PCIE_LANE_EQUALIZATION</id>
-        <default>0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x68,0x68,0x68,0x68,0x68,0x68,0x68,0x68,0x68,0x68,0x68,0x68,0x68,0x68,0x68,0x68,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x77,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
-        </default>
-    </attribute>
-    <!-- End PROC_PCIE_ attributes -->
     <!-- PM_ attributes -->
     <attribute>
         <id>PM_UNDERVOLTING_FRQ_MINIMUM</id>