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| author | Tsung Yeung <tyeung@us.ibm.com> | 2018-12-20 10:39:39 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2019-02-12 10:50:42 -0600 |
| commit | b2027cd8b704587be6ce4dd14327e6730f9d519b (patch) | |
| tree | bf1b0206440c5105e46db51bb1a837ac71290ce9 /src/usr/vpd/spdDDR4.H | |
| parent | 95bbfc78a463c06cd06204ee8cb1b904ec864565 (diff) | |
| download | talos-hostboot-b2027cd8b704587be6ce4dd14327e6730f9d519b.tar.gz talos-hostboot-b2027cd8b704587be6ce4dd14327e6730f9d519b.zip | |
Disable NVDIMM Trigger Before Draminit and Deassert DDR_RESETn During MPIPL
- Per the JEDEC spec, DDR_RESETn is masked from the DRAM when the NVDIMM
is armed. This could cause the training to fail if the trigger is not
disabled before training. Two scenarios where this can happen are warm
reboot and cold boot before the backup power module can deplete the
charge
- Deassert DDR_RESETn in MPIPL before triggering the restore.
- Fix the config flag to enable NVDIMM code
Change-Id: I9d25c2f653fc54d379f0dbab49218f5b59a407a0
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/70035
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/usr/vpd/spdDDR4.H')
| -rwxr-xr-x | src/usr/vpd/spdDDR4.H | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/usr/vpd/spdDDR4.H b/src/usr/vpd/spdDDR4.H index d263f9cd4..bf4d0dfc8 100755 --- a/src/usr/vpd/spdDDR4.H +++ b/src/usr/vpd/spdDDR4.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2013,2016 */ +/* Contributors Listed Below - COPYRIGHT 2013,2019 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -135,6 +135,7 @@ const KeywordData ddr4Data[] = { BASE_CONFIG_CRC, 0x7f, 0x02, 0x00, 0x00, true, false, NA }, { DRAM_STEPPING, 0x160, 0x01, 0x00, 0x00, false, false, NA }, { MANUFACTURING_SECTION_CRC, 0x17f, 0x02, 0x00, 0x00, true, false, NA }, + { NVM_INIT_TIME, 0xCB, 0x01, 0x00, 0x00, false, false, NA }, // Module Specific fields supported on both DDR3 and DDR4 { MODSPEC_COM_NOM_HEIGHT_MAX, 0x80, 0x01, 0x1f, 0x00, false, false, ALL }, { MODSPEC_COM_MAX_THICK_BACK, 0x81, 0x01, 0xf0, 0x04, false, false, ALL }, |
