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| author | aalugore <aalugore@us.ibm.com> | 2016-01-22 13:36:14 -0600 |
|---|---|---|
| committer | Stephen Cprek <smcprek@us.ibm.com> | 2016-04-21 13:51:43 -0500 |
| commit | 4f4f097d65e919bcc8bd5706f50ea0f413b8bfef (patch) | |
| tree | 90030301032f3a87e952e5c161763bab0ad812be /src/usr/vpd/spdDDR4.H | |
| parent | 18e7af4cee8e4a9b88dee257edffb528b969ecd3 (diff) | |
| download | talos-hostboot-4f4f097d65e919bcc8bd5706f50ea0f413b8bfef.tar.gz talos-hostboot-4f4f097d65e919bcc8bd5706f50ea0f413b8bfef.zip | |
DDR4 - Allow SPD writes
-DDR4 has 512-byte EEPROM with 2 256-byte pages.
This commit contains the necessary page switching
logic to support this.
Change-Id: Iaa8e3e344def98b71d6a9e9387c5e0d9137a0397
RTC:137707
ForwardPort: yes
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/797
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: Jenkins OP Build CI
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Tested-by: Jenkins OP HW
Tested-by: FSP CI Jenkins
Reviewed-by: Matthew A. Ploetz <maploetz@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/871
Diffstat (limited to 'src/usr/vpd/spdDDR4.H')
| -rwxr-xr-x | src/usr/vpd/spdDDR4.H | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/usr/vpd/spdDDR4.H b/src/usr/vpd/spdDDR4.H index a3df6f3f7..d263f9cd4 100755 --- a/src/usr/vpd/spdDDR4.H +++ b/src/usr/vpd/spdDDR4.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2013,2015 */ +/* Contributors Listed Below - COPYRIGHT 2013,2016 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -112,6 +112,7 @@ const KeywordData ddr4Data[] = { DRAM_MANUFACTURER_ID, 0x15f, 0x02, 0x00, 0x00, true, false, NA }, { MANUFACTURER_SPECIFIC_DATA, 0x161, 0x1d, 0x00, 0x00, false, false, NA }, { DIMM_BAD_DQ_DATA, 0x180, 0x50, 0x00, 0x00, false, true, NA }, + { MODULE_REVISION_CODE, 0x15d, 0x01, 0x00, 0x00, false, false, NA }, // Normal fields supported on DDR4 only { BANK_GROUP_BITS, 0x04, 0x01, 0xC0, 0x06, false, false, NA }, { BANK_ADDRESS_BITS_DDR4, 0x04, 0x01, 0x30, 0x04, false, false, NA }, @@ -132,7 +133,6 @@ const KeywordData ddr4Data[] = { TRRDS_FINE_OFFSET, 0x77, 0x01, 0x00, 0x00, false, false, NA }, { TCKMAX_FINE_OFFSET, 0x7c, 0x01, 0x00, 0x00, false, false, NA }, { BASE_CONFIG_CRC, 0x7f, 0x02, 0x00, 0x00, true, false, NA }, - { MODULE_REVISION_CODE_DDR4, 0x15d, 0x01, 0x00, 0x00, false, false, NA }, { DRAM_STEPPING, 0x160, 0x01, 0x00, 0x00, false, false, NA }, { MANUFACTURING_SECTION_CRC, 0x17f, 0x02, 0x00, 0x00, true, false, NA }, // Module Specific fields supported on both DDR3 and DDR4 |
