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| author | nagendra <nagendra.g@in.ibm.com> | 2015-07-24 13:55:08 -0500 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2015-10-15 15:00:13 -0500 |
| commit | 29bd2509664ce1040eb98797857d1dc76a0fa42f (patch) | |
| tree | 5bcd33f0f4add9361caf5cab92c16d03d91a2b16 /src/usr/vpd/spdDDR4.H | |
| parent | 568932e9e7a3f6b2e06ef7ec48fb10ed5d3e1f93 (diff) | |
| download | talos-hostboot-29bd2509664ce1040eb98797857d1dc76a0fa42f.tar.gz talos-hostboot-29bd2509664ce1040eb98797857d1dc76a0fa42f.zip | |
New SPD and VPD attributes support for DDR4 DIMM enablement
. Added new SPD attributes support as per DDR4 JEDEC
. Added new VPD attributes as per ver5 Membuff vpd
Change-Id: I9b3eabe6fe1c804b88429548fbac7adf08d8f6ae
RTC: 116143
CQ: SW325324
Backport: release-fips840
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/19337
Tested-by: Jenkins Server
Tested-by: Jenkins OP Build CI
Tested-by: Jenkins OP HW
Tested-by: FSP CI Jenkins
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr/vpd/spdDDR4.H')
| -rw-r--r-- | src/usr/vpd/spdDDR4.H | 31 |
1 files changed, 26 insertions, 5 deletions
diff --git a/src/usr/vpd/spdDDR4.H b/src/usr/vpd/spdDDR4.H index 7e22f13d2..8eb8b3cab 100644 --- a/src/usr/vpd/spdDDR4.H +++ b/src/usr/vpd/spdDDR4.H @@ -67,8 +67,8 @@ const KeywordData ddr4Data[] = // Keyword offset size Bitmsk Shift Spec Writ- Mod // Number Case able Spec // ------------------------------------------------------------------------------------------ + // // Normal fields supported on both DDR3 and DDR4 - { CRC_EXCLUDE, 0x00, 0x01, 0x80, 0x07, false, false, NA }, { SPD_BYTES_TOTAL, 0x00, 0x01, 0x70, 0x04, false, false, NA }, { SPD_BYTES_USED, 0x00, 0x01, 0x0F, 0x00, false, false, NA }, { SPD_MAJOR_REVISION, 0x01, 0x01, 0xF0, 0x04, false, false, NA }, @@ -95,7 +95,6 @@ const KeywordData ddr4Data[] = { SDRAM_THERMAL_REFRESH_OPTIONS, 0x08, 0x01, 0x00, 0x00, false, false, NA }, { MODULE_THERMAL_SENSOR, 0x0e, 0x01, 0x00, 0x00, false, false, NA }, { THERMAL_SENSOR_PRESENT, 0x0e, 0x01, 0x80, 0x07, false, false, NA }, - { THERMAL_SENSOR_ACCURACY, 0x0e, 0x01, 0x7F, 0x00, false, false, NA }, { SDRAM_DEVICE_TYPE , 0x06, 0x01, 0x80, 0x07, false, false, NA }, { SDRAM_DIE_COUNT, 0x06, 0x01, 0x70, 0x04, false, false, NA }, { SDRAM_DEVICE_TYPE_SIGNAL_LOADING, 0x06, 0x01, 0x03, 0x00, false, false, NA }, @@ -150,15 +149,37 @@ const KeywordData ddr4Data[] = { RMM_HEAT_SP_CHARS, 0x84, 0x01, 0x7F, 0x00, false, false, RMM }, { RMM_MFR_ID_CODE, 0x86, 0x02, 0x00, 0x00, true, false, RMM }, { RMM_REG_REV_NUM, 0x87, 0x01, 0x00, 0x00, false, false, RMM }, - { LRMM_HEAT_SP, 0x83, 0x01, 0x80, 0x07, false, false, LRMM }, + { LRMM_HEAT_SP, 0x84, 0x01, 0x80, 0x07, false, false, LRMM }, { LRMM_NUM_ROWS, 0x83, 0x01, 0x0c, 0x02, false, false, LRMM }, { LRMM_MIRRORING, 0x83, 0x01, 0x03, 0x00, false, false, LRMM }, - { LRMM_REVISION_NUM, 0x84, 0x01, 0x00, 0x00, false, false, LRMM }, - { LRMM_MFR_ID_CODE, 0x86, 0x02, 0x00, 0x00, true, false, LRMM }, + { LRMM_REVISION_NUM, 0x87, 0x01, 0x00, 0x00, false, false, LRMM }, + { MODSPEC_MM_MFR_ID_CODE, 0x86, 0x02, 0x00, 0x00, true, false, ALL }, // Module Specific fields supported on DDR4 only { MODSPEC_COM_RAW_CARD_EXT, 0x80, 0x01, 0xe0, 0x05, false, false, ALL }, { UMM_CRC, 0xff, 0x02, 0x00, 0x00, true, false, UMM }, { RMM_ADDR_MAPPING, 0x88, 0x01, 0x01, 0x00, false, false, RMM }, + { MODSPEC_MM_ATTRIBS, 0x83, 0x01, 0x00, 0x00, false, false, ALL }, + { MODSPEC_MM_ADDR_MAPPING, 0x88, 0x02, 0x00, 0x00, false, false, ALL }, + { MODSPEC_MM_DRV_STRENGTH_CNTL, 0x89, 0x01, 0x00, 0x00, false, false, ALL }, + { MODSPEC_MM_DRV_STRENGTH_CK, 0x8a, 0x01, 0x00, 0x00, false, false, ALL }, + { LRMM_VREF_DQ_RANK0, 0x8c, 0x01, 0x00, 0x00, false, false, LRMM }, + { LRMM_VREF_DQ_RANK1, 0x8d, 0x01, 0x00, 0x00, false, false, LRMM }, + { LRMM_VREF_DQ_RANK2, 0x8e, 0x01, 0x00, 0x00, false, false, LRMM }, + { LRMM_VREF_DQ_RANK3, 0x8f, 0x01, 0x00, 0x00, false, false, LRMM }, + { LRMM_VREF_DQ_FOR_DRAM, 0x90, 0x01, 0x00, 0x00, false, false, LRMM }, + { LRMM_MDQ_DRV_LT_1866, 0x91, 0x01, 0x00, 0x00, false, false, LRMM }, + { LRMM_MDQ_DRV_1866_2400, 0x92, 0x01, 0x00, 0x00, false, false, LRMM }, + { LRMM_MDQ_DRV_2400_3200, 0x93, 0x01, 0x00, 0x00, false, false, LRMM }, + { LRMM_DRV_STRENGTH, 0x94, 0x01, 0x00, 0x00, false, false, LRMM }, + { LRMM_ODT_RTT_WR_LT_1866, 0x95, 0x01, 0x07, 0x00, false, false, LRMM }, + { LRMM_ODT_RTT_NOM_LT_1866, 0x95, 0x01, 0x38, 0x03, false, false, LRMM }, + { LRMM_ODT_RTT_WR_1866_2400, 0x96, 0x01, 0x07, 0x00, false, false, LRMM }, + { LRMM_ODT_RTT_NOM_1866_2400, 0x96, 0x01, 0x38, 0x03, false, false, LRMM }, + { LRMM_ODT_RTT_WR_2400_3200, 0x97, 0x01, 0x07, 0x00, false, false, LRMM }, + { LRMM_ODT_RTT_NOM_2400_3200, 0x97, 0x01, 0x38, 0x03, false, false, LRMM }, + { LRMM_ODT_RTT_PARK_LT_1866, 0x98, 0x01, 0x00, 0x00, false, false, LRMM }, + { LRMM_ODT_RTT_PARK_1866_2400, 0x99, 0x01, 0x00, 0x00, false, false, LRMM }, + { LRMM_ODT_RTT_PARK_2400_3200, 0x9a, 0x01, 0x00, 0x00, false, false, LRMM }, { RMM_CRC, 0xff, 0x02, 0x00, 0x00, true, false, RMM }, { LRMM_CRC, 0xff, 0x02, 0x00, 0x00, true, false, LRMM }, { ENTIRE_SPD, 0x00, 0x200, 0x00, 0x00, false, false, ALL }, |
