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author | Mike Baiocchi <mbaiocch@us.ibm.com> | 2017-12-06 07:08:01 -0600 |
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committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2017-12-12 17:05:15 -0500 |
commit | 8fcdfa14a7d3e8615f08c398bec2ee0b7a8d119e (patch) | |
tree | 6e451e32e74b77daa524512213d7d0bd94a18655 /src/usr/util/utiltcemgr.H | |
parent | a6d6b5da3da48be85bedacfb2732a3760b35445c (diff) | |
download | talos-hostboot-8fcdfa14a7d3e8615f08c398bec2ee0b7a8d119e.tar.gz talos-hostboot-8fcdfa14a7d3e8615f08c398bec2ee0b7a8d119e.zip |
Support Verifying and Moving PAYLOAD and HDAT when TCEs are Enabled
This commit makes changes in istep 16 to set up temporary memory
regions that the FSP will use to DMA-via-TCEs the PAYLOAD and HDAT
sections into memory in istep 20. Then in istep 21 Hostboot will
verify and move these sections to the final memory locations.
Change-Id: I3c9e026a8e2c3c40008364c4229915b4a661d0fe
RTC:181900
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50624
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Reviewed-by: Marshall J. Wilks <mjwilks@us.ibm.com>
Reviewed-by: Stephen M. Cprek <smcprek@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/usr/util/utiltcemgr.H')
-rw-r--r-- | src/usr/util/utiltcemgr.H | 56 |
1 files changed, 52 insertions, 4 deletions
diff --git a/src/usr/util/utiltcemgr.H b/src/usr/util/utiltcemgr.H index a4689235c..aabf99d5a 100644 --- a/src/usr/util/utiltcemgr.H +++ b/src/usr/util/utiltcemgr.H @@ -120,8 +120,12 @@ class UtilTceMgr /** size of the Tce Table */ size_t iv_tceTableSize; + /** Tokens for PAYLOAD and HDAT entries in the TCE Table */ + uint32_t iv_payloadToken; + uint32_t iv_hdatToken; + /* Cache of starting addresses of allocated TCEs and their - * tokens (starting entry in the TCE Table) and size + * tokens ((starting entry in the TCE Table) * PAGESIZE) and size * Indexed by token - the position of the first entry of the TCE Table * Returns the starting address and size of the memory allocated by the * entries in the TCE Table @@ -146,6 +150,12 @@ class UtilTceMgr PHBSECURE_TCE_ENABLE = 0x2000000000000000, }; + /** Values related to tokens */ + enum tokenValues : uint32_t + { + INVALID_TOKEN_VALUE = 0xFFFFFFFF, + }; + /** * @brief Responsible for initalizing the TCE Table and mapping the * TCE Table into memory @@ -240,9 +250,11 @@ class UtilTceMgr * Size must be less than (512K * PAGESIZE) or will fail * Assert if not greater than zero * @param[out] o_startingToken - Starting Entry into the table. - * (This is an offset into the array based on - * the TCE index * PAGESIZE. Each TCE entry - * maps to a pagesize of memory) + * @param[out] o_startingToken - Key to the Starting Entry into the table. + * This is an offset into the array based on the + * TCE Index * PAGESIZE. + * FSP uses the token as a DMA Address. + * Each TCE entry maps to a pagesize of memory. * * Note: First time this is called will cause TCE table to be created and * the Processors to be setup to point at the TCE table @@ -287,6 +299,42 @@ class UtilTceMgr */ errlHndl_t initTceInHdw(); + + /** Values related to tokens */ + enum tokenLabels + { + PAYLOAD_TOKEN = 0x0, + HDAT_TOKEN = 0x1, + }; + + /** + * @brief Returns one of two internally stored tokens + * + * @param[in] i_tokenLabel - Specifies which token to return + * Assert if neither PAYLOAD_TOKEN nor + * HDAT_TOKEN + * + * @return uint32_t - Return specified token + * + */ + uint32_t getToken(tokenLabels i_tokenLabel); + + /** + * @brief Sets one of two internally stored tokens + * + * @param[in] i_tokenLabel - Specifies which token to set + * Assert if neither PAYLOAD_TOKEN nor + * HDAT_TOKEN + * + * @param[in] i_tokenValue - Value to be set + * + * @return uint32_t - Set specified token + * + */ + void setToken(tokenLabels i_tokenLabel, + uint32_t i_tokenValue); + + }; // class UtilTceMgr /** |