Implement proc_set_pore_bar HWP

Change-Id: I95562f9c3bb85e3b283020f62beaf65752281167
RTC:	42150
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1393
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

3 files changed, 86 insertions, 2 deletions

diff --git a/src/usr/targeting/common/utilFilter.C b/src/usr/targeting/common/utilFilter.C
index f6fcc3756..20acaf170 100644
--- a/src/usr/targeting/common/utilFilter.C
+++ b/src/usr/targeting/common/utilFilter.C
@@ -32,6 +32,8 @@
 #include <targeting/common/predicates/predicateisfunctional.H>
 #include <targeting/common/predicates/predicatepostfixexpr.H>
 
+#include <sys/task.h>           // task_getcpuid()
+
 
 /**
  * Miscellaneous Filter Utility Functions
@@ -209,4 +211,56 @@ const Target * getParentChip( const Target * i_pChiplet )
     return l_pChip;
 }
 
-};
+
+const TARGETING::Target *   getMasterCore( )
+{
+    uint64_t l_masterCoreID                     =   task_getcpuid() & ~7;
+    const   TARGETING::Target * l_masterCore    =   NULL;
+
+    TARGETING::Target * l_processor =   NULL;
+    (void)TARGETING::targetService().masterProcChipTargetHandle( l_processor );
+    FABRIC_NODE_ID_ATTR l_logicalNodeId =
+                l_processor->getAttr<TARGETING::ATTR_FABRIC_NODE_ID>();
+    FABRIC_CHIP_ID_ATTR l_chipId =
+                l_processor->getAttr<TARGETING::ATTR_FABRIC_CHIP_ID>();
+
+    TargetHandleList l_cores;
+    getChildChiplets( l_cores,
+                      l_processor,
+                      TYPE_CORE,
+                      true );
+
+    TRACDCOMP( g_trac_targeting,
+               "getMasterCore: found %d cores on master proc",
+               l_cores.size()   );
+
+    for ( uint8_t l_coreNum=0; l_coreNum < l_cores.size(); l_coreNum++ )
+    {
+        TARGETING::Target *    l_core  =   l_cores[ l_coreNum ] ;
+
+        CHIP_UNIT_ATTR l_coreId =
+                    l_core->getAttr<TARGETING::ATTR_CHIP_UNIT>();
+
+        uint64_t pir = l_coreId << 3;
+        pir |= l_chipId << 7;
+        pir |= l_logicalNodeId << 10;
+
+        if (pir == l_masterCoreID){
+            TRACDCOMP( g_trac_targeting,
+                       "found master core: 0x%x, PIR=0x%x :",
+                       l_coreId,
+                       pir  );
+            EntityPath l_path;
+            l_path  =   l_core->getAttr<ATTR_PHYS_PATH>();
+            l_path.dump();
+
+            l_masterCore    =   l_core ;
+            break;
+        }
+
+    }   // endfor
+
+    return l_masterCore;
+}
+
+};  // end namespace
diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml
index 6626b2906..a032aaaf9 100644
--- a/src/usr/targeting/common/xmltohb/attribute_types.xml
+++ b/src/usr/targeting/common/xmltohb/attribute_types.xml
@@ -4011,4 +4011,32 @@
   </hwpfToHbAttrMap>
 </attribute>
 
+<attribute>
+    <id>SLW_IMAGE_ADDR</id>
+    <description>
+        Location of runtime winkle image for this processor chip.
+        Written by host_build_winkle (istep 15.1)
+    </description>
+    <simpleType>
+        <uint64_t></uint64_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+</attribute>
+
+<attribute>
+    <id>SLW_IMAGE_SIZE</id>
+    <description>
+        Size of runtime winkle image for this processor chip.
+        Written by host_build_winkle (istep 15.1)
+    </description>
+    <simpleType>
+        <uint64_t></uint64_t>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+</attribute>
+
 </attributes>
diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml
index ba3bce39d..7be57fcef 100644
--- a/src/usr/targeting/common/xmltohb/target_types.xml
+++ b/src/usr/targeting/common/xmltohb/target_types.xml
@@ -204,7 +204,9 @@
      <!--   proc_fab_smp_fabric_attributes.xml  -->
      <attribute><id>FREQ_CORE</id></attribute>
      <attribute><id>PROC_PCIE_NOT_F_LINK</id></attribute>
-
+     <!-- new attribute for isteps 15 & 16 -->
+     <attribute><id>SLW_IMAGE_ADDR</id></attribute>
+     <attribute><id>SLW_IMAGE_SIZE</id></attribute>
 </targetType>
 
 <targetType>