Add compute PCIE config support

Change-Id: Ie32612fedf35b2cc504cabee494e61eba7775c48
RTC:162594
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31938
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

3 files changed, 140 insertions, 94 deletions

diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml
index 0fcd5cc34..a8fd917af 100644
--- a/src/usr/targeting/common/xmltohb/attribute_types.xml
+++ b/src/usr/targeting/common/xmltohb/attribute_types.xml
@@ -16630,22 +16630,22 @@ Measured in GB</description>
     <id>PROC_PCIE_LANE_MASK</id>
     <description>Effective PCIE Lane Mask
         Creator: Firmware
-        Purpose: Holds the effective PCIE lane mask after taking into account
-            any IOP bifurcations.  If no IOP bifurcations present, this is just
-            the value of the PROC_PCIE_LANE_MASK_NON_BIFURCATED attribute
-        Data Format: 2x2 array of uint16_t values.  The first two uint16_t
-            values are lane set 0/1 masks for IOP0, the remaining two uint16_t
-            values are lane set 0/1 masks for IOP1.  A lane set mask indicates
-            which groups of lanes are assigned to an IOP.  For instance, lane
-            set 0 value of 0xFFFF and lane set 1 value of 0x0000 for IOP0 means
-            IOP0 is a x16. Lane set 0 value of 0xFF00 and lane set 1 value of
-            0x00FF for IOP0, means the IOP is bifurcated into two x8s.
-            Each index in the array that is non-0 will require a dedicated PHB.
+        Purpose: Holds the effective PCIE lane mask of each PEC after taking
+            into account any IOP bifurcations. If no IOP bifurcations present,
+            this is just the value of the PEC_PCIE_LANE_MASK_NON_BIFURCATED
+            attribute
+        Data Format: x4 array of uint16_t values.  The uint16_t value is a
+            mask for lane 0, the next for lane 1 and so on until lane 3.
+            A lane set mask indicates which groups of lanes are assigned to an
+            IOP.  For instance, lane set 0 value of 0xFFFF and lane set 1 value
+            of 0x0000 for PEC0 means PEC0 is a x16. Lane set 0 value of 0xFF00
+            and lane set 1 value of 0x00FF for PEC0, means the IOP is bifurcated
+            into two x8s.
     </description>
     <simpleType>
         <uint16_t>
         </uint16_t>
-        <array>3,2</array>
+        <array>4</array>
     </simpleType>
     <persistency>non-volatile</persistency>
     <readable/>
@@ -16653,43 +16653,22 @@ Measured in GB</description>
 </attribute>
 
 <attribute>
-    <id>PROC_PCIE_DSMP_CAPABLE</id>
-    <description>Whether DSMP is enabled for a lane set or not
-        Creator: MRW
-        Purpose: Indicates whether a given IOP / lane set is dedicated to dSMP
-            traffic or not
-        Data Format: 2x2 array of uint8_t values.  The first two uint8_t
-            values are for lane sets 0/1 of IOP0, the remaining two uint8_t
-            values are fpr lane sets 0/1 of IOP1.  If the value at a given
-            array index is 1, that IOP/lane set routes dSMP traffic.
-    </description>
-    <simpleType>
-        <uint8_t>
-        </uint8_t>
-        <array>3,2</array>
-        </simpleType>
-    <persistency>non-volatile</persistency>
-    <readable/>
-</attribute>
-
-<attribute>
-    <id>PROC_PCIE_IOP_REVERSAL</id>
+    <id>PEC_PCIE_IOP_REVERSAL</id>
     <description>Effective PCIE IOP reversal configuration
         Creator: Firmware
         Purpose: Holds the effective PCIE IOP reversal value after taking into
             account any IOP bifurcations.  If no IOP bifurcations present, this
             is just the value of the PROC_PCIE_IOP_REVERSAL_NON_BIFURCATED
             attribute.
-        Data Format: 2x2 array of uint8_t values.  The first two uint8_t
-            values are for lane sets 0/1 of IOP0, the remaining two uint8_t
-            values are for lane sets 0/1 of IOP1.  The given index in the array
-            is a mask which specifies which bit to invert in the lane swap
-            settings for the given IOP/lane set.
+        Data Format: x4 array of uint8_t values. The first uint8_t value is
+            for lane set 0, the second for lane set 1 and so on. The given
+            index in the array is a mask which specifies which bit to invert
+            in the lane swap settings for the given PEC/lane set.
     </description>
     <simpleType>
         <uint8_t>
         </uint8_t>
-        <array>3,2</array>
+        <array>4</array>
     </simpleType>
     <persistency>non-volatile</persistency>
     <readable/>
@@ -16697,132 +16676,118 @@ Measured in GB</description>
 </attribute>
 
 <attribute>
-    <id>PROC_PCIE_IOP_REVERSAL_NON_BIFURCATED</id>
+    <id>PEC_PCIE_IOP_REVERSAL_NON_BIFURCATED</id>
     <description>Base PCIE IOP reversal configuration
         Creator: Firmware
         Purpose: Holds the base PCIE IOP reversal value without considering IOP
             bifurcation.
-        Data Format: 2x2 array of uint8_t values.  The first two uint8_t
-            values are for lane sets 0/1 of IOP0, the remaining two uint8_t
-            values are for lane sets 0/1 of IOP1.  The given index in the array
-            is a mask which specifies which bit to invert in the lane swap
-            settings for the given IOP/lane set
+        Data Format: x4 array of uint8_t values. The first uint8_t value is
+            for lane set 0, the second for lane set 1 and so on. The given
+            index in the array is a mask which specifies which bit to invert
+            in the lane swap settings for the given lane set.
     </description>
     <simpleType>
         <uint8_t>
         </uint8_t>
-        <array>3,2</array>
+        <array>4</array>
     </simpleType>
     <persistency>non-volatile</persistency>
     <readable/>
 </attribute>
 
 <attribute>
-    <id>PROC_PCIE_IOP_SWAP_NON_BIFURCATED</id>
+    <id>PEC_PCIE_IOP_SWAP_NON_BIFURCATED</id>
     <description>Base PCIE IOP swap configuration value
         Creator: MRW
         Purpose: Holds the base IOP swap configuration value without considering
             IOP bifurcation.  The swap value controls how PCIE lanes are
             recordered when the leave the IOP, to provide lane routing
             flexibility.
-        Data Format: 2x2 array of uint8_t values.  The first two uint8_t
-            values are for lane sets 0/1 of IOP0, the remaining two uint8_t
-            values are for lane sets 0/1 of IOP1.  The given index in the array
-            is a value for the hardware which specifies how to swap the PCIE
-            lanes for the given IOP/lane set.
+        Data Format: A uint8_t value. The value specifices for the hardware how
+            to swap the PCIE lanes for the given PEC.
     </description>
     <simpleType>
         <uint8_t></uint8_t>
-        <array>3,2</array>
     </simpleType>
     <persistency>non-volatile</persistency>
     <readable/>
 </attribute>
 
 <attribute>
-    <id>PROC_PCIE_LANE_MASK_NON_BIFURCATED</id>
+    <id>PEC_PCIE_LANE_MASK_NON_BIFURCATED</id>
     <description>PCIE Lane Mask base configuration
         Creator: MRW
         Purpose: Holds the base PCIE lane mask assuming no dynamic IOP
             bifurcations.
-        Data Format: 2x2 array of uint16_t values.  The first two uint16_t
-            values are for lane set 0/1 masks of IOP0, the remaining two
-            values are for lane set 0/1 masks of IOP1.  A lane set mask
+        Data Format: x4 array of uint16_t values. The first uint8_t value is
+            lane set 0, the second for lane set 2 and so on. A lane set mask
             indicates which groups of lanes are assigned to an IOP.  For
             instance, lane set 0 value of 0xFFFF and lane set 1 value of 0x0000
-            for IOP0 means IOP0 is a x16. Lane set 0 value of 0xFF00 and lane
-            set 1 value of 0x00FF for IOP0, means the IOP is split into two x8s.
-            Each array index with non-0 value implies a dedicated PHB.
+            means the PEC is a x16. Lane set 0 value of 0xFF00 and lane
+            set 1 value of 0x00FF, means the PEC is split into two x8s.
     </description>
     <simpleType>
         <uint16_t>
         </uint16_t>
-        <array>3,2</array>
+        <array>4</array>
     </simpleType>
     <persistency>non-volatile</persistency>
     <readable/>
 </attribute>
 
 <attribute>
-    <id>PROC_PCIE_IOP_REVERSAL_BIFURCATED</id>
+    <id>PEC_PCIE_IOP_REVERSAL_BIFURCATED</id>
     <description>Base PCIE IOP reversal configuration
         Creator: Firmware
         Purpose: Holds the PCIE IOP reversal value for cases where the IOP
             is bifurcated
-        Data Format: 2x2 array of uint8_t values.  The first two uint8_t
-            values are for lane sets 0/1 of IOP0, the remaining two uint8_t
-            values are for lane sets 0/1 of IOP1.  The given index in the array
-            is a mask which specifies which bit to invert in the lane swap
-            settings for the given IOP / lane set
+        Data Format: x4 array of uint8_t values. The first uint8_t value is
+            lane set 0, the second for lane set 2 and so on. The given index in
+            the array is a mask which specifies which bit to invert in the lane
+            swap settings for the given lane set
     </description>
     <simpleType>
         <uint8_t>
         </uint8_t>
-        <array>3,2</array>
+        <array>4</array>
     </simpleType>
     <persistency>non-volatile</persistency>
     <readable/>
 </attribute>
 
 <attribute>
-    <id>PROC_PCIE_IOP_SWAP_BIFURCATED</id>
+    <id>PEC_PCIE_IOP_SWAP_BIFURCATED</id>
     <description>Bifurcated PCIE IOP swap configuration value
         Creator: MRW
         Purpose: Holds the base IOP swap configuration value for the IOPs in the
             case where they are bifurcated.  The swap value controls how PCIE
             lanes are recordered when the leave the IOP, to provide lane routing
             flexibility.
-        Data Format: 2x2 array of uint8_t values.  The first two uint8_t
-            values are for lane sets 0/1 of IOP0, the remaining two uint8_t
-            values are for lane sets 0/1 pf IOP1.  The given index in the array
-            is a value for the hardware which specifies how to swap the PCIE
-            lanes for the given IOP/lane set.
+        Data Format: A uint8_t value. The value specifices for the hardware how
+            to swap the PCIE lanes for the given PEC.
     </description>
     <simpleType>
         <uint8_t></uint8_t>
-        <array>3,2</array>
     </simpleType>
     <persistency>non-volatile</persistency>
     <readable/>
 </attribute>
 
 <attribute>
-    <id>PROC_PCIE_LANE_MASK_BIFURCATED</id>
+    <id>PEC_PCIE_LANE_MASK_BIFURCATED</id>
     <description>PCIE Lane Mask bifurcated configuration
         Creator: MRW
         Purpose: Holds the PCIE lane mask assuming IOPs are bifurcated.
-        Data Format: 2x2 array of uint16_t values.  The first two uint16_t
-            values are for lane set 0/1 masks of IOP0, the remaining two
-            values are for lane set 0/1 masks of IOP1.  A lane set mask
-            indicates which groups of lanes are assigned to an IOP.  For
+        Data Format: x4 array of uint16_t values. The first uint8_t value is
+            lane set 0, the second for lane set 2 and so on. A lane set mask
+            indicates which groups of lanes are assigned to an IOP. For
             instance, lane set 0 value of 0xFF00 and lane set 1 value of 0x00FF
-            for IOP0, means the IOP is bifurcated into two x8s.
-            Each non-0 array value implies a dedicated PHB.
+             means the IOP is bifurcated into two x8s.
     </description>
     <simpleType>
         <uint16_t>
         </uint16_t>
-        <array>3,2</array>
+        <array>4</array>
     </simpleType>
     <persistency>non-volatile</persistency>
     <readable/>
@@ -16836,16 +16801,16 @@ Measured in GB</description>
             pluggable slot or not.  If this is the case, and the platform
             supports bifurcation, the card's VPD should be interrogated to
             determine whether to bifurcate the IOP or not.
-        Data Format: 2x2 array of uint8_t values.  The first two values indicate
-            whether lane set 0/1 of IOP0 terminates at a pluggable slot.  The
-            next two values indicate the same for IOP1.  A value of 1 at a given
-            array index indicates the lanes terminate at a pluggable slot, 0
-            otherwise.
+        Data Format: x4 array of uint8_t values.  The first value indicates
+            whether lane set 0 terminates at a pluggable slot.  The
+            next three values indicate the same for lane sets 1-3. A value of
+            1 at a given array index indicates the lanes terminate at a
+            pluggable slot, 0 otherwise.
     </description>
     <simpleType>
         <uint8_t>
         </uint8_t>
-        <array>3,2</array>
+        <array>4</array>
     </simpleType>
     <persistency>non-volatile</persistency>
     <readable/>
@@ -17098,6 +17063,7 @@ Measured in GB</description>
         Number of PCIe IOP units present on target
         Murano/Venice: 2
         Naples: 3
+        Nimbus: 3
   </description>
   <simpleType>
       <uint8_t></uint8_t>
@@ -17111,6 +17077,24 @@ Measured in GB</description>
 </attribute>
 
 <attribute>
+  <id>PROC_PCIE_NUM_PEC</id>
+  <description>
+      creator: platform
+        Number of PCIe PEC units present on target
+        Nimbus: 3
+  </description>
+  <simpleType>
+      <uint8_t></uint8_t>
+  </simpleType>
+  <persistency>non-volatile</persistency>
+  <readable/>
+  <hwpfToHbAttrMap>
+      <id>ATTR_PROC_PCIE_NUM_PEC</id>
+      <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
   <id>PROC_PCIE_NUM_LANES</id>
   <description>
       creator: platform
@@ -17118,6 +17102,7 @@ Measured in GB</description>
         Murano: 24
         Venice: 32
         Naples: 40
+        Nimbus: 48
   </description>
   <simpleType>
       <uint8_t></uint8_t>
diff --git a/src/usr/targeting/common/xmltohb/simics_NIMBUS.system.xml b/src/usr/targeting/common/xmltohb/simics_NIMBUS.system.xml
index 9a55d1955..1b18df577 100644
--- a/src/usr/targeting/common/xmltohb/simics_NIMBUS.system.xml
+++ b/src/usr/targeting/common/xmltohb/simics_NIMBUS.system.xml
@@ -2616,6 +2616,18 @@
         <id>PROC_PCIE_PCS_TX_POWER_SEQ_ENABLE</id>
         <default>0xff</default>
     </attribute>
+    <attribute>
+        <id>PEC_PCIE_LANE_MASK_NON_BIFURCATED</id>
+        <default>0xFFFF,0x0000,0x0000,0x0000</default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_CONFIG</id>
+        <default>0</default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_SWAP</id>
+        <default>0</default>
+    </attribute>
 </targetInstance>
 
 <targetInstance>
@@ -2705,6 +2717,18 @@
         <id>PROC_PCIE_PCS_TX_POWER_SEQ_ENABLE</id>
         <default>0xff</default>
     </attribute>
+    <attribute>
+        <id>PEC_PCIE_LANE_MASK_NON_BIFURCATED</id>
+        <default>0xFF00,0x0000,0x00FF,0x0000</default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_CONFIG</id>
+        <default>0</default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_SWAP</id>
+        <default>0</default>
+    </attribute>
 </targetInstance>
 
 <targetInstance>
@@ -2794,6 +2818,18 @@
         <id>PROC_PCIE_PCS_TX_POWER_SEQ_ENABLE</id>
         <default>0xff</default>
     </attribute>
+    <attribute>
+        <id>PEC_PCIE_LANE_MASK_NON_BIFURCATED</id>
+        <default>0xFF00,0x0000,0x00FF,0x0000</default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_CONFIG</id>
+        <default>0</default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_IOP_SWAP</id>
+        <default>0</default>
+    </attribute>
 </targetInstance>
 
 <!-- Nimbus n0p0pec0 PHB units -->
@@ -5467,7 +5503,6 @@
                  0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0
         </default>
     </attribute>
-
 </targetInstance>
 
 <!-- ZZ n0p1 OCC units -->
@@ -7879,6 +7914,10 @@
         <id>CHIPLET_ID</id>
         <default>0xD</default>
     </attribute>
+    <attribute>
+        <id>PEC_PCIE_LANE_MASK_NON_BIFURCATED</id>
+        <default>0xFFFF,0x0000,0x0000,0x0000</default>
+    </attribute>
 </targetInstance>
 
 <targetInstance>
@@ -7920,6 +7959,10 @@
         <id>CHIPLET_ID</id>
         <default>0xE</default>
     </attribute>
+    <attribute>
+        <id>PEC_PCIE_LANE_MASK_NON_BIFURCATED</id>
+        <default>0xFF00,0x0000,0x00FF,0x0000</default>
+    </attribute>
 </targetInstance>
 
 <targetInstance>
@@ -7961,6 +8004,10 @@
         <id>CHIPLET_ID</id>
         <default>0xF</default>
     </attribute>
+    <attribute>
+        <id>PEC_PCIE_LANE_MASK_NON_BIFURCATED</id>
+        <default>0xFF00,0x0000,0x00FF,0x0000</default>
+    </attribute>
 </targetInstance>
 
 <targetInstance>
diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml
index 3dbc8699d..6ce0345d5 100755
--- a/src/usr/targeting/common/xmltohb/target_types.xml
+++ b/src/usr/targeting/common/xmltohb/target_types.xml
@@ -998,15 +998,19 @@
     <attribute><id>I2C_SLAVE_ADDRESS</id></attribute>
     <attribute>
         <id>PROC_PCIE_NUM_PHB</id>
-        <default>3</default>
+        <default>6</default>
     </attribute>
     <attribute>
         <id>PROC_PCIE_NUM_IOP</id>
-        <default>2</default>
+        <default>3</default>
+    </attribute>
+    <attribute>
+        <id>PROC_PCIE_NUM_PEC</id>
+        <default>3</default>
     </attribute>
     <attribute>
         <id>PROC_PCIE_NUM_LANES</id>
-        <default>24</default>
+        <default>48</default>
     </attribute>
     <attribute><id>PROC_PCIE_PHB_ACTIVE</id></attribute>
     <attribute><id>PROC_DCM_INSTALLED</id></attribute>
@@ -2006,6 +2010,16 @@
     <attribute><id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id>
         <default>0x00000001</default> <!-- GARD -->
     </attribute>
+
+    <attribute><id>PROC_PCIE_LANE_MASK</id></attribute>
+    <attribute><id>PEC_PCIE_LANE_MASK_NON_BIFURCATED</id></attribute>
+    <attribute><id>PEC_PCIE_LANE_MASK_BIFURCATED</id></attribute>
+    <attribute><id>PEC_PCIE_IOP_SWAP_NON_BIFURCATED</id></attribute>
+    <attribute><id>PEC_PCIE_IOP_SWAP_BIFURCATED</id></attribute>
+    <attribute><id>PEC_PCIE_IOP_REVERSAL</id></attribute>
+    <attribute><id>PEC_PCIE_IOP_REVERSAL_NON_BIFURCATED</id></attribute>
+    <attribute><id>PEC_PCIE_IOP_REVERSAL_BIFURCATED</id></attribute>
+
 </targetType><!-- unit-pec-power9 -->
 
 <!-- PHB
@@ -2020,7 +2034,7 @@
     </attribute>
     <attribute>
         <id>PROC_PCIE_NUM_LANES</id>
-        <default>32</default>
+        <default>48</default>
     </attribute>
     <attribute><id>DECONFIG_GARDABLE</id><default>1</default></attribute>
     <attribute><id>HWAS_STATE_CHANGED_SUBSCRIPTION_MASK</id>