Handle processor swap between slots to 1-socket system

If a processor was booted in the second slot, it will be programmed
to use the memory for that slot.  When it is installed in the first
slot it will then get reprogrammed to use the data for slot0.
However, if the new system only contains data for that 1 slot, we
won't be able to find a match to do the initial part of the boot.

This change will force some values into good enough shape to get
the boot far enough to do the SBE update to reprogram the memory
map.

Change-Id: I9b88d4181272104a8c680e9b5e84c4d204fdea05
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/80680
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Reviewed-by: Christian R Geddes <crgeddes@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M Crowell <dcrowell@us.ibm.com>

3 files changed, 101 insertions, 8 deletions

diff --git a/src/usr/targeting/common/xmltohb/attribute_types_hb.xml b/src/usr/targeting/common/xmltohb/attribute_types_hb.xml
index 491e9667b..2ca3f0494 100755
--- a/src/usr/targeting/common/xmltohb/attribute_types_hb.xml
+++ b/src/usr/targeting/common/xmltohb/attribute_types_hb.xml
@@ -230,6 +230,39 @@
     <readable/>
   </attribute>
 
+  <enumerationType>
+    <description>
+        Enumeration specifying a target's CEC degraded mode domain
+    </description>
+    <default>NO</default>
+    <enumerator>
+      <name>NO</name>
+      <value>0</value>
+    </enumerator>
+    <enumerator>
+      <name>BAR_MISMATCH</name>
+      <value>1</value>
+    </enumerator>
+    <id>FORCE_SBE_UPDATE</id>
+  </enumerationType>
+
+  <attribute>
+    <id>FORCE_SBE_UPDATE</id>
+    <description>
+        Set to non-zero to force a SBE update at various places in the IPL.
+    </description>
+    <simpleType>
+      <enumeration>
+        <id>FORCE_SBE_UPDATE</id>
+        <default>NO</default>
+      </enumeration>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hbOnly/>
+  </attribute>
+
   <attribute>
     <!-- Need to add this explicitly to handle the Axone case -->
     <id>FREQ_MCA_MHZ</id>
diff --git a/src/usr/targeting/common/xmltohb/target_types_hb.xml b/src/usr/targeting/common/xmltohb/target_types_hb.xml
index 1f7421305..4b3599cef 100644
--- a/src/usr/targeting/common/xmltohb/target_types_hb.xml
+++ b/src/usr/targeting/common/xmltohb/target_types_hb.xml
@@ -276,6 +276,9 @@
     <attribute>
       <id>FORCE_PRE_PAYLOAD_DRTM</id>
     </attribute>
+    <attribute>
+      <id>FORCE_SBE_UPDATE</id>
+    </attribute>
     <!-- Need to add this explicitly to handle the Axone case -->
     <attribute>
       <id>FREQ_MCA_MHZ</id>
diff --git a/src/usr/targeting/targetservicestart.C b/src/usr/targeting/targetservicestart.C
index 0cce34319..d16d8b75c 100755
--- a/src/usr/targeting/targetservicestart.C
+++ b/src/usr/targeting/targetservicestart.C
@@ -74,6 +74,7 @@
 #include <sbeio/sbeioif.H>
 #include <sys/mm.h>
 #include "../runtime/hdatstructs.H"
+#include <console/consoleif.H>
 
 #ifdef CONFIG_BMC_IPMI
 #include <ipmi/ipmiif.H>
@@ -968,11 +969,65 @@ static void adjustMemoryMap( TargetService& i_targetService )
         // Set the rest of the BARs...
     }
 
-    // We must have found a match somewhere
-    TARG_ASSERT( l_swapVictim != nullptr, "No swap match found" );
+    // We should have found a match, but if a processor was swapped
+    //  between different systems we could end up with a non-match
+    if( l_swapVictim == nullptr )
+    {
+        TARG_INF( "No swap victim was found, forcing master proc to use calculated proc0 values" );
+
+        // figure out what fabric id we actually booted with
+        uint8_t l_bootGroup = 0;
+        uint8_t l_bootChip = 0;
+        getFabricIdFromAddr( l_curXscomBAR, l_bootGroup, l_bootChip );
+        CONSOLE::displayf( NULL, "Module swap detected - handling memory remap from g%d:c%d\n", l_bootGroup, l_bootChip );
+
+        // now adjust the attributes that our early code is going to consume
+        //  to match the fabric id we're currently using
+        ATTR_XSCOM_BASE_ADDRESS_type l_xscomBAR =
+          computeMemoryMapOffset( l_xscomBase, l_bootGroup, l_bootChip );
+        l_pMasterProcChip->setAttr<ATTR_XSCOM_BASE_ADDRESS>(l_xscomBAR);
+
+        ATTR_LPC_BUS_ADDR_type l_lpcBAR =
+          computeMemoryMapOffset( l_lpcBase, l_bootGroup, l_bootChip );
+        l_pMasterProcChip->setAttr<ATTR_LPC_BUS_ADDR>(l_lpcBAR);
+
+        ATTR_PSI_BRIDGE_BASE_ADDR_type l_psiBridgeBAR =
+            computeMemoryMapOffset(MMIO_GROUP0_CHIP0_PSI_BRIDGE_BASE_ADDR,
+                                  l_bootGroup,
+                                  l_bootChip);
+        l_pMasterProcChip->setAttr<ATTR_PSI_BRIDGE_BASE_ADDR>(l_psiBridgeBAR);
+
+        ATTR_XIVE_CONTROLLER_BAR_ADDR_type l_xiveCtrlBAR =
+            computeMemoryMapOffset(MMIO_GROUP0_CHIP0_XIVE_CONTROLLER_BASE_ADDR,
+                                   l_bootGroup,
+                                   l_bootChip);
+        l_pMasterProcChip->setAttr<ATTR_XIVE_CONTROLLER_BAR_ADDR>(l_xiveCtrlBAR);
 
+        ATTR_XIVE_THREAD_MGMT1_BAR_ADDR_type l_xiveThreadMgmtBAR =
+            computeMemoryMapOffset(MMIO_GROUP0_CHIP0_XIVE_THREAD_MGMT1_BASE_ADDR,
+                                   l_bootGroup,
+                                   l_bootChip);
+        TARG_INF( " XIVE_THREAD_MGMT1_BAR =%.16llX", l_xiveThreadMgmtBAR );
+        l_pMasterProcChip->setAttr<ATTR_XIVE_THREAD_MGMT1_BAR_ADDR>(l_xiveThreadMgmtBAR);
+
+        ATTR_PSI_HB_ESB_ADDR_type l_psiHbEsbBAR =
+            computeMemoryMapOffset(MMIO_GROUP0_CHIP0_PSI_HB_ESB_BASE_ADDR,
+                                   l_bootGroup,
+                                   l_bootChip);
+        l_pMasterProcChip->setAttr<ATTR_PSI_HB_ESB_ADDR>(l_psiHbEsbBAR);
+
+        ATTR_INTP_BASE_ADDR_type l_intpBAR =
+            computeMemoryMapOffset(MMIO_GROUP0_CHIP0_INTP_BASE_ADDR,
+                                   l_bootGroup,
+                                   l_bootChip);
+        l_pMasterProcChip->setAttr<ATTR_INTP_BASE_ADDR>(l_intpBAR);
+
+        // Set the attribute to force a SBE update later
+        l_pTopLevel->setAttr<TARGETING::ATTR_FORCE_SBE_UPDATE>
+          (TARGETING::FORCE_SBE_UPDATE_BAR_MISMATCH);
+    }
     // Now swap the BARs between the master and the victim if needed
-    if( l_swapVictim != l_pMasterProcChip )
+    else if( l_swapVictim != l_pMasterProcChip )
     {
         // Walk through all of the attributes we cached above
         SWAP_ATTRIBUTE( ATTR_PROC_EFF_FABRIC_GROUP_ID, l_pMasterProcChip,
@@ -999,17 +1054,19 @@ static void adjustMemoryMap( TargetService& i_targetService )
 
     // Cross-check that what we ended up setting in the attributes
     //  matches the non-TARGETING values that the XSCOM and LPC
-    //  drivers computed
-    if( l_pMasterProcChip->getAttr<ATTR_LPC_BUS_ADDR>()
-        != LPC::get_lpc_bar() )
+    //  drivers computed (only if we found a swap victim)
+    if( l_swapVictim &&
+        (l_pMasterProcChip->getAttr<ATTR_LPC_BUS_ADDR>()
+         != LPC::get_lpc_bar()) )
     {
         TARG_ERR( "LPC attribute=%.16llX, live=%.16llX",
            l_pMasterProcChip->getAttr<ATTR_LPC_BUS_ADDR>(),
            LPC::get_lpc_bar() );
         TARG_ASSERT( false, "LPC BARs are inconsistent" );
     }
-    if( l_pMasterProcChip->getAttr<ATTR_XSCOM_BASE_ADDRESS>()
-        != XSCOM::get_master_bar() )
+    if( l_swapVictim &&
+        (l_pMasterProcChip->getAttr<ATTR_XSCOM_BASE_ADDRESS>()
+         != XSCOM::get_master_bar()) )
     {
         TARG_ERR( "XSCOM attribute=%.16llX, live=%.16llX",
            l_pMasterProcChip->getAttr<ATTR_XSCOM_BASE_ADDRESS>(),