Move MRS attributes to eff_config to calc LRDIMMs

Change-Id: Ie2b6d187d67f8bc7ed975e7627fd31ff343e8969
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33774
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com>
Reviewed-by: Martin Gloff <mgloff@us.ibm.com>
Reviewed-by: Brian R. Silver <bsilver@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33781
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>

2 files changed, 509 insertions, 43 deletions

diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml
index 05391bab7..cf03952ea 100644
--- a/src/usr/targeting/common/xmltohb/attribute_types.xml
+++ b/src/usr/targeting/common/xmltohb/attribute_types.xml
@@ -5,7 +5,7 @@
 <!--                                                                        -->
 <!-- OpenPOWER HostBoot Project                                             -->
 <!--                                                                        -->
-<!-- Contributors Listed Below - COPYRIGHT 2012,2016                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2012,2017                        -->
 <!-- [+] International Business Machines Corp.                              -->
 <!--                                                                        -->
 <!--                                                                        -->
@@ -7555,46 +7555,6 @@ firmware notes: Used as override attribute for pstate procedure
 </attribute>
 
 <attribute>
-    <id>EFF_DRAM_RTT_NOM</id>
-    <description>D
-      DRAM Rtt_Nom.
-      Used in various locations and comes from the MT keyword of the VPD
-    </description>
-    <simpleType>
-        <uint8_t>
-        </uint8_t>
-        <array>2,2,4</array>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_DRAM_RTT_NOM</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
-    <id>EFF_DRAM_RTT_WR</id>
-    <description>
-      DRAM Rtt_WR.
-      Used in various locations and comes from the MT keyword of the VPD
-    </description>
-    <simpleType>
-        <uint8_t>
-        </uint8_t>
-        <array>2,2,4</array>
-    </simpleType>
-    <persistency>volatile-zeroed</persistency>
-    <readable/>
-    <writeable/>
-    <hwpfToHbAttrMap>
-        <id>ATTR_EFF_DRAM_RTT_WR</id>
-        <macro>DIRECT</macro>
-    </hwpfToHbAttrMap>
-</attribute>
-
-<attribute>
     <id>EFF_DRAM_WR_VREF</id>
     <description>
       DRAM Write Vref.
@@ -15549,7 +15509,7 @@ Measured in GB</description>
 <attribute>
     <id>REDUNDANT_CLOCKS</id>
     <description>
-        1 = System has redundant clock oscillators
+        1 = System has redundant clock oscillators
         0 = System does not have redundant clock oscillators
         From the Machine Readable Workbook
     </description>
@@ -21604,7 +21564,131 @@ Measured in GB</description>
         <macro>DIRECT</macro>
     </hwpfToHbAttrMap>
 </attribute>
+<attribute>
+    <id>PROC_PCIE_HOTPLUG_I2C_DEVICE_ADDRESS</id>
+    <!-- TARGET_TYPE_PROC_CHIP -->
+    <description>
+        I2C device address for PCIE hotplug controller
+        creator: platform
+        consumer: p9_pcie_hotplug
+    </description>
+    <simpleType>
+        <uint8_t></uint8_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_PROC_PCIE_HOTPLUG_I2C_DEVICE_ADDRESS</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>PROC_PCIE_HOTPLUG_ENABLE_ACTIONS</id>
+    <!-- TARGET_TYPE_PROC_CHIP -->
+    <description>
+        Sequence of PCIE hotplug controller register writes required to enable
+        slot power
+        creator: platform
+        consumer: p9_pcie_hotplug
+        firmware notes:
+        Primary array index: Sequence number
+        Secondary array index: Address (0) / Data (1)
+    </description>
+    <simpleType>
+        <uint8_t></uint8_t>
+        <array>8,2</array>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_PROC_PCIE_HOTPLUG_ENABLE_ACTIONS</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>PROC_PCIE_HOTPLUG_NUM_ENABLE_ACTIONS</id>
+    <!-- TARGET_TYPE_PROC_CHIP -->
+    <description>
+        Number of valid entries in primary index of
+        ATTR_PROC_PCIE_HOTPLUG_ENABLE_ACTIONS
+        creator: platform
+        consumer: p9_pcie_hotplug
+        ZERO = 0x0,
+        ONE = 0x1,
+        TWO = 0x2,
+        THREE = 0x3,
+        FOUR = 0x4,
+        FIVE = 0x5,
+        SIX = 0x6,
+        SEVEN = 0x7,
+        EIGHT = 0x8
+    </description>
+    <simpleType>
+        <uint8_t></uint8_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_PROC_PCIE_HOTPLUG_NUM_ENABLE_ACTIONS</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>PROC_PCIE_HOTPLUG_DISABLE_ACTIONS</id>
+    <!-- TARGET_TYPE_PROC_CHIP -->
+    <description>
+        Sequence of PCIE hotplug controller register writes required to disable
+        slot power
+        creator: platform
+        consumer: p9_pcie_hotplug
+        firmware notes:
+        Primary array index: Sequence number
+        Secondary array index: Address (0) / Data (1)
+    </description>
+    <simpleType>
+        <uint8_t></uint8_t>
+        <array>8,2</array>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_PROC_PCIE_HOTPLUG_DISABLE_ACTIONS</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>PROC_PCIE_HOTPLUG_NUM_DISABLE_ACTIONS</id>
+    <!-- TARGET_TYPE_PROC_CHIP -->
+    <description>
+        Number of valid entries in primary index of
+        ATTR_PROC_PCIE_HOTPLUG_DISABLE_ACTIONS
+        creator: platform
+        consumer: p9_pcie_hotplug
 
+        ZERO = 0x0,
+        ONE = 0x1,
+        TWO = 0x2,
+        THREE = 0x3,
+        FOUR = 0x4,
+        FIVE = 0x5,
+        SIX = 0x6,
+        SEVEN = 0x7,
+        EIGHT = 0x8
+    </description>
+    <simpleType>
+        <uint8_t></uint8_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_PROC_PCIE_HOTPLUG_NUM_DISABLE_ACTIONS</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
 
 <attribute>
     <id>PROC_PCIE_PCS_RX_CDR_GAIN</id>
@@ -22021,6 +22105,322 @@ Measured in GB</description>
 </attribute>
 
 <attribute>
+  <id>PROC_PCIE_IOP_G3_PLL_CONTROL0</id><!-- @deprecated -->
+  <description>
+      creator: platform (MRW)
+      consumer: p9_pcie_scominit
+      firmware notes:
+        PCIe Gen3 PLL Control Register 0.
+        ATUNE/CPISEL.
+  </description>
+  <simpleType>
+      <uint32_t></uint32_t>
+  </simpleType>
+  <persistency>volatile-zeroed</persistency>
+  <readable/>
+  <hwpfToHbAttrMap>
+      <id>ATTR_PROC_PCIE_IOP_G3_PLL_CONTROL0</id>
+      <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+  <id>PROC_PCIE_IOP_G2_PLL_CONTROL0</id><!-- @deprecated -->
+  <description>
+      creator: platform (MRW)
+      consumer: p9_pcie_scominit
+      firmware notes:
+        PCIe Gen2/Gen1 PLL Control Register 0.
+        ATUNE/CPISEL.
+  </description>
+  <simpleType>
+      <uint32_t></uint32_t>
+  </simpleType>
+  <persistency>volatile-zeroed</persistency>
+  <readable/>
+  <hwpfToHbAttrMap>
+      <id>ATTR_PROC_PCIE_IOP_G2_PLL_CONTROL0</id>
+      <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+  <id>PROC_PCIE_IOP_PLL_GLOBAL_CONTROL0</id><!-- @deprecated -->
+  <description>
+      creator: platform (MRW)
+      consumer: p9_pcie_scominit
+      notes:
+        PCIe PLL Global Control Register 0.
+        REFISRC/REFISINK.
+  </description>
+  <simpleType>
+      <uint32_t></uint32_t>
+  </simpleType>
+  <persistency>volatile-zeroed</persistency>
+  <readable/>
+  <hwpfToHbAttrMap>
+      <id>ATTR_PROC_PCIE_IOP_PLL_GLOBAL_CONTROL0</id>
+      <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+  <id>PROC_PCIE_IOP_PLL_GLOBAL_CONTROL1</id><!-- @deprecated -->
+  <description>
+      creator: platform (MRW)
+      consumer: p9_pcie_scominit
+      notes:
+        PCIe PLL Global Control Register 1.
+    ENBGDOCPSRC/ENBGDOCAMP/REFVREG.
+  </description>
+  <simpleType>
+      <uint32_t></uint32_t>
+  </simpleType>
+  <persistency>volatile-zeroed</persistency>
+  <readable/>
+  <hwpfToHbAttrMap>
+      <id>ATTR_PROC_PCIE_IOP_PLL_GLOBAL_CONTROL1</id>
+      <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+  <id>PROC_PCIE_IOP_PCS_CONTROL0</id><!-- @deprecated -->
+  <description>
+      creator: platform (MRW)
+      consumer: p9_pcie_scominit
+      notes:
+        PCIe PCS Control Register 0.
+        BITLOCKTIME/ADDDREMDELTA_810_B/STARTUPDELTA_810_B/ADDDREMDELTA_810_A/
+        STARTUPDELTA_A/RXREJECTHANDLING/EQCOMLETERESPONSE.
+  </description>
+  <simpleType>
+      <uint32_t></uint32_t>
+  </simpleType>
+  <persistency>volatile-zeroed</persistency>
+  <readable/>
+  <hwpfToHbAttrMap>
+      <id>ATTR_PROC_PCIE_IOP_PCS_CONTROL0</id>
+      <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+  <id>PROC_PCIE_IOP_PCS_CONTROL1</id><!-- @deprecated -->
+  <description>
+      creator: platform (MRW)
+      consumer: p9_pcie_scominit
+      notes:
+        PCIe PCS Control Register 1.
+    RXSIGDETSETTING/ADDDREMDELTA_128130_B/STARTUPDELTA_128130_B/
+        ADDDREMDELTA_128130_A/STARTUPDELTA_128130_A.
+  </description>
+  <simpleType>
+      <uint32_t></uint32_t>
+  </simpleType>
+  <persistency>volatile-zeroed</persistency>
+  <readable/>
+  <hwpfToHbAttrMap>
+      <id>ATTR_PROC_PCIE_IOP_PCS_CONTROL1</id>
+      <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+  <id>PROC_PCIE_IOP_TX_FIFO_OFFSET</id><!-- @deprecated -->
+  <description>
+      creator: platform (MRW)
+      consumer: p9_pcie_scominit
+      notes:
+        PCIe TX FIFO Offset Register.
+    G3OFFSET/G2OFFSET/G1OFFSET.
+        Array index: Lane number (0:15)
+  </description>
+  <simpleType>
+      <uint32_t></uint32_t>
+      <array>16</array>
+  </simpleType>
+  <persistency>volatile-zeroed</persistency>
+  <readable/>
+  <hwpfToHbAttrMap>
+      <id>ATTR_PROC_PCIE_IOP_TX_FIFO_OFFSET</id>
+      <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+  <id>PROC_PCIE_IOP_TX_RCVRDETCNTL</id><!-- @deprecated -->
+  <description>
+      creator: platform (MRW)
+      consumer: p9_pcie_scominit
+      notes:
+        PCIe TX Receiver Detect Control Register.
+        VREFSEL/RCVRDETCNT/DETDRVC/PH1WAIT.
+        Array index: Lane number (0:15)
+  </description>
+  <simpleType>
+      <uint32_t></uint32_t>
+      <array>16</array>
+  </simpleType>
+  <persistency>volatile-zeroed</persistency>
+  <readable/>
+  <hwpfToHbAttrMap>
+      <id>ATTR_PROC_PCIE_IOP_TX_RCVRDETCNTL</id>
+      <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+  <id>PROC_PCIE_IOP_TX_BWLOSS1</id><!-- @deprecated -->
+  <description>
+      creator: platform (MRW)
+      consumer: p9_pcie_scominit
+      notes:
+        PCIe TX Bandwidth Loss Coefficient Register.
+        GEN3BWCOEFF/GEN2BWCOEFF/GEN1BWCOEFF.
+        Array index: Lane number (0:15)
+  </description>
+  <simpleType>
+      <uint32_t></uint32_t>
+      <array>16</array>
+  </simpleType>
+  <persistency>volatile-zeroed</persistency>
+  <readable/>
+  <hwpfToHbAttrMap>
+      <id>ATTR_PROC_PCIE_IOP_TX_BWLOSS1</id>
+      <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+  <id>PROC_PCIE_IOP_RX_VGA_CONTROL2</id><!-- @deprecated -->
+  <description>
+      creator: platform (MRW)
+      consumer: p9_pcie_scominit
+      notes:
+        PCIe RX VGA Control Register 2.
+        GAIN2/GAIN1.
+        Array index: Lane number (0:15)
+  </description>
+  <simpleType>
+      <uint32_t></uint32_t>
+      <array>16</array>
+  </simpleType>
+  <persistency>volatile-zeroed</persistency>
+  <readable/>
+  <hwpfToHbAttrMap>
+      <id>ATTR_PROC_PCIE_IOP_RX_VGA_CONTROL2</id>
+      <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+  <id>PROC_PCIE_IOP_RX_PEAK</id><!-- @deprecated -->
+  <description>
+      creator: platform (MRW)
+      consumer: p9_pcie_scominit
+      notes:
+        PCIe RX Receiver Peaking Value Register.
+    PEAK1/PEAK2/PEAK3.
+        Array index: Lane number (0:15)
+  </description>
+  <simpleType>
+      <uint32_t></uint32_t>
+      <array>16</array>
+  </simpleType>
+  <persistency>volatile-zeroed</persistency>
+  <readable/>
+  <hwpfToHbAttrMap>
+      <id>ATTR_PROC_PCIE_IOP_RX_PEAK</id>
+      <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+  <id>PROC_PCIE_IOP_RX_SDL</id><!-- @deprecated -->
+  <description>
+      creator: platform (MRW)
+      consumer: p9_pcie_scominit
+      notes:
+        PCIe RX Signal Detect Level Register.
+        SDLVL3/SDLVL2/SDLVL1.
+        Array index: Lane number (0:15)
+  </description>
+  <simpleType>
+      <uint32_t></uint32_t>
+      <array>16</array>
+  </simpleType>
+  <persistency>volatile-zeroed</persistency>
+  <readable/>
+  <hwpfToHbAttrMap>
+      <id>ATTR_PROC_PCIE_IOP_RX_SDL</id>
+      <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+  <id>PROC_PCIE_IOP_ZCAL_CONTROL</id><!-- @deprecated -->
+  <description>
+      creator: platform (MRW)
+      consumer: p9_pcie_scominit
+      notes:
+        PCIe ZCAL Control Register.
+        CMPEVALDLY.
+  </description>
+  <simpleType>
+      <uint32_t></uint32_t>
+  </simpleType>
+  <persistency>volatile-zeroed</persistency>
+  <readable/>
+  <hwpfToHbAttrMap>
+      <id>ATTR_PROC_PCIE_IOP_ZCAL_CONTROL</id>
+      <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+  <id>PROC_PCIE_IOP_TX_FFE_GEN1</id><!-- @deprecated -->
+    <description>
+      creator: platform (MRW)
+      consumer: p9_pcie_scominit
+      notes:
+        PCIe TX FFE (Gen1)
+        Array index: Lane number (0:15)
+    </description>
+  <simpleType>
+      <uint32_t></uint32_t>
+      <array>16</array>
+  </simpleType>
+  <persistency>volatile-zeroed</persistency>
+  <readable/>
+  <hwpfToHbAttrMap>
+      <id>ATTR_PROC_PCIE_IOP_TX_FFE_GEN1</id>
+      <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+  <id>PROC_PCIE_IOP_TX_FFE_GEN2</id><!-- @deprecated -->
+    <description>
+      creator: platform (MRW)
+      consumer: p9_pcie_scominit
+      notes:
+        PCIe TX FFE (Gen2)
+        Array index: Lane number (0:15)
+    </description>
+  <simpleType>
+      <uint32_t></uint32_t>
+      <array>16</array>
+  </simpleType>
+  <persistency>volatile-zeroed</persistency>
+  <readable/>
+  <hwpfToHbAttrMap>
+      <id>ATTR_PROC_PCIE_IOP_TX_FFE_GEN2</id>
+      <macro>DIRECT</macro>
+  </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
     <id>IO_XBUS_DCCAL_FLAGS</id>
     <!-- <targetType>TARGET_TYPE_XBUS</targetType> -->
     <description>
@@ -31931,4 +32331,67 @@ Measured in GB</description>
     </hwpfToHbAttrMap>
 </attribute>
 
+<attribute>
+    <id>EFF_DRAM_RTT_NOM</id>
+    <description>
+        RTT_NOM value read to be programmed into MRS02
+        For RDIMMS, this is based off of the VPD
+        For LRDIMMS, this comes from the SPD
+    </description>
+    <simpleType>
+        <uint8_t>
+        </uint8_t>
+        <array>2,2,4</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DRAM_RTT_NOM</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_DRAM_RTT_WR</id>
+    <description>
+        RTT_WR value read to be programmed into MRS02
+        For RDIMMS, this is based off of the VPD
+        For LRDIMMS, this comes from the SPD
+    </description>
+    <simpleType>
+        <uint8_t>
+        </uint8_t>
+        <array>2,2,4</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DRAM_RTT_WR</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
+<attribute>
+    <id>EFF_DRAM_RTT_PARK</id>
+    <description>
+        RTT_PARK value read to be programmed into MRS05
+        For RDIMMS, this is based off of the VPD
+        For LRDIMMS, this comes from the SPD
+    </description>
+    <simpleType>
+        <uint8_t>
+        </uint8_t>
+        <array>2,2,4</array>
+    </simpleType>
+    <persistency>volatile-zeroed</persistency>
+    <readable/>
+    <writeable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_EFF_DRAM_RTT_PARK</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
+
 </attributes>
diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml
index b4f36c019..2a2fd82d7 100755
--- a/src/usr/targeting/common/xmltohb/target_types.xml
+++ b/src/usr/targeting/common/xmltohb/target_types.xml
@@ -5,7 +5,7 @@
 <!--                                                                        -->
 <!-- OpenPOWER HostBoot Project                                             -->
 <!--                                                                        -->
-<!-- Contributors Listed Below - COPYRIGHT 2012,2016                        -->
+<!-- Contributors Listed Below - COPYRIGHT 2012,2017                        -->
 <!-- [+] Google Inc.                                                        -->
 <!-- [+] International Business Machines Corp.                              -->
 <!--                                                                        -->
@@ -1817,6 +1817,9 @@
     <attribute><id>MSS_DIMM_THERMAL_LIMIT</id></attribute>
     <attribute><id>MSS_VREF_CAL_ENABLE</id></attribute>
     <attribute><id>MSS_MRW_UNSUPPORTED_RANK_CONFIG</id></attribute>
+    <attribute><id>EFF_DRAM_RTT_NOM</id></attribute>
+    <attribute><id>EFF_DRAM_RTT_WR</id></attribute>
+    <attribute><id>EFF_DRAM_RTT_PARK</id></attribute>
 </targetType>
 
 <targetType>