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| author | Dan Crowell <dcrowell@us.ibm.com> | 2019-05-31 14:06:03 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2019-06-20 09:28:45 -0500 |
| commit | 1d850029be30edff0f2e660e1f28cb50ae3f2411 (patch) | |
| tree | cbe233925f6f6921c5390681c2b6b68050ff7d7d /src/usr/targeting | |
| parent | be08f8a9709979d2415ae21cd1e7fdd9c47ede2c (diff) | |
| download | talos-hostboot-1d850029be30edff0f2e660e1f28cb50ae3f2411.tar.gz talos-hostboot-1d850029be30edff0f2e660e1f28cb50ae3f2411.zip | |
Force appropriate values for NPU config
Hostboot will do no configuration of the NPUs during boot. Instead
all of the configuration will happen at the OS level.
Change-Id: I78c0bd06053524e9af981f1175c05281e5fdced4
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/78181
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/usr/targeting')
| -rw-r--r-- | src/usr/targeting/common/xmltohb/hb_customized_attrs.xml | 69 |
1 files changed, 69 insertions, 0 deletions
diff --git a/src/usr/targeting/common/xmltohb/hb_customized_attrs.xml b/src/usr/targeting/common/xmltohb/hb_customized_attrs.xml index 25daef3dc..f20120912 100644 --- a/src/usr/targeting/common/xmltohb/hb_customized_attrs.xml +++ b/src/usr/targeting/common/xmltohb/hb_customized_attrs.xml @@ -418,6 +418,7 @@ <no_export/> </attribute> + <!-- Firmware boots rely on the hypervisor/os to enable the NPUs --> <attribute> <id>ATTR_PROC_NPU_PHY0_BAR_ENABLE</id> <default>0</default> @@ -455,6 +456,74 @@ </attribute> <attribute> + <id>ATTR_PROC_NPU_MMIO_BAR_ENABLE</id> + <default>0</default> + <no_export/> + </attribute> + + <attribute> + <id>ATTR_PROC_NPU0_MMIO_BAR_ENABLE</id> + <default>0</default> + <no_export/> + </attribute> + + <attribute> + <id>ATTR_PROC_NPU1_MMIO_BAR_ENABLE</id> + <default>0</default> + <no_export/> + </attribute> + + <attribute> + <id>ATTR_PROC_NPU2_MMIO_BAR_ENABLE</id> + <default>0</default> + <no_export/> + </attribute> + + <attribute> + <id>ATTR_PROC_NPU_MMIO_BAR_BASE_ADDR_OFFSET</id> + <default>0x0000030200000000</default> + <no_export/> + </attribute> + + <attribute> + <id>ATTR_PROC_NPU0_MMIO_BAR_BASE_ADDR_OFFSET</id> + <default>0x0</default> + <no_export/> + </attribute> + + <attribute> + <id>ATTR_PROC_NPU1_MMIO_BAR_BASE_ADDR_OFFSET</id> + <default>0x0</default> + <no_export/> + </attribute> + + <attribute> + <id>ATTR_PROC_NPU2_MMIO_BAR_BASE_ADDR_OFFSET</id> + <default>0x0</default> + <no_export/> + </attribute> + + <attribute> + <id>ATTR_PROC_NPU0_PRI_CONFIG</id> + <default>0x0,0x0,0x0,0x0</default> + <no_export/> + </attribute> + + <attribute> + <id>ATTR_PROC_NPU1_PRI_CONFIG</id> + <default>0x0,0x0,0x0,0x0</default> + <no_export/> + </attribute> + + <attribute> + <id>ATTR_PROC_NPU2_PRI_CONFIG</id> + <default>0x0,0x0,0x0,0x0</default> + <no_export/> + </attribute> + + <!-- end NPU config --> + + <attribute> <id>ATTR_PROC_NX_RNG_BAR_ENABLE</id> <default>0</default> <no_export/> |
