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| author | Nick Bofferding <bofferdn@us.ibm.com> | 2014-10-14 17:11:08 -0500 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2014-10-21 13:04:27 -0500 |
| commit | 198e80b53d58c506c0db4d5de4eb5b8e4bed2aed (patch) | |
| tree | 39584598948756cf0a4fa826f94fc9d75e0d0998 /src/usr/targeting/common/xmltohb/vbu_NAPLES.system.xml | |
| parent | ffe1209fc922a571cc9fc6864c7f437b230aa8af (diff) | |
| download | talos-hostboot-198e80b53d58c506c0db4d5de4eb5b8e4bed2aed.tar.gz talos-hostboot-198e80b53d58c506c0db4d5de4eb5b8e4bed2aed.zip | |
Move FSP-only attributes to common targeting for Open Power
- Added default lane masks to Hostboot system XML files
- Added PCIE config related module IDs and reason codes
- Added new packing function to combine 4x uint8 into 1x uint32
- Added dynamic PCIE config for SP-less environments
- Moved PCIE attributes into common attribute definition
- Attached new PCIE attributes to common target definition
- Defaulted PCIE lanes per proc appropriately for all proc chips
- Added CDM_DOMAIN attribute into common attribute definition
- Attached + defaulted CDM domain in common target definition
- Updated common MRW parser to customize the new PCIE attributes
Change-Id: I3779ca6e6a4803d7e78e21e47a92e0b1a09e657d
RTC: 113488
CMVC-coreq: 942076
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/13997
Tested-by: Jenkins Server
Reviewed-by: STEPHEN M. CPREK <smcprek@us.ibm.com>
Reviewed-by: Andrew J. Geissler <andrewg@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr/targeting/common/xmltohb/vbu_NAPLES.system.xml')
| -rw-r--r-- | src/usr/targeting/common/xmltohb/vbu_NAPLES.system.xml | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/src/usr/targeting/common/xmltohb/vbu_NAPLES.system.xml b/src/usr/targeting/common/xmltohb/vbu_NAPLES.system.xml index bf10d5860..732d0e7ef 100644 --- a/src/usr/targeting/common/xmltohb/vbu_NAPLES.system.xml +++ b/src/usr/targeting/common/xmltohb/vbu_NAPLES.system.xml @@ -516,6 +516,10 @@ <id>PROC_PCIE_PHB_ACTIVE</id> <default>0xE0</default> </attribute> + <attribute> + <id>PROC_PCIE_LANE_MASK_NON_BIFURCATED</id> + <default>0xFFFF,0x0000,0xFFFF,0x0000</default> + </attribute> </targetInstance> <!-- Naples n0p0 EX units @@ -962,6 +966,10 @@ <attribute><id>RNG_BASE_ADDR</id> <default>0x0003FFFF40001000</default> </attribute> + <attribute> + <id>PROC_PCIE_LANE_MASK_NON_BIFURCATED</id> + <default>0xFFFF,0x0000,0xFFFF,0x0000</default> + </attribute> </targetInstance> <!-- Naples n0p1 EX units @@ -1386,6 +1394,10 @@ <attribute><id>RNG_BASE_ADDR</id> <default>0x0003FFFF40002000</default> </attribute> + <attribute> + <id>PROC_PCIE_LANE_MASK_NON_BIFURCATED</id> + <default>0xFFFF,0x0000,0xFFFF,0x0000</default> + </attribute> </targetInstance> <!-- Naples n2p0 EX units @@ -1811,6 +1823,10 @@ <attribute><id>RNG_BASE_ADDR</id> <default>0x0003FFFF40003000</default> </attribute> + <attribute> + <id>PROC_PCIE_LANE_MASK_NON_BIFURCATED</id> + <default>0xFFFF,0x0000,0xFFFF,0x0000</default> + </attribute> </targetInstance> <!-- Naples n2p1 EX units |
