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| author | Mike Baiocchi <baiocchi@us.ibm.com> | 2015-06-19 03:51:14 -0500 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2015-07-29 09:44:29 -0500 |
| commit | d92d751ca50a2ca19bdbdec06ed4ad05339eaf3e (patch) | |
| tree | 635d4f8a53bdfc7f90d28d325802a38b7d3a829b /src/usr/targeting/common/xmltohb/target_types.xml | |
| parent | 296fe5b3960936275c3a1829581b10d5a4894828 (diff) | |
| download | talos-hostboot-d92d751ca50a2ca19bdbdec06ed4ad05339eaf3e.tar.gz talos-hostboot-d92d751ca50a2ca19bdbdec06ed4ad05339eaf3e.zip | |
Changes for Brazos 2z/3z Support
This commit has the hostboot changes for Brazos 2z/3z support along with
some attributes that Hostboot and HWSV share. It also contains memory
XML and HWP changes from SW305517 and SW305518.
Change-Id: I71896dfac6946624bed3e216fe7823bd73e8e6bc
RTC: 125037
CQ:SW305518
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/19306
Reviewed-by: PRACHI GUPTA <pragupta@us.ibm.com>
Reviewed-by: STEPHEN GLANCY <sglancy@us.ibm.com>
Reviewed-by: Michael D. Pardeik <pardeik@us.ibm.com>
Reviewed-by: Michael Baiocchi <baiocchi@us.ibm.com>
Tested-by: Michael Baiocchi <baiocchi@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/19375
Tested-by: Jenkins Server
Tested-by: Jenkins OP Build CI
Reviewed-by: WILLIAM G. HOFFA <wghoffa@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Tested-by: Jenkins OP HW
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr/targeting/common/xmltohb/target_types.xml')
| -rw-r--r-- | src/usr/targeting/common/xmltohb/target_types.xml | 28 |
1 files changed, 22 insertions, 6 deletions
diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml index e85502f92..0d1de1f5a 100644 --- a/src/usr/targeting/common/xmltohb/target_types.xml +++ b/src/usr/targeting/common/xmltohb/target_types.xml @@ -263,12 +263,6 @@ <attribute><id>MSS_CENT_AVDD_SLOPE_ACTIVE</id></attribute> <attribute><id>MSS_CENT_AVDD_SLOPE_INACTIVE</id></attribute> <attribute><id>MSS_CENT_AVDD_INTERCEPT</id></attribute> - <attribute><id>MSS_CENT_VDD_SLOPE_ACTIVE</id></attribute> - <attribute><id>MSS_CENT_VDD_SLOPE_INACTIVE</id></attribute> - <attribute><id>MSS_CENT_VDD_INTERCEPT</id></attribute> - <attribute><id>MSS_CENT_VCS_SLOPE_ACTIVE</id></attribute> - <attribute><id>MSS_CENT_VCS_SLOPE_INACTIVE</id></attribute> - <attribute><id>MSS_CENT_VCS_INTERCEPT</id></attribute> <attribute><id>MSS_VOLT_VPP_SLOPE</id></attribute> <attribute><id>MSS_VOLT_VPP_INTERCEPT</id></attribute> <attribute><id>MSS_VOLT_DDR3_VDDR_SLOPE</id></attribute> @@ -920,6 +914,28 @@ <attribute><id>TPM_BACKUP_INFO</id></attribute> <attribute><id>EEPROM_VPD_PRIMARY_INFO</id></attribute> <attribute><id>VPD_REC_NUM</id></attribute> + <attribute><id>MSS_CENT_VDD_SLOPE_ACTIVE</id></attribute> + <attribute><id>MSS_CENT_VDD_SLOPE_INACTIVE</id></attribute> + <attribute><id>MSS_CENT_VDD_INTERCEPT</id></attribute> + <attribute><id>MSS_CENT_VCS_SLOPE_ACTIVE</id></attribute> + <attribute><id>MSS_CENT_VCS_SLOPE_INACTIVE</id></attribute> + <attribute><id>MSS_CENT_VCS_INTERCEPT</id></attribute> + <attribute><id>MSS_VOLT_VPP_SLOPE_POST_DRAM_INIT</id></attribute> + <attribute><id>MSS_VOLT_VPP_INTERCEPT_POST_DRAM_INIT</id></attribute> + <attribute><id>MSS_VOLT_VPP_SLOPE_EFF_CONFIG</id></attribute> + <attribute><id>MSS_VOLT_VPP_INTERCEPT_EFF_CONFIG</id></attribute> + <attribute><id>MRW_DDR3_VDDR_MAX_LIMIT_POST_DRAM_INIT</id></attribute> + <attribute><id>MRW_DDR4_VDDR_MAX_LIMIT_POST_DRAM_INIT</id></attribute> + <attribute><id>MRW_DDR3_VDDR_MAX_LIMIT_EFF_CONFIG</id></attribute> + <attribute><id>MRW_DDR4_VDDR_MAX_LIMIT_EFF_CONFIG</id></attribute> + <attribute><id>MSS_VOLT_DDR3_VDDR_SLOPE_POST_DRAM_INIT</id></attribute> + <attribute><id>MSS_VOLT_DDR3_VDDR_INTERCEPT_POST_DRAM_INIT</id></attribute> + <attribute><id>MSS_VOLT_DDR3_VDDR_SLOPE_EFF_CONFIG</id></attribute> + <attribute><id>MSS_VOLT_DDR3_VDDR_INTERCEPT_EFF_CONFIG</id></attribute> + <attribute><id>MSS_VOLT_DDR4_VDDR_SLOPE_POST_DRAM_INIT</id></attribute> + <attribute><id>MSS_VOLT_DDR4_VDDR_INTERCEPT_POST_DRAM_INIT</id></attribute> + <attribute><id>MSS_VOLT_DDR4_VDDR_SLOPE_EFF_CONFIG</id></attribute> + <attribute><id>MSS_VOLT_DDR4_VDDR_INTERCEPT_EFF_CONFIG</id></attribute> </targetType> <targetType> |
