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author | Stephen Cprek <smcprek@us.ibm.com> | 2013-11-14 16:08:29 -0600 |
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committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2013-12-02 16:01:23 -0600 |
commit | f827f40812a56d64960a9810c5c75df7e1c78256 (patch) | |
tree | d0d6510a6367f40cafcfc98748d6d7b895609324 /src/usr/targeting/common/xmltohb/simics_VENICE.system.xml | |
parent | 24f1be401fef97a5a13cf39b9f507adb8cd5af32 (diff) | |
download | talos-hostboot-f827f40812a56d64960a9810c5c75df7e1c78256.tar.gz talos-hostboot-f827f40812a56d64960a9810c5c75df7e1c78256.zip |
Added PORE target support
Change-Id: If36fbeaf629375b7158b29d44fc0ead5b3d33304
RTC: 89232
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/7255
Tested-by: Jenkins Server
Reviewed-by: Brian H. Horton <brianh@linux.ibm.com>
Reviewed-by: SHELDON R. BAILEY <baileysh@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr/targeting/common/xmltohb/simics_VENICE.system.xml')
-rw-r--r-- | src/usr/targeting/common/xmltohb/simics_VENICE.system.xml | 159 |
1 files changed, 159 insertions, 0 deletions
diff --git a/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml b/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml index 5348557df..288f1c80d 100644 --- a/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml +++ b/src/usr/targeting/common/xmltohb/simics_VENICE.system.xml @@ -1438,6 +1438,26 @@ </attribute> </targetInstance> +<!-- venice n0p0 PORE unit --> + +<targetInstance> + <id>sys0node0proc0pore0</id> + <type>unit-pore-venice</type> + <attribute><id>HUID</id><default>0x001F0000</default></attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-0/pore-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>physical:sys-0/node-0/proc-0/pore-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> +</targetInstance> + <!-- Venice n0p1 processor chip --> <targetInstance> @@ -2595,6 +2615,25 @@ </attribute> </targetInstance> +<!-- venice n0p1 PORE unit --> + +<targetInstance> + <id>sys0node0proc1pore0</id> + <type>unit-pore-venice</type> + <attribute><id>HUID</id><default>0x001F0001</default></attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-1/pore-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>physical:sys-0/node-0/proc-1/pore-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> +</targetInstance> <!-- Venice n0p2 processor chip --> @@ -3754,6 +3793,26 @@ </attribute> </targetInstance> +<!-- venice n0p2 PORE unit --> + +<targetInstance> + <id>sys0node0proc2pore0</id> + <type>unit-pore-venice</type> + <attribute><id>HUID</id><default>0x001F0002</default></attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-2/pore-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>physical:sys-0/node-0/proc-2/pore-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> +</targetInstance> + <!-- Venice n0p3 processor chip --> @@ -4912,6 +4971,26 @@ </attribute> </targetInstance> +<!-- venice n0p3 PORE unit --> + +<targetInstance> + <id>sys0node0proc3pore0</id> + <type>unit-pore-venice</type> + <attribute><id>HUID</id><default>0x001F0003</default></attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-3/pore-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>physical:sys-0/node-0/proc-3/pore-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> +</targetInstance> + <!-- Venice n0p4 processor chip --> <targetInstance> @@ -6038,6 +6117,26 @@ </attribute> </targetInstance> +<!-- venice n0p4 PORE unit --> + +<targetInstance> + <id>sys0node0proc4pore0</id> + <type>unit-pore-venice</type> + <attribute><id>HUID</id><default>0x001F0004</default></attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-4/pore-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>physical:sys-0/node-0/proc-4/pore-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> +</targetInstance> + <!-- Venice n0p5 processor chip --> <targetInstance> @@ -7162,6 +7261,26 @@ </attribute> </targetInstance> +<!-- venice n0p5 PORE unit --> + +<targetInstance> + <id>sys0node0proc5pore0</id> + <type>unit-pore-venice</type> + <attribute><id>HUID</id><default>0x001F0005</default></attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-5/pore-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>physical:sys-0/node-0/proc-5/pore-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> +</targetInstance> + <!-- Venice n0p6 processor chip --> <targetInstance> @@ -8286,6 +8405,26 @@ </attribute> </targetInstance> +<!-- venice n0p6 PORE unit --> + +<targetInstance> + <id>sys0node0proc6pore0</id> + <type>unit-pore-venice</type> + <attribute><id>HUID</id><default>0x001F0006</default></attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-6/pore-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>physical:sys-0/node-0/proc-6/pore-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> +</targetInstance> + <!-- Venice n0p7 processor chip --> <targetInstance> @@ -9409,6 +9548,26 @@ </attribute> </targetInstance> +<!-- venice n0p7 PORE unit --> + +<targetInstance> + <id>sys0node0proc7pore0</id> + <type>unit-pore-venice</type> + <attribute><id>HUID</id><default>0x001F0007</default></attribute> + <attribute> + <id>PHYS_PATH</id> + <default>physical:sys-0/node-0/proc-7/pore-0</default> + </attribute> + <attribute> + <id>AFFINITY_PATH</id> + <default>physical:sys-0/node-0/proc-7/pore-0</default> + </attribute> + <attribute> + <id>CHIP_UNIT</id> + <default>0</default> + </attribute> +</targetInstance> + <!-- Centaur n0p0 : start --> <targetInstance> |