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authorMike Baiocchi <mbaiocch@us.ibm.com>2018-07-03 09:29:59 -0500
committerWilliam G. Hoffa <wghoffa@us.ibm.com>2018-07-06 23:26:48 -0400
commita76fe8f24e07ab143cdd8591983c12925eae281a (patch)
tree6fea8349987aeed1ab8d84af47a246735eb575a3 /src/usr/sbeio
parentea5c84fe7741f94fb1198483f9e833fcaae202e5 (diff)
downloadtalos-hostboot-a76fe8f24e07ab143cdd8591983c12925eae281a.tar.gz
talos-hostboot-a76fe8f24e07ab143cdd8591983c12925eae281a.zip
Read HW Key Hash From SBE Seeprom via ChipOp when applicable
This commit uses SBEIO ChipOps to read the HW Key Hash from the SBE Seeprom when reading from the Seeprom that booted the processor. This will help avoid I2C collisions when both Hostboot and the SBE try to access the same SBE Seeprom at the same time. Change-Id: I5693cc59aa2a7259f07363328bd8513c943f0a06 CQ:SW435288 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61958 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Diffstat (limited to 'src/usr/sbeio')
-rw-r--r--src/usr/sbeio/sbe_psuReadSeeprom.C24
1 files changed, 15 insertions, 9 deletions
diff --git a/src/usr/sbeio/sbe_psuReadSeeprom.C b/src/usr/sbeio/sbe_psuReadSeeprom.C
index 9550b0cdd..bf8e59dac 100644
--- a/src/usr/sbeio/sbe_psuReadSeeprom.C
+++ b/src/usr/sbeio/sbe_psuReadSeeprom.C
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2012,2017 */
+/* Contributors Listed Below - COPYRIGHT 2012,2018 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -41,20 +41,17 @@ TRACDCOMP(g_trac_sbeio,"psuReadSeeprom: " printf_string,##args)
#define SBE_TRACF(printf_string,args...) \
TRACFCOMP(g_trac_sbeio,"psuReadSeeprom: " printf_string,##args)
+#define READ_SEEPROM_SIZE_ALIGNMENT_BYTES 128
+#define READ_SEEPROM_DEST_ADDR_ALIGNMENT_BYTES 8
+
+
namespace SBEIO
{
/**
* @brief Sends a PSU chipOp to request Seeprom read from SBE
*
- * @param[in] i_target Target with SBE to send read request to
- * @param[in] i_seepromOffset Offset in the seeprom image where we want
- * to start copying from (ignores ECC)
- * @param[in] i_readSize Amount of bytes we want to copy (ignores ECC)
- * @param[in] i_destAddr Address that hostboot has prepared which the
- * sbe will write too
- * @param[out] o_opSupported Bool which tells us if the sbe supports the
- * chipOp or not
+ * @note - details in sbeioif.H
*
* @return errlHndl_t Error log handle on failure.
*
@@ -69,6 +66,11 @@ namespace SBEIO
SBE_TRACD(ENTER_MRK "sending psu seeprom read request command from HB -> SBE");
+ // Verify input parameters meet restrictions
+ assert(i_target!=nullptr,"sendPsuReadSeeprom: i_target was nullptr");
+ assert((i_readSize % CHIPOP_READ_SEEPROM_SIZE_ALIGNMENT_BYTES) == 0,"sendPsuReadSeeprom: i_readSize 0x%X is not 128B aligned", i_readSize);
+ assert((i_destAddr % CHIPOP_READ_SEEPROM_DEST_ADDR_ALIGNMENT_BYTES) == 0,"sendPsuReadSeeprom: i_destAddr 0x%X is not 8B aligned", i_destAddr);
+
// set up PSU command message
SbePsu::psuCommand l_psuCommand(
SbePsu::SBE_REQUIRE_RESPONSE |
@@ -98,6 +100,10 @@ namespace SBEIO
errl = nullptr;
o_opSupported = false;
}
+ else
+ {
+ o_opSupported = true;
+ }
SBE_TRACD(EXIT_MRK "sendPsuReadSeeprom");
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