Insert bootloader image into SBE SEEPROM

4) Bootloader-related changes associated with Story 138226: Changes
for P9 SBE.

Change-Id: If9788c3bb2b56fbbaf4f668a1e153da79ad1757f
RTC: 139757
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28276
Reviewed-by: Matt Derksen <v2cibmd@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

1 files changed, 52 insertions, 0 deletions

diff --git a/src/usr/sbe/sbe_update.H b/src/usr/sbe/sbe_update.H
index bbeb105ba..79d3cae2a 100644
--- a/src/usr/sbe/sbe_update.H
+++ b/src/usr/sbe/sbe_update.H
@@ -95,6 +95,15 @@ namespace SBE
     const uint64_t NONSECURE_VER_EYECATCH = 0x56455253494F4E00; //'VERSION\0'
     const uint32_t SUPPORTED_TOC_VER = 0x00000001;
 
+    // PNOR HBBL Partition constants
+    const uint64_t HBBL_START_ADDRESS  = 0x0000000000003000;
+    const size_t   HBBL_MAX_SIZE       = 20*KILOBYTE;         // 20KB
+    const uint64_t HBBL_END_EYECATCHER = 0x4842424C656E6400;  // 'HBBLend\0'
+
+    // Cacheline Size and Mask
+    const uint64_t CACHELINE_SIZE = 128;
+    const uint64_t CACHELINE_MASK = CACHELINE_SIZE - 1;
+
     // MVPD SB Keyword contants
     const size_t  MVPD_SB_RECORD_SIZE = 129;
 
@@ -229,6 +238,15 @@ namespace SBE
     } PACKED;
 
     /**
+     * @brief Layout of Hostboot Bootloader (HBBL) end of load data
+     */
+    struct hbblEndData_t
+    {
+        uint64_t eyecatcher;                 // Expected to contain 'HBBLend\0'
+        uint64_t address;                    // bootloader.ld end_load_address
+    } PACKED;
+
+    /**
      * @brief Layout of SB keyword in MVPD
      */
     struct mvpdSbKeyword_t
@@ -378,6 +396,26 @@ namespace SBE
 
 
     /**
+     * @brief Append HBBL Immage to SBE Image
+     *
+     * @param[in] i_section          Pointer to HBBL Image to append
+     *
+     * @param[in] i_section_size     Cacheline size of HBBL Image
+     *
+     * @param[in] i_image            Pointer to SBE image in memory (non-ecc)
+     *
+     * @param[in/out] io_image_size  in: space available for enlarged XIP image
+     *                               out: size of enlarged XIP image
+     *
+     * @return errlHndl_t    Error log handle on failure.
+     */
+    errlHndl_t appendHbblToSbe(void*     i_section,
+                               uint32_t  i_section_size,
+                               void*     i_image,
+                               uint32_t& io_image_size);
+
+
+    /**
      * @brief Customize SBE Image for current Processor
      *
      * @param[in] i_target      Target processor to customize
@@ -594,6 +632,20 @@ namespace SBE
 
 
     /**
+     * @brief Calculates size for a block of code or data such that the block
+     *        can be aligned on cachelines.
+     *
+     * @param[in]  i_size     Size of block code or data
+     *
+     * @return Size of block adjusted to cacheline boundary
+     */
+    inline size_t setCachelineSize(size_t i_size)
+    {
+        return (i_size + CACHELINE_MASK) & ~(CACHELINE_MASK);
+    }
+
+
+    /**
      * @brief Calculates ECC size for a block of code or data allowing for
      *        padding at chip boundaries so 9-byte segment (8 bytes of code
      *        or data and 1 byte of ECC) does not straddle the boundary.