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author | Dean Sanner <dsanner@us.ibm.com> | 2014-09-18 15:00:23 -0500 |
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committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2014-10-21 08:17:52 -0500 |
commit | c7ea7224ea722c3930cb2605211246791ddb3932 (patch) | |
tree | 91e6f9a4c0e1ab05631e3b90a7db2e3342b6856f /src/usr/pnor | |
parent | c9cf241bc97ff6aba866d6acf167fd910a0f39c5 (diff) | |
download | talos-hostboot-c7ea7224ea722c3930cb2605211246791ddb3932.tar.gz talos-hostboot-c7ea7224ea722c3930cb2605211246791ddb3932.zip |
Update PNOR build script to handle two sides
Change-Id: I61db4d83ba8ea7ddc61c776625b43a07ee0039b0
RTC: 115870
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/13479
Tested-by: Jenkins Server
Reviewed-by: STEPHEN M. CPREK <smcprek@us.ibm.com>
Reviewed-by: WILLIAM G. HOFFA <wghoffa@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr/pnor')
-rw-r--r-- | src/usr/pnor/HBconfig | 4 | ||||
-rw-r--r-- | src/usr/pnor/pnordd.H | 1 | ||||
-rw-r--r-- | src/usr/pnor/sfc_ast2400.H | 10 |
3 files changed, 13 insertions, 2 deletions
diff --git a/src/usr/pnor/HBconfig b/src/usr/pnor/HBconfig index bc1ebc9dd..298144c8a 100644 --- a/src/usr/pnor/HBconfig +++ b/src/usr/pnor/HBconfig @@ -33,3 +33,7 @@ config ALLOW_MACRONIX_PNOR help Include support for Macronix PNOR chips +config PNOR_IS_32MB + default n + help + Size of the attached flash chip is 32MB, if not set then 64MB is default diff --git a/src/usr/pnor/pnordd.H b/src/usr/pnor/pnordd.H index 4b086e36b..589f60e27 100644 --- a/src/usr/pnor/pnordd.H +++ b/src/usr/pnor/pnordd.H @@ -135,7 +135,6 @@ class PnorDD LPC_SFC_CMDREG_OFFSET = 0xF0000C00, /** LPC Offest to SFC Cmd Regs */ LPC_SFC_CMDBUF_OFFSET = 0xF0000D00, /** LPC Off to SFC Cmd Buf space */ - LPC_TOP_OF_FLASH_OFFSET = 0xFFFFFFFF, ECCB_STAT_REG = 0x000B0022, /**< ECCB Status Reg (FW) */ diff --git a/src/usr/pnor/sfc_ast2400.H b/src/usr/pnor/sfc_ast2400.H index 7b4527c09..a76b66413 100644 --- a/src/usr/pnor/sfc_ast2400.H +++ b/src/usr/pnor/sfc_ast2400.H @@ -264,8 +264,16 @@ class SfcAST2400 : public SfcDD /** @brief General Constants */ enum { + LPC_TOP_OF_FLASH_OFFSET = 0x0FFFFFFF, +#ifdef CONFIG_PNOR_IS_32MB + PNOR_SIZE = 32*MEGABYTE, +#else //default to 64MB + PNOR_SIZE = 64*MEGABYTE, +#endif + //The direct offset value must be equal to <top of flash>-<pnor size>+1 + // for the SBE to work so we can rely on that same assertion /**< Offset to direct read space, from FW base */ - LPC_SFC_MMIO_OFFSET = 0x0E000000, + LPC_SFC_MMIO_OFFSET = LPC_TOP_OF_FLASH_OFFSET-PNOR_SIZE+1, /**< Offset to SPI Controller Register Space */ LPC_SFC_CTLR_BASE = 0x1E789000, |