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author | Adam Muhle <armuhle@us.ibm.com> | 2012-12-13 13:21:57 -0600 |
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committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2012-12-15 08:12:47 -0600 |
commit | f448a9337fa31ff7b83a5b00330818c54a495e73 (patch) | |
tree | 7642b526a20428811d820e88020e804ba31ca023 /src/usr/mvpd/test/mvpdtest.H | |
parent | 324f861e17b03b087e9b413bed2bc7180e7cb862 (diff) | |
download | talos-hostboot-f448a9337fa31ff7b83a5b00330818c54a495e73.tar.gz talos-hostboot-f448a9337fa31ff7b83a5b00330818c54a495e73.zip |
Full support for 8MB and 4MB cache sizes
Updating activate_thread to check if we're using fakePNOR
and if any of the L3 Cache is deconfigured. If all
8MB are available, it will make a call to extend Hostboot
memory to all 8MB.
Change-Id: Ib32c9aa02e643228382e2a72dcb780d2f78989fe
RTC: 49137
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/2683
Tested-by: Jenkins Server
Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr/mvpd/test/mvpdtest.H')
-rwxr-xr-x | src/usr/mvpd/test/mvpdtest.H | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/src/usr/mvpd/test/mvpdtest.H b/src/usr/mvpd/test/mvpdtest.H index 4befd407c..059b81c0c 100755 --- a/src/usr/mvpd/test/mvpdtest.H +++ b/src/usr/mvpd/test/mvpdtest.H @@ -87,52 +87,79 @@ mvpdTestData mvpdData[] = { LRP0, pdV }, { LRP0, pdP }, { LRP0, pdM }, + { LRP0, CH }, { LRP1, VD }, { LRP1, pdV }, { LRP1, pdP }, { LRP1, pdM }, + { LRP1, CH }, { LRP2, VD }, { LRP2, pdV }, { LRP2, pdP }, { LRP2, pdM }, + { LRP2, CH }, { LRP3, VD }, { LRP3, pdV }, { LRP3, pdP }, { LRP3, pdM }, + { LRP3, CH }, */ { LRP4, VD }, { LRP4, pdV }, { LRP4, pdP }, { LRP4, pdM }, + { LRP4, CH }, { LRP5, VD }, { LRP5, pdV }, { LRP5, pdP }, { LRP5, pdM }, + { LRP5, CH }, { LRP6, VD }, { LRP6, pdV }, { LRP6, pdP }, { LRP6, pdM }, + { LRP6, CH }, /* // TODO no LRP7,LRP8,LRP9,LRPA,LRPB,LWPO,LWP1,LWP2,LWP3 in test data, pull for now RTC 51716 { LRP7, VD }, { LRP7, pdV }, { LRP7, pdP }, { LRP7, pdM }, + { LRP7, CH }, { LRP8, VD }, { LRP8, pdV }, { LRP8, pdP }, { LRP8, pdM }, + { LRP8, CH }, { LRP9, VD }, { LRP9, pdV }, { LRP9, pdP }, { LRP9, pdM }, + { LRP9, CH }, { LRPA, VD }, { LRPA, pdV }, { LRPA, pdP }, { LRPA, pdM }, + { LRPA, CH }, { LRPB, VD }, { LRPB, pdV }, { LRPB, pdP }, { LRPB, pdM }, + { LRPB, CH }, + { LRPC, VD }, + { LRPC, pdV }, + { LRPC, pdP }, + { LRPC, pdM }, + { LRPC, CH }, + { LRPD, VD }, + { LRPD, pdV }, + { LRPD, pdP }, + { LRPD, pdM }, + { LRPD, CH }, + { LRPE, VD }, + { LRPE, pdV }, + { LRPE, pdP }, + { LRPE, pdM }, + { LRPE, CH }, { LWP0, VD }, { LWP0, pd2 }, { LWP0, pd3 }, @@ -183,6 +210,18 @@ mvpdTestData mvpdData[] = { LWPB, pd2 }, { LWPB, pd3 }, { LWPB, IN }, + { LWPC, VD }, + { LWPC, pd2 }, + { LWPC, pd3 }, + { LWPC, IN }, + { LWPD, VD }, + { LWPD, pd2 }, + { LWPD, pd3 }, + { LWPD, IN }, + { LWPE, VD }, + { LWPE, pd2 }, + { LWPE, pd3 }, + { LWPE, IN }, */ { VINI, DR }, { VINI, VZ }, |