diff options
| author | Bill Hoffa <wghoffa@us.ibm.com> | 2018-10-10 08:49:08 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2019-02-08 15:42:06 -0600 |
| commit | e36e0019e0b97ee66e649fd32a708e2905b26623 (patch) | |
| tree | bc8cb284194865a10d3c8f75f72a36bccf6d1643 /src/usr/lpc | |
| parent | dc1efdb95ce7198d29797abd165d6ce2fd30f5ad (diff) | |
| download | talos-hostboot-e36e0019e0b97ee66e649fd32a708e2905b26623.tar.gz talos-hostboot-e36e0019e0b97ee66e649fd32a708e2905b26623.zip | |
HBBL LPC Error Checking
- To avoid IPL delays, the LPC status register should be
checked prior to loading the entire PNOR image
(done via LPC). If an error condition occurs, HBBL
should fail out.
Change-Id: I5d716213f468e28191db794bf3e5480af547b26e
CQ: SW446254
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68442
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/usr/lpc')
| -rw-r--r-- | src/usr/lpc/lpcdd.C | 8 | ||||
| -rw-r--r-- | src/usr/lpc/lpcdd.H | 4 |
2 files changed, 5 insertions, 7 deletions
diff --git a/src/usr/lpc/lpcdd.C b/src/usr/lpc/lpcdd.C index 558ab4d5b..a661bb7f0 100644 --- a/src/usr/lpc/lpcdd.C +++ b/src/usr/lpc/lpcdd.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2014,2018 */ +/* Contributors Listed Below - COPYRIGHT 2014,2019 */ /* [+] Google Inc. */ /* [+] International Business Machines Corp. */ /* */ @@ -523,7 +523,7 @@ errlHndl_t LpcDD::hwReset( ResetLevels i_resetLevel ) uint32_t * l_status_ptr = reinterpret_cast<uint32_t*>(l_addr); //Clear under mask - aka write 1 clears - *l_status_ptr = OPB_ERROR_MASK; + *l_status_ptr = LPC::OPB_ERROR_MASK; eieio(); //Clear related bits in the LPCM OPB Master Accumulated @@ -534,7 +534,7 @@ errlHndl_t LpcDD::hwReset( ResetLevels i_resetLevel ) uint32_t * l_accum_status_ptr = reinterpret_cast<uint32_t*>(l_addr); //Clear under mask - aka write 1 clears - *l_accum_status_ptr = OPB_ERROR_MASK; + *l_accum_status_ptr = LPC::OPB_ERROR_MASK; eieio(); //Reset LPCHC Logic @@ -1116,7 +1116,7 @@ errlHndl_t LpcDD::checkForLpcErrors() eieio(); // Mask error bits - opbm_err_union.data32 = (opbm_buffer & OPB_ERROR_MASK); + opbm_err_union.data32 = (opbm_buffer & LPC::OPB_ERROR_MASK); lpchc_err_union.data32 = (lpchc_buffer & LPCHC_ERROR_MASK); // First look for errors in the OPBM bit mask diff --git a/src/usr/lpc/lpcdd.H b/src/usr/lpc/lpcdd.H index be7af6aef..e7f5397f1 100644 --- a/src/usr/lpc/lpcdd.H +++ b/src/usr/lpc/lpcdd.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2014,2017 */ +/* Contributors Listed Below - COPYRIGHT 2014,2019 */ /* [+] Google Inc. */ /* [+] International Business Machines Corp. */ /* */ @@ -214,8 +214,6 @@ class LpcDD /** LPC Host Controller Reset Register */ LPCHC_RESET_REG = 0x20FC, - OPB_ERROR_MASK = 0x20000FC3, /**< OPBM Error Bits MASK */ - LPCHC_ERROR_MASK = 0x000004FC /**< LPCHC Error Bits MASK */ }; |
