Add Functionality To Allow FSP to Enable TCEs For Testing

This commit adds an attribute that the FSP team can use to tell
Hostboot to enable the TCE path for DMAs.  When the FSP sets this
attribute, the hostboot code will initialize the TCE settings.

Change-Id: I24c71f31264645cac5840caad1b59b90fe465fb4
RTC:168745
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48036
Reviewed-by: Stephen M. Cprek <smcprek@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>

3 files changed, 64 insertions, 39 deletions

diff --git a/src/usr/isteps/istep10/call_proc_chiplet_scominit.C b/src/usr/isteps/istep10/call_proc_chiplet_scominit.C
index f7df9989a..51fa4b75b 100644
--- a/src/usr/isteps/istep10/call_proc_chiplet_scominit.C
+++ b/src/usr/isteps/istep10/call_proc_chiplet_scominit.C
@@ -63,6 +63,9 @@
 #include <p9_chiplet_scominit.H>
 #include <p9_psi_scominit.H>
 
+// Util TCE Support
+#include <util/utiltce.H>
+
 namespace   ISTEP_10
 {
 
@@ -141,6 +144,30 @@ void*    call_proc_chiplet_scominit( void    *io_pArgs )
         }
     } // end of going through all processors
 
+    // Enable TCEs with an empty TCE Table, if necessary
+    // This will prevent the FSP from DMAing to system memory without
+    // hostboot's knowledge
+    if ( TCE::utilUseTcesForDmas() )
+    {
+        l_err = TCE::utilEnableTcesWithoutTceTable();
+
+        if (l_err)
+        {
+            TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
+             "call_proc_chiplet_scominit: utilEnableTcesWithoutTceTable "
+             "returned ERROR 0x%.4X",
+             l_err->reasonCode());
+
+            // Create IStep error log and cross ref to error that occurred
+            l_StepError.addErrorDetails( l_err );
+
+            // Commit the error log and move on
+            // Note: Error log should already be deleted and set to NULL
+            // after committing
+            errlCommit(l_err, HWPF_COMP_ID);
+        }
+    }
+
     TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
                              "call_proc_chiplet_scominit exit" );
 
diff --git a/src/usr/isteps/istep16/call_host_ipl_complete.C b/src/usr/isteps/istep16/call_host_ipl_complete.C
index 87eca889b..12397d6c6 100644
--- a/src/usr/isteps/istep16/call_host_ipl_complete.C
+++ b/src/usr/isteps/istep16/call_host_ipl_complete.C
@@ -86,20 +86,19 @@ void* call_host_ipl_complete (void *io_pArgs)
         }
 
 
-
         // Setup the TCEs needed for the FSP to DMA the PAYLOAD
-/*      @TODO RTC 168745 - make this call when FSP is ready for TCE Support
- *                         and add check that we're on a FSP system
- *      NOTE:  add check to do this only on FSP-based systems
- *        l_err = TCE::utilSetupPayloadTces();
- *
- *       if( l_err )
- *       {
- *           TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
- *                      ERR_MRK"TCE::utilSetupPayloadTces failed");
- *           break;
- *       }
- */
+        if (TCE::utilUseTcesForDmas())
+        {
+            l_err = TCE::utilSetupPayloadTces();
+
+            if( l_err )
+            {
+                TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+                           ERR_MRK"TCE::utilSetupPayloadTces failed");
+                // Don't continue with the rest of this istep
+                break;
+            }
+        }
 
         // Initialize the RUNTIME DATA attributes
         // that HDAT needs to allocate memory for us.
diff --git a/src/usr/isteps/istep21/call_host_runtime_setup.C b/src/usr/isteps/istep21/call_host_runtime_setup.C
index 48bda6b9b..767f7c422 100644
--- a/src/usr/isteps/istep21/call_host_runtime_setup.C
+++ b/src/usr/isteps/istep21/call_host_runtime_setup.C
@@ -70,6 +70,31 @@ void* call_host_runtime_setup (void *io_pArgs)
 
     do
     {
+        // Close PAYLOAD TCEs
+        // @TODO RTC 168745 - also close HDAT TCEs
+        if (TCE::utilUseTcesForDmas())
+        {
+
+            l_err = TCE::utilClosePayloadTces();
+            if ( l_err )
+            {
+                TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+                           "Failed TCE::utilClosePayloadTces" );
+                // break from do loop if error occurred
+                break;
+            }
+
+            // Disable all TCEs
+            l_err = TCE::utilDisableTces();
+            if ( l_err )
+            {
+                TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+                           "Failed TCE::utilDisableTces" );
+                // break from do loop if error occurred
+                break;
+            }
+        }
+
         //Need to send System Configuration down to SBE
         //Use targeting code to get a list of all processors
         TARGETING::TargetHandleList l_procChips;
@@ -340,32 +365,6 @@ void* call_host_runtime_setup (void *io_pArgs)
         }
 #endif
 
-        // Close PAYLOAD TCEs
-/*      @TODO RTC 168745 - make this call when FSP is ready for TCE Support
- *                         and add check that we're on a FSP system
- *      NOTE:  move this call to the start of this function
- *      NOTE:  add check to do this only on FSP-based systems
- *        l_err = TCE::utilClosePayloadTces();
- *       if ( l_err )
- *       {
- *           TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
- *                      "Failed TCE::utilClosePayloadTces" );
- *           // break from do loop if error occured
- *           break;
- *       }
- *
- *
- *       // Disable all TCEs
- *       l_err = TCE::utilDisableTces();
- *       if ( l_err )
- *       {
- *           TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
- *                      "Failed TCE::utilDisableTces" );
- *           // break from do loop if error occured
- *           break;
- *       }
- */
-
     } while(0);
 
     if( l_err )