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| author | Dzuy Nguyen <dzuy@us.ibm.com> | 2017-05-25 11:07:55 -0500 |
|---|---|---|
| committer | William G. Hoffa <wghoffa@us.ibm.com> | 2017-06-01 09:20:17 -0400 |
| commit | 392272c0247878a832473157e7d2e6023496ca99 (patch) | |
| tree | fe0d5c5eb67def2c627ef50efa2d9eb1d8e7a948 /src/usr/isteps | |
| parent | 1551812fabb4988129f15356aca8af7786240097 (diff) | |
| download | talos-hostboot-392272c0247878a832473157e7d2e6023496ca99.tar.gz talos-hostboot-392272c0247878a832473157e7d2e6023496ca99.zip | |
Handling of functional NX chiplet
Change-Id: I0aaaf935a0b761d0c09b260315781889562dc32e
RTC: 174401
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40982
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Diffstat (limited to 'src/usr/isteps')
| -rw-r--r-- | src/usr/isteps/istep10/call_host_rng_bist.C | 53 | ||||
| -rw-r--r-- | src/usr/isteps/istep16/call_host_secure_rng.C | 55 |
2 files changed, 80 insertions, 28 deletions
diff --git a/src/usr/isteps/istep10/call_host_rng_bist.C b/src/usr/isteps/istep10/call_host_rng_bist.C index b1ccc5144..68d243547 100644 --- a/src/usr/isteps/istep10/call_host_rng_bist.C +++ b/src/usr/isteps/istep10/call_host_rng_bist.C @@ -42,6 +42,7 @@ #include <isteps/hwpisteperror.H> #include <errl/errludtarget.H> +#include <errl/errlreasoncodes.H> #include <initservice/isteps_trace.H> #include <initservice/initserviceif.H> @@ -86,23 +87,49 @@ void* call_host_rng_bist( void *io_pArgs ) // Loop through all processors including master for (const auto & l_cpu_target: l_cpuTargetList) { - const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>l_fapi2_proc_target( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>l_fapi2_proc_target( l_cpu_target); - - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + // Check for functional NX + TARGETING::TargetHandleList l_nxTargetList; + getChildChiplets(l_nxTargetList, l_cpu_target, TYPE_NX, true); + if (l_nxTargetList.empty()) + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "p9_rng_init_phase1: no functional NX found for proc %.8X", + TARGETING::get_huid(l_cpu_target)); + continue; + } + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "Running p9_rng_init_phase1 HWP on processor target %.8X", TARGETING::get_huid(l_cpu_target) ); - FAPI_INVOKE_HWP(l_err, p9_rng_init_phase1, l_fapi2_proc_target); - if(l_err) - { - TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, - "ERROR: call p9_rng_init_phase1, PLID=0x%x", - l_err->plid()); - l_StepError.addErrorDetails(l_err); - errlCommit(l_err, HWPF_COMP_ID); - } - + FAPI_INVOKE_HWP(l_err, p9_rng_init_phase1, l_fapi2_proc_target); + if(l_err) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR: call p9_rng_init_phase1, PLID=0x%x, rc=0x%.4X", + l_err->plid(), l_err->reasonCode()); + + for (const auto l_callout : l_err->getUDSections( + HWPF_COMP_ID, + ERRORLOG::ERRL_UDT_CALLOUT)) + { + if(reinterpret_cast<HWAS::callout_ud_t*> + (l_callout)->type == HWAS::HW_CALLOUT) + { + for (const auto & l_nxTarget: l_nxTargetList) + { + l_err->addHwCallout( l_nxTarget, + HWAS::SRCI_PRIORITY_HIGH, + HWAS::DECONFIG, + HWAS::GARD_NULL ); + } + } + } + + l_StepError.addErrorDetails(l_err); + errlCommit(l_err, HWPF_COMP_ID); + } } // end of going through all processors TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, diff --git a/src/usr/isteps/istep16/call_host_secure_rng.C b/src/usr/isteps/istep16/call_host_secure_rng.C index 5a5150475..9ca7e0f45 100644 --- a/src/usr/isteps/istep16/call_host_secure_rng.C +++ b/src/usr/isteps/istep16/call_host_secure_rng.C @@ -45,6 +45,7 @@ #include <isteps/hwpisteperror.H> #include <errl/errludtarget.H> +#include <errl/errlreasoncodes.H> #include <initservice/isteps_trace.H> #include <initservice/initserviceif.H> @@ -89,23 +90,47 @@ void* call_host_secure_rng( void *io_pArgs ) // Loop through all processors including master for (const auto & l_cpu_target: l_cpuTargetList) { - const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>l_fapi2_proc_target( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>l_fapi2_proc_target( l_cpu_target); - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "Running host_secure_rng HWP on processor target %.8X", - TARGETING::get_huid(l_cpu_target) ); - - FAPI_INVOKE_HWP(l_err, p9_rng_init_phase2, l_fapi2_proc_target); - if(l_err) - { - TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, - "ERROR: call p9_rng_init_phase2, PLID=0x%x", - l_err->plid()); - l_StepError.addErrorDetails(l_err); - errlCommit(l_err, HWPF_COMP_ID); - } - + // Check for functional NX + TARGETING::TargetHandleList l_nxTargetList; + getChildChiplets(l_nxTargetList, l_cpu_target, TYPE_NX, true); + if (l_nxTargetList.empty()) + { + TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, + "Running host_secure_rng; no functional NX found for proc %.8X", + TARGETING::get_huid(l_cpu_target)); + continue; + } + + FAPI_INVOKE_HWP(l_err, p9_rng_init_phase2, l_fapi2_proc_target); + if(l_err) + { + TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, + "ERROR: call p9_rng_init_phase2, PLID=0x%x, rc=0x%.4X", + l_err->plid(), l_err->reasonCode()); + + for (const auto l_callout : l_err->getUDSections( + HWPF_COMP_ID, + ERRORLOG::ERRL_UDT_CALLOUT)) + { + if(reinterpret_cast<HWAS::callout_ud_t*> + (l_callout)->type == HWAS::HW_CALLOUT) + { + for (const auto & l_nxTarget: l_nxTargetList) + { + l_err->addHwCallout( l_nxTarget, + HWAS::SRCI_PRIORITY_HIGH, + HWAS::DECONFIG, + HWAS::GARD_NULL ); + } + } + } + + l_StepError.addErrorDetails(l_err); + errlCommit(l_err, HWPF_COMP_ID); + } } // end of going through all processors TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, |
