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| author | Marty Gloff <mgloff@us.ibm.com> | 2016-07-27 11:55:38 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-08-10 14:14:54 -0400 |
| commit | 0f64c7b414998e6f9b1b7211f55f0ca481208070 (patch) | |
| tree | baac50f47ccab0274015612fa1faf9c8172fc10f /src/usr/isteps | |
| parent | 15a7b3ec80e826ed07c57739693d9e98a17d2b33 (diff) | |
| download | talos-hostboot-0f64c7b414998e6f9b1b7211f55f0ca481208070.tar.gz talos-hostboot-0f64c7b414998e6f9b1b7211f55f0ca481208070.zip | |
Handle 8MB reduced cache mode
Check scom register (0x1001181B) for reduced cache mode and expand the
memory footprint appropriately, reduced 8MB or full 10MB.
Change-Id: I5920572077cdcee317e7b3b9abe999e6de295459
RTC:152954
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27522
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/usr/isteps')
| -rw-r--r-- | src/usr/isteps/istep06/thread_activate/thread_activate.C | 43 |
1 files changed, 40 insertions, 3 deletions
diff --git a/src/usr/isteps/istep06/thread_activate/thread_activate.C b/src/usr/isteps/istep06/thread_activate/thread_activate.C index 1d5d2de14..84fdd8187 100644 --- a/src/usr/isteps/istep06/thread_activate/thread_activate.C +++ b/src/usr/isteps/istep06/thread_activate/thread_activate.C @@ -46,12 +46,14 @@ #include <arch/pirformat.H> // targeting support +#include <targeting/common/target.H> #include <targeting/common/commontargeting.H> #include <targeting/common/utilFilter.H> // fapi support #include <fapi2.H> #include <fapi2_target.H> +#include <fapi2_hw_access.H> #include <plat_hwp_invoker.H> #include <istep_reasoncodes.H> #include <p9_cpu_special_wakeup.H> @@ -417,9 +419,44 @@ void activate_threads( errlHndl_t& io_rtaskRetErrl ) if ((!PNOR::usingL3Cache()) && (!getCacheDeconfig(l_masterCoreID))) { - TRACFCOMP( g_fapiTd, - "activate_threads: Extending cache to 8MB" ); - mm_extend(MM_EXTEND_FULL_CACHE); + // Get EX + TARGETING::Target* l_ex = + (TARGETING::Target*)getExChiplet(l_masterCore); + assert(l_ex != NULL); + + // Check SCOM 0x1001181B for reduced cache mode + uint64_t l_reducedCacheMode = 0; + size_t l_size = sizeof(l_reducedCacheMode); + l_errl = deviceRead(l_ex, + reinterpret_cast<void*>(&l_reducedCacheMode), + l_size, + DEVICE_SCOM_ADDRESS( + EX_L3_EDRAM_BANK_FAIL_SCOM_RD)); + + if(l_errl) + { + TRACFCOMP( g_fapiTd, + ERR_MRK"activate_threads: Could not get " + "SCOM 0x%.8X, reason code 0x%.8X, EX HUID=%.8X", + EX_L3_EDRAM_BANK_FAIL_SCOM_RD, + l_errl->reasonCode(), + TARGETING::get_huid(l_ex) ); + break; + } + + if(l_reducedCacheMode) + { + TRACFCOMP( g_fapiTd, + "activate_threads: Extending cache to 8MB" ); + mm_extend(MM_EXTEND_REDUCED_CACHE); + } + else + { + TRACFCOMP( g_fapiTd, + "activate_threads: Extending cache to 10MB" ); + mm_extend(MM_EXTEND_FULL_CACHE); + } + } } while(0); |
