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authorMatt Derksen <v2cibmd@us.ibm.com>2016-03-04 10:45:33 -0600
committerWilliam G. Hoffa <wghoffa@us.ibm.com>2016-04-04 09:09:35 -0400
commit287d15e08990eb8ad9892ca94ac38ebe35f9229e (patch)
treef2e0b3d9c559d3db9b156ff3f84a6783b1764d26 /src/usr/isteps/istep08/call_proc_pcie_scominit.C
parent4b4772ef8b18f2e9c80795c47b3a5f81b3521c1f (diff)
downloadtalos-hostboot-287d15e08990eb8ad9892ca94ac38ebe35f9229e.tar.gz
talos-hostboot-287d15e08990eb8ad9892ca94ac38ebe35f9229e.zip
ISTEP08 HWP enablement
Change-Id: Id999da8e97c0bcd5cefabdeb2fe7c80d1efbf5da RTC: 146576 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/21463 Tested-by: Jenkins Server Tested-by: FSP CI Jenkins Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Diffstat (limited to 'src/usr/isteps/istep08/call_proc_pcie_scominit.C')
-rw-r--r--src/usr/isteps/istep08/call_proc_pcie_scominit.C81
1 files changed, 44 insertions, 37 deletions
diff --git a/src/usr/isteps/istep08/call_proc_pcie_scominit.C b/src/usr/isteps/istep08/call_proc_pcie_scominit.C
index ebf26d82e..92a4c1432 100644
--- a/src/usr/isteps/istep08/call_proc_pcie_scominit.C
+++ b/src/usr/isteps/istep08/call_proc_pcie_scominit.C
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER HostBoot Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2015 */
+/* Contributors Listed Below - COPYRIGHT 2015,2016 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -51,17 +51,17 @@
#include <targeting/common/commontargeting.H>
#include <targeting/common/utilFilter.H>
+#include <fapi2/target.H>
+#include <fapi2/plat_hwp_invoker.H>
+
// MVPD
#include <devicefw/userif.H>
#include <vpd/mvpdenums.H>
#include <config.h>
-// -- prototype includes --
-// Add any customized routines that you don't want overwritten into
-// "start_clocks_on_nest_chiplets_custom.C" and include
-// the prototypes here.
-// #include "nest_chiplets_custom.H"
+#include <p9_pcie_scominit.H>
+
namespace ISTEP_08
{
@@ -76,20 +76,29 @@ using namespace TARGETING;
void* call_proc_pcie_scominit( void *io_pArgs )
{
errlHndl_t l_errl = NULL;
- //@TODO RTC:134078
-/* IStepError l_StepError;
+ IStepError l_StepError;
bool spBaseServicesEnabled = INITSERVICE::spBaseServicesEnabled();
- TARGETING::TargetHandleList l_procTargetList;
- getAllChips(l_procTargetList, TYPE_PROC);
+ //
+ // get the master Proc target, we want to IGNORE this one.
+ //
+ TARGETING::Target* l_pMasterProcTarget = NULL;
+ TARGETING::targetService().masterProcChipTargetHandle(l_pMasterProcTarget);
+
+ //
+ // get a list of all the procs in the system
+ //
+ TARGETING::TargetHandleList l_cpuTargetList;
+ getAllChips(l_cpuTargetList, TYPE_PROC);
- for ( TargetHandleList::const_iterator
- l_iter = l_procTargetList.begin();
- l_iter != l_procTargetList.end();
- ++l_iter )
+ for (const auto & l_cpu_target: l_cpuTargetList)
{
- TARGETING::Target* const l_proc_target = *l_iter;
+ if ( l_cpu_target == l_pMasterProcTarget )
+ {
+ // we are just checking the Slave PCI's, skip the master
+ continue;
+ }
// Compute the PCIE attribute config on all non-SP systems, since SP
// won't be there to do it.
@@ -97,41 +106,41 @@ void* call_proc_pcie_scominit( void *io_pArgs )
{
// Unlike SP which operates on all present procs, the SP-less
// algorithm only needs to operate on functional ones
- l_errl = computeProcPcieConfigAttrs(l_proc_target);
+ // TODO-RTC:149525
+ //l_errl = computeProcPcieConfigAttrs(l_cpu_target);
if(l_errl != NULL)
{
// Any failure to configure PCIE that makes it to this handler
// implies a firmware bug that should be fixed, everything else
// is tolerated internally (usually as disabled PHBs)
- TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
- ERR_MRK "call_proc_pcie_scominit> Failed in call to "
- "computeProcPcieConfigAttrs for target with HUID = "
- "0x%08X",
- l_proc_target->getAttr<TARGETING::ATTR_HUID>());
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+ ERR_MRK "call_proc_pcie_scominit> Failed in call to "
+ "computeProcPcieConfigAttrs for target with HUID = "
+ "0x%08X",
+ l_cpu_target->getAttr<TARGETING::ATTR_HUID>() );
l_StepError.addErrorDetails(l_errl);
errlCommit( l_errl, ISTEP_COMP_ID );
}
}
- const fapi::Target l_fapi_proc_target( TARGET_TYPE_PROC_CHIP,
- ( const_cast<TARGETING::Target*>(l_proc_target) ));
+ const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> l_fapi2_proc_target(
+ l_cpu_target);
TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
- "Running proc_pcie_scominit HWP on "
- "target HUID %.8X", TARGETING::get_huid(l_proc_target));
+ "Running p9_pcie_scominit HWP on "
+ "target HUID %.8X", TARGETING::get_huid(l_cpu_target) );
- // call the HWP with each fapi::Target
- // @TODO RTC: 134078
- //FAPI_INVOKE_HWP(l_errl, p9_pcie_scominit, l_fapi_proc_target);
+ // call the HWP with each fapi2::Target
+ FAPI_INVOKE_HWP(l_errl, p9_pcie_scominit, l_fapi2_proc_target);
if (l_errl)
{
- TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
- "ERROR 0x%.8X : proc_pcie_scominit HWP returns error",
- l_errl->reasonCode());
+ TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
+ "ERROR 0x%.8X : p9_pcie_scominit HWP returned error",
+ l_errl->reasonCode() );
// capture the target data in the elog
- ErrlUserDetailsTarget(l_proc_target).addToLog( l_errl );
+ ErrlUserDetailsTarget(l_cpu_target).addToLog( l_errl );
// Create IStep error log and cross reference to error that occurred
l_StepError.addErrorDetails( l_errl );
@@ -143,16 +152,14 @@ void* call_proc_pcie_scominit( void *io_pArgs )
else
{
TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
- "SUCCESS : proc_pcie_scominit HWP" );
+ "SUCCESS : proc_pcie_scominit HWP" );
}
- }
+ } // end of looping through all processors
TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
- "call_proc_pcie_scominit exit" );
+ "call_proc_pcie_scominit exit" );
// end task, returning any errorlogs to IStepDisp
return l_StepError.getErrorHandle();
- */
- return l_errl;
}
};
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