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| author | Dean Sanner <dsanner@us.ibm.com> | 2017-12-05 15:10:45 -0600 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2018-09-24 12:17:16 -0500 |
| commit | fcfd722a6abb01f780c10de0f5d801a9c4210ebd (patch) | |
| tree | 49cfafdc273b1aa7989d851d7c17fbb74dd54b0b /src/usr/intr | |
| parent | 69cc45d8f059a113f6bad12e1fdd82123497893a (diff) | |
| download | talos-hostboot-fcfd722a6abb01f780c10de0f5d801a9c4210ebd.tar.gz talos-hostboot-fcfd722a6abb01f780c10de0f5d801a9c4210ebd.zip | |
Support HB running in SMF
Support SMF for P9N/P9C. Lots of minor tweaks to make this
work, but the biggest is to run userspace in problem state
This is needed because for SMF Hostboot will need to run in S=1,
HV=0,PR=1 (and kernel in S=1, HV=1, PR=0)
This commit makes P9 HB userpsace run in HV=0 PR=1 and kernel in
HV=1, PR=0.
Change-Id: Ia4771df5e8858c6b7ae54b0746e62b283afb4bc4
RTC: 197243
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/50530
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/usr/intr')
| -rw-r--r-- | src/usr/intr/intrrp.C | 4 | ||||
| -rw-r--r-- | src/usr/intr/intrrp.H | 7 |
2 files changed, 8 insertions, 3 deletions
diff --git a/src/usr/intr/intrrp.C b/src/usr/intr/intrrp.C index 119b4d6c7..dffdc6273 100644 --- a/src/usr/intr/intrrp.C +++ b/src/usr/intr/intrrp.C @@ -3140,9 +3140,11 @@ errlHndl_t IntrRp::setXiveIvpeTmBAR1(TARGETING::Target * i_target, //Map Memory Internally for HB and store in member variable void *l_xiveTmBar1Address = reinterpret_cast<void *>(l_baseBarValue); + // SMF doesn't allow the user space to touch Ultravisor page (page 0), + // so we have to use page 1. Map 2 page sizes to be able to access page1 iv_xiveTmBar1Address = reinterpret_cast<uint64_t *> - (mmio_dev_map(l_xiveTmBar1Address, PAGE_SIZE)); + (mmio_dev_map(l_xiveTmBar1Address, PAGE_SIZE*2)); } while(0); diff --git a/src/usr/intr/intrrp.H b/src/usr/intr/intrrp.H index 2595ca105..3f00f2900 100644 --- a/src/usr/intr/intrrp.H +++ b/src/usr/intr/intrrp.H @@ -233,8 +233,11 @@ namespace INTR XIVE_RESET_POWERBUS_QUIESCE_ENABLE = 0x4000000000000000, XIVE_RESET_POWERBUS_QUIESCE_TIMEOUT = 1000000, //1 millisecond XIVE_RESET_UNIT_ENABLE = 0x8000000000000000, - ACK_HYPERVISOR_INT_REG_OFFSET = 0x830/sizeof(uint16_t), - PULL_THREAD_CONTEXT_OFFSET = 0x838/sizeof(uint8_t), + + //For SMF use Hype offset as common between non SMF/SMF + ACK_HYPERVISOR_INT_REG_OFFSET = 0x1830/sizeof(uint16_t), + PULL_THREAD_CONTEXT_OFFSET = 0x1838/sizeof(uint8_t), + POWERBUS_STATE_QUIESCE = 0xC000000000000000, MAX_PSU_LONG_TIMEOUT_NS = 5000*NS_PER_MSEC, //5 seconds |
