RTC Story 36901 - Use LPC Memory

This includes a hack to allow access to our fake PNOR data via
the ECCB scom registers.  This hack will be removed once Simics
provides a real ECCB model.

Changes to INTR testcase were needed due to bugs exposed by the
timing changes when enabling this new code.

Note that the default operating mode will remain LPC_MEM because
the current version of the ECCB model causes the IPL to take
close to 10 minutes to complete.

Change-Id: Icc236bffd52ba8214ec920f9a496adec138e54d9
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/692
Tested-by: Jenkins Server
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

1 files changed, 25 insertions, 7 deletions

diff --git a/src/usr/intr/test/intrtest.H b/src/usr/intr/test/intrtest.H
index 712e97a6e..5135d3371 100644
--- a/src/usr/intr/test/intrtest.H
+++ b/src/usr/intr/test/intrtest.H
@@ -30,6 +30,10 @@
 #include <kernel/console.H>
 #include <targeting/targetservice.H>
 #include <targeting/util.H>
+#include <sys/time.h>
+#include <sys/mmio.h>
+
+extern trace_desc_t * g_trac_intr;
 
 
 class IntrTest: public CxxTest::TestSuite
@@ -67,7 +71,7 @@ class IntrTest: public CxxTest::TestSuite
                     uint64_t offset = (chip << 20) | (thread << 12);
 
                     uint32_t * addr =
-                        reinterpret_cast<uint32_t *>(cv_baseAddr + offset);
+                        reinterpret_cast<uint32_t *>(iv_baseAddr + offset);
 
                     if(offset == 0) // Master cpu
                     {
@@ -114,7 +118,7 @@ class IntrTest: public CxxTest::TestSuite
                 return;
             }
 
-            uint32_t * addr = reinterpret_cast<uint32_t *>(cv_baseAddr);
+            uint32_t * addr = reinterpret_cast<uint32_t *>(iv_baseAddr);
 
             errlHndl_t err = INTR::disableExternalInterrupts();
 
@@ -161,8 +165,6 @@ class IntrTest: public CxxTest::TestSuite
                 return;
             }
 
-            extern trace_desc_t * g_trac_intr;
-
             errlHndl_t err = NULL;
 
             // Need to register a msgq
@@ -177,7 +179,7 @@ class IntrTest: public CxxTest::TestSuite
 
             // Force an interrupt by writing to the MFFR on master
             volatile uint8_t * mfrr = 
-                reinterpret_cast<uint8_t *>(cv_baseAddr+12);
+                reinterpret_cast<uint8_t *>(iv_baseAddr+12);
             *(mfrr) = 0x55;
             *(mfrr) = 0xff;
 
@@ -192,12 +194,28 @@ class IntrTest: public CxxTest::TestSuite
         }
 
 
+      IntrTest() : CxxTest::TestSuite()
+      {
+          iv_baseAddr = reinterpret_cast<uint64_t>
+            (mmio_dev_map(reinterpret_cast<void*>(cv_realAddr),THIRTYTWO_MB));
+          TRACDCOMP(g_trac_intr,"IntrTest()> iv_baseAddr=0x%.X",iv_baseAddr);
+      };
+
+
+      ~IntrTest()
+      {
+          mmio_dev_unmap(reinterpret_cast<void*>(iv_baseAddr));
+      };
+
     private:
 
-        static uint64_t cv_baseAddr;
+      uint64_t iv_baseAddr;
+      static const uint64_t cv_realAddr;
 };
 
-uint64_t IntrTest::cv_baseAddr = 0x20000000000ul;
+//note: this must be changed if the BAR changes
+const uint64_t IntrTest::cv_realAddr = 0x3fbff9000000ul;
+
 
 
 #endif