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authorDean Sanner <dsanner@us.ibm.com>2014-04-03 10:45:39 -0500
committerA. Patrick Williams III <iawillia@us.ibm.com>2014-04-03 11:33:41 -0500
commitb7ae1209c26699f076b2c8b14db761f625d69784 (patch)
tree9e3b0a34995e87cf8a457cf7e82e4d8d98be0eda /src/usr/intr/intrrp.H
parenta1ae2a2a50b16d5cb1f45d61b571994de6cb3065 (diff)
downloadtalos-hostboot-b7ae1209c26699f076b2c8b14db761f625d69784.tar.gz
talos-hostboot-b7ae1209c26699f076b2c8b14db761f625d69784.zip
Remove EOIs for PCIe on MPIPL
Change-Id: I69fd098449410888c9358868dc3affbc16d906bb CQ: SW248383 Backport: release-fips810 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/10105 Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com> Tested-by: Jenkins Server
Diffstat (limited to 'src/usr/intr/intrrp.H')
-rw-r--r--src/usr/intr/intrrp.H12
1 files changed, 0 insertions, 12 deletions
diff --git a/src/usr/intr/intrrp.H b/src/usr/intr/intrrp.H
index aff759f58..2cebf3794 100644
--- a/src/usr/intr/intrrp.H
+++ b/src/usr/intr/intrrp.H
@@ -492,18 +492,6 @@ namespace INTR
uint32_t& o_irsn, uint32_t& o_num);
/**
- * Read the PCIE interrupt source numbers out of the HW
- *
- * @param i_target Processor target to read value from
- * @param o_irsn List of IRSN for the PCIE units
- * @param o_num Number of interrupts behind IRSN
- * @return an error handle on error
- */
- errlHndl_t getPcieIRSNs(TARGETING::Target * i_target,
- std::vector<uint32_t> &o_irsn,
- std::vector<uint32_t> &o_num);
-
- /**
* Read the NX interrupt source number out of the HW
*
* @param i_target Processor target to read value from
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