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| author | Dan Crowell <dcrowell@us.ibm.com> | 2018-11-05 10:51:20 -0600 |
|---|---|---|
| committer | William G. Hoffa <wghoffa@us.ibm.com> | 2018-11-27 09:51:59 -0600 |
| commit | cbf7565aeb3f5294dc1aef26e94421f74d5e9c50 (patch) | |
| tree | 6ae0dfe61eaee944937f1cb35f40f1a38b03973f /src/usr/initservice | |
| parent | e3007bd7476f9f3a5ebde23d0ea12a845965d8fa (diff) | |
| download | talos-hostboot-cbf7565aeb3f5294dc1aef26e94421f74d5e9c50.tar.gz talos-hostboot-cbf7565aeb3f5294dc1aef26e94421f74d5e9c50.zip | |
Progress code tweaks
Added additional calls to poke the watchdog during draminit
training advanced in anticipation of FSP using the progress
codes as a finer granularity timeout mechanism.
Started rolling the internalStep nibble of our CFAM reg istep
counter as a way to show internal progress in long-running steps
Change-Id: I7a3bd08d9ab71b020a05b7476b3e31f8c81c4f86
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68393
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Diffstat (limited to 'src/usr/initservice')
| -rw-r--r-- | src/usr/initservice/istepdispatcher/istepdispatcher.C | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/usr/initservice/istepdispatcher/istepdispatcher.C b/src/usr/initservice/istepdispatcher/istepdispatcher.C index 532199d3a..b7336780d 100644 --- a/src/usr/initservice/istepdispatcher/istepdispatcher.C +++ b/src/usr/initservice/istepdispatcher/istepdispatcher.C @@ -2424,6 +2424,7 @@ void IStepDispatcher::handlePerstMsg(msg_t * & io_pMsg) errlHndl_t IStepDispatcher::sendProgressCode(bool i_needsLock) { static uint8_t lastIstep = 0, lastSubstep = 0; + static uint8_t internalStep = 0; errlHndl_t err = NULL; if (i_needsLock) @@ -2439,12 +2440,16 @@ errlHndl_t IStepDispatcher::sendProgressCode(bool i_needsLock) //--- Display istep in Simics console MAGIC_INST_PRINT_ISTEP( iv_curIStep, iv_curSubStep ); + + // Reset internalStep counter since we are on a new istep + internalStep = 0; } //--- Save step to a scratch reg SPLESS::MboxScratch5_HB_t l_scratch5; l_scratch5.magic = SPLESS::ISTEP_PROGRESS_MAGIC; l_scratch5.stepStart = 1; + l_scratch5.internalStep = internalStep++; //increment on each call l_scratch5.majorStep = iv_curIStep; l_scratch5.minorStep = iv_curSubStep; Util::writeScratchReg( SPLESS::MBOX_SCRATCH_REG5, |
