IBSCOM Enablement and Error Handling

Enable IBSCOM for Centaur DD2.x chips
Add appropriate error handling
Flip scom to FSI after IBSCOM fail
Enable reconfig loop cleanup

Code verified on hardware

Change-Id: I394789b900e5779dded78dd5fbcc9b9257e856fb
RTC: 69115
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/7410
Tested-by: Jenkins Server
Reviewed-by: Michael Baiocchi <baiocchi@us.ibm.com>
Reviewed-by: ADAM R. MUHLE <armuhle@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

1 files changed, 18 insertions, 0 deletions

diff --git a/src/usr/ibscom/ibscom.H b/src/usr/ibscom/ibscom.H
index 3ba3c34f1..f1742b3e5 100644
--- a/src/usr/ibscom/ibscom.H
+++ b/src/usr/ibscom/ibscom.H
@@ -67,6 +67,24 @@ errlHndl_t ibscomPerformOp(DeviceFW::OperationType i_opType,
                           int64_t i_accessType,
                           va_list i_args);
 
+/**
+ * Bit definition for MBSIBERR0
+ */
+struct MBSIBERRO_Reg_t
+{
+    union
+    {
+        uint64_t data;
+        struct
+        {
+            uint64_t addr:32;    //MBSIBERR0Q_IB_HOST_ADDRESS
+            uint64_t errvalid:1; //MBSIBERR0Q_IB_HOST_ERROR_VALID
+            uint64_t piberr:3;   //MBSIBERR0Q_IB_HOST_ERROR_STATUS
+            uint64_t iswrite:1;  //MBSIBERR0Q_IB_HOST_WRITE_NOT_READ
+            uint64_t reserved:27;
+        };
+    };
+};
 
 
 };