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authorChristian Geddes <crgeddes@us.ibm.com>2019-07-26 10:50:15 -0500
committerDaniel M Crowell <dcrowell@us.ibm.com>2019-08-01 16:50:12 -0500
commit7e05c2e69bf8e9c94b7ab0da63b62546fe79796e (patch)
tree141274862aaa2ab5126affcc94ebe039fd7bc989 /src/usr/i2c
parentb3043ae1686d2c01fc55f431c954a23d775923b5 (diff)
downloadtalos-hostboot-7e05c2e69bf8e9c94b7ab0da63b62546fe79796e.tar.gz
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Always update EECACHE header when we find a new eeprom entry
The plan of this caching algorithm is to make a cache entry for every OCMB/DIMM, Proc, and Node eeprom that we detect in the XML. We will only copy the contents of the EEPROM if the target is found to be present, but we still must make header entries in for targets that are not present. Change-Id: I46328b84f7095eec9df7abb2f40b0d11ed0c4324 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/81192 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Matt Derksen <mderkse1@us.ibm.com> Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Glenn Miles <milesg@ibm.com> Reviewed-by: Daniel M Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/usr/i2c')
-rw-r--r--src/usr/i2c/eepromCache.C17
1 files changed, 11 insertions, 6 deletions
diff --git a/src/usr/i2c/eepromCache.C b/src/usr/i2c/eepromCache.C
index 851459376..436496d01 100644
--- a/src/usr/i2c/eepromCache.C
+++ b/src/usr/i2c/eepromCache.C
@@ -102,6 +102,9 @@ errlHndl_t cacheEeprom(TARGETING::Target* i_target,
bool l_updateHeader = true;
bool l_updateContents = true;
+ // Initially assume this is a new eeprom cache entry
+ bool l_newEntryDetected = true;
+
do{
// eepromReadAttributes keys off the eepromRole value
// to determine what attribute to lookup to get eeprom info
@@ -222,6 +225,9 @@ errlHndl_t cacheEeprom(TARGETING::Target* i_target,
if( memcmp(l_recordHeaderToUpdate, &l_eepromRecordHeader, NUM_BYTE_UNIQUE_ID ) == 0 )
{
l_recordHeaderToUpdateIndex = i;
+ // We have matched with existing eeprom in the PNOR's EECACHE
+ // section. So we know this is not a new entry.
+ l_newEntryDetected = false;
if( l_recordHeaderToUpdate->completeRecord.cache_copy_size != l_eepromRecordHeader.completeRecord.cache_copy_size)
{
@@ -414,16 +420,15 @@ errlHndl_t cacheEeprom(TARGETING::Target* i_target,
else if(!i_present)
{
// If the target is not present, then do not update contents
- // or header
l_updateContents = false;
- l_updateHeader = false;
+ // Only update header if this is a new entry
+ l_updateHeader = l_newEntryDetected;
}
- // The check below makes sure that is isnt a new entry, because
- // new entries do not have internal_offset set in header.
+ // The check below makes sure that is isnt a new entry
// If there is a matching header entry in PNOR marked 'invalid'
// but we now see the target as present, this indicates a replacement
// part has been added where a part was removed
- else if(l_recordHeaderToUpdate->completeRecord.internal_offset != UNSET_INTERNAL_OFFSET_VALUE)
+ else if(!l_newEntryDetected)
{
TRACFCOMP(g_trac_eeprom, "cacheEeprom() Detected replacement of a part"
" Master 0x%.08X Engine 0x%.02X"
@@ -953,4 +958,4 @@ uint64_t lookupEepromHeaderAddr(const eepromRecordHeader& i_eepromRecordHeader)
return l_vaddr;
}
-}
+} \ No newline at end of file
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