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author | Thi Tran <thi@us.ibm.com> | 2014-03-26 21:23:11 -0500 |
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committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2014-03-27 08:20:33 -0500 |
commit | e2669f40b53e00d9eee4a2f3b6bbc745df423535 (patch) | |
tree | a7f601ccd3fc04a2b4feee6770280021e2d0d5f6 /src/usr/hwpf | |
parent | b9896f73b25f5bb2cd29d8b78e904ba9c267763d (diff) | |
download | talos-hostboot-e2669f40b53e00d9eee4a2f3b6bbc745df423535.tar.gz talos-hostboot-e2669f40b53e00d9eee4a2f3b6bbc745df423535.zip |
INITPROC: Hostboot SW252901 MBSFIR[3]
Change-Id: Ie9e323098cf7475d8748c8b878345348977a9580
CQ:SW252901
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/9935
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr/hwpf')
-rw-r--r-- | src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_setup.C | 38 | ||||
-rw-r--r-- | src/usr/hwpf/hwp/initfiles/p8.tpbridge.scom.initfile | 86 |
2 files changed, 121 insertions, 3 deletions
diff --git a/src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_setup.C b/src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_setup.C index b2dd7ed34..eebb5fae2 100644 --- a/src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_setup.C +++ b/src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_setup.C @@ -5,7 +5,7 @@ /* */ /* IBM CONFIDENTIAL */ /* */ -/* COPYRIGHT International Business Machines Corp. 2012,2013 */ +/* COPYRIGHT International Business Machines Corp. 2012,2014 */ /* */ /* p1 */ /* */ @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: cen_mem_pll_setup.C,v 1.25 2013/11/15 16:30:00 mfred Exp $ +// $Id: cen_mem_pll_setup.C,v 1.26 2014/03/19 13:58:05 mfred Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/cen_mem_pll_setup.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2012 @@ -52,6 +52,10 @@ const uint16_t POLL_COUNT_MAX = 50; // Number of times to poll fo // CFAM FSI STATUS register bit/field definitions const uint8_t FSI_STATUS_MEM_PLL_LOCK_BIT = 25; +// TP LFIR bit/field definitions +const uint8_t TP_LFIR_ERRORS_FROM_NEST_PLL_LOCK_BIT = 19; +const uint8_t TP_LFIR_ERRORS_FROM_MEM_PLL_LOCK_BIT = 20; + extern "C" { using namespace fapi; @@ -61,6 +65,8 @@ fapi::ReturnCode cen_mem_pll_setup(const fapi::Target & i_target) // Target is centaur fapi::ReturnCode rc; ecmdDataBufferBase cfam_data(32); + uint32_t rc_ecmd = 0; + ecmdDataBufferBase scom_data(64); uint32_t poll_count = 0; uint32_t done_polling = 0; @@ -110,6 +116,31 @@ fapi::ReturnCode cen_mem_pll_setup(const fapi::Target & i_target) FAPI_INF("Centaur MEM PLL is now locked."); } + + FAPI_DBG("Clearing the FIR PLL lock error bits and unmasking TP LFIR PLL lock error bits ..."); + rc_ecmd |= scom_data.flushTo1(); + rc_ecmd |= scom_data.clearBit(TP_LFIR_ERRORS_FROM_NEST_PLL_LOCK_BIT); + rc_ecmd |= scom_data.clearBit(TP_LFIR_ERRORS_FROM_MEM_PLL_LOCK_BIT); + if (rc_ecmd) + { + FAPI_ERR("Error 0x%x setting up ecmd data buffer to clear TP LFIR PLL Lock bits.", rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } + rc = fapiPutScom(i_target, TP_PERV_LFIR_AND_0x0104000B, scom_data); + if (!rc.ok()) + { + FAPI_ERR("Error writing Pervasive LFIR AND Register."); + break; + } + rc = fapiPutScom(i_target, TP_PERV_LFIR_MASK_AND_0x0104000E, scom_data); + if (!rc.ok()) + { + FAPI_ERR("Error writing Pervasive LFIR Mask AND Register."); + break; + } + + } while(0); FAPI_INF("********* cen_mem_pll_setup complete *********"); @@ -125,6 +156,9 @@ fapi::ReturnCode cen_mem_pll_setup(const fapi::Target & i_target) This section is automatically updated by CVS when you check in this file. Be sure to create CVS comments when you commit so that they can be included here. $Log: cen_mem_pll_setup.C,v $ +Revision 1.26 2014/03/19 13:58:05 mfred +Update to clear and unmask the PLL lock FIR bits after the PLL locks. SW249390. + Revision 1.25 2013/11/15 16:30:00 mfred Changes made by Mike Jones for gerrit review, mostly for improved error handling. diff --git a/src/usr/hwpf/hwp/initfiles/p8.tpbridge.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.tpbridge.scom.initfile index df80d0613..94559c4c4 100644 --- a/src/usr/hwpf/hwp/initfiles/p8.tpbridge.scom.initfile +++ b/src/usr/hwpf/hwp/initfiles/p8.tpbridge.scom.initfile @@ -1,4 +1,4 @@ -#-- $Id: p8.tpbridge.scom.initfile,v 1.6 2013/12/16 14:20:14 jmcgill Exp $ +#-- $Id: p8.tpbridge.scom.initfile,v 1.7 2014/03/20 11:18:57 bgeukes Exp $ #------------------------------------------------------------------------------- #-- #-- (C) Copyright International Business Machines Corp. 2011 @@ -112,3 +112,87 @@ scom 0x02010943 { 0:63, 0x1FC0000000000000; } +#### Perform PERV SCOM overwrites to support PLL lock handling by FW through PCB structure +#### Code goes into this initfile, as a dedicated one for PERV content only was not +#### possible at 2014/03/17 anymore. + + +#-------------------------------------------------------------------------------- +#-- Clearing Lock Bit Errors from early IPL phase +#-------------------------------------------------------------------------------- +# PERV Slave Lock Register +# clearing PLL Lock Error Indication +scom 0x010F001F { + bits, scom_data; + 0:63, 0x0000007800000000; +} + +# Nest Slave Lock Register +# clearing PLL Lock Error Indication +scom 0x020F001F { + bits, scom_data; + 0:63, 0x0000007800000000; +} + +# We keep XBUS pll masked as this will not be used in production mode +## XBUS Slave Lock Register +## clearing PLL Lock Error Indication +#scom 0x040F001F { +# bits, scom_data; +# 0:63, 0x0000007800000000; +#} + +# ABUS Slave Lock Register +# clearing PLL Lock Error Indication +scom 0x080F001F { + bits, scom_data; + 0:63, 0x0000007800000000; +} + +# PCI Slave Lock Register +# clearing PLL Lock Error Indication +scom 0x090F001F { + bits, scom_data; + 0:63, 0x0000007800000000; +} + + +#-------------------------------------------------------------------------------- +#-- SCOM initializations of Mask Bits +#-------------------------------------------------------------------------------- + +# PERV Slave Config Register +# un Masking PLL Lock Error Indication +scom 0x010F001E { + bits, scom_data; + 0:63, 0x0070000000000000; +} + +# Nest Slave Config Register +# un Masking PLL Lock Error Indication +scom 0x020F001E { + bits, scom_data; + 0:63, 0x0070000000000000; +} + +# We keep XBUS pll masked as this will not be used in production mode +## XBUS Slave Config Register +## un Masking PLL Lock Error Indication +#scom 0x040F001E { +# bits, scom_data; +# 0:63, 0x0070000000000000; +#} + +# Abus Slave Config Register +# un Masking PLL Lock Error Indication +scom 0x080F001E { + bits, scom_data; + 0:63, 0x0070000000000000; +} + +# PCI Slave Config Register +# un Masking PLL Lock Error Indication +scom 0x090F001E { + bits, scom_data; + 0:63, 0x0070000000000000; +} |